1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <rte_common.h>
7 #include <rte_malloc.h>
8 #include <rte_memzone.h>
10 #include <rte_bus_pci.h>
11 #include <rte_atomic.h>
12 #include <rte_prefetch.h>
15 #include "qat_device.h"
19 #include "adf_transport_access_macros.h"
22 #define ADF_MAX_DESC 4096
23 #define ADF_MIN_DESC 128
25 #define ADF_ARB_REG_SLOT 0x1000
26 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
28 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
29 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
30 (ADF_ARB_REG_SLOT * index), value)
33 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
34 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
35 /* queue pairs which provide an asymmetric crypto service */
36 [QAT_SERVICE_ASYMMETRIC] = {
38 .service_type = QAT_SERVICE_ASYMMETRIC,
46 .service_type = QAT_SERVICE_ASYMMETRIC,
54 /* queue pairs which provide a symmetric crypto service */
55 [QAT_SERVICE_SYMMETRIC] = {
57 .service_type = QAT_SERVICE_SYMMETRIC,
65 .service_type = QAT_SERVICE_SYMMETRIC,
73 /* queue pairs which provide a compression service */
74 [QAT_SERVICE_COMPRESSION] = {
76 .service_type = QAT_SERVICE_COMPRESSION,
83 .service_type = QAT_SERVICE_COMPRESSION,
93 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
94 uint32_t queue_size_bytes);
95 static void qat_queue_delete(struct qat_queue *queue);
96 static int qat_queue_create(struct qat_pci_device *qat_dev,
97 struct qat_queue *queue, struct qat_qp_config *, uint8_t dir);
98 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
99 uint32_t *queue_size_for_csr);
100 static void adf_configure_queues(struct qat_qp *queue);
101 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
102 rte_spinlock_t *lock);
103 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
104 rte_spinlock_t *lock);
107 int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
108 enum qat_service_type service)
112 for (i = 0, count = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++)
113 if (qp_hw_data[i].service_type == service)
118 static const struct rte_memzone *
119 queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
122 const struct rte_memzone *mz;
124 mz = rte_memzone_lookup(queue_name);
126 if (((size_t)queue_size <= mz->len) &&
127 ((socket_id == SOCKET_ID_ANY) ||
128 (socket_id == mz->socket_id))) {
129 QAT_LOG(DEBUG, "re-use memzone already "
130 "allocated for %s", queue_name);
134 QAT_LOG(ERR, "Incompatible memzone already "
135 "allocated %s, size %u, socket %d. "
136 "Requested size %u, socket %u",
137 queue_name, (uint32_t)mz->len,
138 mz->socket_id, queue_size, socket_id);
142 QAT_LOG(DEBUG, "Allocate memzone for %s, size %u on socket %u",
143 queue_name, queue_size, socket_id);
144 return rte_memzone_reserve_aligned(queue_name, queue_size,
145 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
148 int qat_qp_setup(struct qat_pci_device *qat_dev,
149 struct qat_qp **qp_addr,
150 uint16_t queue_pair_id,
151 struct qat_qp_config *qat_qp_conf)
155 struct rte_pci_device *pci_dev = qat_dev->pci_dev;
156 char op_cookie_pool_name[RTE_RING_NAMESIZE];
159 QAT_LOG(DEBUG, "Setup qp %u on qat pci device %d gen %d",
160 queue_pair_id, qat_dev->qat_dev_id, qat_dev->qat_dev_gen);
162 if ((qat_qp_conf->nb_descriptors > ADF_MAX_DESC) ||
163 (qat_qp_conf->nb_descriptors < ADF_MIN_DESC)) {
164 QAT_LOG(ERR, "Can't create qp for %u descriptors",
165 qat_qp_conf->nb_descriptors);
169 if (pci_dev->mem_resource[0].addr == NULL) {
170 QAT_LOG(ERR, "Could not find VF config space "
171 "(UIO driver attached?).");
175 /* Allocate the queue pair data structure. */
176 qp = rte_zmalloc("qat PMD qp metadata",
177 sizeof(*qp), RTE_CACHE_LINE_SIZE);
179 QAT_LOG(ERR, "Failed to alloc mem for qp struct");
182 qp->nb_descriptors = qat_qp_conf->nb_descriptors;
183 qp->op_cookies = rte_zmalloc("qat PMD op cookie pointer",
184 qat_qp_conf->nb_descriptors * sizeof(*qp->op_cookies),
185 RTE_CACHE_LINE_SIZE);
186 if (qp->op_cookies == NULL) {
187 QAT_LOG(ERR, "Failed to alloc mem for cookie");
192 qp->mmap_bar_addr = pci_dev->mem_resource[0].addr;
195 if (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,
196 ADF_RING_DIR_TX) != 0) {
197 QAT_LOG(ERR, "Tx queue create failed "
198 "queue_pair_id=%u", queue_pair_id);
202 if (qat_queue_create(qat_dev, &(qp->rx_q), qat_qp_conf,
203 ADF_RING_DIR_RX) != 0) {
204 QAT_LOG(ERR, "Rx queue create failed "
205 "queue_pair_id=%hu", queue_pair_id);
206 qat_queue_delete(&(qp->tx_q));
210 adf_configure_queues(qp);
211 adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr,
212 &qat_dev->arb_csr_lock);
214 snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,
215 "%s%d_cookies_%s_qp%hu",
216 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
217 qat_qp_conf->service_str, queue_pair_id);
219 QAT_LOG(DEBUG, "cookiepool: %s", op_cookie_pool_name);
220 qp->op_cookie_pool = rte_mempool_lookup(op_cookie_pool_name);
221 if (qp->op_cookie_pool == NULL)
222 qp->op_cookie_pool = rte_mempool_create(op_cookie_pool_name,
224 qat_qp_conf->cookie_size, 64, 0,
225 NULL, NULL, NULL, NULL, qat_qp_conf->socket_id,
227 if (!qp->op_cookie_pool) {
228 QAT_LOG(ERR, "QAT PMD Cannot create"
233 for (i = 0; i < qp->nb_descriptors; i++) {
234 if (rte_mempool_get(qp->op_cookie_pool, &qp->op_cookies[i])) {
235 QAT_LOG(ERR, "QAT PMD Cannot get op_cookie");
240 qp->qat_dev_gen = qat_dev->qat_dev_gen;
241 qp->build_request = qat_qp_conf->build_request;
242 qp->service_type = qat_qp_conf->hw->service_type;
243 qp->qat_dev = qat_dev;
245 QAT_LOG(DEBUG, "QP setup complete: id: %d, cookiepool: %s",
246 queue_pair_id, op_cookie_pool_name);
252 if (qp->op_cookie_pool)
253 rte_mempool_free(qp->op_cookie_pool);
254 rte_free(qp->op_cookies);
259 int qat_qp_release(struct qat_qp **qp_addr)
261 struct qat_qp *qp = *qp_addr;
265 QAT_LOG(DEBUG, "qp already freed");
269 QAT_LOG(DEBUG, "Free qp on qat_pci device %d",
270 qp->qat_dev->qat_dev_id);
272 /* Don't free memory if there are still responses to be processed */
273 if (qp->inflights16 == 0) {
274 qat_queue_delete(&(qp->tx_q));
275 qat_queue_delete(&(qp->rx_q));
280 adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr,
281 &qp->qat_dev->arb_csr_lock);
283 for (i = 0; i < qp->nb_descriptors; i++)
284 rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);
286 if (qp->op_cookie_pool)
287 rte_mempool_free(qp->op_cookie_pool);
289 rte_free(qp->op_cookies);
296 static void qat_queue_delete(struct qat_queue *queue)
298 const struct rte_memzone *mz;
302 QAT_LOG(DEBUG, "Invalid queue");
305 QAT_LOG(DEBUG, "Free ring %d, memzone: %s",
306 queue->hw_queue_number, queue->memz_name);
308 mz = rte_memzone_lookup(queue->memz_name);
310 /* Write an unused pattern to the queue memory. */
311 memset(queue->base_addr, 0x7F, queue->queue_size);
312 status = rte_memzone_free(mz);
314 QAT_LOG(ERR, "Error %d on freeing queue %s",
315 status, queue->memz_name);
317 QAT_LOG(DEBUG, "queue %s doesn't exist",
323 qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,
324 struct qat_qp_config *qp_conf, uint8_t dir)
328 const struct rte_memzone *qp_mz;
329 struct rte_pci_device *pci_dev = qat_dev->pci_dev;
331 uint16_t desc_size = (dir == ADF_RING_DIR_TX ?
332 qp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);
333 uint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);
335 queue->hw_bundle_number = qp_conf->hw->hw_bundle_num;
336 queue->hw_queue_number = (dir == ADF_RING_DIR_TX ?
337 qp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);
339 if (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
340 QAT_LOG(ERR, "Invalid descriptor size %d", desc_size);
345 * Allocate a memzone for the queue - create a unique name.
347 snprintf(queue->memz_name, sizeof(queue->memz_name),
349 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
350 qp_conf->service_str, "qp_mem",
351 queue->hw_bundle_number, queue->hw_queue_number);
352 qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
355 QAT_LOG(ERR, "Failed to allocate ring memzone");
359 queue->base_addr = (char *)qp_mz->addr;
360 queue->base_phys_addr = qp_mz->iova;
361 if (qat_qp_check_queue_alignment(queue->base_phys_addr,
363 QAT_LOG(ERR, "Invalid alignment on queue create "
365 queue->base_phys_addr);
367 goto queue_create_err;
370 if (adf_verify_queue_size(desc_size, qp_conf->nb_descriptors,
371 &(queue->queue_size)) != 0) {
372 QAT_LOG(ERR, "Invalid num inflights");
374 goto queue_create_err;
377 queue->max_inflights = ADF_MAX_INFLIGHTS(queue->queue_size,
378 ADF_BYTES_TO_MSG_SIZE(desc_size));
379 queue->modulo_mask = (1 << ADF_RING_SIZE_MODULO(queue->queue_size)) - 1;
381 if (queue->max_inflights < 2) {
382 QAT_LOG(ERR, "Invalid num inflights");
384 goto queue_create_err;
388 queue->msg_size = desc_size;
391 * Write an unused pattern to the queue memory.
393 memset(queue->base_addr, 0x7F, queue_size_bytes);
395 queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
398 io_addr = pci_dev->mem_resource[0].addr;
400 WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
401 queue->hw_queue_number, queue_base);
403 QAT_LOG(DEBUG, "RING: Name:%s, size in CSR: %u, in bytes %u,"
404 " nb msgs %u, msg_size %u, max_inflights %u modulo mask %u",
406 queue->queue_size, queue_size_bytes,
407 qp_conf->nb_descriptors, desc_size,
408 queue->max_inflights, queue->modulo_mask);
413 rte_memzone_free(qp_mz);
417 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
418 uint32_t queue_size_bytes)
420 if (((queue_size_bytes - 1) & phys_addr) != 0)
425 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
426 uint32_t *p_queue_size_for_csr)
428 uint8_t i = ADF_MIN_RING_SIZE;
430 for (; i <= ADF_MAX_RING_SIZE; i++)
431 if ((msg_size * msg_num) ==
432 (uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {
433 *p_queue_size_for_csr = i;
436 QAT_LOG(ERR, "Invalid ring size %d", msg_size * msg_num);
440 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
441 rte_spinlock_t *lock)
443 uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +
445 txq->hw_bundle_number);
448 rte_spinlock_lock(lock);
449 value = ADF_CSR_RD(base_addr, arb_csr_offset);
450 value |= (0x01 << txq->hw_queue_number);
451 ADF_CSR_WR(base_addr, arb_csr_offset, value);
452 rte_spinlock_unlock(lock);
455 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
456 rte_spinlock_t *lock)
458 uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +
460 txq->hw_bundle_number);
463 rte_spinlock_lock(lock);
464 value = ADF_CSR_RD(base_addr, arb_csr_offset);
465 value &= ~(0x01 << txq->hw_queue_number);
466 ADF_CSR_WR(base_addr, arb_csr_offset, value);
467 rte_spinlock_unlock(lock);
470 static void adf_configure_queues(struct qat_qp *qp)
472 uint32_t queue_config;
473 struct qat_queue *queue = &qp->tx_q;
475 queue_config = BUILD_RING_CONFIG(queue->queue_size);
477 WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
478 queue->hw_queue_number, queue_config);
482 BUILD_RESP_RING_CONFIG(queue->queue_size,
483 ADF_RING_NEAR_WATERMARK_512,
484 ADF_RING_NEAR_WATERMARK_0);
486 WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
487 queue->hw_queue_number, queue_config);
490 static inline uint32_t adf_modulo(uint32_t data, uint32_t modulo_mask)
492 return data & modulo_mask;
496 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
497 WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
498 q->hw_queue_number, q->tail);
499 q->nb_pending_requests = 0;
500 q->csr_tail = q->tail;
504 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
506 uint32_t old_head, new_head;
509 old_head = q->csr_head;
511 max_head = qp->nb_descriptors * q->msg_size;
513 /* write out free descriptors */
514 void *cur_desc = (uint8_t *)q->base_addr + old_head;
516 if (new_head < old_head) {
517 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
518 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
520 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
522 q->nb_processed_responses = 0;
523 q->csr_head = new_head;
525 /* write current head to CSR */
526 WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
527 q->hw_queue_number, new_head);
531 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
533 register struct qat_queue *queue;
534 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
535 register uint32_t nb_ops_sent = 0;
537 uint16_t nb_ops_possible = nb_ops;
538 register uint8_t *base_addr;
539 register uint32_t tail;
542 if (unlikely(nb_ops == 0))
545 /* read params used a lot in main loop into registers */
546 queue = &(tmp_qp->tx_q);
547 base_addr = (uint8_t *)queue->base_addr;
550 /* Find how many can actually fit on the ring */
551 tmp_qp->inflights16 += nb_ops;
552 overflow = tmp_qp->inflights16 - queue->max_inflights;
554 tmp_qp->inflights16 -= overflow;
555 nb_ops_possible = nb_ops - overflow;
556 if (nb_ops_possible == 0)
560 while (nb_ops_sent != nb_ops_possible) {
561 ret = tmp_qp->build_request(*ops, base_addr + tail,
562 tmp_qp->op_cookies[tail / queue->msg_size],
563 tmp_qp->qat_dev_gen);
565 tmp_qp->stats.enqueue_err_count++;
567 * This message cannot be enqueued,
568 * decrease number of ops that wasn't sent
570 tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
571 if (nb_ops_sent == 0)
576 tail = adf_modulo(tail + queue->msg_size, queue->modulo_mask);
582 tmp_qp->stats.enqueued_count += nb_ops_sent;
583 queue->nb_pending_requests += nb_ops_sent;
584 if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
585 queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
586 txq_write_tail(tmp_qp, queue);
592 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
594 struct qat_queue *rx_queue, *tx_queue;
595 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
597 uint32_t resp_counter = 0;
600 rx_queue = &(tmp_qp->rx_q);
601 tx_queue = &(tmp_qp->tx_q);
602 head = rx_queue->head;
603 resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
605 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
606 resp_counter != nb_ops) {
608 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
609 qat_sym_process_response(ops, resp_msg);
610 else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
611 qat_comp_process_response(ops, resp_msg);
613 head = adf_modulo(head + rx_queue->msg_size,
614 rx_queue->modulo_mask);
616 resp_msg = (uint8_t *)rx_queue->base_addr + head;
620 if (resp_counter > 0) {
621 rx_queue->head = head;
622 tmp_qp->stats.dequeued_count += resp_counter;
623 rx_queue->nb_processed_responses += resp_counter;
624 tmp_qp->inflights16 -= resp_counter;
626 if (rx_queue->nb_processed_responses >
627 QAT_CSR_HEAD_WRITE_THRESH)
628 rxq_free_desc(tmp_qp, rx_queue);
630 /* also check if tail needs to be advanced */
631 if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
632 tx_queue->tail != tx_queue->csr_tail) {
633 txq_write_tail(tmp_qp, tx_queue);
638 __attribute__((weak)) int
639 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)