1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <rte_common.h>
7 #include <rte_malloc.h>
8 #include <rte_memzone.h>
10 #include <rte_bus_pci.h>
11 #include <rte_atomic.h>
12 #include <rte_prefetch.h>
15 #include "qat_device.h"
20 #include "adf_transport_access_macros.h"
23 #define ADF_MAX_DESC 4096
24 #define ADF_MIN_DESC 128
26 #define ADF_ARB_REG_SLOT 0x1000
27 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
29 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
30 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
31 (ADF_ARB_REG_SLOT * index), value)
34 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
35 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
36 /* queue pairs which provide an asymmetric crypto service */
37 [QAT_SERVICE_ASYMMETRIC] = {
39 .service_type = QAT_SERVICE_ASYMMETRIC,
47 .service_type = QAT_SERVICE_ASYMMETRIC,
55 /* queue pairs which provide a symmetric crypto service */
56 [QAT_SERVICE_SYMMETRIC] = {
58 .service_type = QAT_SERVICE_SYMMETRIC,
66 .service_type = QAT_SERVICE_SYMMETRIC,
74 /* queue pairs which provide a compression service */
75 [QAT_SERVICE_COMPRESSION] = {
77 .service_type = QAT_SERVICE_COMPRESSION,
84 .service_type = QAT_SERVICE_COMPRESSION,
95 const struct qat_qp_hw_data qat_gen3_qps[QAT_MAX_SERVICES]
96 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
97 /* queue pairs which provide an asymmetric crypto service */
98 [QAT_SERVICE_ASYMMETRIC] = {
100 .service_type = QAT_SERVICE_ASYMMETRIC,
108 /* queue pairs which provide a symmetric crypto service */
109 [QAT_SERVICE_SYMMETRIC] = {
111 .service_type = QAT_SERVICE_SYMMETRIC,
119 /* queue pairs which provide a compression service */
120 [QAT_SERVICE_COMPRESSION] = {
122 .service_type = QAT_SERVICE_COMPRESSION,
132 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
133 uint32_t queue_size_bytes);
134 static void qat_queue_delete(struct qat_queue *queue);
135 static int qat_queue_create(struct qat_pci_device *qat_dev,
136 struct qat_queue *queue, struct qat_qp_config *, uint8_t dir);
137 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
138 uint32_t *queue_size_for_csr);
139 static void adf_configure_queues(struct qat_qp *queue);
140 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
141 rte_spinlock_t *lock);
142 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
143 rte_spinlock_t *lock);
146 int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
147 enum qat_service_type service)
151 for (i = 0, count = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++)
152 if (qp_hw_data[i].service_type == service)
157 static const struct rte_memzone *
158 queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
161 const struct rte_memzone *mz;
163 mz = rte_memzone_lookup(queue_name);
165 if (((size_t)queue_size <= mz->len) &&
166 ((socket_id == SOCKET_ID_ANY) ||
167 (socket_id == mz->socket_id))) {
168 QAT_LOG(DEBUG, "re-use memzone already "
169 "allocated for %s", queue_name);
173 QAT_LOG(ERR, "Incompatible memzone already "
174 "allocated %s, size %u, socket %d. "
175 "Requested size %u, socket %u",
176 queue_name, (uint32_t)mz->len,
177 mz->socket_id, queue_size, socket_id);
181 QAT_LOG(DEBUG, "Allocate memzone for %s, size %u on socket %u",
182 queue_name, queue_size, socket_id);
183 return rte_memzone_reserve_aligned(queue_name, queue_size,
184 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
187 int qat_qp_setup(struct qat_pci_device *qat_dev,
188 struct qat_qp **qp_addr,
189 uint16_t queue_pair_id,
190 struct qat_qp_config *qat_qp_conf)
194 struct rte_pci_device *pci_dev = qat_dev->pci_dev;
195 char op_cookie_pool_name[RTE_RING_NAMESIZE];
198 QAT_LOG(DEBUG, "Setup qp %u on qat pci device %d gen %d",
199 queue_pair_id, qat_dev->qat_dev_id, qat_dev->qat_dev_gen);
201 if ((qat_qp_conf->nb_descriptors > ADF_MAX_DESC) ||
202 (qat_qp_conf->nb_descriptors < ADF_MIN_DESC)) {
203 QAT_LOG(ERR, "Can't create qp for %u descriptors",
204 qat_qp_conf->nb_descriptors);
208 if (pci_dev->mem_resource[0].addr == NULL) {
209 QAT_LOG(ERR, "Could not find VF config space "
210 "(UIO driver attached?).");
214 /* Allocate the queue pair data structure. */
215 qp = rte_zmalloc_socket("qat PMD qp metadata",
216 sizeof(*qp), RTE_CACHE_LINE_SIZE,
217 qat_qp_conf->socket_id);
219 QAT_LOG(ERR, "Failed to alloc mem for qp struct");
222 qp->nb_descriptors = qat_qp_conf->nb_descriptors;
223 qp->op_cookies = rte_zmalloc_socket("qat PMD op cookie pointer",
224 qat_qp_conf->nb_descriptors * sizeof(*qp->op_cookies),
225 RTE_CACHE_LINE_SIZE, qat_qp_conf->socket_id);
226 if (qp->op_cookies == NULL) {
227 QAT_LOG(ERR, "Failed to alloc mem for cookie");
232 qp->mmap_bar_addr = pci_dev->mem_resource[0].addr;
233 qp->enqueued = qp->dequeued = 0;
235 if (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,
236 ADF_RING_DIR_TX) != 0) {
237 QAT_LOG(ERR, "Tx queue create failed "
238 "queue_pair_id=%u", queue_pair_id);
242 qp->max_inflights = ADF_MAX_INFLIGHTS(qp->tx_q.queue_size,
243 ADF_BYTES_TO_MSG_SIZE(qp->tx_q.msg_size));
245 if (qp->max_inflights < 2) {
246 QAT_LOG(ERR, "Invalid num inflights");
247 qat_queue_delete(&(qp->tx_q));
251 if (qat_queue_create(qat_dev, &(qp->rx_q), qat_qp_conf,
252 ADF_RING_DIR_RX) != 0) {
253 QAT_LOG(ERR, "Rx queue create failed "
254 "queue_pair_id=%hu", queue_pair_id);
255 qat_queue_delete(&(qp->tx_q));
259 adf_configure_queues(qp);
260 adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr,
261 &qat_dev->arb_csr_lock);
263 snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,
264 "%s%d_cookies_%s_qp%hu",
265 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
266 qat_qp_conf->service_str, queue_pair_id);
268 QAT_LOG(DEBUG, "cookiepool: %s", op_cookie_pool_name);
269 qp->op_cookie_pool = rte_mempool_lookup(op_cookie_pool_name);
270 if (qp->op_cookie_pool == NULL)
271 qp->op_cookie_pool = rte_mempool_create(op_cookie_pool_name,
273 qat_qp_conf->cookie_size, 64, 0,
274 NULL, NULL, NULL, NULL,
275 qat_dev->pci_dev->device.numa_node,
277 if (!qp->op_cookie_pool) {
278 QAT_LOG(ERR, "QAT PMD Cannot create"
283 for (i = 0; i < qp->nb_descriptors; i++) {
284 if (rte_mempool_get(qp->op_cookie_pool, &qp->op_cookies[i])) {
285 QAT_LOG(ERR, "QAT PMD Cannot get op_cookie");
288 memset(qp->op_cookies[i], 0, qat_qp_conf->cookie_size);
291 qp->qat_dev_gen = qat_dev->qat_dev_gen;
292 qp->build_request = qat_qp_conf->build_request;
293 qp->service_type = qat_qp_conf->hw->service_type;
294 qp->qat_dev = qat_dev;
296 QAT_LOG(DEBUG, "QP setup complete: id: %d, cookiepool: %s",
297 queue_pair_id, op_cookie_pool_name);
303 if (qp->op_cookie_pool)
304 rte_mempool_free(qp->op_cookie_pool);
305 rte_free(qp->op_cookies);
310 int qat_qp_release(struct qat_qp **qp_addr)
312 struct qat_qp *qp = *qp_addr;
316 QAT_LOG(DEBUG, "qp already freed");
320 QAT_LOG(DEBUG, "Free qp on qat_pci device %d",
321 qp->qat_dev->qat_dev_id);
323 /* Don't free memory if there are still responses to be processed */
324 if ((qp->enqueued - qp->dequeued) == 0) {
325 qat_queue_delete(&(qp->tx_q));
326 qat_queue_delete(&(qp->rx_q));
331 adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr,
332 &qp->qat_dev->arb_csr_lock);
334 for (i = 0; i < qp->nb_descriptors; i++)
335 rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);
337 if (qp->op_cookie_pool)
338 rte_mempool_free(qp->op_cookie_pool);
340 rte_free(qp->op_cookies);
347 static void qat_queue_delete(struct qat_queue *queue)
349 const struct rte_memzone *mz;
353 QAT_LOG(DEBUG, "Invalid queue");
356 QAT_LOG(DEBUG, "Free ring %d, memzone: %s",
357 queue->hw_queue_number, queue->memz_name);
359 mz = rte_memzone_lookup(queue->memz_name);
361 /* Write an unused pattern to the queue memory. */
362 memset(queue->base_addr, 0x7F, queue->queue_size);
363 status = rte_memzone_free(mz);
365 QAT_LOG(ERR, "Error %d on freeing queue %s",
366 status, queue->memz_name);
368 QAT_LOG(DEBUG, "queue %s doesn't exist",
374 qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,
375 struct qat_qp_config *qp_conf, uint8_t dir)
379 const struct rte_memzone *qp_mz;
380 struct rte_pci_device *pci_dev = qat_dev->pci_dev;
382 uint16_t desc_size = (dir == ADF_RING_DIR_TX ?
383 qp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);
384 uint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);
386 queue->hw_bundle_number = qp_conf->hw->hw_bundle_num;
387 queue->hw_queue_number = (dir == ADF_RING_DIR_TX ?
388 qp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);
390 if (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
391 QAT_LOG(ERR, "Invalid descriptor size %d", desc_size);
396 * Allocate a memzone for the queue - create a unique name.
398 snprintf(queue->memz_name, sizeof(queue->memz_name),
400 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
401 qp_conf->service_str, "qp_mem",
402 queue->hw_bundle_number, queue->hw_queue_number);
403 qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
404 qat_dev->pci_dev->device.numa_node);
406 QAT_LOG(ERR, "Failed to allocate ring memzone");
410 queue->base_addr = (char *)qp_mz->addr;
411 queue->base_phys_addr = qp_mz->iova;
412 if (qat_qp_check_queue_alignment(queue->base_phys_addr,
414 QAT_LOG(ERR, "Invalid alignment on queue create "
416 queue->base_phys_addr);
418 goto queue_create_err;
421 if (adf_verify_queue_size(desc_size, qp_conf->nb_descriptors,
422 &(queue->queue_size)) != 0) {
423 QAT_LOG(ERR, "Invalid num inflights");
425 goto queue_create_err;
428 queue->modulo_mask = (1 << ADF_RING_SIZE_MODULO(queue->queue_size)) - 1;
431 queue->msg_size = desc_size;
434 * Write an unused pattern to the queue memory.
436 memset(queue->base_addr, 0x7F, queue_size_bytes);
438 queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
441 io_addr = pci_dev->mem_resource[0].addr;
443 WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
444 queue->hw_queue_number, queue_base);
446 QAT_LOG(DEBUG, "RING: Name:%s, size in CSR: %u, in bytes %u,"
447 " nb msgs %u, msg_size %u, modulo mask %u",
449 queue->queue_size, queue_size_bytes,
450 qp_conf->nb_descriptors, desc_size,
456 rte_memzone_free(qp_mz);
460 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
461 uint32_t queue_size_bytes)
463 if (((queue_size_bytes - 1) & phys_addr) != 0)
468 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
469 uint32_t *p_queue_size_for_csr)
471 uint8_t i = ADF_MIN_RING_SIZE;
473 for (; i <= ADF_MAX_RING_SIZE; i++)
474 if ((msg_size * msg_num) ==
475 (uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {
476 *p_queue_size_for_csr = i;
479 QAT_LOG(ERR, "Invalid ring size %d", msg_size * msg_num);
483 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
484 rte_spinlock_t *lock)
486 uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +
488 txq->hw_bundle_number);
491 rte_spinlock_lock(lock);
492 value = ADF_CSR_RD(base_addr, arb_csr_offset);
493 value |= (0x01 << txq->hw_queue_number);
494 ADF_CSR_WR(base_addr, arb_csr_offset, value);
495 rte_spinlock_unlock(lock);
498 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
499 rte_spinlock_t *lock)
501 uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +
503 txq->hw_bundle_number);
506 rte_spinlock_lock(lock);
507 value = ADF_CSR_RD(base_addr, arb_csr_offset);
508 value &= ~(0x01 << txq->hw_queue_number);
509 ADF_CSR_WR(base_addr, arb_csr_offset, value);
510 rte_spinlock_unlock(lock);
513 static void adf_configure_queues(struct qat_qp *qp)
515 uint32_t queue_config;
516 struct qat_queue *queue = &qp->tx_q;
518 queue_config = BUILD_RING_CONFIG(queue->queue_size);
520 WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
521 queue->hw_queue_number, queue_config);
525 BUILD_RESP_RING_CONFIG(queue->queue_size,
526 ADF_RING_NEAR_WATERMARK_512,
527 ADF_RING_NEAR_WATERMARK_0);
529 WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
530 queue->hw_queue_number, queue_config);
533 static inline uint32_t adf_modulo(uint32_t data, uint32_t modulo_mask)
535 return data & modulo_mask;
539 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
540 WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
541 q->hw_queue_number, q->tail);
542 q->csr_tail = q->tail;
546 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
548 uint32_t old_head, new_head;
551 old_head = q->csr_head;
553 max_head = qp->nb_descriptors * q->msg_size;
555 /* write out free descriptors */
556 void *cur_desc = (uint8_t *)q->base_addr + old_head;
558 if (new_head < old_head) {
559 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
560 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
562 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
564 q->nb_processed_responses = 0;
565 q->csr_head = new_head;
567 /* write current head to CSR */
568 WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
569 q->hw_queue_number, new_head);
573 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
575 register struct qat_queue *queue;
576 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
577 register uint32_t nb_ops_sent = 0;
579 uint16_t nb_ops_possible = nb_ops;
580 register uint8_t *base_addr;
581 register uint32_t tail;
583 if (unlikely(nb_ops == 0))
586 /* read params used a lot in main loop into registers */
587 queue = &(tmp_qp->tx_q);
588 base_addr = (uint8_t *)queue->base_addr;
591 /* Find how many can actually fit on the ring */
593 /* dequeued can only be written by one thread, but it may not
594 * be this thread. As it's 4-byte aligned it will be read
595 * atomically here by any Intel CPU.
596 * enqueued can wrap before dequeued, but cannot
597 * lap it as var size of enq/deq (uint32_t) > var size of
598 * max_inflights (uint16_t). In reality inflights is never
599 * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
600 * On wrapping, the calculation still returns the correct
601 * positive value as all three vars are unsigned.
604 tmp_qp->enqueued - tmp_qp->dequeued;
606 if ((inflights + nb_ops) > tmp_qp->max_inflights) {
607 nb_ops_possible = tmp_qp->max_inflights - inflights;
608 if (nb_ops_possible == 0)
611 /* QAT has plenty of work queued already, so don't waste cycles
612 * enqueueing, wait til the application has gathered a bigger
613 * burst or some completed ops have been dequeued
615 if (tmp_qp->min_enq_burst_threshold && inflights >
616 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
617 tmp_qp->min_enq_burst_threshold) {
618 tmp_qp->stats.threshold_hit_count++;
624 while (nb_ops_sent != nb_ops_possible) {
625 ret = tmp_qp->build_request(*ops, base_addr + tail,
626 tmp_qp->op_cookies[tail / queue->msg_size],
627 tmp_qp->qat_dev_gen);
629 tmp_qp->stats.enqueue_err_count++;
630 /* This message cannot be enqueued */
631 if (nb_ops_sent == 0)
636 tail = adf_modulo(tail + queue->msg_size, queue->modulo_mask);
642 tmp_qp->enqueued += nb_ops_sent;
643 tmp_qp->stats.enqueued_count += nb_ops_sent;
644 txq_write_tail(tmp_qp, queue);
649 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
651 struct qat_queue *rx_queue;
652 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
654 uint32_t resp_counter = 0;
657 rx_queue = &(tmp_qp->rx_q);
658 head = rx_queue->head;
659 resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
661 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
662 resp_counter != nb_ops) {
664 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
665 qat_sym_process_response(ops, resp_msg);
666 else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
667 qat_comp_process_response(ops, resp_msg,
668 tmp_qp->op_cookies[head / rx_queue->msg_size],
669 &tmp_qp->stats.dequeue_err_count);
670 else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC) {
671 #ifdef BUILD_QAT_ASYM
672 qat_asym_process_response(ops, resp_msg,
673 tmp_qp->op_cookies[head / rx_queue->msg_size]);
677 head = adf_modulo(head + rx_queue->msg_size,
678 rx_queue->modulo_mask);
680 resp_msg = (uint8_t *)rx_queue->base_addr + head;
684 if (resp_counter > 0) {
685 rx_queue->head = head;
686 tmp_qp->dequeued += resp_counter;
687 tmp_qp->stats.dequeued_count += resp_counter;
688 rx_queue->nb_processed_responses += resp_counter;
690 if (rx_queue->nb_processed_responses >
691 QAT_CSR_HEAD_WRITE_THRESH)
692 rxq_free_desc(tmp_qp, rx_queue);
699 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
700 void *op_cookie __rte_unused,
701 uint64_t *dequeue_err_count __rte_unused)