1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <rte_common.h>
6 #include <rte_cycles.h>
8 #include <rte_malloc.h>
9 #include <rte_memzone.h>
11 #include <rte_bus_pci.h>
12 #include <rte_atomic.h>
13 #include <rte_prefetch.h>
16 #include "qat_device.h"
22 #define QAT_CQ_MAX_DEQ_RETRIES 10
24 #define ADF_MAX_DESC 4096
25 #define ADF_MIN_DESC 128
27 struct qat_qp_hw_spec_funcs*
28 qat_qp_hw_spec[QAT_N_GENS];
30 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
31 uint32_t queue_size_bytes);
32 static void qat_queue_delete(struct qat_queue *queue);
33 static int qat_queue_create(struct qat_pci_device *qat_dev,
34 struct qat_queue *queue, struct qat_qp_config *, uint8_t dir);
35 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
36 uint32_t *queue_size_for_csr);
37 static int adf_configure_queues(struct qat_qp *queue,
38 enum qat_device_gen qat_dev_gen);
39 static int adf_queue_arb_enable(struct qat_pci_device *qat_dev,
40 struct qat_queue *txq, void *base_addr, rte_spinlock_t *lock);
41 static int adf_queue_arb_disable(enum qat_device_gen qat_dev_gen,
42 struct qat_queue *txq, void *base_addr, rte_spinlock_t *lock);
43 static int qat_qp_build_ring_base(struct qat_pci_device *qat_dev,
44 void *io_addr, struct qat_queue *queue);
45 static const struct rte_memzone *queue_dma_zone_reserve(const char *queue_name,
46 uint32_t queue_size, int socket_id);
47 static int qat_qp_csr_setup(struct qat_pci_device *qat_dev, void *io_addr,
51 qat_qp_setup(struct qat_pci_device *qat_dev,
52 struct qat_qp **qp_addr,
53 uint16_t queue_pair_id,
54 struct qat_qp_config *qat_qp_conf)
56 struct qat_qp *qp = NULL;
57 struct rte_pci_device *pci_dev =
58 qat_pci_devs[qat_dev->qat_dev_id].pci_dev;
59 char op_cookie_pool_name[RTE_RING_NAMESIZE];
60 struct qat_dev_hw_spec_funcs *ops_hw =
61 qat_dev_hw_spec[qat_dev->qat_dev_gen];
65 QAT_LOG(DEBUG, "Setup qp %u on qat pci device %d gen %d",
66 queue_pair_id, qat_dev->qat_dev_id, qat_dev->qat_dev_gen);
68 if ((qat_qp_conf->nb_descriptors > ADF_MAX_DESC) ||
69 (qat_qp_conf->nb_descriptors < ADF_MIN_DESC)) {
70 QAT_LOG(ERR, "Can't create qp for %u descriptors",
71 qat_qp_conf->nb_descriptors);
75 if (ops_hw->qat_dev_get_transport_bar == NULL) {
77 "QAT Internal Error: qat_dev_get_transport_bar not set for gen %d",
78 qat_dev->qat_dev_gen);
82 io_addr = ops_hw->qat_dev_get_transport_bar(pci_dev)->addr;
83 if (io_addr == NULL) {
84 QAT_LOG(ERR, "Could not find VF config space "
85 "(UIO driver attached?).");
89 /* Allocate the queue pair data structure. */
90 qp = rte_zmalloc_socket("qat PMD qp metadata",
91 sizeof(*qp), RTE_CACHE_LINE_SIZE,
92 qat_qp_conf->socket_id);
94 QAT_LOG(ERR, "Failed to alloc mem for qp struct");
97 qp->nb_descriptors = qat_qp_conf->nb_descriptors;
98 qp->op_cookies = rte_zmalloc_socket("qat PMD op cookie pointer",
99 qat_qp_conf->nb_descriptors * sizeof(*qp->op_cookies),
100 RTE_CACHE_LINE_SIZE, qat_qp_conf->socket_id);
101 if (qp->op_cookies == NULL) {
102 QAT_LOG(ERR, "Failed to alloc mem for cookie");
107 qp->mmap_bar_addr = io_addr;
108 qp->enqueued = qp->dequeued = 0;
110 if (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,
111 ADF_RING_DIR_TX) != 0) {
112 QAT_LOG(ERR, "Tx queue create failed "
113 "queue_pair_id=%u", queue_pair_id);
117 qp->max_inflights = ADF_MAX_INFLIGHTS(qp->tx_q.queue_size,
118 ADF_BYTES_TO_MSG_SIZE(qp->tx_q.msg_size));
120 if (qp->max_inflights < 2) {
121 QAT_LOG(ERR, "Invalid num inflights");
122 qat_queue_delete(&(qp->tx_q));
126 if (qat_queue_create(qat_dev, &(qp->rx_q), qat_qp_conf,
127 ADF_RING_DIR_RX) != 0) {
128 QAT_LOG(ERR, "Rx queue create failed "
129 "queue_pair_id=%hu", queue_pair_id);
130 qat_queue_delete(&(qp->tx_q));
134 snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,
135 "%s%d_cookies_%s_qp%hu",
136 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
137 qat_qp_conf->service_str, queue_pair_id);
139 QAT_LOG(DEBUG, "cookiepool: %s", op_cookie_pool_name);
140 qp->op_cookie_pool = rte_mempool_lookup(op_cookie_pool_name);
141 if (qp->op_cookie_pool == NULL)
142 qp->op_cookie_pool = rte_mempool_create(op_cookie_pool_name,
144 qat_qp_conf->cookie_size, 64, 0,
145 NULL, NULL, NULL, NULL,
146 pci_dev->device.numa_node,
148 if (!qp->op_cookie_pool) {
149 QAT_LOG(ERR, "QAT PMD Cannot create"
151 qat_queue_delete(&(qp->tx_q));
152 qat_queue_delete(&(qp->rx_q));
156 for (i = 0; i < qp->nb_descriptors; i++) {
157 if (rte_mempool_get(qp->op_cookie_pool, &qp->op_cookies[i])) {
158 QAT_LOG(ERR, "QAT PMD Cannot get op_cookie");
161 memset(qp->op_cookies[i], 0, qat_qp_conf->cookie_size);
164 qp->qat_dev_gen = qat_dev->qat_dev_gen;
165 qp->service_type = qat_qp_conf->hw->service_type;
166 qp->qat_dev = qat_dev;
168 QAT_LOG(DEBUG, "QP setup complete: id: %d, cookiepool: %s",
169 queue_pair_id, op_cookie_pool_name);
171 qat_qp_csr_setup(qat_dev, io_addr, qp);
178 if (qp->op_cookie_pool)
179 rte_mempool_free(qp->op_cookie_pool);
182 rte_free(qp->op_cookies);
191 qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,
192 struct qat_qp_config *qp_conf, uint8_t dir)
194 const struct rte_memzone *qp_mz;
195 struct rte_pci_device *pci_dev =
196 qat_pci_devs[qat_dev->qat_dev_id].pci_dev;
198 uint16_t desc_size = (dir == ADF_RING_DIR_TX ?
199 qp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);
200 uint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);
202 queue->hw_bundle_number = qp_conf->hw->hw_bundle_num;
203 queue->hw_queue_number = (dir == ADF_RING_DIR_TX ?
204 qp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);
206 if (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
207 QAT_LOG(ERR, "Invalid descriptor size %d", desc_size);
212 * Allocate a memzone for the queue - create a unique name.
214 snprintf(queue->memz_name, sizeof(queue->memz_name),
216 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
217 qp_conf->service_str, "qp_mem",
218 queue->hw_bundle_number, queue->hw_queue_number);
219 qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
220 pci_dev->device.numa_node);
222 QAT_LOG(ERR, "Failed to allocate ring memzone");
226 queue->base_addr = (char *)qp_mz->addr;
227 queue->base_phys_addr = qp_mz->iova;
228 if (qat_qp_check_queue_alignment(queue->base_phys_addr,
230 QAT_LOG(ERR, "Invalid alignment on queue create "
232 queue->base_phys_addr);
234 goto queue_create_err;
237 if (adf_verify_queue_size(desc_size, qp_conf->nb_descriptors,
238 &(queue->queue_size)) != 0) {
239 QAT_LOG(ERR, "Invalid num inflights");
241 goto queue_create_err;
244 queue->modulo_mask = (1 << ADF_RING_SIZE_MODULO(queue->queue_size)) - 1;
247 queue->msg_size = desc_size;
249 /* For fast calculation of cookie index, relies on msg_size being 2^n */
250 queue->trailz = __builtin_ctz(desc_size);
253 * Write an unused pattern to the queue memory.
255 memset(queue->base_addr, 0x7F, queue_size_bytes);
257 QAT_LOG(DEBUG, "RING: Name:%s, size in CSR: %u, in bytes %u,"
258 " nb msgs %u, msg_size %u, modulo mask %u",
260 queue->queue_size, queue_size_bytes,
261 qp_conf->nb_descriptors, desc_size,
267 rte_memzone_free(qp_mz);
271 static const struct rte_memzone *
272 queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
275 const struct rte_memzone *mz;
277 mz = rte_memzone_lookup(queue_name);
279 if (((size_t)queue_size <= mz->len) &&
280 ((socket_id == SOCKET_ID_ANY) ||
281 (socket_id == mz->socket_id))) {
282 QAT_LOG(DEBUG, "re-use memzone already "
283 "allocated for %s", queue_name);
287 QAT_LOG(ERR, "Incompatible memzone already "
288 "allocated %s, size %u, socket %d. "
289 "Requested size %u, socket %u",
290 queue_name, (uint32_t)mz->len,
291 mz->socket_id, queue_size, socket_id);
295 QAT_LOG(DEBUG, "Allocate memzone for %s, size %u on socket %u",
296 queue_name, queue_size, socket_id);
297 return rte_memzone_reserve_aligned(queue_name, queue_size,
298 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
302 qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr)
305 struct qat_qp *qp = *qp_addr;
309 QAT_LOG(DEBUG, "qp already freed");
313 QAT_LOG(DEBUG, "Free qp on qat_pci device %d",
314 qp->qat_dev->qat_dev_id);
316 /* Don't free memory if there are still responses to be processed */
317 if ((qp->enqueued - qp->dequeued) == 0) {
318 qat_queue_delete(&(qp->tx_q));
319 qat_queue_delete(&(qp->rx_q));
324 ret = adf_queue_arb_disable(qat_dev_gen, &(qp->tx_q),
325 qp->mmap_bar_addr, &qp->qat_dev->arb_csr_lock);
329 for (i = 0; i < qp->nb_descriptors; i++)
330 rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);
332 if (qp->op_cookie_pool)
333 rte_mempool_free(qp->op_cookie_pool);
335 rte_free(qp->op_cookies);
343 qat_queue_delete(struct qat_queue *queue)
345 const struct rte_memzone *mz;
349 QAT_LOG(DEBUG, "Invalid queue");
352 QAT_LOG(DEBUG, "Free ring %d, memzone: %s",
353 queue->hw_queue_number, queue->memz_name);
355 mz = rte_memzone_lookup(queue->memz_name);
357 /* Write an unused pattern to the queue memory. */
358 memset(queue->base_addr, 0x7F, queue->queue_size);
359 status = rte_memzone_free(mz);
361 QAT_LOG(ERR, "Error %d on freeing queue %s",
362 status, queue->memz_name);
364 QAT_LOG(DEBUG, "queue %s doesn't exist",
369 static int __rte_unused
370 adf_queue_arb_enable(struct qat_pci_device *qat_dev, struct qat_queue *txq,
371 void *base_addr, rte_spinlock_t *lock)
373 struct qat_qp_hw_spec_funcs *ops =
374 qat_qp_hw_spec[qat_dev->qat_dev_gen];
376 RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_arb_enable,
378 ops->qat_qp_adf_arb_enable(txq, base_addr, lock);
383 adf_queue_arb_disable(enum qat_device_gen qat_dev_gen, struct qat_queue *txq,
384 void *base_addr, rte_spinlock_t *lock)
386 struct qat_qp_hw_spec_funcs *ops =
387 qat_qp_hw_spec[qat_dev_gen];
389 RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_arb_disable,
391 ops->qat_qp_adf_arb_disable(txq, base_addr, lock);
395 static int __rte_unused
396 qat_qp_build_ring_base(struct qat_pci_device *qat_dev, void *io_addr,
397 struct qat_queue *queue)
399 struct qat_qp_hw_spec_funcs *ops =
400 qat_qp_hw_spec[qat_dev->qat_dev_gen];
402 RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_build_ring_base,
404 ops->qat_qp_build_ring_base(io_addr, queue);
409 qat_qps_per_service(struct qat_pci_device *qat_dev,
410 enum qat_service_type service)
412 struct qat_qp_hw_spec_funcs *ops =
413 qat_qp_hw_spec[qat_dev->qat_dev_gen];
415 RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_rings_per_service,
417 return ops->qat_qp_rings_per_service(qat_dev, service);
420 const struct qat_qp_hw_data *
421 qat_qp_get_hw_data(struct qat_pci_device *qat_dev,
422 enum qat_service_type service, uint16_t qp_id)
424 struct qat_qp_hw_spec_funcs *ops =
425 qat_qp_hw_spec[qat_dev->qat_dev_gen];
427 RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_get_hw_data, NULL);
428 return ops->qat_qp_get_hw_data(qat_dev, service, qp_id);
432 qat_read_qp_config(struct qat_pci_device *qat_dev)
434 struct qat_dev_hw_spec_funcs *ops_hw =
435 qat_dev_hw_spec[qat_dev->qat_dev_gen];
437 RTE_FUNC_PTR_OR_ERR_RET(ops_hw->qat_dev_read_config,
439 return ops_hw->qat_dev_read_config(qat_dev);
442 static int __rte_unused
443 adf_configure_queues(struct qat_qp *qp, enum qat_device_gen qat_dev_gen)
445 struct qat_qp_hw_spec_funcs *ops =
446 qat_qp_hw_spec[qat_dev_gen];
448 RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_configure_queues,
450 ops->qat_qp_adf_configure_queues(qp);
455 txq_write_tail(enum qat_device_gen qat_dev_gen,
456 struct qat_qp *qp, struct qat_queue *q)
458 struct qat_qp_hw_spec_funcs *ops =
459 qat_qp_hw_spec[qat_dev_gen];
462 * Pointer check should be done during
465 ops->qat_qp_csr_write_tail(qp, q);
469 qat_qp_csr_write_head(enum qat_device_gen qat_dev_gen, struct qat_qp *qp,
470 struct qat_queue *q, uint32_t new_head)
472 struct qat_qp_hw_spec_funcs *ops =
473 qat_qp_hw_spec[qat_dev_gen];
476 * Pointer check should be done during
479 ops->qat_qp_csr_write_head(qp, q, new_head);
483 qat_qp_csr_setup(struct qat_pci_device *qat_dev,
484 void *io_addr, struct qat_qp *qp)
486 struct qat_qp_hw_spec_funcs *ops =
487 qat_qp_hw_spec[qat_dev->qat_dev_gen];
489 RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_csr_setup,
491 ops->qat_qp_csr_setup(qat_dev, io_addr, qp);
497 void rxq_free_desc(enum qat_device_gen qat_dev_gen, struct qat_qp *qp,
500 uint32_t old_head, new_head;
503 old_head = q->csr_head;
505 max_head = qp->nb_descriptors * q->msg_size;
507 /* write out free descriptors */
508 void *cur_desc = (uint8_t *)q->base_addr + old_head;
510 if (new_head < old_head) {
511 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
512 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
514 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
516 q->nb_processed_responses = 0;
517 q->csr_head = new_head;
519 qat_qp_csr_write_head(qat_dev_gen, qp, q, new_head);
523 qat_qp_check_queue_alignment(uint64_t phys_addr, uint32_t queue_size_bytes)
525 if (((queue_size_bytes - 1) & phys_addr) != 0)
531 adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
532 uint32_t *p_queue_size_for_csr)
534 uint8_t i = ADF_MIN_RING_SIZE;
536 for (; i <= ADF_MAX_RING_SIZE; i++)
537 if ((msg_size * msg_num) ==
538 (uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {
539 *p_queue_size_for_csr = i;
542 QAT_LOG(ERR, "Invalid ring size %d", msg_size * msg_num);
546 static inline uint32_t
547 adf_modulo(uint32_t data, uint32_t modulo_mask)
549 return data & modulo_mask;
553 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
555 register struct qat_queue *queue;
556 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
557 register uint32_t nb_ops_sent = 0;
558 register int ret = -1;
559 uint16_t nb_ops_possible = nb_ops;
560 register uint8_t *base_addr;
561 register uint32_t tail;
563 if (unlikely(nb_ops == 0))
566 /* read params used a lot in main loop into registers */
567 queue = &(tmp_qp->tx_q);
568 base_addr = (uint8_t *)queue->base_addr;
571 /* Find how many can actually fit on the ring */
573 /* dequeued can only be written by one thread, but it may not
574 * be this thread. As it's 4-byte aligned it will be read
575 * atomically here by any Intel CPU.
576 * enqueued can wrap before dequeued, but cannot
577 * lap it as var size of enq/deq (uint32_t) > var size of
578 * max_inflights (uint16_t). In reality inflights is never
579 * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
580 * On wrapping, the calculation still returns the correct
581 * positive value as all three vars are unsigned.
584 tmp_qp->enqueued - tmp_qp->dequeued;
586 if ((inflights + nb_ops) > tmp_qp->max_inflights) {
587 nb_ops_possible = tmp_qp->max_inflights - inflights;
588 if (nb_ops_possible == 0)
591 /* QAT has plenty of work queued already, so don't waste cycles
592 * enqueueing, wait til the application has gathered a bigger
593 * burst or some completed ops have been dequeued
595 if (tmp_qp->min_enq_burst_threshold && inflights >
596 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
597 tmp_qp->min_enq_burst_threshold) {
598 tmp_qp->stats.threshold_hit_count++;
604 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
605 qat_sym_preprocess_requests(ops, nb_ops_possible);
608 while (nb_ops_sent != nb_ops_possible) {
609 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC) {
611 ret = qat_sym_build_request(*ops, base_addr + tail,
612 tmp_qp->op_cookies[tail >> queue->trailz],
613 tmp_qp->qat_dev_gen);
615 } else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION) {
616 ret = qat_comp_build_request(*ops, base_addr + tail,
617 tmp_qp->op_cookies[tail >> queue->trailz],
618 tmp_qp->qat_dev_gen);
619 } else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC) {
620 #ifdef BUILD_QAT_ASYM
621 ret = qat_asym_build_request(*ops, base_addr + tail,
622 tmp_qp->op_cookies[tail >> queue->trailz],
623 tmp_qp->qat_dev_gen);
627 tmp_qp->stats.enqueue_err_count++;
628 /* This message cannot be enqueued */
629 if (nb_ops_sent == 0)
634 tail = adf_modulo(tail + queue->msg_size, queue->modulo_mask);
640 tmp_qp->enqueued += nb_ops_sent;
641 tmp_qp->stats.enqueued_count += nb_ops_sent;
642 txq_write_tail(tmp_qp->qat_dev_gen, tmp_qp, queue);
646 /* Use this for compression only - but keep consistent with above common
647 * function as much as possible.
650 qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops)
652 register struct qat_queue *queue;
653 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
654 register uint32_t nb_ops_sent = 0;
655 register int nb_desc_to_build;
656 uint16_t nb_ops_possible = nb_ops;
657 register uint8_t *base_addr;
658 register uint32_t tail;
660 int descriptors_built, total_descriptors_built = 0;
661 int nb_remaining_descriptors;
664 if (unlikely(nb_ops == 0))
667 /* read params used a lot in main loop into registers */
668 queue = &(tmp_qp->tx_q);
669 base_addr = (uint8_t *)queue->base_addr;
672 /* Find how many can actually fit on the ring */
674 /* dequeued can only be written by one thread, but it may not
675 * be this thread. As it's 4-byte aligned it will be read
676 * atomically here by any Intel CPU.
677 * enqueued can wrap before dequeued, but cannot
678 * lap it as var size of enq/deq (uint32_t) > var size of
679 * max_inflights (uint16_t). In reality inflights is never
680 * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
681 * On wrapping, the calculation still returns the correct
682 * positive value as all three vars are unsigned.
685 tmp_qp->enqueued - tmp_qp->dequeued;
687 /* Find how many can actually fit on the ring */
688 overflow = (inflights + nb_ops) - tmp_qp->max_inflights;
690 nb_ops_possible = nb_ops - overflow;
691 if (nb_ops_possible == 0)
695 /* QAT has plenty of work queued already, so don't waste cycles
696 * enqueueing, wait til the application has gathered a bigger
697 * burst or some completed ops have been dequeued
699 if (tmp_qp->min_enq_burst_threshold && inflights >
700 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
701 tmp_qp->min_enq_burst_threshold) {
702 tmp_qp->stats.threshold_hit_count++;
707 /* At this point nb_ops_possible is assuming a 1:1 mapping
708 * between ops and descriptors.
709 * Fewer may be sent if some ops have to be split.
710 * nb_ops_possible is <= burst size.
711 * Find out how many spaces are actually available on the qp in case
714 nb_remaining_descriptors = nb_ops_possible
715 + ((overflow >= 0) ? 0 : overflow * (-1));
716 QAT_DP_LOG(DEBUG, "Nb ops requested %d, nb descriptors remaining %d",
717 nb_ops, nb_remaining_descriptors);
719 while (nb_ops_sent != nb_ops_possible &&
720 nb_remaining_descriptors > 0) {
721 struct qat_comp_op_cookie *cookie =
722 tmp_qp->op_cookies[tail >> queue->trailz];
724 descriptors_built = 0;
726 QAT_DP_LOG(DEBUG, "--- data length: %u",
727 ((struct rte_comp_op *)*ops)->src.length);
729 nb_desc_to_build = qat_comp_build_request(*ops,
730 base_addr + tail, cookie, tmp_qp->qat_dev_gen);
731 QAT_DP_LOG(DEBUG, "%d descriptors built, %d remaining, "
732 "%d ops sent, %d descriptors needed",
733 total_descriptors_built, nb_remaining_descriptors,
734 nb_ops_sent, nb_desc_to_build);
736 if (unlikely(nb_desc_to_build < 0)) {
737 /* this message cannot be enqueued */
738 tmp_qp->stats.enqueue_err_count++;
739 if (nb_ops_sent == 0)
742 } else if (unlikely(nb_desc_to_build > 1)) {
743 /* this op is too big and must be split - get more
744 * descriptors and retry
747 QAT_DP_LOG(DEBUG, "Build %d descriptors for this op",
750 nb_remaining_descriptors -= nb_desc_to_build;
751 if (nb_remaining_descriptors >= 0) {
752 /* There are enough remaining descriptors
755 int ret2 = qat_comp_build_multiple_requests(
759 if (unlikely(ret2 < 1)) {
761 "Failed to build (%d) descriptors, status %d",
762 nb_desc_to_build, ret2);
764 qat_comp_free_split_op_memzones(cookie,
765 nb_desc_to_build - 1);
767 tmp_qp->stats.enqueue_err_count++;
769 /* This message cannot be enqueued */
770 if (nb_ops_sent == 0)
774 descriptors_built = ret2;
775 total_descriptors_built +=
777 nb_remaining_descriptors -=
780 "Multiple descriptors (%d) built ok",
784 QAT_DP_LOG(ERR, "For the current op, number of requested descriptors (%d) "
785 "exceeds number of available descriptors (%d)",
787 nb_remaining_descriptors +
790 qat_comp_free_split_op_memzones(cookie,
791 nb_desc_to_build - 1);
793 /* Not enough extra descriptors */
794 if (nb_ops_sent == 0)
799 descriptors_built = 1;
800 total_descriptors_built++;
801 nb_remaining_descriptors--;
802 QAT_DP_LOG(DEBUG, "Single descriptor built ok");
805 tail = adf_modulo(tail + (queue->msg_size * descriptors_built),
813 tmp_qp->enqueued += total_descriptors_built;
814 tmp_qp->stats.enqueued_count += nb_ops_sent;
815 txq_write_tail(tmp_qp->qat_dev_gen, tmp_qp, queue);
820 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
822 struct qat_queue *rx_queue;
823 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
825 uint32_t op_resp_counter = 0, fw_resp_counter = 0;
829 rx_queue = &(tmp_qp->rx_q);
830 head = rx_queue->head;
831 resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
833 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
834 op_resp_counter != nb_ops) {
838 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
839 qat_sym_process_response(ops, resp_msg,
840 tmp_qp->op_cookies[head >> rx_queue->trailz]);
841 else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
842 nb_fw_responses = qat_comp_process_response(
844 tmp_qp->op_cookies[head >> rx_queue->trailz],
845 &tmp_qp->stats.dequeue_err_count);
846 #ifdef BUILD_QAT_ASYM
847 else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC)
848 qat_asym_process_response(ops, resp_msg,
849 tmp_qp->op_cookies[head >> rx_queue->trailz]);
852 head = adf_modulo(head + rx_queue->msg_size,
853 rx_queue->modulo_mask);
855 resp_msg = (uint8_t *)rx_queue->base_addr + head;
857 if (nb_fw_responses) {
858 /* only move on to next op if one was ready to return
865 /* A compression op may be broken up into multiple fw requests.
866 * Only count fw responses as complete once ALL the responses
867 * associated with an op have been processed, as the cookie
868 * data from the first response must be available until
869 * finished with all firmware responses.
871 fw_resp_counter += nb_fw_responses;
873 rx_queue->nb_processed_responses++;
876 tmp_qp->dequeued += fw_resp_counter;
877 tmp_qp->stats.dequeued_count += op_resp_counter;
879 rx_queue->head = head;
880 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
881 rxq_free_desc(tmp_qp->qat_dev_gen, tmp_qp, rx_queue);
883 QAT_DP_LOG(DEBUG, "Dequeue burst return: %u, QAT responses: %u",
884 op_resp_counter, fw_resp_counter);
886 return op_resp_counter;
889 /* This is almost same as dequeue_op_burst, without the atomic, without stats
890 * and without the op. Dequeues one response.
893 qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
897 struct qat_queue *queue = &(qp->rx_q);
898 struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
899 ((uint8_t *)queue->base_addr + queue->head);
901 while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
902 *(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
903 /* loop waiting for response until we reach the timeout */
907 if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
908 /* response received */
911 /* check status flag */
912 if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
913 resp_msg->comn_hdr.comn_status) ==
914 ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
916 memcpy(out_data, resp_msg, queue->msg_size);
918 memset(out_data, 0, queue->msg_size);
921 queue->head = adf_modulo(queue->head + queue->msg_size,
923 rxq_free_desc(qp->qat_dev_gen, qp, queue);
929 /* Sends a NULL message and extracts QAT fw version from the response.
930 * Used to determine detailed capabilities based on the fw version number.
931 * This assumes that there are no inflight messages, i.e. assumes there's space
932 * on the qp, one message is sent and only one response collected.
933 * Returns fw version number or 0 for unknown version or a negative error code.
936 qat_cq_get_fw_version(struct qat_qp *qp)
938 struct qat_queue *queue = &(qp->tx_q);
939 uint8_t *base_addr = (uint8_t *)queue->base_addr;
940 struct icp_qat_fw_comn_req null_msg;
941 struct icp_qat_fw_comn_resp response;
943 /* prepare the NULL request */
944 memset(&null_msg, 0, sizeof(null_msg));
945 null_msg.comn_hdr.hdr_flags =
946 ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
947 null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
948 null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
950 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
951 QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
954 /* send the NULL request */
955 memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
956 queue->tail = adf_modulo(queue->tail + queue->msg_size,
958 txq_write_tail(qp->qat_dev_gen, qp, queue);
960 /* receive a response */
961 if (qat_cq_dequeue_response(qp, &response)) {
963 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
964 QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
967 /* if LW0 bit 24 is set - then the fw version was returned */
968 if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
969 ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
970 ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
971 return response.resrvd[0]; /* return LW4 */
973 return 0; /* not set - we don't know fw version */
976 QAT_LOG(ERR, "No response received");
981 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
982 void *op_cookie __rte_unused,
983 uint64_t *dequeue_err_count __rte_unused)