drivers/common/qat/qat_qp.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #include <rte_common.h>
   6 #include <rte_cycles.h>
   7 #include <rte_dev.h>
   8 #include <rte_malloc.h>
   9 #include <rte_memzone.h>
  10 #include <rte_pci.h>
  11 #include <rte_bus_pci.h>
  12 #include <rte_atomic.h>
  13 #include <rte_prefetch.h>
  14
  15 #include "qat_logs.h"
  16 #include "qat_device.h"
  17 #include "qat_qp.h"
  18 #include "qat_sym.h"
  19 #include "qat_asym.h"
  20 #include "qat_comp.h"
  21
  22 #define QAT_CQ_MAX_DEQ_RETRIES 10
  23
  24 #define ADF_MAX_DESC                            4096
  25 #define ADF_MIN_DESC                            128
  26
  27 struct qat_qp_hw_spec_funcs*
  28         qat_qp_hw_spec[QAT_N_GENS];
  29
  30 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
  31         uint32_t queue_size_bytes);
  32 static void qat_queue_delete(struct qat_queue *queue);
  33 static int qat_queue_create(struct qat_pci_device *qat_dev,
  34         struct qat_queue *queue, struct qat_qp_config *, uint8_t dir);
  35 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
  36         uint32_t *queue_size_for_csr);
  37 static int adf_configure_queues(struct qat_qp *queue,
  38         enum qat_device_gen qat_dev_gen);
  39 static int adf_queue_arb_enable(struct qat_pci_device *qat_dev,
  40         struct qat_queue *txq, void *base_addr, rte_spinlock_t *lock);
  41 static int adf_queue_arb_disable(enum qat_device_gen qat_dev_gen,
  42         struct qat_queue *txq, void *base_addr, rte_spinlock_t *lock);
  43 static int qat_qp_build_ring_base(struct qat_pci_device *qat_dev,
  44         void *io_addr, struct qat_queue *queue);
  45 static const struct rte_memzone *queue_dma_zone_reserve(const char *queue_name,
  46         uint32_t queue_size, int socket_id);
  47 static int qat_qp_csr_setup(struct qat_pci_device *qat_dev, void *io_addr,
  48         struct qat_qp *qp);
  49
  50 int
  51 qat_qp_setup(struct qat_pci_device *qat_dev,
  52                 struct qat_qp **qp_addr,
  53                 uint16_t queue_pair_id,
  54                 struct qat_qp_config *qat_qp_conf)
  55 {
  56         struct qat_qp *qp = NULL;
  57         struct rte_pci_device *pci_dev =
  58                         qat_pci_devs[qat_dev->qat_dev_id].pci_dev;
  59         char op_cookie_pool_name[RTE_RING_NAMESIZE];
  60         struct qat_dev_hw_spec_funcs *ops_hw =
  61                 qat_dev_hw_spec[qat_dev->qat_dev_gen];
  62         void *io_addr;
  63         uint32_t i;
  64
  65         QAT_LOG(DEBUG, "Setup qp %u on qat pci device %d gen %d",
  66                 queue_pair_id, qat_dev->qat_dev_id, qat_dev->qat_dev_gen);
  67
  68         if ((qat_qp_conf->nb_descriptors > ADF_MAX_DESC) ||
  69                 (qat_qp_conf->nb_descriptors < ADF_MIN_DESC)) {
  70                 QAT_LOG(ERR, "Can't create qp for %u descriptors",
  71                                 qat_qp_conf->nb_descriptors);
  72                 return -EINVAL;
  73         }
  74
  75         if (ops_hw->qat_dev_get_transport_bar == NULL)  {
  76                 QAT_LOG(ERR,
  77                         "QAT Internal Error: qat_dev_get_transport_bar not set for gen %d",
  78                         qat_dev->qat_dev_gen);
  79                 goto create_err;
  80         }
  81
  82         io_addr = ops_hw->qat_dev_get_transport_bar(pci_dev)->addr;
  83         if (io_addr == NULL) {
  84                 QAT_LOG(ERR, "Could not find VF config space "
  85                                 "(UIO driver attached?).");
  86                 return -EINVAL;
  87         }
  88
  89         /* Allocate the queue pair data structure. */
  90         qp = rte_zmalloc_socket("qat PMD qp metadata",
  91                                 sizeof(*qp), RTE_CACHE_LINE_SIZE,
  92                                 qat_qp_conf->socket_id);
  93         if (qp == NULL) {
  94                 QAT_LOG(ERR, "Failed to alloc mem for qp struct");
  95                 return -ENOMEM;
  96         }
  97         qp->nb_descriptors = qat_qp_conf->nb_descriptors;
  98         qp->op_cookies = rte_zmalloc_socket("qat PMD op cookie pointer",
  99                         qat_qp_conf->nb_descriptors * sizeof(*qp->op_cookies),
 100                         RTE_CACHE_LINE_SIZE, qat_qp_conf->socket_id);
 101         if (qp->op_cookies == NULL) {
 102                 QAT_LOG(ERR, "Failed to alloc mem for cookie");
 103                 rte_free(qp);
 104                 return -ENOMEM;
 105         }
 106
 107         qp->mmap_bar_addr = io_addr;
 108         qp->enqueued = qp->dequeued = 0;
 109
 110         if (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,
 111                                         ADF_RING_DIR_TX) != 0) {
 112                 QAT_LOG(ERR, "Tx queue create failed "
 113                                 "queue_pair_id=%u", queue_pair_id);
 114                 goto create_err;
 115         }
 116
 117         qp->max_inflights = ADF_MAX_INFLIGHTS(qp->tx_q.queue_size,
 118                                 ADF_BYTES_TO_MSG_SIZE(qp->tx_q.msg_size));
 119
 120         if (qp->max_inflights < 2) {
 121                 QAT_LOG(ERR, "Invalid num inflights");
 122                 qat_queue_delete(&(qp->tx_q));
 123                 goto create_err;
 124         }
 125
 126         if (qat_queue_create(qat_dev, &(qp->rx_q), qat_qp_conf,
 127                                         ADF_RING_DIR_RX) != 0) {
 128                 QAT_LOG(ERR, "Rx queue create failed "
 129                                 "queue_pair_id=%hu", queue_pair_id);
 130                 qat_queue_delete(&(qp->tx_q));
 131                 goto create_err;
 132         }
 133
 134         snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,
 135                                         "%s%d_cookies_%s_qp%hu",
 136                 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
 137                 qat_qp_conf->service_str, queue_pair_id);
 138
 139         QAT_LOG(DEBUG, "cookiepool: %s", op_cookie_pool_name);
 140         qp->op_cookie_pool = rte_mempool_lookup(op_cookie_pool_name);
 141         if (qp->op_cookie_pool == NULL)
 142                 qp->op_cookie_pool = rte_mempool_create(op_cookie_pool_name,
 143                                 qp->nb_descriptors,
 144                                 qat_qp_conf->cookie_size, 64, 0,
 145                                 NULL, NULL, NULL, NULL,
 146                                 pci_dev->device.numa_node,
 147                                 0);
 148         if (!qp->op_cookie_pool) {
 149                 QAT_LOG(ERR, "QAT PMD Cannot create"
 150                                 " op mempool");
 151                 qat_queue_delete(&(qp->tx_q));
 152                 qat_queue_delete(&(qp->rx_q));
 153                 goto create_err;
 154         }
 155
 156         for (i = 0; i < qp->nb_descriptors; i++) {
 157                 if (rte_mempool_get(qp->op_cookie_pool, &qp->op_cookies[i])) {
 158                         QAT_LOG(ERR, "QAT PMD Cannot get op_cookie");
 159                         goto create_err;
 160                 }
 161                 memset(qp->op_cookies[i], 0, qat_qp_conf->cookie_size);
 162         }
 163
 164         qp->qat_dev_gen = qat_dev->qat_dev_gen;
 165         qp->service_type = qat_qp_conf->hw->service_type;
 166         qp->qat_dev = qat_dev;
 167
 168         QAT_LOG(DEBUG, "QP setup complete: id: %d, cookiepool: %s",
 169                         queue_pair_id, op_cookie_pool_name);
 170
 171         qat_qp_csr_setup(qat_dev, io_addr, qp);
 172
 173         *qp_addr = qp;
 174         return 0;
 175
 176 create_err:
 177         if (qp) {
 178                 rte_mempool_free(qp->op_cookie_pool);
 179
 180                 rte_free(qp->op_cookies);
 181
 182                 rte_free(qp);
 183         }
 184
 185         return -EFAULT;
 186 }
 187
 188 static int
 189 qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,
 190                 struct qat_qp_config *qp_conf, uint8_t dir)
 191 {
 192         const struct rte_memzone *qp_mz;
 193         struct rte_pci_device *pci_dev =
 194                         qat_pci_devs[qat_dev->qat_dev_id].pci_dev;
 195         int ret = 0;
 196         uint16_t desc_size = (dir == ADF_RING_DIR_TX ?
 197                         qp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);
 198         uint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);
 199
 200         queue->hw_bundle_number = qp_conf->hw->hw_bundle_num;
 201         queue->hw_queue_number = (dir == ADF_RING_DIR_TX ?
 202                         qp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);
 203
 204         if (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
 205                 QAT_LOG(ERR, "Invalid descriptor size %d", desc_size);
 206                 return -EINVAL;
 207         }
 208
 209         /*
 210          * Allocate a memzone for the queue - create a unique name.
 211          */
 212         snprintf(queue->memz_name, sizeof(queue->memz_name),
 213                         "%s_%d_%s_%s_%d_%d",
 214                 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
 215                 qp_conf->service_str, "qp_mem",
 216                 queue->hw_bundle_number, queue->hw_queue_number);
 217         qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
 218                         pci_dev->device.numa_node);
 219         if (qp_mz == NULL) {
 220                 QAT_LOG(ERR, "Failed to allocate ring memzone");
 221                 return -ENOMEM;
 222         }
 223
 224         queue->base_addr = (char *)qp_mz->addr;
 225         queue->base_phys_addr = qp_mz->iova;
 226         if (qat_qp_check_queue_alignment(queue->base_phys_addr,
 227                         queue_size_bytes)) {
 228                 QAT_LOG(ERR, "Invalid alignment on queue create "
 229                                         " 0x%"PRIx64"\n",
 230                                         queue->base_phys_addr);
 231                 ret = -EFAULT;
 232                 goto queue_create_err;
 233         }
 234
 235         if (adf_verify_queue_size(desc_size, qp_conf->nb_descriptors,
 236                         &(queue->queue_size)) != 0) {
 237                 QAT_LOG(ERR, "Invalid num inflights");
 238                 ret = -EINVAL;
 239                 goto queue_create_err;
 240         }
 241
 242         queue->modulo_mask = (1 << ADF_RING_SIZE_MODULO(queue->queue_size)) - 1;
 243         queue->head = 0;
 244         queue->tail = 0;
 245         queue->msg_size = desc_size;
 246
 247         /* For fast calculation of cookie index, relies on msg_size being 2^n */
 248         queue->trailz = __builtin_ctz(desc_size);
 249
 250         /*
 251          * Write an unused pattern to the queue memory.
 252          */
 253         memset(queue->base_addr, 0x7F, queue_size_bytes);
 254
 255         QAT_LOG(DEBUG, "RING: Name:%s, size in CSR: %u, in bytes %u,"
 256                 " nb msgs %u, msg_size %u, modulo mask %u",
 257                         queue->memz_name,
 258                         queue->queue_size, queue_size_bytes,
 259                         qp_conf->nb_descriptors, desc_size,
 260                         queue->modulo_mask);
 261
 262         return 0;
 263
 264 queue_create_err:
 265         rte_memzone_free(qp_mz);
 266         return ret;
 267 }
 268
 269 static const struct rte_memzone *
 270 queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
 271                 int socket_id)
 272 {
 273         const struct rte_memzone *mz;
 274
 275         mz = rte_memzone_lookup(queue_name);
 276         if (mz != 0) {
 277                 if (((size_t)queue_size <= mz->len) &&
 278                                 ((socket_id == SOCKET_ID_ANY) ||
 279                                         (socket_id == mz->socket_id))) {
 280                         QAT_LOG(DEBUG, "re-use memzone already "
 281                                         "allocated for %s", queue_name);
 282                         return mz;
 283                 }
 284
 285                 QAT_LOG(ERR, "Incompatible memzone already "
 286                                 "allocated %s, size %u, socket %d. "
 287                                 "Requested size %u, socket %u",
 288                                 queue_name, (uint32_t)mz->len,
 289                                 mz->socket_id, queue_size, socket_id);
 290                 return NULL;
 291         }
 292
 293         QAT_LOG(DEBUG, "Allocate memzone for %s, size %u on socket %u",
 294                                         queue_name, queue_size, socket_id);
 295         return rte_memzone_reserve_aligned(queue_name, queue_size,
 296                 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
 297 }
 298
 299 int
 300 qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr)
 301 {
 302         int ret;
 303         struct qat_qp *qp = *qp_addr;
 304         uint32_t i;
 305
 306         if (qp == NULL) {
 307                 QAT_LOG(DEBUG, "qp already freed");
 308                 return 0;
 309         }
 310
 311         QAT_LOG(DEBUG, "Free qp on qat_pci device %d",
 312                                 qp->qat_dev->qat_dev_id);
 313
 314         /* Don't free memory if there are still responses to be processed */
 315         if ((qp->enqueued - qp->dequeued) == 0) {
 316                 qat_queue_delete(&(qp->tx_q));
 317                 qat_queue_delete(&(qp->rx_q));
 318         } else {
 319                 return -EAGAIN;
 320         }
 321
 322         ret = adf_queue_arb_disable(qat_dev_gen, &(qp->tx_q),
 323                         qp->mmap_bar_addr, &qp->qat_dev->arb_csr_lock);
 324         if (ret)
 325                 return ret;
 326
 327         for (i = 0; i < qp->nb_descriptors; i++)
 328                 rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);
 329
 330         rte_mempool_free(qp->op_cookie_pool);
 331
 332         rte_free(qp->op_cookies);
 333         rte_free(qp);
 334         *qp_addr = NULL;
 335         return 0;
 336 }
 337
 338
 339 static void
 340 qat_queue_delete(struct qat_queue *queue)
 341 {
 342         const struct rte_memzone *mz;
 343         int status = 0;
 344
 345         if (queue == NULL) {
 346                 QAT_LOG(DEBUG, "Invalid queue");
 347                 return;
 348         }
 349         QAT_LOG(DEBUG, "Free ring %d, memzone: %s",
 350                         queue->hw_queue_number, queue->memz_name);
 351
 352         mz = rte_memzone_lookup(queue->memz_name);
 353         if (mz != NULL) {
 354                 /* Write an unused pattern to the queue memory. */
 355                 memset(queue->base_addr, 0x7F, queue->queue_size);
 356                 status = rte_memzone_free(mz);
 357                 if (status != 0)
 358                         QAT_LOG(ERR, "Error %d on freeing queue %s",
 359                                         status, queue->memz_name);
 360         } else {
 361                 QAT_LOG(DEBUG, "queue %s doesn't exist",
 362                                 queue->memz_name);
 363         }
 364 }
 365
 366 static int __rte_unused
 367 adf_queue_arb_enable(struct qat_pci_device *qat_dev, struct qat_queue *txq,
 368                 void *base_addr, rte_spinlock_t *lock)
 369 {
 370         struct qat_qp_hw_spec_funcs *ops =
 371                 qat_qp_hw_spec[qat_dev->qat_dev_gen];
 372
 373         RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_arb_enable,
 374                         -ENOTSUP);
 375         ops->qat_qp_adf_arb_enable(txq, base_addr, lock);
 376         return 0;
 377 }
 378
 379 static int
 380 adf_queue_arb_disable(enum qat_device_gen qat_dev_gen, struct qat_queue *txq,
 381                 void *base_addr, rte_spinlock_t *lock)
 382 {
 383         struct qat_qp_hw_spec_funcs *ops =
 384                 qat_qp_hw_spec[qat_dev_gen];
 385
 386         RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_arb_disable,
 387                         -ENOTSUP);
 388         ops->qat_qp_adf_arb_disable(txq, base_addr, lock);
 389         return 0;
 390 }
 391
 392 static int __rte_unused
 393 qat_qp_build_ring_base(struct qat_pci_device *qat_dev, void *io_addr,
 394                 struct qat_queue *queue)
 395 {
 396         struct qat_qp_hw_spec_funcs *ops =
 397                 qat_qp_hw_spec[qat_dev->qat_dev_gen];
 398
 399         RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_build_ring_base,
 400                         -ENOTSUP);
 401         ops->qat_qp_build_ring_base(io_addr, queue);
 402         return 0;
 403 }
 404
 405 int
 406 qat_qps_per_service(struct qat_pci_device *qat_dev,
 407                 enum qat_service_type service)
 408 {
 409         struct qat_qp_hw_spec_funcs *ops =
 410                 qat_qp_hw_spec[qat_dev->qat_dev_gen];
 411
 412         RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_rings_per_service,
 413                         -ENOTSUP);
 414         return ops->qat_qp_rings_per_service(qat_dev, service);
 415 }
 416
 417 const struct qat_qp_hw_data *
 418 qat_qp_get_hw_data(struct qat_pci_device *qat_dev,
 419                 enum qat_service_type service, uint16_t qp_id)
 420 {
 421         struct qat_qp_hw_spec_funcs *ops =
 422                 qat_qp_hw_spec[qat_dev->qat_dev_gen];
 423
 424         RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_get_hw_data, NULL);
 425         return ops->qat_qp_get_hw_data(qat_dev, service, qp_id);
 426 }
 427
 428 int
 429 qat_read_qp_config(struct qat_pci_device *qat_dev)
 430 {
 431         struct qat_dev_hw_spec_funcs *ops_hw =
 432                 qat_dev_hw_spec[qat_dev->qat_dev_gen];
 433
 434         RTE_FUNC_PTR_OR_ERR_RET(ops_hw->qat_dev_read_config,
 435                         -ENOTSUP);
 436         return ops_hw->qat_dev_read_config(qat_dev);
 437 }
 438
 439 static int __rte_unused
 440 adf_configure_queues(struct qat_qp *qp, enum qat_device_gen qat_dev_gen)
 441 {
 442         struct qat_qp_hw_spec_funcs *ops =
 443                 qat_qp_hw_spec[qat_dev_gen];
 444
 445         RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_adf_configure_queues,
 446                         -ENOTSUP);
 447         ops->qat_qp_adf_configure_queues(qp);
 448         return 0;
 449 }
 450
 451 static inline void
 452 txq_write_tail(enum qat_device_gen qat_dev_gen,
 453                 struct qat_qp *qp, struct qat_queue *q)
 454 {
 455         struct qat_qp_hw_spec_funcs *ops =
 456                 qat_qp_hw_spec[qat_dev_gen];
 457
 458         /*
 459          * Pointer check should be done during
 460          * initialization
 461          */
 462         ops->qat_qp_csr_write_tail(qp, q);
 463 }
 464
 465 static inline void
 466 qat_qp_csr_write_head(enum qat_device_gen qat_dev_gen, struct qat_qp *qp,
 467                         struct qat_queue *q, uint32_t new_head)
 468 {
 469         struct qat_qp_hw_spec_funcs *ops =
 470                 qat_qp_hw_spec[qat_dev_gen];
 471
 472         /*
 473          * Pointer check should be done during
 474          * initialization
 475          */
 476         ops->qat_qp_csr_write_head(qp, q, new_head);
 477 }
 478
 479 static int
 480 qat_qp_csr_setup(struct qat_pci_device *qat_dev,
 481                 void *io_addr, struct qat_qp *qp)
 482 {
 483         struct qat_qp_hw_spec_funcs *ops =
 484                 qat_qp_hw_spec[qat_dev->qat_dev_gen];
 485
 486         RTE_FUNC_PTR_OR_ERR_RET(ops->qat_qp_csr_setup,
 487                         -ENOTSUP);
 488         ops->qat_qp_csr_setup(qat_dev, io_addr, qp);
 489         return 0;
 490 }
 491
 492
 493 static inline
 494 void rxq_free_desc(enum qat_device_gen qat_dev_gen, struct qat_qp *qp,
 495                                 struct qat_queue *q)
 496 {
 497         uint32_t old_head, new_head;
 498         uint32_t max_head;
 499
 500         old_head = q->csr_head;
 501         new_head = q->head;
 502         max_head = qp->nb_descriptors * q->msg_size;
 503
 504         /* write out free descriptors */
 505         void *cur_desc = (uint8_t *)q->base_addr + old_head;
 506
 507         if (new_head < old_head) {
 508                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
 509                 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
 510         } else {
 511                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
 512         }
 513         q->nb_processed_responses = 0;
 514         q->csr_head = new_head;
 515
 516         qat_qp_csr_write_head(qat_dev_gen, qp, q, new_head);
 517 }
 518
 519 static int
 520 qat_qp_check_queue_alignment(uint64_t phys_addr, uint32_t queue_size_bytes)
 521 {
 522         if (((queue_size_bytes - 1) & phys_addr) != 0)
 523                 return -EINVAL;
 524         return 0;
 525 }
 526
 527 static int
 528 adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
 529                 uint32_t *p_queue_size_for_csr)
 530 {
 531         uint8_t i = ADF_MIN_RING_SIZE;
 532
 533         for (; i <= ADF_MAX_RING_SIZE; i++)
 534                 if ((msg_size * msg_num) ==
 535                                 (uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {
 536                         *p_queue_size_for_csr = i;
 537                         return 0;
 538                 }
 539         QAT_LOG(ERR, "Invalid ring size %d", msg_size * msg_num);
 540         return -EINVAL;
 541 }
 542
 543 static inline uint32_t
 544 adf_modulo(uint32_t data, uint32_t modulo_mask)
 545 {
 546         return data & modulo_mask;
 547 }
 548
 549 uint16_t
 550 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 551 {
 552         register struct qat_queue *queue;
 553         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 554         register uint32_t nb_ops_sent = 0;
 555         register int ret = -1;
 556         uint16_t nb_ops_possible = nb_ops;
 557         register uint8_t *base_addr;
 558         register uint32_t tail;
 559
 560         if (unlikely(nb_ops == 0))
 561                 return 0;
 562
 563         /* read params used a lot in main loop into registers */
 564         queue = &(tmp_qp->tx_q);
 565         base_addr = (uint8_t *)queue->base_addr;
 566         tail = queue->tail;
 567
 568         /* Find how many can actually fit on the ring */
 569         {
 570                 /* dequeued can only be written by one thread, but it may not
 571                  * be this thread. As it's 4-byte aligned it will be read
 572                  * atomically here by any Intel CPU.
 573                  * enqueued can wrap before dequeued, but cannot
 574                  * lap it as var size of enq/deq (uint32_t) > var size of
 575                  * max_inflights (uint16_t). In reality inflights is never
 576                  * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
 577                  * On wrapping, the calculation still returns the correct
 578                  * positive value as all three vars are unsigned.
 579                  */
 580                 uint32_t inflights =
 581                         tmp_qp->enqueued - tmp_qp->dequeued;
 582
 583                 if ((inflights + nb_ops) > tmp_qp->max_inflights) {
 584                         nb_ops_possible = tmp_qp->max_inflights - inflights;
 585                         if (nb_ops_possible == 0)
 586                                 return 0;
 587                 }
 588                 /* QAT has plenty of work queued already, so don't waste cycles
 589                  * enqueueing, wait til the application has gathered a bigger
 590                  * burst or some completed ops have been dequeued
 591                  */
 592                 if (tmp_qp->min_enq_burst_threshold && inflights >
 593                                 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
 594                                 tmp_qp->min_enq_burst_threshold) {
 595                         tmp_qp->stats.threshold_hit_count++;
 596                         return 0;
 597                 }
 598         }
 599
 600 #ifdef BUILD_QAT_SYM
 601         if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
 602                 qat_sym_preprocess_requests(ops, nb_ops_possible);
 603 #endif
 604
 605         while (nb_ops_sent != nb_ops_possible) {
 606                 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC) {
 607 #ifdef BUILD_QAT_SYM
 608                         ret = qat_sym_build_request(*ops, base_addr + tail,
 609                                 tmp_qp->op_cookies[tail >> queue->trailz],
 610                                 tmp_qp->qat_dev_gen);
 611 #endif
 612                 } else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION) {
 613                         ret = qat_comp_build_request(*ops, base_addr + tail,
 614                                 tmp_qp->op_cookies[tail >> queue->trailz],
 615                                 tmp_qp->qat_dev_gen);
 616                 } else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC) {
 617 #ifdef BUILD_QAT_ASYM
 618                         ret = qat_asym_build_request(*ops, base_addr + tail,
 619                                 tmp_qp->op_cookies[tail >> queue->trailz],
 620                                 tmp_qp->qat_dev_gen);
 621 #endif
 622                 }
 623                 if (ret != 0) {
 624                         tmp_qp->stats.enqueue_err_count++;
 625                         /* This message cannot be enqueued */
 626                         if (nb_ops_sent == 0)
 627                                 return 0;
 628                         goto kick_tail;
 629                 }
 630
 631                 tail = adf_modulo(tail + queue->msg_size, queue->modulo_mask);
 632                 ops++;
 633                 nb_ops_sent++;
 634         }
 635 kick_tail:
 636         queue->tail = tail;
 637         tmp_qp->enqueued += nb_ops_sent;
 638         tmp_qp->stats.enqueued_count += nb_ops_sent;
 639         txq_write_tail(tmp_qp->qat_dev_gen, tmp_qp, queue);
 640         return nb_ops_sent;
 641 }
 642
 643 /* Use this for compression only - but keep consistent with above common
 644  * function as much as possible.
 645  */
 646 uint16_t
 647 qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops)
 648 {
 649         register struct qat_queue *queue;
 650         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 651         register uint32_t nb_ops_sent = 0;
 652         register int nb_desc_to_build;
 653         uint16_t nb_ops_possible = nb_ops;
 654         register uint8_t *base_addr;
 655         register uint32_t tail;
 656
 657         int descriptors_built, total_descriptors_built = 0;
 658         int nb_remaining_descriptors;
 659         int overflow = 0;
 660
 661         if (unlikely(nb_ops == 0))
 662                 return 0;
 663
 664         /* read params used a lot in main loop into registers */
 665         queue = &(tmp_qp->tx_q);
 666         base_addr = (uint8_t *)queue->base_addr;
 667         tail = queue->tail;
 668
 669         /* Find how many can actually fit on the ring */
 670         {
 671                 /* dequeued can only be written by one thread, but it may not
 672                  * be this thread. As it's 4-byte aligned it will be read
 673                  * atomically here by any Intel CPU.
 674                  * enqueued can wrap before dequeued, but cannot
 675                  * lap it as var size of enq/deq (uint32_t) > var size of
 676                  * max_inflights (uint16_t). In reality inflights is never
 677                  * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
 678                  * On wrapping, the calculation still returns the correct
 679                  * positive value as all three vars are unsigned.
 680                  */
 681                 uint32_t inflights =
 682                         tmp_qp->enqueued - tmp_qp->dequeued;
 683
 684                 /* Find how many can actually fit on the ring */
 685                 overflow = (inflights + nb_ops) - tmp_qp->max_inflights;
 686                 if (overflow > 0) {
 687                         nb_ops_possible = nb_ops - overflow;
 688                         if (nb_ops_possible == 0)
 689                                 return 0;
 690                 }
 691
 692                 /* QAT has plenty of work queued already, so don't waste cycles
 693                  * enqueueing, wait til the application has gathered a bigger
 694                  * burst or some completed ops have been dequeued
 695                  */
 696                 if (tmp_qp->min_enq_burst_threshold && inflights >
 697                                 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
 698                                 tmp_qp->min_enq_burst_threshold) {
 699                         tmp_qp->stats.threshold_hit_count++;
 700                         return 0;
 701                 }
 702         }
 703
 704         /* At this point nb_ops_possible is assuming a 1:1 mapping
 705          * between ops and descriptors.
 706          * Fewer may be sent if some ops have to be split.
 707          * nb_ops_possible is <= burst size.
 708          * Find out how many spaces are actually available on the qp in case
 709          * more are needed.
 710          */
 711         nb_remaining_descriptors = nb_ops_possible
 712                          + ((overflow >= 0) ? 0 : overflow * (-1));
 713         QAT_DP_LOG(DEBUG, "Nb ops requested %d, nb descriptors remaining %d",
 714                         nb_ops, nb_remaining_descriptors);
 715
 716         while (nb_ops_sent != nb_ops_possible &&
 717                                 nb_remaining_descriptors > 0) {
 718                 struct qat_comp_op_cookie *cookie =
 719                                 tmp_qp->op_cookies[tail >> queue->trailz];
 720
 721                 descriptors_built = 0;
 722
 723                 QAT_DP_LOG(DEBUG, "--- data length: %u",
 724                            ((struct rte_comp_op *)*ops)->src.length);
 725
 726                 nb_desc_to_build = qat_comp_build_request(*ops,
 727                                 base_addr + tail, cookie, tmp_qp->qat_dev_gen);
 728                 QAT_DP_LOG(DEBUG, "%d descriptors built, %d remaining, "
 729                         "%d ops sent, %d descriptors needed",
 730                         total_descriptors_built, nb_remaining_descriptors,
 731                         nb_ops_sent, nb_desc_to_build);
 732
 733                 if (unlikely(nb_desc_to_build < 0)) {
 734                         /* this message cannot be enqueued */
 735                         tmp_qp->stats.enqueue_err_count++;
 736                         if (nb_ops_sent == 0)
 737                                 return 0;
 738                         goto kick_tail;
 739                 } else if (unlikely(nb_desc_to_build > 1)) {
 740                         /* this op is too big and must be split - get more
 741                          * descriptors and retry
 742                          */
 743
 744                         QAT_DP_LOG(DEBUG, "Build %d descriptors for this op",
 745                                         nb_desc_to_build);
 746
 747                         nb_remaining_descriptors -= nb_desc_to_build;
 748                         if (nb_remaining_descriptors >= 0) {
 749                                 /* There are enough remaining descriptors
 750                                  * so retry
 751                                  */
 752                                 int ret2 = qat_comp_build_multiple_requests(
 753                                                 *ops, tmp_qp, tail,
 754                                                 nb_desc_to_build);
 755
 756                                 if (unlikely(ret2 < 1)) {
 757                                         QAT_DP_LOG(DEBUG,
 758                                                         "Failed to build (%d) descriptors, status %d",
 759                                                         nb_desc_to_build, ret2);
 760
 761                                         qat_comp_free_split_op_memzones(cookie,
 762                                                         nb_desc_to_build - 1);
 763
 764                                         tmp_qp->stats.enqueue_err_count++;
 765
 766                                         /* This message cannot be enqueued */
 767                                         if (nb_ops_sent == 0)
 768                                                 return 0;
 769                                         goto kick_tail;
 770                                 } else {
 771                                         descriptors_built = ret2;
 772                                         total_descriptors_built +=
 773                                                         descriptors_built;
 774                                         nb_remaining_descriptors -=
 775                                                         descriptors_built;
 776                                         QAT_DP_LOG(DEBUG,
 777                                                         "Multiple descriptors (%d) built ok",
 778                                                         descriptors_built);
 779                                 }
 780                         } else {
 781                                 QAT_DP_LOG(ERR, "For the current op, number of requested descriptors (%d) "
 782                                                 "exceeds number of available descriptors (%d)",
 783                                                 nb_desc_to_build,
 784                                                 nb_remaining_descriptors +
 785                                                         nb_desc_to_build);
 786
 787                                 qat_comp_free_split_op_memzones(cookie,
 788                                                 nb_desc_to_build - 1);
 789
 790                                 /* Not enough extra descriptors */
 791                                 if (nb_ops_sent == 0)
 792                                         return 0;
 793                                 goto kick_tail;
 794                         }
 795                 } else {
 796                         descriptors_built = 1;
 797                         total_descriptors_built++;
 798                         nb_remaining_descriptors--;
 799                         QAT_DP_LOG(DEBUG, "Single descriptor built ok");
 800                 }
 801
 802                 tail = adf_modulo(tail + (queue->msg_size * descriptors_built),
 803                                   queue->modulo_mask);
 804                 ops++;
 805                 nb_ops_sent++;
 806         }
 807
 808 kick_tail:
 809         queue->tail = tail;
 810         tmp_qp->enqueued += total_descriptors_built;
 811         tmp_qp->stats.enqueued_count += nb_ops_sent;
 812         txq_write_tail(tmp_qp->qat_dev_gen, tmp_qp, queue);
 813         return nb_ops_sent;
 814 }
 815
 816 uint16_t
 817 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 818 {
 819         struct qat_queue *rx_queue;
 820         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 821         uint32_t head;
 822         uint32_t op_resp_counter = 0, fw_resp_counter = 0;
 823         uint8_t *resp_msg;
 824         int nb_fw_responses;
 825
 826         rx_queue = &(tmp_qp->rx_q);
 827         head = rx_queue->head;
 828         resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
 829
 830         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 831                         op_resp_counter != nb_ops) {
 832
 833                 nb_fw_responses = 1;
 834
 835                 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
 836                         qat_sym_process_response(ops, resp_msg,
 837                                 tmp_qp->op_cookies[head >> rx_queue->trailz]);
 838                 else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
 839                         nb_fw_responses = qat_comp_process_response(
 840                                 ops, resp_msg,
 841                                 tmp_qp->op_cookies[head >> rx_queue->trailz],
 842                                 &tmp_qp->stats.dequeue_err_count);
 843 #ifdef BUILD_QAT_ASYM
 844                 else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC)
 845                         qat_asym_process_response(ops, resp_msg,
 846                                 tmp_qp->op_cookies[head >> rx_queue->trailz]);
 847 #endif
 848
 849                 head = adf_modulo(head + rx_queue->msg_size,
 850                                   rx_queue->modulo_mask);
 851
 852                 resp_msg = (uint8_t *)rx_queue->base_addr + head;
 853
 854                 if (nb_fw_responses) {
 855                         /* only move on to next op if one was ready to return
 856                          * to API
 857                          */
 858                         ops++;
 859                         op_resp_counter++;
 860                 }
 861
 862                  /* A compression op may be broken up into multiple fw requests.
 863                   * Only count fw responses as complete once ALL the responses
 864                   * associated with an op have been processed, as the cookie
 865                   * data from the first response must be available until
 866                   * finished with all firmware responses.
 867                   */
 868                 fw_resp_counter += nb_fw_responses;
 869
 870                 rx_queue->nb_processed_responses++;
 871         }
 872
 873         tmp_qp->dequeued += fw_resp_counter;
 874         tmp_qp->stats.dequeued_count += op_resp_counter;
 875
 876         rx_queue->head = head;
 877         if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
 878                 rxq_free_desc(tmp_qp->qat_dev_gen, tmp_qp, rx_queue);
 879
 880         QAT_DP_LOG(DEBUG, "Dequeue burst return: %u, QAT responses: %u",
 881                         op_resp_counter, fw_resp_counter);
 882
 883         return op_resp_counter;
 884 }
 885
 886 /* This is almost same as dequeue_op_burst, without the atomic, without stats
 887  * and without the op. Dequeues one response.
 888  */
 889 static uint8_t
 890 qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
 891 {
 892         uint8_t result = 0;
 893         uint8_t retries = 0;
 894         struct qat_queue *queue = &(qp->rx_q);
 895         struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
 896                         ((uint8_t *)queue->base_addr + queue->head);
 897
 898         while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
 899                         *(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
 900                 /* loop waiting for response until we reach the timeout */
 901                 rte_delay_ms(20);
 902         }
 903
 904         if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
 905                 /* response received */
 906                 result = 1;
 907
 908                 /* check status flag */
 909                 if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 910                                 resp_msg->comn_hdr.comn_status) ==
 911                                 ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
 912                         /* success */
 913                         memcpy(out_data, resp_msg, queue->msg_size);
 914                 } else {
 915                         memset(out_data, 0, queue->msg_size);
 916                 }
 917
 918                 queue->head = adf_modulo(queue->head + queue->msg_size,
 919                                 queue->modulo_mask);
 920                 rxq_free_desc(qp->qat_dev_gen, qp, queue);
 921         }
 922
 923         return result;
 924 }
 925
 926 /* Sends a NULL message and extracts QAT fw version from the response.
 927  * Used to determine detailed capabilities based on the fw version number.
 928  * This assumes that there are no inflight messages, i.e. assumes there's space
 929  * on the qp, one message is sent and only one response collected.
 930  * Returns fw version number or 0 for unknown version or a negative error code.
 931  */
 932 int
 933 qat_cq_get_fw_version(struct qat_qp *qp)
 934 {
 935         struct qat_queue *queue = &(qp->tx_q);
 936         uint8_t *base_addr = (uint8_t *)queue->base_addr;
 937         struct icp_qat_fw_comn_req null_msg;
 938         struct icp_qat_fw_comn_resp response;
 939
 940         /* prepare the NULL request */
 941         memset(&null_msg, 0, sizeof(null_msg));
 942         null_msg.comn_hdr.hdr_flags =
 943                 ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
 944         null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
 945         null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
 946
 947 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
 948         QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
 949 #endif
 950
 951         /* send the NULL request */
 952         memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
 953         queue->tail = adf_modulo(queue->tail + queue->msg_size,
 954                         queue->modulo_mask);
 955         txq_write_tail(qp->qat_dev_gen, qp, queue);
 956
 957         /* receive a response */
 958         if (qat_cq_dequeue_response(qp, &response)) {
 959
 960 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
 961                 QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
 962                                 sizeof(response));
 963 #endif
 964                 /* if LW0 bit 24 is set - then the fw version was returned */
 965                 if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
 966                                 ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
 967                                 ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
 968                         return response.resrvd[0]; /* return LW4 */
 969                 else
 970                         return 0; /* not set - we don't know fw version */
 971         }
 972
 973         QAT_LOG(ERR, "No response received");
 974         return -EINVAL;
 975 }
 976
 977 __rte_weak int
 978 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
 979                           void *op_cookie __rte_unused,
 980                           uint64_t *dequeue_err_count __rte_unused)
 981 {
 982         return  0;
 983 }