1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2018 Intel Corporation
5 #include <rte_common.h>
6 #include <rte_cycles.h>
8 #include <rte_malloc.h>
9 #include <rte_memzone.h>
11 #include <rte_bus_pci.h>
12 #include <rte_atomic.h>
13 #include <rte_prefetch.h>
16 #include "qat_device.h"
21 #include "adf_transport_access_macros.h"
23 #define QAT_CQ_MAX_DEQ_RETRIES 10
25 #define ADF_MAX_DESC 4096
26 #define ADF_MIN_DESC 128
28 #define ADF_ARB_REG_SLOT 0x1000
29 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
31 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
32 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
33 (ADF_ARB_REG_SLOT * index), value)
36 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
37 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
38 /* queue pairs which provide an asymmetric crypto service */
39 [QAT_SERVICE_ASYMMETRIC] = {
41 .service_type = QAT_SERVICE_ASYMMETRIC,
49 .service_type = QAT_SERVICE_ASYMMETRIC,
57 /* queue pairs which provide a symmetric crypto service */
58 [QAT_SERVICE_SYMMETRIC] = {
60 .service_type = QAT_SERVICE_SYMMETRIC,
68 .service_type = QAT_SERVICE_SYMMETRIC,
76 /* queue pairs which provide a compression service */
77 [QAT_SERVICE_COMPRESSION] = {
79 .service_type = QAT_SERVICE_COMPRESSION,
86 .service_type = QAT_SERVICE_COMPRESSION,
97 const struct qat_qp_hw_data qat_gen3_qps[QAT_MAX_SERVICES]
98 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
99 /* queue pairs which provide an asymmetric crypto service */
100 [QAT_SERVICE_ASYMMETRIC] = {
102 .service_type = QAT_SERVICE_ASYMMETRIC,
110 /* queue pairs which provide a symmetric crypto service */
111 [QAT_SERVICE_SYMMETRIC] = {
113 .service_type = QAT_SERVICE_SYMMETRIC,
121 /* queue pairs which provide a compression service */
122 [QAT_SERVICE_COMPRESSION] = {
124 .service_type = QAT_SERVICE_COMPRESSION,
134 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
135 uint32_t queue_size_bytes);
136 static void qat_queue_delete(struct qat_queue *queue);
137 static int qat_queue_create(struct qat_pci_device *qat_dev,
138 struct qat_queue *queue, struct qat_qp_config *, uint8_t dir);
139 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
140 uint32_t *queue_size_for_csr);
141 static void adf_configure_queues(struct qat_qp *queue);
142 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
143 rte_spinlock_t *lock);
144 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
145 rte_spinlock_t *lock);
148 int qat_qps_per_service(struct qat_pci_device *qat_dev,
149 enum qat_service_type service)
151 int i = 0, count = 0, max_ops_per_srv = 0;
152 const struct qat_qp_hw_data*
153 sym_hw_qps = qat_gen_config[qat_dev->qat_dev_gen]
154 .qp_hw_data[service];
156 max_ops_per_srv = ADF_MAX_QPS_ON_ANY_SERVICE;
157 for (; i < max_ops_per_srv; i++)
158 if (sym_hw_qps[i].service_type == service)
164 static const struct rte_memzone *
165 queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
168 const struct rte_memzone *mz;
170 mz = rte_memzone_lookup(queue_name);
172 if (((size_t)queue_size <= mz->len) &&
173 ((socket_id == SOCKET_ID_ANY) ||
174 (socket_id == mz->socket_id))) {
175 QAT_LOG(DEBUG, "re-use memzone already "
176 "allocated for %s", queue_name);
180 QAT_LOG(ERR, "Incompatible memzone already "
181 "allocated %s, size %u, socket %d. "
182 "Requested size %u, socket %u",
183 queue_name, (uint32_t)mz->len,
184 mz->socket_id, queue_size, socket_id);
188 QAT_LOG(DEBUG, "Allocate memzone for %s, size %u on socket %u",
189 queue_name, queue_size, socket_id);
190 return rte_memzone_reserve_aligned(queue_name, queue_size,
191 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
194 int qat_qp_setup(struct qat_pci_device *qat_dev,
195 struct qat_qp **qp_addr,
196 uint16_t queue_pair_id,
197 struct qat_qp_config *qat_qp_conf)
201 struct rte_pci_device *pci_dev =
202 qat_pci_devs[qat_dev->qat_dev_id].pci_dev;
203 char op_cookie_pool_name[RTE_RING_NAMESIZE];
206 QAT_LOG(DEBUG, "Setup qp %u on qat pci device %d gen %d",
207 queue_pair_id, qat_dev->qat_dev_id, qat_dev->qat_dev_gen);
209 if ((qat_qp_conf->nb_descriptors > ADF_MAX_DESC) ||
210 (qat_qp_conf->nb_descriptors < ADF_MIN_DESC)) {
211 QAT_LOG(ERR, "Can't create qp for %u descriptors",
212 qat_qp_conf->nb_descriptors);
216 if (pci_dev->mem_resource[0].addr == NULL) {
217 QAT_LOG(ERR, "Could not find VF config space "
218 "(UIO driver attached?).");
222 /* Allocate the queue pair data structure. */
223 qp = rte_zmalloc_socket("qat PMD qp metadata",
224 sizeof(*qp), RTE_CACHE_LINE_SIZE,
225 qat_qp_conf->socket_id);
227 QAT_LOG(ERR, "Failed to alloc mem for qp struct");
230 qp->nb_descriptors = qat_qp_conf->nb_descriptors;
231 qp->op_cookies = rte_zmalloc_socket("qat PMD op cookie pointer",
232 qat_qp_conf->nb_descriptors * sizeof(*qp->op_cookies),
233 RTE_CACHE_LINE_SIZE, qat_qp_conf->socket_id);
234 if (qp->op_cookies == NULL) {
235 QAT_LOG(ERR, "Failed to alloc mem for cookie");
240 qp->mmap_bar_addr = pci_dev->mem_resource[0].addr;
241 qp->enqueued = qp->dequeued = 0;
243 if (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,
244 ADF_RING_DIR_TX) != 0) {
245 QAT_LOG(ERR, "Tx queue create failed "
246 "queue_pair_id=%u", queue_pair_id);
250 qp->max_inflights = ADF_MAX_INFLIGHTS(qp->tx_q.queue_size,
251 ADF_BYTES_TO_MSG_SIZE(qp->tx_q.msg_size));
253 if (qp->max_inflights < 2) {
254 QAT_LOG(ERR, "Invalid num inflights");
255 qat_queue_delete(&(qp->tx_q));
259 if (qat_queue_create(qat_dev, &(qp->rx_q), qat_qp_conf,
260 ADF_RING_DIR_RX) != 0) {
261 QAT_LOG(ERR, "Rx queue create failed "
262 "queue_pair_id=%hu", queue_pair_id);
263 qat_queue_delete(&(qp->tx_q));
267 adf_configure_queues(qp);
268 adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr,
269 &qat_dev->arb_csr_lock);
271 snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,
272 "%s%d_cookies_%s_qp%hu",
273 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
274 qat_qp_conf->service_str, queue_pair_id);
276 QAT_LOG(DEBUG, "cookiepool: %s", op_cookie_pool_name);
277 qp->op_cookie_pool = rte_mempool_lookup(op_cookie_pool_name);
278 if (qp->op_cookie_pool == NULL)
279 qp->op_cookie_pool = rte_mempool_create(op_cookie_pool_name,
281 qat_qp_conf->cookie_size, 64, 0,
282 NULL, NULL, NULL, NULL,
283 pci_dev->device.numa_node,
285 if (!qp->op_cookie_pool) {
286 QAT_LOG(ERR, "QAT PMD Cannot create"
291 for (i = 0; i < qp->nb_descriptors; i++) {
292 if (rte_mempool_get(qp->op_cookie_pool, &qp->op_cookies[i])) {
293 QAT_LOG(ERR, "QAT PMD Cannot get op_cookie");
296 memset(qp->op_cookies[i], 0, qat_qp_conf->cookie_size);
299 qp->qat_dev_gen = qat_dev->qat_dev_gen;
300 qp->service_type = qat_qp_conf->hw->service_type;
301 qp->qat_dev = qat_dev;
303 QAT_LOG(DEBUG, "QP setup complete: id: %d, cookiepool: %s",
304 queue_pair_id, op_cookie_pool_name);
310 if (qp->op_cookie_pool)
311 rte_mempool_free(qp->op_cookie_pool);
312 rte_free(qp->op_cookies);
317 int qat_qp_release(struct qat_qp **qp_addr)
319 struct qat_qp *qp = *qp_addr;
323 QAT_LOG(DEBUG, "qp already freed");
327 QAT_LOG(DEBUG, "Free qp on qat_pci device %d",
328 qp->qat_dev->qat_dev_id);
330 /* Don't free memory if there are still responses to be processed */
331 if ((qp->enqueued - qp->dequeued) == 0) {
332 qat_queue_delete(&(qp->tx_q));
333 qat_queue_delete(&(qp->rx_q));
338 adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr,
339 &qp->qat_dev->arb_csr_lock);
341 for (i = 0; i < qp->nb_descriptors; i++)
342 rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);
344 if (qp->op_cookie_pool)
345 rte_mempool_free(qp->op_cookie_pool);
347 rte_free(qp->op_cookies);
354 static void qat_queue_delete(struct qat_queue *queue)
356 const struct rte_memzone *mz;
360 QAT_LOG(DEBUG, "Invalid queue");
363 QAT_LOG(DEBUG, "Free ring %d, memzone: %s",
364 queue->hw_queue_number, queue->memz_name);
366 mz = rte_memzone_lookup(queue->memz_name);
368 /* Write an unused pattern to the queue memory. */
369 memset(queue->base_addr, 0x7F, queue->queue_size);
370 status = rte_memzone_free(mz);
372 QAT_LOG(ERR, "Error %d on freeing queue %s",
373 status, queue->memz_name);
375 QAT_LOG(DEBUG, "queue %s doesn't exist",
381 qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,
382 struct qat_qp_config *qp_conf, uint8_t dir)
386 const struct rte_memzone *qp_mz;
387 struct rte_pci_device *pci_dev =
388 qat_pci_devs[qat_dev->qat_dev_id].pci_dev;
390 uint16_t desc_size = (dir == ADF_RING_DIR_TX ?
391 qp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);
392 uint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);
394 queue->hw_bundle_number = qp_conf->hw->hw_bundle_num;
395 queue->hw_queue_number = (dir == ADF_RING_DIR_TX ?
396 qp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);
398 if (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
399 QAT_LOG(ERR, "Invalid descriptor size %d", desc_size);
404 * Allocate a memzone for the queue - create a unique name.
406 snprintf(queue->memz_name, sizeof(queue->memz_name),
408 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
409 qp_conf->service_str, "qp_mem",
410 queue->hw_bundle_number, queue->hw_queue_number);
411 qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
412 pci_dev->device.numa_node);
414 QAT_LOG(ERR, "Failed to allocate ring memzone");
418 queue->base_addr = (char *)qp_mz->addr;
419 queue->base_phys_addr = qp_mz->iova;
420 if (qat_qp_check_queue_alignment(queue->base_phys_addr,
422 QAT_LOG(ERR, "Invalid alignment on queue create "
424 queue->base_phys_addr);
426 goto queue_create_err;
429 if (adf_verify_queue_size(desc_size, qp_conf->nb_descriptors,
430 &(queue->queue_size)) != 0) {
431 QAT_LOG(ERR, "Invalid num inflights");
433 goto queue_create_err;
436 queue->modulo_mask = (1 << ADF_RING_SIZE_MODULO(queue->queue_size)) - 1;
439 queue->msg_size = desc_size;
441 /* For fast calculation of cookie index, relies on msg_size being 2^n */
442 queue->trailz = __builtin_ctz(desc_size);
445 * Write an unused pattern to the queue memory.
447 memset(queue->base_addr, 0x7F, queue_size_bytes);
449 queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
452 io_addr = pci_dev->mem_resource[0].addr;
454 WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
455 queue->hw_queue_number, queue_base);
457 QAT_LOG(DEBUG, "RING: Name:%s, size in CSR: %u, in bytes %u,"
458 " nb msgs %u, msg_size %u, modulo mask %u",
460 queue->queue_size, queue_size_bytes,
461 qp_conf->nb_descriptors, desc_size,
467 rte_memzone_free(qp_mz);
471 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
472 uint32_t queue_size_bytes)
474 if (((queue_size_bytes - 1) & phys_addr) != 0)
479 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
480 uint32_t *p_queue_size_for_csr)
482 uint8_t i = ADF_MIN_RING_SIZE;
484 for (; i <= ADF_MAX_RING_SIZE; i++)
485 if ((msg_size * msg_num) ==
486 (uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {
487 *p_queue_size_for_csr = i;
490 QAT_LOG(ERR, "Invalid ring size %d", msg_size * msg_num);
494 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
495 rte_spinlock_t *lock)
497 uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +
499 txq->hw_bundle_number);
502 rte_spinlock_lock(lock);
503 value = ADF_CSR_RD(base_addr, arb_csr_offset);
504 value |= (0x01 << txq->hw_queue_number);
505 ADF_CSR_WR(base_addr, arb_csr_offset, value);
506 rte_spinlock_unlock(lock);
509 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
510 rte_spinlock_t *lock)
512 uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +
514 txq->hw_bundle_number);
517 rte_spinlock_lock(lock);
518 value = ADF_CSR_RD(base_addr, arb_csr_offset);
519 value &= ~(0x01 << txq->hw_queue_number);
520 ADF_CSR_WR(base_addr, arb_csr_offset, value);
521 rte_spinlock_unlock(lock);
524 static void adf_configure_queues(struct qat_qp *qp)
526 uint32_t queue_config;
527 struct qat_queue *queue = &qp->tx_q;
529 queue_config = BUILD_RING_CONFIG(queue->queue_size);
531 WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
532 queue->hw_queue_number, queue_config);
536 BUILD_RESP_RING_CONFIG(queue->queue_size,
537 ADF_RING_NEAR_WATERMARK_512,
538 ADF_RING_NEAR_WATERMARK_0);
540 WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
541 queue->hw_queue_number, queue_config);
544 static inline uint32_t adf_modulo(uint32_t data, uint32_t modulo_mask)
546 return data & modulo_mask;
550 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
551 WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
552 q->hw_queue_number, q->tail);
553 q->csr_tail = q->tail;
557 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
559 uint32_t old_head, new_head;
562 old_head = q->csr_head;
564 max_head = qp->nb_descriptors * q->msg_size;
566 /* write out free descriptors */
567 void *cur_desc = (uint8_t *)q->base_addr + old_head;
569 if (new_head < old_head) {
570 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
571 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
573 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
575 q->nb_processed_responses = 0;
576 q->csr_head = new_head;
578 /* write current head to CSR */
579 WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
580 q->hw_queue_number, new_head);
584 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
586 register struct qat_queue *queue;
587 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
588 register uint32_t nb_ops_sent = 0;
589 register int ret = -1;
590 uint16_t nb_ops_possible = nb_ops;
591 register uint8_t *base_addr;
592 register uint32_t tail;
594 if (unlikely(nb_ops == 0))
597 /* read params used a lot in main loop into registers */
598 queue = &(tmp_qp->tx_q);
599 base_addr = (uint8_t *)queue->base_addr;
602 /* Find how many can actually fit on the ring */
604 /* dequeued can only be written by one thread, but it may not
605 * be this thread. As it's 4-byte aligned it will be read
606 * atomically here by any Intel CPU.
607 * enqueued can wrap before dequeued, but cannot
608 * lap it as var size of enq/deq (uint32_t) > var size of
609 * max_inflights (uint16_t). In reality inflights is never
610 * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
611 * On wrapping, the calculation still returns the correct
612 * positive value as all three vars are unsigned.
615 tmp_qp->enqueued - tmp_qp->dequeued;
617 if ((inflights + nb_ops) > tmp_qp->max_inflights) {
618 nb_ops_possible = tmp_qp->max_inflights - inflights;
619 if (nb_ops_possible == 0)
622 /* QAT has plenty of work queued already, so don't waste cycles
623 * enqueueing, wait til the application has gathered a bigger
624 * burst or some completed ops have been dequeued
626 if (tmp_qp->min_enq_burst_threshold && inflights >
627 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
628 tmp_qp->min_enq_burst_threshold) {
629 tmp_qp->stats.threshold_hit_count++;
635 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
636 qat_sym_preprocess_requests(ops, nb_ops_possible);
639 while (nb_ops_sent != nb_ops_possible) {
640 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC) {
642 ret = qat_sym_build_request(*ops, base_addr + tail,
643 tmp_qp->op_cookies[tail >> queue->trailz],
644 tmp_qp->qat_dev_gen);
646 } else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION) {
647 ret = qat_comp_build_request(*ops, base_addr + tail,
648 tmp_qp->op_cookies[tail >> queue->trailz],
649 tmp_qp->qat_dev_gen);
650 } else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC) {
651 #ifdef BUILD_QAT_ASYM
652 ret = qat_asym_build_request(*ops, base_addr + tail,
653 tmp_qp->op_cookies[tail >> queue->trailz],
654 tmp_qp->qat_dev_gen);
658 tmp_qp->stats.enqueue_err_count++;
659 /* This message cannot be enqueued */
660 if (nb_ops_sent == 0)
665 tail = adf_modulo(tail + queue->msg_size, queue->modulo_mask);
671 tmp_qp->enqueued += nb_ops_sent;
672 tmp_qp->stats.enqueued_count += nb_ops_sent;
673 txq_write_tail(tmp_qp, queue);
677 /* Use this for compression only - but keep consistent with above common
678 * function as much as possible.
681 qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops)
683 register struct qat_queue *queue;
684 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
685 register uint32_t nb_ops_sent = 0;
686 register int nb_desc_to_build;
687 uint16_t nb_ops_possible = nb_ops;
688 register uint8_t *base_addr;
689 register uint32_t tail;
691 int descriptors_built, total_descriptors_built = 0;
692 int nb_remaining_descriptors;
695 if (unlikely(nb_ops == 0))
698 /* read params used a lot in main loop into registers */
699 queue = &(tmp_qp->tx_q);
700 base_addr = (uint8_t *)queue->base_addr;
703 /* Find how many can actually fit on the ring */
705 /* dequeued can only be written by one thread, but it may not
706 * be this thread. As it's 4-byte aligned it will be read
707 * atomically here by any Intel CPU.
708 * enqueued can wrap before dequeued, but cannot
709 * lap it as var size of enq/deq (uint32_t) > var size of
710 * max_inflights (uint16_t). In reality inflights is never
711 * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
712 * On wrapping, the calculation still returns the correct
713 * positive value as all three vars are unsigned.
716 tmp_qp->enqueued - tmp_qp->dequeued;
718 /* Find how many can actually fit on the ring */
719 overflow = (inflights + nb_ops) - tmp_qp->max_inflights;
721 nb_ops_possible = nb_ops - overflow;
722 if (nb_ops_possible == 0)
726 /* QAT has plenty of work queued already, so don't waste cycles
727 * enqueueing, wait til the application has gathered a bigger
728 * burst or some completed ops have been dequeued
730 if (tmp_qp->min_enq_burst_threshold && inflights >
731 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
732 tmp_qp->min_enq_burst_threshold) {
733 tmp_qp->stats.threshold_hit_count++;
738 /* At this point nb_ops_possible is assuming a 1:1 mapping
739 * between ops and descriptors.
740 * Fewer may be sent if some ops have to be split.
741 * nb_ops_possible is <= burst size.
742 * Find out how many spaces are actually available on the qp in case
745 nb_remaining_descriptors = nb_ops_possible
746 + ((overflow >= 0) ? 0 : overflow * (-1));
747 QAT_DP_LOG(DEBUG, "Nb ops requested %d, nb descriptors remaining %d",
748 nb_ops, nb_remaining_descriptors);
750 while (nb_ops_sent != nb_ops_possible &&
751 nb_remaining_descriptors > 0) {
752 struct qat_comp_op_cookie *cookie =
753 tmp_qp->op_cookies[tail >> queue->trailz];
755 descriptors_built = 0;
757 QAT_DP_LOG(DEBUG, "--- data length: %u",
758 ((struct rte_comp_op *)*ops)->src.length);
760 nb_desc_to_build = qat_comp_build_request(*ops,
761 base_addr + tail, cookie, tmp_qp->qat_dev_gen);
762 QAT_DP_LOG(DEBUG, "%d descriptors built, %d remaining, "
763 "%d ops sent, %d descriptors needed",
764 total_descriptors_built, nb_remaining_descriptors,
765 nb_ops_sent, nb_desc_to_build);
767 if (unlikely(nb_desc_to_build < 0)) {
768 /* this message cannot be enqueued */
769 tmp_qp->stats.enqueue_err_count++;
770 if (nb_ops_sent == 0)
773 } else if (unlikely(nb_desc_to_build > 1)) {
774 /* this op is too big and must be split - get more
775 * descriptors and retry
778 QAT_DP_LOG(DEBUG, "Build %d descriptors for this op",
781 nb_remaining_descriptors -= nb_desc_to_build;
782 if (nb_remaining_descriptors >= 0) {
783 /* There are enough remaining descriptors
786 int ret2 = qat_comp_build_multiple_requests(
790 if (unlikely(ret2 < 1)) {
792 "Failed to build (%d) descriptors, status %d",
793 nb_desc_to_build, ret2);
795 qat_comp_free_split_op_memzones(cookie,
796 nb_desc_to_build - 1);
798 tmp_qp->stats.enqueue_err_count++;
800 /* This message cannot be enqueued */
801 if (nb_ops_sent == 0)
805 descriptors_built = ret2;
806 total_descriptors_built +=
808 nb_remaining_descriptors -=
811 "Multiple descriptors (%d) built ok",
815 QAT_DP_LOG(ERR, "For the current op, number of requested descriptors (%d) "
816 "exceeds number of available descriptors (%d)",
818 nb_remaining_descriptors +
821 qat_comp_free_split_op_memzones(cookie,
822 nb_desc_to_build - 1);
824 /* Not enough extra descriptors */
825 if (nb_ops_sent == 0)
830 descriptors_built = 1;
831 total_descriptors_built++;
832 nb_remaining_descriptors--;
833 QAT_DP_LOG(DEBUG, "Single descriptor built ok");
836 tail = adf_modulo(tail + (queue->msg_size * descriptors_built),
844 tmp_qp->enqueued += total_descriptors_built;
845 tmp_qp->stats.enqueued_count += nb_ops_sent;
846 txq_write_tail(tmp_qp, queue);
851 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
853 struct qat_queue *rx_queue;
854 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
856 uint32_t op_resp_counter = 0, fw_resp_counter = 0;
860 rx_queue = &(tmp_qp->rx_q);
861 head = rx_queue->head;
862 resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
864 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
865 op_resp_counter != nb_ops) {
869 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
870 qat_sym_process_response(ops, resp_msg,
871 tmp_qp->op_cookies[head >> rx_queue->trailz]);
872 else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
873 nb_fw_responses = qat_comp_process_response(
875 tmp_qp->op_cookies[head >> rx_queue->trailz],
876 &tmp_qp->stats.dequeue_err_count);
877 #ifdef BUILD_QAT_ASYM
878 else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC)
879 qat_asym_process_response(ops, resp_msg,
880 tmp_qp->op_cookies[head >> rx_queue->trailz]);
883 head = adf_modulo(head + rx_queue->msg_size,
884 rx_queue->modulo_mask);
886 resp_msg = (uint8_t *)rx_queue->base_addr + head;
888 if (nb_fw_responses) {
889 /* only move on to next op if one was ready to return
896 /* A compression op may be broken up into multiple fw requests.
897 * Only count fw responses as complete once ALL the responses
898 * associated with an op have been processed, as the cookie
899 * data from the first response must be available until
900 * finished with all firmware responses.
902 fw_resp_counter += nb_fw_responses;
904 rx_queue->nb_processed_responses++;
907 tmp_qp->dequeued += fw_resp_counter;
908 tmp_qp->stats.dequeued_count += op_resp_counter;
910 rx_queue->head = head;
911 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
912 rxq_free_desc(tmp_qp, rx_queue);
914 QAT_DP_LOG(DEBUG, "Dequeue burst return: %u, QAT responses: %u",
915 op_resp_counter, fw_resp_counter);
917 return op_resp_counter;
920 /* This is almost same as dequeue_op_burst, without the atomic, without stats
921 * and without the op. Dequeues one response.
924 qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
928 struct qat_queue *queue = &(qp->rx_q);
929 struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
930 ((uint8_t *)queue->base_addr + queue->head);
932 while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
933 *(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
934 /* loop waiting for response until we reach the timeout */
938 if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
939 /* response received */
942 /* check status flag */
943 if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
944 resp_msg->comn_hdr.comn_status) ==
945 ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
947 memcpy(out_data, resp_msg, queue->msg_size);
949 memset(out_data, 0, queue->msg_size);
952 queue->head = adf_modulo(queue->head + queue->msg_size,
954 rxq_free_desc(qp, queue);
960 /* Sends a NULL message and extracts QAT fw version from the response.
961 * Used to determine detailed capabilities based on the fw version number.
962 * This assumes that there are no inflight messages, i.e. assumes there's space
963 * on the qp, one message is sent and only one response collected.
964 * Returns fw version number or 0 for unknown version or a negative error code.
967 qat_cq_get_fw_version(struct qat_qp *qp)
969 struct qat_queue *queue = &(qp->tx_q);
970 uint8_t *base_addr = (uint8_t *)queue->base_addr;
971 struct icp_qat_fw_comn_req null_msg;
972 struct icp_qat_fw_comn_resp response;
974 /* prepare the NULL request */
975 memset(&null_msg, 0, sizeof(null_msg));
976 null_msg.comn_hdr.hdr_flags =
977 ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
978 null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
979 null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
981 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
982 QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
985 /* send the NULL request */
986 memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
987 queue->tail = adf_modulo(queue->tail + queue->msg_size,
989 txq_write_tail(qp, queue);
991 /* receive a response */
992 if (qat_cq_dequeue_response(qp, &response)) {
994 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
995 QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
998 /* if LW0 bit 24 is set - then the fw version was returned */
999 if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
1000 ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
1001 ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
1002 return response.resrvd[0]; /* return LW4 */
1004 return 0; /* not set - we don't know fw version */
1007 QAT_LOG(ERR, "No response received");
1012 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
1013 void *op_cookie __rte_unused,
1014 uint64_t *dequeue_err_count __rte_unused)