vdpa/mlx5: support queue update
[dpdk.git] / drivers / common / qat / qat_qp.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2018 Intel Corporation
3  */
4 #ifndef _QAT_QP_H_
5 #define _QAT_QP_H_
6
7 #include "qat_common.h"
8 #include "adf_transport_access_macros.h"
9
10 struct qat_pci_device;
11
12 #define QAT_CSR_HEAD_WRITE_THRESH 32U
13 /* number of requests to accumulate before writing head CSR */
14
15 #define QAT_QP_MIN_INFL_THRESHOLD       256
16
17 typedef int (*build_request_t)(void *op,
18                 uint8_t *req, void *op_cookie,
19                 enum qat_device_gen qat_dev_gen);
20 /**< Build a request from an op. */
21
22 /**
23  * Structure with data needed for creation of queue pair.
24  */
25 struct qat_qp_hw_data {
26         enum qat_service_type service_type;
27         uint8_t hw_bundle_num;
28         uint8_t tx_ring_num;
29         uint8_t rx_ring_num;
30         uint16_t tx_msg_size;
31         uint16_t rx_msg_size;
32 };
33 /**
34  * Structure with data needed for creation of queue pair.
35  */
36 struct qat_qp_config {
37         const struct qat_qp_hw_data *hw;
38         uint32_t nb_descriptors;
39         uint32_t cookie_size;
40         int socket_id;
41         build_request_t build_request;
42         const char *service_str;
43 };
44
45 /**
46  * Structure associated with each queue.
47  */
48 struct qat_queue {
49         char            memz_name[RTE_MEMZONE_NAMESIZE];
50         void            *base_addr;             /* Base address */
51         rte_iova_t      base_phys_addr;         /* Queue physical address */
52         uint32_t        head;                   /* Shadow copy of the head */
53         uint32_t        tail;                   /* Shadow copy of the tail */
54         uint32_t        modulo_mask;
55         uint32_t        msg_size;
56         uint32_t        queue_size;
57         uint8_t         trailz;
58         uint8_t         hw_bundle_number;
59         uint8_t         hw_queue_number;
60         /* HW queue aka ring offset on bundle */
61         uint32_t        csr_head;               /* last written head value */
62         uint32_t        csr_tail;               /* last written tail value */
63         uint16_t        nb_processed_responses;
64         /* number of responses processed since last CSR head write */
65 };
66
67 struct qat_qp {
68         void                    *mmap_bar_addr;
69         struct qat_queue        tx_q;
70         struct qat_queue        rx_q;
71         struct qat_common_stats stats;
72         struct rte_mempool *op_cookie_pool;
73         void **op_cookies;
74         uint32_t nb_descriptors;
75         enum qat_device_gen qat_dev_gen;
76         build_request_t build_request;
77         enum qat_service_type service_type;
78         struct qat_pci_device *qat_dev;
79         /**< qat device this qp is on */
80         uint32_t enqueued;
81         uint32_t dequeued __rte_aligned(4);
82         uint16_t max_inflights;
83         uint16_t min_enq_burst_threshold;
84 } __rte_cache_aligned;
85
86 extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
87 extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
88
89 uint16_t
90 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
91
92 uint16_t
93 qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);
94
95 uint16_t
96 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops);
97
98 int
99 qat_qp_release(struct qat_qp **qp_addr);
100
101 int
102 qat_qp_setup(struct qat_pci_device *qat_dev,
103                 struct qat_qp **qp_addr, uint16_t queue_pair_id,
104                 struct qat_qp_config *qat_qp_conf);
105
106 int
107 qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
108                         enum qat_service_type service);
109
110 int
111 qat_cq_get_fw_version(struct qat_qp *qp);
112
113 /* Needed for weak function*/
114 int
115 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
116                           void *op_cookie __rte_unused,
117                           uint64_t *dequeue_err_count __rte_unused);
118
119 #endif /* _QAT_QP_H_ */