1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018-2022 Intel Corporation
7 #include "qat_common.h"
8 #include "adf_transport_access_macros.h"
10 #define QAT_CSR_HEAD_WRITE_THRESH 32U
11 /* number of requests to accumulate before writing head CSR */
13 #define QAT_QP_MIN_INFL_THRESHOLD 256
15 struct qat_pci_device;
18 * Structure associated with each queue.
21 char memz_name[RTE_MEMZONE_NAMESIZE];
22 void *base_addr; /* Base address */
23 rte_iova_t base_phys_addr; /* Queue physical address */
24 uint32_t head; /* Shadow copy of the head */
25 uint32_t tail; /* Shadow copy of the tail */
30 uint8_t hw_bundle_number;
31 uint8_t hw_queue_number;
32 /* HW queue aka ring offset on bundle */
33 uint32_t csr_head; /* last written head value */
34 uint32_t csr_tail; /* last written tail value */
35 uint16_t nb_processed_responses;
36 /* number of responses processed since last CSR head write */
40 * Type define qat_op_build_request_t function pointer, passed in as argument
41 * in enqueue op burst, where a build request assigned base on the type of
51 * an opaque data may be used to store context may be useful between
52 * 2 enqueue operations.
56 * - 0 if the crypto request is build successfully,
59 typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg,
60 void *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen);
63 * Type define qat_op_dequeue_t function pointer, passed in as argument
64 * in dequeue op burst, where a dequeue op assigned base on the type of
70 * qat response msg pointer
73 * @param dequeue_err_count
74 * dequeue error counter
76 * - 0 if dequeue OP is successful
79 typedef int (*qat_op_dequeue_t)(void **op, uint8_t *resp, void *op_cookie,
80 uint64_t *dequeue_err_count __rte_unused);
82 #define QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE 2
86 struct qat_queue tx_q;
87 struct qat_queue rx_q;
88 struct qat_common_stats stats;
89 struct rte_mempool *op_cookie_pool;
91 uint32_t nb_descriptors;
92 uint64_t opaque[QAT_BUILD_REQUEST_MAX_OPAQUE_SIZE];
93 enum qat_device_gen qat_dev_gen;
94 enum qat_service_type service_type;
95 struct qat_pci_device *qat_dev;
96 /**< qat device this qp is on */
98 uint32_t dequeued __rte_aligned(4);
99 uint16_t max_inflights;
100 uint16_t min_enq_burst_threshold;
101 } __rte_cache_aligned;
104 * Structure with data needed for creation of queue pair.
106 struct qat_qp_hw_data {
107 enum qat_service_type service_type;
108 uint8_t hw_bundle_num;
111 uint16_t tx_msg_size;
112 uint16_t rx_msg_size;
116 * Structure with data needed for creation of queue pair.
118 struct qat_qp_config {
119 const struct qat_qp_hw_data *hw;
120 uint32_t nb_descriptors;
121 uint32_t cookie_size;
123 const char *service_str;
127 qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,
128 void **ops, uint16_t nb_ops);
131 qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops);
134 qat_dequeue_op_burst(void *qp, void **ops,
135 qat_op_dequeue_t qat_dequeue_process_response, uint16_t nb_ops);
138 qat_qp_release(enum qat_device_gen qat_dev_gen, struct qat_qp **qp_addr);
141 qat_qp_setup(struct qat_pci_device *qat_dev,
142 struct qat_qp **qp_addr, uint16_t queue_pair_id,
143 struct qat_qp_config *qat_qp_conf);
146 qat_qps_per_service(struct qat_pci_device *qat_dev,
147 enum qat_service_type service);
149 const struct qat_qp_hw_data *
150 qat_qp_get_hw_data(struct qat_pci_device *qat_dev,
151 enum qat_service_type service, uint16_t qp_id);
154 qat_cq_get_fw_version(struct qat_qp *qp);
156 /* Needed for weak function*/
158 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
159 void *op_cookie __rte_unused,
160 uint64_t *dequeue_err_count __rte_unused);
162 qat_read_qp_config(struct qat_pci_device *qat_dev);
165 * Function prototypes for GENx specific queue pair operations.
167 typedef int (*qat_qp_rings_per_service_t)
168 (struct qat_pci_device *, enum qat_service_type);
170 typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);
172 typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,
175 typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,
178 typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);
180 typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue *q);
182 typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,
185 typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,
188 typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(
189 struct qat_pci_device *dev, enum qat_service_type service_type,
192 struct qat_qp_hw_spec_funcs {
193 qat_qp_rings_per_service_t qat_qp_rings_per_service;
194 qat_qp_build_ring_base_t qat_qp_build_ring_base;
195 qat_qp_adf_arb_enable_t qat_qp_adf_arb_enable;
196 qat_qp_adf_arb_disable_t qat_qp_adf_arb_disable;
197 qat_qp_adf_configure_queues_t qat_qp_adf_configure_queues;
198 qat_qp_csr_write_tail_t qat_qp_csr_write_tail;
199 qat_qp_csr_write_head_t qat_qp_csr_write_head;
200 qat_qp_csr_setup_t qat_qp_csr_setup;
201 qat_qp_get_hw_data_t qat_qp_get_hw_data;
204 extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];
206 #endif /* _QAT_QP_H_ */