1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
7 #include "qat_common.h"
8 #include "adf_transport_access_macros.h"
10 struct qat_pci_device;
12 #define QAT_CSR_HEAD_WRITE_THRESH 32U
13 /* number of requests to accumulate before writing head CSR */
14 #define QAT_CSR_TAIL_WRITE_THRESH 32U
15 /* number of requests to accumulate before writing tail CSR */
16 #define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
17 /* number of inflights below which no tail write coalescing should occur */
19 typedef int (*build_request_t)(void *op,
20 uint8_t *req, void *op_cookie,
21 enum qat_device_gen qat_dev_gen);
22 /**< Build a request from an op. */
25 * Structure with data needed for creation of queue pair.
27 struct qat_qp_hw_data {
28 enum qat_service_type service_type;
29 uint8_t hw_bundle_num;
36 * Structure with data needed for creation of queue pair.
38 struct qat_qp_config {
39 const struct qat_qp_hw_data *hw;
40 uint32_t nb_descriptors;
43 build_request_t build_request;
44 const char *service_str;
48 * Structure associated with each queue.
51 char memz_name[RTE_MEMZONE_NAMESIZE];
52 void *base_addr; /* Base address */
53 rte_iova_t base_phys_addr; /* Queue physical address */
54 uint32_t head; /* Shadow copy of the head */
55 uint32_t tail; /* Shadow copy of the tail */
58 uint16_t max_inflights;
60 uint8_t hw_bundle_number;
61 uint8_t hw_queue_number;
62 /* HW queue aka ring offset on bundle */
63 uint32_t csr_head; /* last written head value */
64 uint32_t csr_tail; /* last written tail value */
65 uint16_t nb_processed_responses;
66 /* number of responses processed since last CSR head write */
67 uint16_t nb_pending_requests;
68 /* number of requests pending since last CSR tail write */
74 struct qat_queue tx_q;
75 struct qat_queue rx_q;
76 struct qat_common_stats stats;
77 struct rte_mempool *op_cookie_pool;
79 uint32_t nb_descriptors;
80 enum qat_device_gen qat_dev_gen;
81 build_request_t build_request;
82 enum qat_service_type service_type;
83 struct qat_pci_device *qat_dev;
84 /**< qat device this qp is on */
85 } __rte_cache_aligned;
87 extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
88 extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
91 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
94 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops);
97 qat_qp_release(struct qat_qp **qp_addr);
100 qat_qp_setup(struct qat_pci_device *qat_dev,
101 struct qat_qp **qp_addr, uint16_t queue_pair_id,
102 struct qat_qp_config *qat_qp_conf);
105 qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
106 enum qat_service_type service);
108 /* Needed for weak function*/
110 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused);
112 #endif /* _QAT_QP_H_ */