1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
16 * Non-interrupting event queue requires interrrupting event queue to
17 * refer to for wake-up events even if wake ups are never used.
18 * It could be even non-allocated event queue.
20 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
22 static __checkReturn boolean_t
25 __in efx_qword_t *eqp,
26 __in const efx_ev_callbacks_t *eecp,
29 static __checkReturn boolean_t
32 __in efx_qword_t *eqp,
33 __in const efx_ev_callbacks_t *eecp,
36 static __checkReturn boolean_t
39 __in efx_qword_t *eqp,
40 __in const efx_ev_callbacks_t *eecp,
43 static __checkReturn boolean_t
46 __in efx_qword_t *eqp,
47 __in const efx_ev_callbacks_t *eecp,
50 static __checkReturn boolean_t
53 __in efx_qword_t *eqp,
54 __in const efx_ev_callbacks_t *eecp,
58 static __checkReturn efx_rc_t
61 __in uint32_t instance,
63 __in uint32_t timer_ns)
66 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
67 MC_CMD_SET_EVQ_TMR_OUT_LEN);
70 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
71 req.emr_in_buf = payload;
72 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
73 req.emr_out_buf = payload;
74 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
76 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
77 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
78 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
79 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
81 efx_mcdi_execute(enp, &req);
83 if (req.emr_rc != 0) {
88 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
98 EFSYS_PROBE1(fail1, efx_rc_t, rc);
104 __checkReturn efx_rc_t
108 _NOTE(ARGUNUSED(enp))
116 _NOTE(ARGUNUSED(enp))
119 __checkReturn efx_rc_t
122 __in unsigned int index,
123 __in efsys_mem_t *esmp,
130 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
134 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
136 if (index >= encp->enc_evq_limit) {
141 if (us > encp->enc_evq_timer_max_us) {
147 * NO_CONT_EV mode is only requested from the firmware when creating
148 * receive queues, but here it needs to be specified at event queue
149 * creation, as the event handler needs to know which format is in use.
151 * If EFX_EVQ_FLAGS_NO_CONT_EV is specified, all receive queues for this
152 * event queue will be created in NO_CONT_EV mode.
154 * See SF-109306-TC 5.11 "Events for RXQs in NO_CONT_EV mode".
156 if (flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
157 if (enp->en_nic_cfg.enc_no_cont_ev_mode_supported == B_FALSE) {
163 /* Set up the handler table */
164 eep->ee_rx = ef10_ev_rx;
165 eep->ee_tx = ef10_ev_tx;
166 eep->ee_driver = ef10_ev_driver;
167 eep->ee_drv_gen = ef10_ev_drv_gen;
168 eep->ee_mcdi = ef10_ev_mcdi;
170 /* Set up the event queue */
171 /* INIT_EVQ expects function-relative vector number */
172 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
173 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
175 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
177 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
178 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
180 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
184 * Interrupts may be raised for events immediately after the queue is
185 * created. See bug58606.
188 if (encp->enc_init_evq_v2_supported) {
190 * On Medford the low latency license is required to enable RX
191 * and event cut through and to disable RX batching. If event
192 * queue type in flags is auto, we let the firmware decide the
193 * settings to use. If the adapter has a low latency license,
194 * it will choose the best settings for low latency, otherwise
195 * it will choose the best settings for throughput.
197 rc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,
203 * On Huntington we need to specify the settings to use.
204 * If event queue type in flags is auto, we favour throughput
205 * if the adapter is running virtualization supporting firmware
206 * (i.e. the full featured firmware variant)
207 * and latency otherwise. The Ethernet Virtual Bridging
208 * capability is used to make this decision. (Note though that
209 * the low latency firmware variant is also best for
210 * throughput and corresponding type should be specified
213 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
214 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
231 EFSYS_PROBE1(fail1, efx_rc_t, rc);
240 efx_nic_t *enp = eep->ee_enp;
242 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
244 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
247 __checkReturn efx_rc_t
250 __in unsigned int count)
252 efx_nic_t *enp = eep->ee_enp;
256 rptr = count & eep->ee_mask;
258 if (enp->en_nic_cfg.enc_bug35388_workaround) {
259 EFX_STATIC_ASSERT(EF10_EVQ_MINNEVS >
260 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
261 EFX_STATIC_ASSERT(EF10_EVQ_MAXNEVS <
262 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
264 EFX_POPULATE_DWORD_2(dword,
265 ERF_DD_EVQ_IND_RPTR_FLAGS,
266 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
268 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
269 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
272 EFX_POPULATE_DWORD_2(dword,
273 ERF_DD_EVQ_IND_RPTR_FLAGS,
274 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
276 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
277 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
280 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
281 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
288 static __checkReturn efx_rc_t
289 efx_mcdi_driver_event(
292 __in efx_qword_t data)
295 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
296 MC_CMD_DRIVER_EVENT_OUT_LEN);
299 req.emr_cmd = MC_CMD_DRIVER_EVENT;
300 req.emr_in_buf = payload;
301 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
302 req.emr_out_buf = payload;
303 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
305 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
307 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
308 EFX_QWORD_FIELD(data, EFX_DWORD_0));
309 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
310 EFX_QWORD_FIELD(data, EFX_DWORD_1));
312 efx_mcdi_execute(enp, &req);
314 if (req.emr_rc != 0) {
322 EFSYS_PROBE1(fail1, efx_rc_t, rc);
332 efx_nic_t *enp = eep->ee_enp;
335 EFX_POPULATE_QWORD_3(event,
336 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
337 ESF_DZ_DRV_SUB_CODE, 0,
338 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
340 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
343 __checkReturn efx_rc_t
346 __in unsigned int us)
348 efx_nic_t *enp = eep->ee_enp;
349 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
354 /* Check that hardware and MCDI use the same timer MODE values */
355 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
356 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
357 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
358 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
359 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
360 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
361 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
362 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
364 if (us > encp->enc_evq_timer_max_us) {
369 /* If the value is zero then disable the timer */
371 mode = FFE_CZ_TIMER_MODE_DIS;
373 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
376 if (encp->enc_bug61265_workaround) {
377 uint32_t ns = us * 1000;
379 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
385 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
388 if (encp->enc_bug35388_workaround) {
389 EFX_POPULATE_DWORD_3(dword,
390 ERF_DD_EVQ_IND_TIMER_FLAGS,
391 EFE_DD_EVQ_IND_TIMER_FLAGS,
392 ERF_DD_EVQ_IND_TIMER_MODE, mode,
393 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
394 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
395 eep->ee_index, &dword, 0);
398 * NOTE: The TMR_REL field introduced in Medford2 is
399 * ignored on earlier EF10 controllers. See bug66418
400 * comment 9 for details.
402 EFX_POPULATE_DWORD_3(dword,
403 ERF_DZ_TC_TIMER_MODE, mode,
404 ERF_DZ_TC_TIMER_VAL, ticks,
405 ERF_FZ_TC_TMR_REL_VAL, ticks);
406 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
407 eep->ee_index, &dword, 0);
418 EFSYS_PROBE1(fail1, efx_rc_t, rc);
426 ef10_ev_qstats_update(
428 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
432 for (id = 0; id < EV_NQSTATS; id++) {
433 efsys_stat_t *essp = &stat[id];
435 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
436 eep->ee_stat[id] = 0;
439 #endif /* EFSYS_OPT_QSTATS */
441 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
443 static __checkReturn boolean_t
444 ef10_ev_rx_packed_stream(
446 __in efx_qword_t *eqp,
447 __in const efx_ev_callbacks_t *eecp,
451 uint32_t pkt_count_lbits;
453 boolean_t should_abort;
454 efx_evq_rxq_state_t *eersp;
455 unsigned int pkt_count;
456 unsigned int current_id;
457 boolean_t new_buffer;
459 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
460 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
461 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
465 eersp = &eep->ee_rxq_state[label];
468 * RX_DSC_PTR_LBITS has least significant bits of the global
469 * (not per-buffer) packet counter. It is guaranteed that
470 * maximum number of completed packets fits in lbits-mask.
471 * So, modulo lbits-mask arithmetic should be used to calculate
472 * packet counter increment.
474 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
475 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
476 eersp->eers_rx_stream_npackets += pkt_count;
479 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
480 #if EFSYS_OPT_RX_PACKED_STREAM
482 * If both packed stream and equal stride super-buffer
483 * modes are compiled in, in theory credits should be
484 * be maintained for packed stream only, but right now
485 * these modes are not distinguished in the event queue
486 * Rx queue state and it is OK to increment the counter
487 * regardless (it might be event cheaper than branching
488 * since neighbour structure member are updated as well).
490 eersp->eers_rx_packed_stream_credits++;
492 eersp->eers_rx_read_ptr++;
494 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
496 /* Check for errors that invalidate checksum and L3/L4 fields */
497 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
498 /* RX frame truncated */
499 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
500 flags |= EFX_DISCARD;
503 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
504 /* Bad Ethernet frame CRC */
505 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
506 flags |= EFX_DISCARD;
510 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
511 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
512 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
516 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
517 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
519 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
520 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
523 /* If we're not discarding the packet then it is ok */
524 if (~flags & EFX_DISCARD)
525 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
527 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
528 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
531 return (should_abort);
534 #endif /* EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER */
536 static __checkReturn boolean_t
539 __in efx_qword_t *eqp,
540 __in const efx_ev_callbacks_t *eecp,
543 efx_nic_t *enp = eep->ee_enp;
547 uint32_t eth_tag_class;
550 uint32_t next_read_lbits;
553 boolean_t should_abort;
554 efx_evq_rxq_state_t *eersp;
555 unsigned int desc_count;
556 unsigned int last_used_id;
558 EFX_EV_QSTAT_INCR(eep, EV_RX);
560 /* Discard events after RXQ/TXQ errors, or hardware not available */
561 if (enp->en_reset_flags &
562 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
565 /* Basic packet information */
566 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
567 eersp = &eep->ee_rxq_state[label];
569 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
571 * Packed stream events are very different,
572 * so handle them separately
574 if (eersp->eers_rx_packed_stream)
575 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
578 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
579 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
580 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
581 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
582 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
583 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
586 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
587 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
588 * and values for all EF10 controllers.
590 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
591 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
592 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
593 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
595 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
597 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
598 /* Drop this event */
605 * This may be part of a scattered frame, or it may be a
606 * truncated frame if scatter is disabled on this RXQ.
607 * Overlength frames can be received if e.g. a VF is configured
608 * for 1500 MTU but connected to a port set to 9000 MTU
610 * FIXME: There is not yet any driver that supports scatter on
611 * Huntington. Scatter support is required for OSX.
613 flags |= EFX_PKT_CONT;
616 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
617 flags |= EFX_PKT_UNICAST;
620 * Increment the count of descriptors read.
622 * In NO_CONT_EV mode, RX_DSC_PTR_LBITS is actually a packet count, but
623 * when scatter is disabled, there is only one descriptor per packet and
624 * so it can be treated the same.
626 * TODO: Support scatter in NO_CONT_EV mode.
628 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
629 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
630 eersp->eers_rx_read_ptr += desc_count;
632 /* Calculate the index of the last descriptor consumed */
633 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
635 if (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
637 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
639 /* Always read the length from the prefix in NO_CONT_EV mode. */
640 flags |= EFX_PKT_PREFIX_LEN;
643 * Check for an aborted scatter, signalled by the ABORT bit in
644 * NO_CONT_EV mode. The ABORT bit was not used before NO_CONT_EV
645 * mode was added as it was broken in Huntington silicon.
647 if (EFX_QWORD_FIELD(*eqp, ESF_EZ_RX_ABORT) != 0) {
648 flags |= EFX_DISCARD;
651 } else if (desc_count > 1) {
653 * FIXME: add error checking to make sure this a batched event.
654 * This could also be an aborted scatter, see Bug36629.
656 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
657 flags |= EFX_PKT_PREFIX_LEN;
660 /* Check for errors that invalidate checksum and L3/L4 fields */
661 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
662 /* RX frame truncated */
663 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
664 flags |= EFX_DISCARD;
667 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
668 /* Bad Ethernet frame CRC */
669 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
670 flags |= EFX_DISCARD;
673 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
675 * Hardware parse failed, due to malformed headers
676 * or headers that are too long for the parser.
677 * Headers and checksums must be validated by the host.
679 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
683 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
684 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
685 flags |= EFX_PKT_VLAN_TAGGED;
689 case ESE_DZ_L3_CLASS_IP4:
690 case ESE_DZ_L3_CLASS_IP4_FRAG:
691 flags |= EFX_PKT_IPV4;
692 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
693 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
695 flags |= EFX_CKSUM_IPV4;
699 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
700 * only 2 bits wide on Medford2. Check it is safe to use the
701 * Medford2 field and values for all EF10 controllers.
703 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
704 ESF_DE_RX_L4_CLASS_LBN);
705 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
706 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
707 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
708 ESE_DE_L4_CLASS_UNKNOWN);
710 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
711 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
712 flags |= EFX_PKT_TCP;
713 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
714 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
715 flags |= EFX_PKT_UDP;
717 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
721 case ESE_DZ_L3_CLASS_IP6:
722 case ESE_DZ_L3_CLASS_IP6_FRAG:
723 flags |= EFX_PKT_IPV6;
726 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
727 * only 2 bits wide on Medford2. Check it is safe to use the
728 * Medford2 field and values for all EF10 controllers.
730 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
731 ESF_DE_RX_L4_CLASS_LBN);
732 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
733 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
734 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
735 ESE_DE_L4_CLASS_UNKNOWN);
737 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
738 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
739 flags |= EFX_PKT_TCP;
740 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
741 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
742 flags |= EFX_PKT_UDP;
744 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
749 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
753 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
754 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
755 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
757 flags |= EFX_CKSUM_TCPUDP;
762 /* If we're not discarding the packet then it is ok */
763 if (~flags & EFX_DISCARD)
764 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
766 EFSYS_ASSERT(eecp->eec_rx != NULL);
767 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
769 return (should_abort);
772 static __checkReturn boolean_t
775 __in efx_qword_t *eqp,
776 __in const efx_ev_callbacks_t *eecp,
779 efx_nic_t *enp = eep->ee_enp;
782 boolean_t should_abort;
784 EFX_EV_QSTAT_INCR(eep, EV_TX);
786 /* Discard events after RXQ/TXQ errors, or hardware not available */
787 if (enp->en_reset_flags &
788 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
791 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
792 /* Drop this event */
796 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
797 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
798 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
800 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
802 EFSYS_ASSERT(eecp->eec_tx != NULL);
803 should_abort = eecp->eec_tx(arg, label, id);
805 return (should_abort);
808 static __checkReturn boolean_t
811 __in efx_qword_t *eqp,
812 __in const efx_ev_callbacks_t *eecp,
816 boolean_t should_abort;
818 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
819 should_abort = B_FALSE;
821 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
823 case ESE_DZ_DRV_TIMER_EV: {
826 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
828 EFSYS_ASSERT(eecp->eec_timer != NULL);
829 should_abort = eecp->eec_timer(arg, id);
833 case ESE_DZ_DRV_WAKE_UP_EV: {
836 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
838 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
839 should_abort = eecp->eec_wake_up(arg, id);
843 case ESE_DZ_DRV_START_UP_EV:
844 EFSYS_ASSERT(eecp->eec_initialized != NULL);
845 should_abort = eecp->eec_initialized(arg);
849 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
850 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
851 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
855 return (should_abort);
858 static __checkReturn boolean_t
861 __in efx_qword_t *eqp,
862 __in const efx_ev_callbacks_t *eecp,
866 boolean_t should_abort;
868 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
869 should_abort = B_FALSE;
871 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
872 if (data >= ((uint32_t)1 << 16)) {
873 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
874 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
875 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
880 EFSYS_ASSERT(eecp->eec_software != NULL);
881 should_abort = eecp->eec_software(arg, (uint16_t)data);
883 return (should_abort);
886 static __checkReturn boolean_t
889 __in efx_qword_t *eqp,
890 __in const efx_ev_callbacks_t *eecp,
893 efx_nic_t *enp = eep->ee_enp;
895 boolean_t should_abort = B_FALSE;
897 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
899 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
901 case MCDI_EVENT_CODE_BADSSERT:
902 efx_mcdi_ev_death(enp, EINTR);
905 case MCDI_EVENT_CODE_CMDDONE:
907 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
908 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
909 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
912 #if EFSYS_OPT_MCDI_PROXY_AUTH
913 case MCDI_EVENT_CODE_PROXY_RESPONSE:
915 * This event notifies a function that an authorization request
916 * has been processed. If the request was authorized then the
917 * function can now re-send the original MCDI request.
918 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
920 efx_mcdi_ev_proxy_response(enp,
921 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
922 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
924 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
926 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
927 case MCDI_EVENT_CODE_PROXY_REQUEST:
928 efx_mcdi_ev_proxy_request(enp,
929 MCDI_EV_FIELD(eqp, PROXY_REQUEST_BUFF_INDEX));
931 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
933 case MCDI_EVENT_CODE_LINKCHANGE: {
934 efx_link_mode_t link_mode;
936 ef10_phy_link_ev(enp, eqp, &link_mode);
937 should_abort = eecp->eec_link_change(arg, link_mode);
941 case MCDI_EVENT_CODE_SENSOREVT: {
942 #if EFSYS_OPT_MON_STATS
944 efx_mon_stat_value_t value;
947 /* Decode monitor stat for MCDI sensor (if supported) */
948 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
949 /* Report monitor stat change */
950 should_abort = eecp->eec_monitor(arg, id, value);
951 } else if (rc == ENOTSUP) {
952 should_abort = eecp->eec_exception(arg,
953 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
954 MCDI_EV_FIELD(eqp, DATA));
956 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
962 case MCDI_EVENT_CODE_SCHEDERR:
963 /* Informational only */
966 case MCDI_EVENT_CODE_REBOOT:
967 /* Falcon/Siena only (should not been seen with Huntington). */
968 efx_mcdi_ev_death(enp, EIO);
971 case MCDI_EVENT_CODE_MC_REBOOT:
972 /* MC_REBOOT event is used for Huntington (EF10) and later. */
973 efx_mcdi_ev_death(enp, EIO);
976 case MCDI_EVENT_CODE_MAC_STATS_DMA:
977 #if EFSYS_OPT_MAC_STATS
978 if (eecp->eec_mac_stats != NULL) {
979 eecp->eec_mac_stats(arg,
980 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
985 case MCDI_EVENT_CODE_FWALERT: {
986 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
988 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
989 should_abort = eecp->eec_exception(arg,
990 EFX_EXCEPTION_FWALERT_SRAM,
991 MCDI_EV_FIELD(eqp, FWALERT_DATA));
993 should_abort = eecp->eec_exception(arg,
994 EFX_EXCEPTION_UNKNOWN_FWALERT,
995 MCDI_EV_FIELD(eqp, DATA));
999 case MCDI_EVENT_CODE_TX_ERR: {
1001 * After a TXQ error is detected, firmware sends a TX_ERR event.
1002 * This may be followed by TX completions (which we discard),
1003 * and then finally by a TX_FLUSH event. Firmware destroys the
1004 * TXQ automatically after sending the TX_FLUSH event.
1006 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1008 EFSYS_PROBE2(tx_descq_err,
1009 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1010 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1012 /* Inform the driver that a reset is required. */
1013 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1014 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1018 case MCDI_EVENT_CODE_TX_FLUSH: {
1019 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1022 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1023 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1024 * We want to wait for all completions, so ignore the events
1025 * with TX_FLUSH_TO_DRIVER.
1027 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1028 should_abort = B_FALSE;
1032 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1034 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1036 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1037 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1041 case MCDI_EVENT_CODE_RX_ERR: {
1043 * After an RXQ error is detected, firmware sends an RX_ERR
1044 * event. This may be followed by RX events (which we discard),
1045 * and then finally by an RX_FLUSH event. Firmware destroys the
1046 * RXQ automatically after sending the RX_FLUSH event.
1048 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1050 EFSYS_PROBE2(rx_descq_err,
1051 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1052 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1054 /* Inform the driver that a reset is required. */
1055 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1056 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1060 case MCDI_EVENT_CODE_RX_FLUSH: {
1061 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1064 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1065 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1066 * We want to wait for all completions, so ignore the events
1067 * with RX_FLUSH_TO_DRIVER.
1069 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1070 should_abort = B_FALSE;
1074 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1076 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1078 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1079 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1084 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1085 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1086 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1090 return (should_abort);
1094 ef10_ev_rxlabel_init(
1095 __in efx_evq_t *eep,
1096 __in efx_rxq_t *erp,
1097 __in unsigned int label,
1098 __in efx_rxq_type_t type)
1100 efx_evq_rxq_state_t *eersp;
1101 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1102 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1103 boolean_t es_super_buffer = (type == EFX_RXQ_TYPE_ES_SUPER_BUFFER);
1106 _NOTE(ARGUNUSED(type))
1107 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1108 eersp = &eep->ee_rxq_state[label];
1110 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1112 #if EFSYS_OPT_RX_PACKED_STREAM
1114 * For packed stream modes, the very first event will
1115 * have a new buffer flag set, so it will be incremented,
1116 * yielding the correct pointer. That results in a simpler
1117 * code than trying to detect start-of-the-world condition
1118 * in the event handler.
1120 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1122 eersp->eers_rx_read_ptr = 0;
1124 eersp->eers_rx_mask = erp->er_mask;
1125 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1126 eersp->eers_rx_stream_npackets = 0;
1127 eersp->eers_rx_packed_stream = packed_stream || es_super_buffer;
1129 #if EFSYS_OPT_RX_PACKED_STREAM
1130 if (packed_stream) {
1131 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1132 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1133 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1134 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1136 * A single credit is allocated to the queue when it is started.
1137 * It is immediately spent by the first packet which has NEW
1138 * BUFFER flag set, though, but still we shall take into
1139 * account, as to not wrap around the maximum number of credits
1142 eersp->eers_rx_packed_stream_credits--;
1143 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1144 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1150 ef10_ev_rxlabel_fini(
1151 __in efx_evq_t *eep,
1152 __in unsigned int label)
1154 efx_evq_rxq_state_t *eersp;
1156 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1157 eersp = &eep->ee_rxq_state[label];
1159 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1161 eersp->eers_rx_read_ptr = 0;
1162 eersp->eers_rx_mask = 0;
1163 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1164 eersp->eers_rx_stream_npackets = 0;
1165 eersp->eers_rx_packed_stream = B_FALSE;
1167 #if EFSYS_OPT_RX_PACKED_STREAM
1168 eersp->eers_rx_packed_stream_credits = 0;
1172 #endif /* EFX_OPTS_EF10() */