1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
9 #if EFSYS_OPT_MON_STATS
16 * Non-interrupting event queue requires interrrupting event queue to
17 * refer to for wake-up events even if wake ups are never used.
18 * It could be even non-allocated event queue.
20 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
22 static __checkReturn boolean_t
25 __in efx_qword_t *eqp,
26 __in const efx_ev_callbacks_t *eecp,
29 static __checkReturn boolean_t
32 __in efx_qword_t *eqp,
33 __in const efx_ev_callbacks_t *eecp,
36 static __checkReturn boolean_t
39 __in efx_qword_t *eqp,
40 __in const efx_ev_callbacks_t *eecp,
43 static __checkReturn boolean_t
46 __in efx_qword_t *eqp,
47 __in const efx_ev_callbacks_t *eecp,
51 static __checkReturn efx_rc_t
54 __in uint32_t instance,
56 __in uint32_t timer_ns)
59 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_EVQ_TMR_IN_LEN,
60 MC_CMD_SET_EVQ_TMR_OUT_LEN);
63 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
64 req.emr_in_buf = payload;
65 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
66 req.emr_out_buf = payload;
67 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
69 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
70 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
71 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
72 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
74 efx_mcdi_execute(enp, &req);
76 if (req.emr_rc != 0) {
81 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
91 EFSYS_PROBE1(fail1, efx_rc_t, rc);
97 __checkReturn efx_rc_t
101 _NOTE(ARGUNUSED(enp))
109 _NOTE(ARGUNUSED(enp))
112 __checkReturn efx_rc_t
115 __in unsigned int index,
116 __in efsys_mem_t *esmp,
123 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
126 boolean_t low_latency;
128 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
131 * NO_CONT_EV mode is only requested from the firmware when creating
132 * receive queues, but here it needs to be specified at event queue
133 * creation, as the event handler needs to know which format is in use.
135 * If EFX_EVQ_FLAGS_NO_CONT_EV is specified, all receive queues for this
136 * event queue will be created in NO_CONT_EV mode.
138 * See SF-109306-TC 5.11 "Events for RXQs in NO_CONT_EV mode".
140 if (flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
141 if (enp->en_nic_cfg.enc_no_cont_ev_mode_supported == B_FALSE) {
147 /* Set up the handler table */
148 eep->ee_rx = ef10_ev_rx;
149 eep->ee_tx = ef10_ev_tx;
150 eep->ee_driver = ef10_ev_driver;
151 eep->ee_drv_gen = ef10_ev_drv_gen;
152 eep->ee_mcdi = ef10_ev_mcdi;
154 /* Set up the event queue */
155 /* INIT_EVQ expects function-relative vector number */
156 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
157 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
159 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
161 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
162 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
164 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
168 * Interrupts may be raised for events immediately after the queue is
169 * created. See bug58606.
173 * On Huntington we need to specify the settings to use.
174 * If event queue type in flags is auto, we favour throughput
175 * if the adapter is running virtualization supporting firmware
176 * (i.e. the full featured firmware variant)
177 * and latency otherwise. The Ethernet Virtual Bridging
178 * capability is used to make this decision. (Note though that
179 * the low latency firmware variant is also best for
180 * throughput and corresponding type should be specified
183 * If FW supports EvQ types (e.g. on Medford and Medford2) the
184 * type which is specified in flags is passed to FW to make the
185 * decision and low_latency hint is ignored.
187 low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
188 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
198 EFSYS_PROBE1(fail1, efx_rc_t, rc);
207 efx_nic_t *enp = eep->ee_enp;
209 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
211 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
214 __checkReturn efx_rc_t
217 __in unsigned int count)
219 efx_nic_t *enp = eep->ee_enp;
223 rptr = count & eep->ee_mask;
225 if (enp->en_nic_cfg.enc_bug35388_workaround) {
226 EFX_STATIC_ASSERT(EF10_EVQ_MINNEVS >
227 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
228 EFX_STATIC_ASSERT(EF10_EVQ_MAXNEVS <
229 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
231 EFX_POPULATE_DWORD_2(dword,
232 ERF_DD_EVQ_IND_RPTR_FLAGS,
233 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
235 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
236 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
239 EFX_POPULATE_DWORD_2(dword,
240 ERF_DD_EVQ_IND_RPTR_FLAGS,
241 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
243 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
244 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
247 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
248 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
255 static __checkReturn efx_rc_t
256 efx_mcdi_driver_event(
259 __in efx_qword_t data)
262 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_DRIVER_EVENT_IN_LEN,
263 MC_CMD_DRIVER_EVENT_OUT_LEN);
266 req.emr_cmd = MC_CMD_DRIVER_EVENT;
267 req.emr_in_buf = payload;
268 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
269 req.emr_out_buf = payload;
270 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
272 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
274 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
275 EFX_QWORD_FIELD(data, EFX_DWORD_0));
276 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
277 EFX_QWORD_FIELD(data, EFX_DWORD_1));
279 efx_mcdi_execute(enp, &req);
281 if (req.emr_rc != 0) {
289 EFSYS_PROBE1(fail1, efx_rc_t, rc);
299 efx_nic_t *enp = eep->ee_enp;
302 EFX_POPULATE_QWORD_3(event,
303 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
304 ESF_DZ_DRV_SUB_CODE, 0,
305 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
307 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
310 __checkReturn efx_rc_t
313 __in unsigned int us)
315 efx_nic_t *enp = eep->ee_enp;
316 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
321 /* Check that hardware and MCDI use the same timer MODE values */
322 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
323 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
324 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
325 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
326 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
327 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
328 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
329 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
331 if (us > encp->enc_evq_timer_max_us) {
336 /* If the value is zero then disable the timer */
338 mode = FFE_CZ_TIMER_MODE_DIS;
340 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
343 if (encp->enc_bug61265_workaround) {
344 uint32_t ns = us * 1000;
346 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
352 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
355 if (encp->enc_bug35388_workaround) {
356 EFX_POPULATE_DWORD_3(dword,
357 ERF_DD_EVQ_IND_TIMER_FLAGS,
358 EFE_DD_EVQ_IND_TIMER_FLAGS,
359 ERF_DD_EVQ_IND_TIMER_MODE, mode,
360 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
361 EFX_BAR_VI_WRITED(enp, ER_DD_EVQ_INDIRECT,
362 eep->ee_index, &dword, 0);
365 * NOTE: The TMR_REL field introduced in Medford2 is
366 * ignored on earlier EF10 controllers. See bug66418
367 * comment 9 for details.
369 EFX_POPULATE_DWORD_3(dword,
370 ERF_DZ_TC_TIMER_MODE, mode,
371 ERF_DZ_TC_TIMER_VAL, ticks,
372 ERF_FZ_TC_TMR_REL_VAL, ticks);
373 EFX_BAR_VI_WRITED(enp, ER_DZ_EVQ_TMR_REG,
374 eep->ee_index, &dword, 0);
385 EFSYS_PROBE1(fail1, efx_rc_t, rc);
393 ef10_ev_qstats_update(
395 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
399 for (id = 0; id < EV_NQSTATS; id++) {
400 efsys_stat_t *essp = &stat[id];
402 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
403 eep->ee_stat[id] = 0;
406 #endif /* EFSYS_OPT_QSTATS */
408 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
410 static __checkReturn boolean_t
411 ef10_ev_rx_packed_stream(
413 __in efx_qword_t *eqp,
414 __in const efx_ev_callbacks_t *eecp,
418 uint32_t pkt_count_lbits;
420 boolean_t should_abort;
421 efx_evq_rxq_state_t *eersp;
422 unsigned int pkt_count;
423 unsigned int current_id;
424 boolean_t new_buffer;
426 pkt_count_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
427 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
428 new_buffer = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_ROTATE);
432 eersp = &eep->ee_rxq_state[label];
435 * RX_DSC_PTR_LBITS has least significant bits of the global
436 * (not per-buffer) packet counter. It is guaranteed that
437 * maximum number of completed packets fits in lbits-mask.
438 * So, modulo lbits-mask arithmetic should be used to calculate
439 * packet counter increment.
441 pkt_count = (pkt_count_lbits - eersp->eers_rx_stream_npackets) &
442 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
443 eersp->eers_rx_stream_npackets += pkt_count;
446 flags |= EFX_PKT_PACKED_STREAM_NEW_BUFFER;
447 #if EFSYS_OPT_RX_PACKED_STREAM
449 * If both packed stream and equal stride super-buffer
450 * modes are compiled in, in theory credits should be
451 * be maintained for packed stream only, but right now
452 * these modes are not distinguished in the event queue
453 * Rx queue state and it is OK to increment the counter
454 * regardless (it might be event cheaper than branching
455 * since neighbour structure member are updated as well).
457 eersp->eers_rx_packed_stream_credits++;
459 eersp->eers_rx_read_ptr++;
461 current_id = eersp->eers_rx_read_ptr & eersp->eers_rx_mask;
463 /* Check for errors that invalidate checksum and L3/L4 fields */
464 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
465 /* RX frame truncated */
466 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
467 flags |= EFX_DISCARD;
470 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
471 /* Bad Ethernet frame CRC */
472 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
473 flags |= EFX_DISCARD;
477 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
478 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
479 flags |= EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE;
483 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR))
484 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
486 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR))
487 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
490 /* If we're not discarding the packet then it is ok */
491 if (~flags & EFX_DISCARD)
492 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
494 EFSYS_ASSERT(eecp->eec_rx_ps != NULL);
495 should_abort = eecp->eec_rx_ps(arg, label, current_id, pkt_count,
498 return (should_abort);
501 #endif /* EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER */
503 static __checkReturn boolean_t
506 __in efx_qword_t *eqp,
507 __in const efx_ev_callbacks_t *eecp,
510 efx_nic_t *enp = eep->ee_enp;
514 uint32_t eth_tag_class;
517 uint32_t next_read_lbits;
520 boolean_t should_abort;
521 efx_evq_rxq_state_t *eersp;
522 unsigned int desc_count;
523 unsigned int last_used_id;
525 EFX_EV_QSTAT_INCR(eep, EV_RX);
527 /* Discard events after RXQ/TXQ errors, or hardware not available */
528 if (enp->en_reset_flags &
529 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
532 /* Basic packet information */
533 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
534 eersp = &eep->ee_rxq_state[label];
536 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
538 * Packed stream events are very different,
539 * so handle them separately
541 if (eersp->eers_rx_packed_stream)
542 return (ef10_ev_rx_packed_stream(eep, eqp, eecp, arg));
545 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
546 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
547 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
548 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
549 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
550 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
553 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
554 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
555 * and values for all EF10 controllers.
557 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN == ESF_DE_RX_L4_CLASS_LBN);
558 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
559 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
560 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN == ESE_DE_L4_CLASS_UNKNOWN);
562 l4_class = EFX_QWORD_FIELD(*eqp, ESF_FZ_RX_L4_CLASS);
564 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
565 /* Drop this event */
572 * This may be part of a scattered frame, or it may be a
573 * truncated frame if scatter is disabled on this RXQ.
574 * Overlength frames can be received if e.g. a VF is configured
575 * for 1500 MTU but connected to a port set to 9000 MTU
577 * FIXME: There is not yet any driver that supports scatter on
578 * Huntington. Scatter support is required for OSX.
580 flags |= EFX_PKT_CONT;
583 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
584 flags |= EFX_PKT_UNICAST;
587 * Increment the count of descriptors read.
589 * In NO_CONT_EV mode, RX_DSC_PTR_LBITS is actually a packet count, but
590 * when scatter is disabled, there is only one descriptor per packet and
591 * so it can be treated the same.
593 * TODO: Support scatter in NO_CONT_EV mode.
595 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
596 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
597 eersp->eers_rx_read_ptr += desc_count;
599 /* Calculate the index of the last descriptor consumed */
600 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
602 if (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV) {
604 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
606 /* Always read the length from the prefix in NO_CONT_EV mode. */
607 flags |= EFX_PKT_PREFIX_LEN;
610 * Check for an aborted scatter, signalled by the ABORT bit in
611 * NO_CONT_EV mode. The ABORT bit was not used before NO_CONT_EV
612 * mode was added as it was broken in Huntington silicon.
614 if (EFX_QWORD_FIELD(*eqp, ESF_EZ_RX_ABORT) != 0) {
615 flags |= EFX_DISCARD;
618 } else if (desc_count > 1) {
620 * FIXME: add error checking to make sure this a batched event.
621 * This could also be an aborted scatter, see Bug36629.
623 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
624 flags |= EFX_PKT_PREFIX_LEN;
627 /* Check for errors that invalidate checksum and L3/L4 fields */
628 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {
629 /* RX frame truncated */
630 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
631 flags |= EFX_DISCARD;
634 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
635 /* Bad Ethernet frame CRC */
636 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
637 flags |= EFX_DISCARD;
640 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
642 * Hardware parse failed, due to malformed headers
643 * or headers that are too long for the parser.
644 * Headers and checksums must be validated by the host.
646 EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
650 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
651 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
652 flags |= EFX_PKT_VLAN_TAGGED;
656 case ESE_DZ_L3_CLASS_IP4:
657 case ESE_DZ_L3_CLASS_IP4_FRAG:
658 flags |= EFX_PKT_IPV4;
659 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
660 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
662 flags |= EFX_CKSUM_IPV4;
666 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
667 * only 2 bits wide on Medford2. Check it is safe to use the
668 * Medford2 field and values for all EF10 controllers.
670 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
671 ESF_DE_RX_L4_CLASS_LBN);
672 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
673 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
674 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
675 ESE_DE_L4_CLASS_UNKNOWN);
677 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
678 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
679 flags |= EFX_PKT_TCP;
680 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
681 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
682 flags |= EFX_PKT_UDP;
684 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
688 case ESE_DZ_L3_CLASS_IP6:
689 case ESE_DZ_L3_CLASS_IP6_FRAG:
690 flags |= EFX_PKT_IPV6;
693 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is
694 * only 2 bits wide on Medford2. Check it is safe to use the
695 * Medford2 field and values for all EF10 controllers.
697 EFX_STATIC_ASSERT(ESF_FZ_RX_L4_CLASS_LBN ==
698 ESF_DE_RX_L4_CLASS_LBN);
699 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_TCP == ESE_DE_L4_CLASS_TCP);
700 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UDP == ESE_DE_L4_CLASS_UDP);
701 EFX_STATIC_ASSERT(ESE_FZ_L4_CLASS_UNKNOWN ==
702 ESE_DE_L4_CLASS_UNKNOWN);
704 if (l4_class == ESE_FZ_L4_CLASS_TCP) {
705 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
706 flags |= EFX_PKT_TCP;
707 } else if (l4_class == ESE_FZ_L4_CLASS_UDP) {
708 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
709 flags |= EFX_PKT_UDP;
711 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
716 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
720 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
721 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
722 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
724 flags |= EFX_CKSUM_TCPUDP;
729 /* If we're not discarding the packet then it is ok */
730 if (~flags & EFX_DISCARD)
731 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
733 EFSYS_ASSERT(eecp->eec_rx != NULL);
734 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
736 return (should_abort);
739 static __checkReturn boolean_t
742 __in efx_qword_t *eqp,
743 __in const efx_ev_callbacks_t *eecp,
746 efx_nic_t *enp = eep->ee_enp;
749 boolean_t should_abort;
751 EFX_EV_QSTAT_INCR(eep, EV_TX);
753 /* Discard events after RXQ/TXQ errors, or hardware not available */
754 if (enp->en_reset_flags &
755 (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR | EFX_RESET_HW_UNAVAIL))
758 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
759 /* Drop this event */
763 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
764 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
765 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
767 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
769 EFSYS_ASSERT(eecp->eec_tx != NULL);
770 should_abort = eecp->eec_tx(arg, label, id);
772 return (should_abort);
775 static __checkReturn boolean_t
778 __in efx_qword_t *eqp,
779 __in const efx_ev_callbacks_t *eecp,
783 boolean_t should_abort;
785 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
786 should_abort = B_FALSE;
788 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
790 case ESE_DZ_DRV_TIMER_EV: {
793 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
795 EFSYS_ASSERT(eecp->eec_timer != NULL);
796 should_abort = eecp->eec_timer(arg, id);
800 case ESE_DZ_DRV_WAKE_UP_EV: {
803 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
805 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
806 should_abort = eecp->eec_wake_up(arg, id);
810 case ESE_DZ_DRV_START_UP_EV:
811 EFSYS_ASSERT(eecp->eec_initialized != NULL);
812 should_abort = eecp->eec_initialized(arg);
816 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
817 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
818 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
822 return (should_abort);
825 static __checkReturn boolean_t
828 __in efx_qword_t *eqp,
829 __in const efx_ev_callbacks_t *eecp,
833 boolean_t should_abort;
835 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
836 should_abort = B_FALSE;
838 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
839 if (data >= ((uint32_t)1 << 16)) {
840 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
841 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
842 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
847 EFSYS_ASSERT(eecp->eec_software != NULL);
848 should_abort = eecp->eec_software(arg, (uint16_t)data);
850 return (should_abort);
853 #endif /* EFX_OPTS_EF10() */
855 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
857 __checkReturn boolean_t
860 __in efx_qword_t *eqp,
861 __in const efx_ev_callbacks_t *eecp,
864 efx_nic_t *enp = eep->ee_enp;
866 boolean_t should_abort = B_FALSE;
868 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
870 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
872 case MCDI_EVENT_CODE_BADSSERT:
873 efx_mcdi_ev_death(enp, EINTR);
876 case MCDI_EVENT_CODE_CMDDONE:
878 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
879 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
880 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
883 #if EFSYS_OPT_MCDI_PROXY_AUTH
884 case MCDI_EVENT_CODE_PROXY_RESPONSE:
886 * This event notifies a function that an authorization request
887 * has been processed. If the request was authorized then the
888 * function can now re-send the original MCDI request.
889 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
891 efx_mcdi_ev_proxy_response(enp,
892 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
893 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
895 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
897 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
898 case MCDI_EVENT_CODE_PROXY_REQUEST:
899 efx_mcdi_ev_proxy_request(enp,
900 MCDI_EV_FIELD(eqp, PROXY_REQUEST_BUFF_INDEX));
902 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
904 case MCDI_EVENT_CODE_LINKCHANGE: {
905 efx_link_mode_t link_mode;
907 ef10_phy_link_ev(enp, eqp, &link_mode);
908 should_abort = eecp->eec_link_change(arg, link_mode);
912 case MCDI_EVENT_CODE_SENSOREVT: {
913 #if EFSYS_OPT_MON_STATS
915 efx_mon_stat_value_t value;
918 /* Decode monitor stat for MCDI sensor (if supported) */
919 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
920 /* Report monitor stat change */
921 should_abort = eecp->eec_monitor(arg, id, value);
922 } else if (rc == ENOTSUP) {
923 should_abort = eecp->eec_exception(arg,
924 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
925 MCDI_EV_FIELD(eqp, DATA));
927 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
933 case MCDI_EVENT_CODE_SCHEDERR:
934 /* Informational only */
937 case MCDI_EVENT_CODE_REBOOT:
938 /* Falcon/Siena only (should not been seen with Huntington). */
939 efx_mcdi_ev_death(enp, EIO);
942 case MCDI_EVENT_CODE_MC_REBOOT:
943 /* MC_REBOOT event is used for Huntington (EF10) and later. */
944 efx_mcdi_ev_death(enp, EIO);
947 case MCDI_EVENT_CODE_MAC_STATS_DMA:
948 #if EFSYS_OPT_MAC_STATS
949 if (eecp->eec_mac_stats != NULL) {
950 eecp->eec_mac_stats(arg,
951 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
956 case MCDI_EVENT_CODE_FWALERT: {
957 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
959 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
960 should_abort = eecp->eec_exception(arg,
961 EFX_EXCEPTION_FWALERT_SRAM,
962 MCDI_EV_FIELD(eqp, FWALERT_DATA));
964 should_abort = eecp->eec_exception(arg,
965 EFX_EXCEPTION_UNKNOWN_FWALERT,
966 MCDI_EV_FIELD(eqp, DATA));
970 case MCDI_EVENT_CODE_TX_ERR: {
972 * After a TXQ error is detected, firmware sends a TX_ERR event.
973 * This may be followed by TX completions (which we discard),
974 * and then finally by a TX_FLUSH event. Firmware destroys the
975 * TXQ automatically after sending the TX_FLUSH event.
977 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
979 EFSYS_PROBE2(tx_descq_err,
980 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
981 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
983 /* Inform the driver that a reset is required. */
984 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
985 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
989 case MCDI_EVENT_CODE_TX_FLUSH: {
990 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
993 * EF10 firmware sends two TX_FLUSH events: one to the txq's
994 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
995 * We want to wait for all completions, so ignore the events
996 * with TX_FLUSH_TO_DRIVER.
998 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
999 should_abort = B_FALSE;
1003 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1005 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1007 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1008 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1012 case MCDI_EVENT_CODE_RX_ERR: {
1014 * After an RXQ error is detected, firmware sends an RX_ERR
1015 * event. This may be followed by RX events (which we discard),
1016 * and then finally by an RX_FLUSH event. Firmware destroys the
1017 * RXQ automatically after sending the RX_FLUSH event.
1019 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1021 EFSYS_PROBE2(rx_descq_err,
1022 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1023 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1025 /* Inform the driver that a reset is required. */
1026 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1027 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1031 case MCDI_EVENT_CODE_RX_FLUSH: {
1032 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1035 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1036 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1037 * We want to wait for all completions, so ignore the events
1038 * with RX_FLUSH_TO_DRIVER.
1040 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1041 should_abort = B_FALSE;
1045 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1047 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1049 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1050 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1055 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1056 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1057 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1061 return (should_abort);
1064 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1069 ef10_ev_rxlabel_init(
1070 __in efx_evq_t *eep,
1071 __in efx_rxq_t *erp,
1072 __in unsigned int label,
1073 __in efx_rxq_type_t type)
1075 efx_evq_rxq_state_t *eersp;
1076 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1077 boolean_t packed_stream = (type == EFX_RXQ_TYPE_PACKED_STREAM);
1078 boolean_t es_super_buffer = (type == EFX_RXQ_TYPE_ES_SUPER_BUFFER);
1081 _NOTE(ARGUNUSED(type))
1082 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1083 eersp = &eep->ee_rxq_state[label];
1085 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1087 #if EFSYS_OPT_RX_PACKED_STREAM
1089 * For packed stream modes, the very first event will
1090 * have a new buffer flag set, so it will be incremented,
1091 * yielding the correct pointer. That results in a simpler
1092 * code than trying to detect start-of-the-world condition
1093 * in the event handler.
1095 eersp->eers_rx_read_ptr = packed_stream ? ~0 : 0;
1097 eersp->eers_rx_read_ptr = 0;
1099 eersp->eers_rx_mask = erp->er_mask;
1100 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1101 eersp->eers_rx_stream_npackets = 0;
1102 eersp->eers_rx_packed_stream = packed_stream || es_super_buffer;
1104 #if EFSYS_OPT_RX_PACKED_STREAM
1105 if (packed_stream) {
1106 eersp->eers_rx_packed_stream_credits = (eep->ee_mask + 1) /
1107 EFX_DIV_ROUND_UP(EFX_RX_PACKED_STREAM_MEM_PER_CREDIT,
1108 EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE);
1109 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, !=, 0);
1111 * A single credit is allocated to the queue when it is started.
1112 * It is immediately spent by the first packet which has NEW
1113 * BUFFER flag set, though, but still we shall take into
1114 * account, as to not wrap around the maximum number of credits
1117 eersp->eers_rx_packed_stream_credits--;
1118 EFSYS_ASSERT3U(eersp->eers_rx_packed_stream_credits, <=,
1119 EFX_RX_PACKED_STREAM_MAX_CREDITS);
1125 ef10_ev_rxlabel_fini(
1126 __in efx_evq_t *eep,
1127 __in unsigned int label)
1129 efx_evq_rxq_state_t *eersp;
1131 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1132 eersp = &eep->ee_rxq_state[label];
1134 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1136 eersp->eers_rx_read_ptr = 0;
1137 eersp->eers_rx_mask = 0;
1138 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1139 eersp->eers_rx_stream_npackets = 0;
1140 eersp->eers_rx_packed_stream = B_FALSE;
1142 #if EFSYS_OPT_RX_PACKED_STREAM
1143 eersp->eers_rx_packed_stream_credits = 0;
1147 #endif /* EFX_OPTS_EF10() */