1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
20 #define EF10_TXQ_MINNDESCS 512
22 #define EF10_EVQ_DESC_SIZE (sizeof (efx_qword_t))
23 #define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t))
24 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
26 /* Number of hardware EVQ buffers (for compile-time resource dimensions) */
27 #define EF10_EVQ_MAXNBUFS (64)
29 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
30 #define EF10_TXQ_MAXNBUFS 8
32 #if EFSYS_OPT_HUNTINGTON
33 # if (EF10_EVQ_MAXNBUFS < HUNT_EVQ_MAXNBUFS)
34 # error "EF10_EVQ_MAXNBUFS too small"
36 #endif /* EFSYS_OPT_HUNTINGTON */
38 # if (EF10_EVQ_MAXNBUFS < MEDFORD_EVQ_MAXNBUFS)
39 # error "EF10_EVQ_MAXNBUFS too small"
41 #endif /* EFSYS_OPT_MEDFORD */
42 #if EFSYS_OPT_MEDFORD2
43 # if (EF10_EVQ_MAXNBUFS < MEDFORD2_EVQ_MAXNBUFS)
44 # error "EF10_EVQ_MAXNBUFS too small"
46 #endif /* EFSYS_OPT_MEDFORD2 */
48 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
49 #define EF10_MAX_PIOBUF_NBUFS (16)
51 #if EFSYS_OPT_HUNTINGTON
52 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
53 # error "EF10_MAX_PIOBUF_NBUFS too small"
55 #endif /* EFSYS_OPT_HUNTINGTON */
57 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
58 # error "EF10_MAX_PIOBUF_NBUFS too small"
60 #endif /* EFSYS_OPT_MEDFORD */
61 #if EFSYS_OPT_MEDFORD2
62 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
63 # error "EF10_MAX_PIOBUF_NBUFS too small"
65 #endif /* EFSYS_OPT_MEDFORD2 */
70 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
71 * possibly be increased, or the write size reported by newer firmware used
74 #define EF10_NVRAM_CHUNK 0x80
77 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
78 * to an 8 descriptor boundary.
80 #define EF10_RX_WPTR_ALIGN 8
83 * Max byte offset into the packet the TCP header must start for the hardware
84 * to be able to parse the packet correctly.
86 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
88 /* Invalid RSS context handle */
89 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
95 extern __checkReturn efx_rc_t
102 __in efx_nic_t *enp);
105 extern __checkReturn efx_rc_t
108 __in unsigned int index,
109 __in efsys_mem_t *esmp,
115 __in efx_evq_t *eep);
120 __in efx_evq_t *eep);
123 extern __checkReturn efx_rc_t
126 __in unsigned int count);
135 extern __checkReturn efx_rc_t
138 __in unsigned int us);
143 ef10_ev_qstats_update(
145 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
146 #endif /* EFSYS_OPT_QSTATS */
150 ef10_ev_rxlabel_init(
153 __in unsigned int label,
154 __in efx_rxq_type_t type);
158 ef10_ev_rxlabel_fini(
160 __in unsigned int label);
163 extern __checkReturn boolean_t
166 __in efx_qword_t *eqp,
167 __in const efx_ev_callbacks_t *eecp,
173 extern __checkReturn efx_rc_t
176 __in efx_intr_type_t type,
177 __in efsys_mem_t *esmp);
182 __in efx_nic_t *enp);
187 __in efx_nic_t *enp);
191 ef10_intr_disable_unlocked(
192 __in efx_nic_t *enp);
195 extern __checkReturn efx_rc_t
198 __in unsigned int level);
202 ef10_intr_status_line(
204 __out boolean_t *fatalp,
205 __out uint32_t *qmaskp);
209 ef10_intr_status_message(
211 __in unsigned int message,
212 __out boolean_t *fatalp);
217 __in efx_nic_t *enp);
222 __in efx_nic_t *enp);
227 extern __checkReturn efx_rc_t
228 efx_mcdi_vadaptor_alloc(
230 __in uint32_t port_id);
233 extern __checkReturn efx_rc_t
234 efx_mcdi_vadaptor_free(
236 __in uint32_t port_id);
239 extern __checkReturn efx_rc_t
240 ef10_upstream_port_vadaptor_alloc(
241 __in efx_nic_t *enp);
244 extern __checkReturn efx_rc_t
246 __in efx_nic_t *enp);
249 extern __checkReturn efx_rc_t
250 ef10_nic_set_drv_limits(
251 __inout efx_nic_t *enp,
252 __in efx_drv_limits_t *edlp);
255 extern __checkReturn efx_rc_t
256 ef10_nic_get_vi_pool(
258 __out uint32_t *vi_countp);
261 extern __checkReturn efx_rc_t
262 ef10_nic_get_bar_region(
264 __in efx_nic_region_t region,
265 __out uint32_t *offsetp,
266 __out size_t *sizep);
269 extern __checkReturn efx_rc_t
271 __in efx_nic_t *enp);
274 extern __checkReturn efx_rc_t
276 __in efx_nic_t *enp);
279 extern __checkReturn boolean_t
280 ef10_nic_hw_unavailable(
281 __in efx_nic_t *enp);
285 ef10_nic_set_hw_unavailable(
286 __in efx_nic_t *enp);
291 extern __checkReturn efx_rc_t
292 ef10_nic_register_test(
293 __in efx_nic_t *enp);
295 #endif /* EFSYS_OPT_DIAG */
300 __in efx_nic_t *enp);
305 __in efx_nic_t *enp);
311 extern __checkReturn efx_rc_t
314 __out efx_link_mode_t *link_modep);
317 extern __checkReturn efx_rc_t
320 __out boolean_t *mac_upp);
323 extern __checkReturn efx_rc_t
325 __in efx_nic_t *enp);
328 extern __checkReturn efx_rc_t
330 __in efx_nic_t *enp);
333 extern __checkReturn efx_rc_t
339 extern __checkReturn efx_rc_t
340 ef10_mac_reconfigure(
341 __in efx_nic_t *enp);
344 extern __checkReturn efx_rc_t
345 ef10_mac_multicast_list_set(
346 __in efx_nic_t *enp);
349 extern __checkReturn efx_rc_t
350 ef10_mac_filter_default_rxq_set(
353 __in boolean_t using_rss);
357 ef10_mac_filter_default_rxq_clear(
358 __in efx_nic_t *enp);
360 #if EFSYS_OPT_LOOPBACK
363 extern __checkReturn efx_rc_t
364 ef10_mac_loopback_set(
366 __in efx_link_mode_t link_mode,
367 __in efx_loopback_type_t loopback_type);
369 #endif /* EFSYS_OPT_LOOPBACK */
371 #if EFSYS_OPT_MAC_STATS
374 extern __checkReturn efx_rc_t
375 ef10_mac_stats_get_mask(
377 __inout_bcount(mask_size) uint32_t *maskp,
378 __in size_t mask_size);
381 extern __checkReturn efx_rc_t
382 ef10_mac_stats_update(
384 __in efsys_mem_t *esmp,
385 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
386 __inout_opt uint32_t *generationp);
388 #endif /* EFSYS_OPT_MAC_STATS */
396 extern __checkReturn efx_rc_t
399 __in const efx_mcdi_transport_t *mtp);
404 __in efx_nic_t *enp);
408 ef10_mcdi_send_request(
410 __in_bcount(hdr_len) void *hdrp,
412 __in_bcount(sdu_len) void *sdup,
413 __in size_t sdu_len);
416 extern __checkReturn boolean_t
417 ef10_mcdi_poll_response(
418 __in efx_nic_t *enp);
422 ef10_mcdi_read_response(
424 __out_bcount(length) void *bufferp,
430 ef10_mcdi_poll_reboot(
431 __in efx_nic_t *enp);
434 extern __checkReturn efx_rc_t
435 ef10_mcdi_feature_supported(
437 __in efx_mcdi_feature_id_t id,
438 __out boolean_t *supportedp);
442 ef10_mcdi_get_timeout(
444 __in efx_mcdi_req_t *emrp,
445 __out uint32_t *timeoutp);
447 #endif /* EFSYS_OPT_MCDI */
451 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
454 extern __checkReturn efx_rc_t
455 ef10_nvram_buf_read_tlv(
457 __in_bcount(max_seg_size) caddr_t seg_data,
458 __in size_t max_seg_size,
460 __deref_out_bcount_opt(*sizep) caddr_t *datap,
461 __out size_t *sizep);
464 extern __checkReturn efx_rc_t
465 ef10_nvram_buf_write_tlv(
466 __inout_bcount(partn_size) caddr_t partn_data,
467 __in size_t partn_size,
469 __in_bcount(tag_size) caddr_t tag_data,
470 __in size_t tag_size,
471 __out size_t *total_lengthp);
474 extern __checkReturn efx_rc_t
475 ef10_nvram_partn_read_tlv(
479 __deref_out_bcount_opt(*sizep) caddr_t *datap,
480 __out size_t *sizep);
483 extern __checkReturn efx_rc_t
484 ef10_nvram_partn_write_tlv(
488 __in_bcount(size) caddr_t data,
492 extern __checkReturn efx_rc_t
493 ef10_nvram_partn_write_segment_tlv(
497 __in_bcount(size) caddr_t data,
499 __in boolean_t all_segments);
502 extern __checkReturn efx_rc_t
503 ef10_nvram_partn_lock(
505 __in uint32_t partn);
508 extern __checkReturn efx_rc_t
509 ef10_nvram_partn_unlock(
512 __out_opt uint32_t *resultp);
514 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
521 extern __checkReturn efx_rc_t
523 __in efx_nic_t *enp);
525 #endif /* EFSYS_OPT_DIAG */
528 extern __checkReturn efx_rc_t
529 ef10_nvram_type_to_partn(
531 __in efx_nvram_type_t type,
532 __out uint32_t *partnp);
535 extern __checkReturn efx_rc_t
536 ef10_nvram_partn_size(
539 __out size_t *sizep);
542 extern __checkReturn efx_rc_t
543 ef10_nvram_partn_info(
546 __out efx_nvram_info_t * enip);
549 extern __checkReturn efx_rc_t
550 ef10_nvram_partn_rw_start(
553 __out size_t *chunk_sizep);
556 extern __checkReturn efx_rc_t
557 ef10_nvram_partn_read_mode(
560 __in unsigned int offset,
561 __out_bcount(size) caddr_t data,
566 extern __checkReturn efx_rc_t
567 ef10_nvram_partn_read(
570 __in unsigned int offset,
571 __out_bcount(size) caddr_t data,
575 extern __checkReturn efx_rc_t
576 ef10_nvram_partn_read_backup(
579 __in unsigned int offset,
580 __out_bcount(size) caddr_t data,
584 extern __checkReturn efx_rc_t
585 ef10_nvram_partn_erase(
588 __in unsigned int offset,
592 extern __checkReturn efx_rc_t
593 ef10_nvram_partn_write(
596 __in unsigned int offset,
597 __in_bcount(size) caddr_t data,
601 extern __checkReturn efx_rc_t
602 ef10_nvram_partn_rw_finish(
605 __out_opt uint32_t *verify_resultp);
608 extern __checkReturn efx_rc_t
609 ef10_nvram_partn_get_version(
612 __out uint32_t *subtypep,
613 __out_ecount(4) uint16_t version[4]);
616 extern __checkReturn efx_rc_t
617 ef10_nvram_partn_set_version(
620 __in_ecount(4) uint16_t version[4]);
623 extern __checkReturn efx_rc_t
624 ef10_nvram_buffer_validate(
626 __in_bcount(buffer_size)
628 __in size_t buffer_size);
632 ef10_nvram_buffer_init(
633 __out_bcount(buffer_size)
635 __in size_t buffer_size);
638 extern __checkReturn efx_rc_t
639 ef10_nvram_buffer_create(
640 __in uint32_t partn_type,
641 __out_bcount(buffer_size)
643 __in size_t buffer_size);
646 extern __checkReturn efx_rc_t
647 ef10_nvram_buffer_find_item_start(
648 __in_bcount(buffer_size)
650 __in size_t buffer_size,
651 __out uint32_t *startp);
654 extern __checkReturn efx_rc_t
655 ef10_nvram_buffer_find_end(
656 __in_bcount(buffer_size)
658 __in size_t buffer_size,
659 __in uint32_t offset,
660 __out uint32_t *endp);
663 extern __checkReturn __success(return != B_FALSE) boolean_t
664 ef10_nvram_buffer_find_item(
665 __in_bcount(buffer_size)
667 __in size_t buffer_size,
668 __in uint32_t offset,
669 __out uint32_t *startp,
670 __out uint32_t *lengthp);
673 extern __checkReturn efx_rc_t
674 ef10_nvram_buffer_peek_item(
675 __in_bcount(buffer_size)
677 __in size_t buffer_size,
678 __in uint32_t offset,
679 __out uint32_t *tagp,
680 __out uint32_t *lengthp,
681 __out uint32_t *value_offsetp);
684 extern __checkReturn efx_rc_t
685 ef10_nvram_buffer_get_item(
686 __in_bcount(buffer_size)
688 __in size_t buffer_size,
689 __in uint32_t offset,
690 __in uint32_t length,
691 __out uint32_t *tagp,
692 __out_bcount_part(value_max_size, *lengthp)
694 __in size_t value_max_size,
695 __out uint32_t *lengthp);
698 extern __checkReturn efx_rc_t
699 ef10_nvram_buffer_insert_item(
700 __in_bcount(buffer_size)
702 __in size_t buffer_size,
703 __in uint32_t offset,
705 __in_bcount(length) caddr_t valuep,
706 __in uint32_t length,
707 __out uint32_t *lengthp);
710 extern __checkReturn efx_rc_t
711 ef10_nvram_buffer_modify_item(
712 __in_bcount(buffer_size)
714 __in size_t buffer_size,
715 __in uint32_t offset,
717 __in_bcount(length) caddr_t valuep,
718 __in uint32_t length,
719 __out uint32_t *lengthp);
722 extern __checkReturn efx_rc_t
723 ef10_nvram_buffer_delete_item(
724 __in_bcount(buffer_size)
726 __in size_t buffer_size,
727 __in uint32_t offset,
728 __in uint32_t length,
732 extern __checkReturn efx_rc_t
733 ef10_nvram_buffer_finish(
734 __in_bcount(buffer_size)
736 __in size_t buffer_size);
738 #endif /* EFSYS_OPT_NVRAM */
743 typedef struct ef10_link_state_s {
744 efx_phy_link_state_t epls;
745 #if EFSYS_OPT_LOOPBACK
746 efx_loopback_type_t els_loopback;
748 boolean_t els_mac_up;
755 __in efx_qword_t *eqp,
756 __out efx_link_mode_t *link_modep);
759 extern __checkReturn efx_rc_t
762 __out ef10_link_state_t *elsp);
765 extern __checkReturn efx_rc_t
771 extern __checkReturn efx_rc_t
772 ef10_phy_reconfigure(
773 __in efx_nic_t *enp);
776 extern __checkReturn efx_rc_t
778 __in efx_nic_t *enp);
781 extern __checkReturn efx_rc_t
784 __out uint32_t *ouip);
787 extern __checkReturn efx_rc_t
788 ef10_phy_link_state_get(
790 __out efx_phy_link_state_t *eplsp);
792 #if EFSYS_OPT_PHY_STATS
795 extern __checkReturn efx_rc_t
796 ef10_phy_stats_update(
798 __in efsys_mem_t *esmp,
799 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
801 #endif /* EFSYS_OPT_PHY_STATS */
806 extern __checkReturn efx_rc_t
807 ef10_bist_enable_offline(
808 __in efx_nic_t *enp);
811 extern __checkReturn efx_rc_t
814 __in efx_bist_type_t type);
817 extern __checkReturn efx_rc_t
820 __in efx_bist_type_t type,
821 __out efx_bist_result_t *resultp,
822 __out_opt __drv_when(count > 0, __notnull)
823 uint32_t *value_maskp,
824 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
825 unsigned long *valuesp,
832 __in efx_bist_type_t type);
834 #endif /* EFSYS_OPT_BIST */
839 extern __checkReturn efx_rc_t
841 __in efx_nic_t *enp);
846 __in efx_nic_t *enp);
849 extern __checkReturn efx_rc_t
852 __in unsigned int index,
853 __in unsigned int label,
854 __in efsys_mem_t *esmp,
860 __out unsigned int *addedp);
865 __in efx_txq_t *etp);
868 extern __checkReturn efx_rc_t
871 __in_ecount(ndescs) efx_buffer_t *ebp,
872 __in unsigned int ndescs,
873 __in unsigned int completed,
874 __inout unsigned int *addedp);
880 __in unsigned int added,
881 __in unsigned int pushed);
883 #if EFSYS_OPT_RX_PACKED_STREAM
886 ef10_rx_qpush_ps_credits(
887 __in efx_rxq_t *erp);
890 extern __checkReturn uint8_t *
891 ef10_rx_qps_packet_info(
893 __in uint8_t *buffer,
894 __in uint32_t buffer_length,
895 __in uint32_t current_offset,
896 __out uint16_t *lengthp,
897 __out uint32_t *next_offsetp,
898 __out uint32_t *timestamp);
902 extern __checkReturn efx_rc_t
905 __in unsigned int ns);
908 extern __checkReturn efx_rc_t
910 __in efx_txq_t *etp);
915 __in efx_txq_t *etp);
918 extern __checkReturn efx_rc_t
920 __in efx_txq_t *etp);
924 ef10_tx_qpio_disable(
925 __in efx_txq_t *etp);
928 extern __checkReturn efx_rc_t
931 __in_ecount(buf_length) uint8_t *buffer,
932 __in size_t buf_length,
933 __in size_t pio_buf_offset);
936 extern __checkReturn efx_rc_t
939 __in size_t pkt_length,
940 __in unsigned int completed,
941 __inout unsigned int *addedp);
944 extern __checkReturn efx_rc_t
947 __in_ecount(n) efx_desc_t *ed,
949 __in unsigned int completed,
950 __inout unsigned int *addedp);
954 ef10_tx_qdesc_dma_create(
956 __in efsys_dma_addr_t addr,
959 __out efx_desc_t *edp);
963 ef10_tx_qdesc_tso_create(
965 __in uint16_t ipv4_id,
966 __in uint32_t tcp_seq,
967 __in uint8_t tcp_flags,
968 __out efx_desc_t *edp);
972 ef10_tx_qdesc_tso2_create(
974 __in uint16_t ipv4_id,
975 __in uint16_t outer_ipv4_id,
976 __in uint32_t tcp_seq,
977 __in uint16_t tcp_mss,
978 __out_ecount(count) efx_desc_t *edp,
983 ef10_tx_qdesc_vlantci_create(
985 __in uint16_t vlan_tci,
986 __out efx_desc_t *edp);
990 ef10_tx_qdesc_checksum_create(
993 __out efx_desc_t *edp);
999 ef10_tx_qstats_update(
1000 __in efx_txq_t *etp,
1001 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1003 #endif /* EFSYS_OPT_QSTATS */
1005 typedef uint32_t efx_piobuf_handle_t;
1007 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
1010 extern __checkReturn efx_rc_t
1012 __inout efx_nic_t *enp,
1013 __out uint32_t *bufnump,
1014 __out efx_piobuf_handle_t *handlep,
1015 __out uint32_t *blknump,
1016 __out uint32_t *offsetp,
1017 __out size_t *sizep);
1020 extern __checkReturn efx_rc_t
1022 __inout efx_nic_t *enp,
1023 __in uint32_t bufnum,
1024 __in uint32_t blknum);
1027 extern __checkReturn efx_rc_t
1029 __inout efx_nic_t *enp,
1030 __in uint32_t vi_index,
1031 __in efx_piobuf_handle_t handle);
1034 extern __checkReturn efx_rc_t
1035 ef10_nic_pio_unlink(
1036 __inout efx_nic_t *enp,
1037 __in uint32_t vi_index);
1045 extern __checkReturn efx_rc_t
1047 __in efx_nic_t *enp);
1050 extern __checkReturn efx_rc_t
1052 __in efx_nic_t *enp,
1053 __out size_t *sizep);
1056 extern __checkReturn efx_rc_t
1058 __in efx_nic_t *enp,
1059 __out_bcount(size) caddr_t data,
1063 extern __checkReturn efx_rc_t
1065 __in efx_nic_t *enp,
1066 __in_bcount(size) caddr_t data,
1070 extern __checkReturn efx_rc_t
1072 __in efx_nic_t *enp,
1073 __in_bcount(size) caddr_t data,
1077 extern __checkReturn efx_rc_t
1079 __in efx_nic_t *enp,
1080 __in_bcount(size) caddr_t data,
1082 __inout efx_vpd_value_t *evvp);
1085 extern __checkReturn efx_rc_t
1087 __in efx_nic_t *enp,
1088 __in_bcount(size) caddr_t data,
1090 __in efx_vpd_value_t *evvp);
1093 extern __checkReturn efx_rc_t
1095 __in efx_nic_t *enp,
1096 __in_bcount(size) caddr_t data,
1098 __out efx_vpd_value_t *evvp,
1099 __inout unsigned int *contp);
1102 extern __checkReturn efx_rc_t
1104 __in efx_nic_t *enp,
1105 __in_bcount(size) caddr_t data,
1111 __in efx_nic_t *enp);
1113 #endif /* EFSYS_OPT_VPD */
1119 extern __checkReturn efx_rc_t
1121 __in efx_nic_t *enp);
1123 #if EFSYS_OPT_RX_SCATTER
1125 extern __checkReturn efx_rc_t
1126 ef10_rx_scatter_enable(
1127 __in efx_nic_t *enp,
1128 __in unsigned int buf_size);
1129 #endif /* EFSYS_OPT_RX_SCATTER */
1132 #if EFSYS_OPT_RX_SCALE
1135 extern __checkReturn efx_rc_t
1136 ef10_rx_scale_context_alloc(
1137 __in efx_nic_t *enp,
1138 __in efx_rx_scale_context_type_t type,
1139 __in uint32_t num_queues,
1140 __out uint32_t *rss_contextp);
1143 extern __checkReturn efx_rc_t
1144 ef10_rx_scale_context_free(
1145 __in efx_nic_t *enp,
1146 __in uint32_t rss_context);
1149 extern __checkReturn efx_rc_t
1150 ef10_rx_scale_mode_set(
1151 __in efx_nic_t *enp,
1152 __in uint32_t rss_context,
1153 __in efx_rx_hash_alg_t alg,
1154 __in efx_rx_hash_type_t type,
1155 __in boolean_t insert);
1158 extern __checkReturn efx_rc_t
1159 ef10_rx_scale_key_set(
1160 __in efx_nic_t *enp,
1161 __in uint32_t rss_context,
1162 __in_ecount(n) uint8_t *key,
1166 extern __checkReturn efx_rc_t
1167 ef10_rx_scale_tbl_set(
1168 __in efx_nic_t *enp,
1169 __in uint32_t rss_context,
1170 __in_ecount(n) unsigned int *table,
1174 extern __checkReturn uint32_t
1175 ef10_rx_prefix_hash(
1176 __in efx_nic_t *enp,
1177 __in efx_rx_hash_alg_t func,
1178 __in uint8_t *buffer);
1180 #endif /* EFSYS_OPT_RX_SCALE */
1183 extern __checkReturn efx_rc_t
1184 ef10_rx_prefix_pktlen(
1185 __in efx_nic_t *enp,
1186 __in uint8_t *buffer,
1187 __out uint16_t *lengthp);
1192 __in efx_rxq_t *erp,
1193 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1195 __in unsigned int ndescs,
1196 __in unsigned int completed,
1197 __in unsigned int added);
1202 __in efx_rxq_t *erp,
1203 __in unsigned int added,
1204 __inout unsigned int *pushedp);
1207 extern __checkReturn efx_rc_t
1209 __in efx_rxq_t *erp);
1214 __in efx_rxq_t *erp);
1216 union efx_rxq_type_data_u;
1219 extern __checkReturn efx_rc_t
1221 __in efx_nic_t *enp,
1222 __in unsigned int index,
1223 __in unsigned int label,
1224 __in efx_rxq_type_t type,
1225 __in_opt const union efx_rxq_type_data_u *type_data,
1226 __in efsys_mem_t *esmp,
1229 __in unsigned int flags,
1230 __in efx_evq_t *eep,
1231 __in efx_rxq_t *erp);
1236 __in efx_rxq_t *erp);
1241 __in efx_nic_t *enp);
1243 #if EFSYS_OPT_FILTER
1245 enum efx_filter_replacement_policy_e;
1247 typedef struct ef10_filter_handle_s {
1250 } ef10_filter_handle_t;
1252 typedef struct ef10_filter_entry_s {
1253 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1254 ef10_filter_handle_t efe_handle;
1255 } ef10_filter_entry_t;
1258 * BUSY flag indicates that an update is in progress.
1259 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1261 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1262 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1263 #define EFX_EF10_FILTER_FLAGS 3U
1266 * Size of the hash table used by the driver. Doesn't need to be the
1267 * same size as the hardware's table.
1269 #define EFX_EF10_FILTER_TBL_ROWS 8192
1271 /* Only need to allow for one directed and one unknown unicast filter */
1272 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1274 /* Allow for the broadcast address to be added to the multicast list */
1275 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1278 * For encapsulated packets, there is one filter each for each combination of
1279 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1280 * multicast inner frames.
1282 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1284 typedef struct ef10_filter_table_s {
1285 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1286 efx_rxq_t *eft_default_rxq;
1287 boolean_t eft_using_rss;
1288 uint32_t eft_unicst_filter_indexes[
1289 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1290 uint32_t eft_unicst_filter_count;
1291 uint32_t eft_mulcst_filter_indexes[
1292 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1293 uint32_t eft_mulcst_filter_count;
1294 boolean_t eft_using_all_mulcst;
1295 uint32_t eft_encap_filter_indexes[
1296 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1297 uint32_t eft_encap_filter_count;
1298 } ef10_filter_table_t;
1301 extern __checkReturn efx_rc_t
1303 __in efx_nic_t *enp);
1308 __in efx_nic_t *enp);
1311 extern __checkReturn efx_rc_t
1312 ef10_filter_restore(
1313 __in efx_nic_t *enp);
1316 extern __checkReturn efx_rc_t
1318 __in efx_nic_t *enp,
1319 __inout efx_filter_spec_t *spec,
1320 __in enum efx_filter_replacement_policy_e policy);
1323 extern __checkReturn efx_rc_t
1325 __in efx_nic_t *enp,
1326 __inout efx_filter_spec_t *spec);
1329 extern __checkReturn efx_rc_t
1330 ef10_filter_supported_filters(
1331 __in efx_nic_t *enp,
1332 __out_ecount(buffer_length) uint32_t *buffer,
1333 __in size_t buffer_length,
1334 __out size_t *list_lengthp);
1337 extern __checkReturn efx_rc_t
1338 ef10_filter_reconfigure(
1339 __in efx_nic_t *enp,
1340 __in_ecount(6) uint8_t const *mac_addr,
1341 __in boolean_t all_unicst,
1342 __in boolean_t mulcst,
1343 __in boolean_t all_mulcst,
1344 __in boolean_t brdcst,
1345 __in_ecount(6*count) uint8_t const *addrs,
1346 __in uint32_t count);
1350 ef10_filter_get_default_rxq(
1351 __in efx_nic_t *enp,
1352 __out efx_rxq_t **erpp,
1353 __out boolean_t *using_rss);
1357 ef10_filter_default_rxq_set(
1358 __in efx_nic_t *enp,
1359 __in efx_rxq_t *erp,
1360 __in boolean_t using_rss);
1364 ef10_filter_default_rxq_clear(
1365 __in efx_nic_t *enp);
1368 #endif /* EFSYS_OPT_FILTER */
1371 extern __checkReturn efx_rc_t
1372 efx_mcdi_get_function_info(
1373 __in efx_nic_t *enp,
1374 __out uint32_t *pfp,
1375 __out_opt uint32_t *vfp);
1378 extern __checkReturn efx_rc_t
1379 efx_mcdi_privilege_mask(
1380 __in efx_nic_t *enp,
1383 __out uint32_t *maskp);
1386 extern __checkReturn efx_rc_t
1387 efx_mcdi_get_port_assignment(
1388 __in efx_nic_t *enp,
1389 __out uint32_t *portp);
1392 extern __checkReturn efx_rc_t
1393 efx_mcdi_get_port_modes(
1394 __in efx_nic_t *enp,
1395 __out uint32_t *modesp,
1396 __out_opt uint32_t *current_modep,
1397 __out_opt uint32_t *default_modep);
1400 extern __checkReturn efx_rc_t
1401 ef10_nic_get_port_mode_bandwidth(
1402 __in efx_nic_t *enp,
1403 __out uint32_t *bandwidth_mbpsp);
1406 extern __checkReturn efx_rc_t
1407 efx_mcdi_get_mac_address_pf(
1408 __in efx_nic_t *enp,
1409 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1412 extern __checkReturn efx_rc_t
1413 efx_mcdi_get_mac_address_vf(
1414 __in efx_nic_t *enp,
1415 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1418 extern __checkReturn efx_rc_t
1420 __in efx_nic_t *enp,
1421 __out uint32_t *sys_freqp,
1422 __out uint32_t *dpcpu_freqp);
1426 extern __checkReturn efx_rc_t
1427 efx_mcdi_get_rxdp_config(
1428 __in efx_nic_t *enp,
1429 __out uint32_t *end_paddingp);
1432 extern __checkReturn efx_rc_t
1433 efx_mcdi_get_vector_cfg(
1434 __in efx_nic_t *enp,
1435 __out_opt uint32_t *vec_basep,
1436 __out_opt uint32_t *pf_nvecp,
1437 __out_opt uint32_t *vf_nvecp);
1440 extern __checkReturn efx_rc_t
1442 __in efx_nic_t *enp,
1443 __in uint32_t min_vi_count,
1444 __in uint32_t max_vi_count,
1445 __out uint32_t *vi_basep,
1446 __out uint32_t *vi_countp,
1447 __out uint32_t *vi_shiftp);
1450 extern __checkReturn efx_rc_t
1452 __in efx_nic_t *enp);
1455 extern __checkReturn efx_rc_t
1456 ef10_get_privilege_mask(
1457 __in efx_nic_t *enp,
1458 __out uint32_t *maskp);
1461 extern __checkReturn efx_rc_t
1462 efx_mcdi_nic_board_cfg(
1463 __in efx_nic_t *enp);
1466 extern __checkReturn efx_rc_t
1467 efx_mcdi_entity_reset(
1468 __in efx_nic_t *enp);
1470 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1473 extern __checkReturn efx_rc_t
1474 efx_mcdi_get_nic_global(
1475 __in efx_nic_t *enp,
1477 __out uint32_t *valuep);
1480 extern __checkReturn efx_rc_t
1481 efx_mcdi_set_nic_global(
1482 __in efx_nic_t *enp,
1484 __in uint32_t value);
1486 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1490 extern __checkReturn efx_rc_t
1492 __in efx_nic_t *enp);
1497 __in efx_nic_t *enp);
1500 extern __checkReturn efx_rc_t
1501 ef10_evb_vswitch_alloc(
1502 __in efx_nic_t *enp,
1503 __out efx_vswitch_id_t *vswitch_idp);
1507 extern __checkReturn efx_rc_t
1508 ef10_evb_vswitch_free(
1509 __in efx_nic_t *enp,
1510 __in efx_vswitch_id_t vswitch_id);
1513 extern __checkReturn efx_rc_t
1514 ef10_evb_vport_alloc(
1515 __in efx_nic_t *enp,
1516 __in efx_vswitch_id_t vswitch_id,
1517 __in efx_vport_type_t vport_type,
1519 __in boolean_t vlan_restrict,
1520 __out efx_vport_id_t *vport_idp);
1524 extern __checkReturn efx_rc_t
1525 ef10_evb_vport_free(
1526 __in efx_nic_t *enp,
1527 __in efx_vswitch_id_t vswitch_id,
1528 __in efx_vport_id_t vport_id);
1531 extern __checkReturn efx_rc_t
1532 ef10_evb_vport_mac_addr_add(
1533 __in efx_nic_t *enp,
1534 __in efx_vswitch_id_t vswitch_id,
1535 __in efx_vport_id_t vport_id,
1536 __in_ecount(6) uint8_t *addrp);
1539 extern __checkReturn efx_rc_t
1540 ef10_evb_vport_mac_addr_del(
1541 __in efx_nic_t *enp,
1542 __in efx_vswitch_id_t vswitch_id,
1543 __in efx_vport_id_t vport_id,
1544 __in_ecount(6) uint8_t *addrp);
1547 extern __checkReturn efx_rc_t
1548 ef10_evb_vadaptor_alloc(
1549 __in efx_nic_t *enp,
1550 __in efx_vswitch_id_t vswitch_id,
1551 __in efx_vport_id_t vport_id);
1555 extern __checkReturn efx_rc_t
1556 ef10_evb_vadaptor_free(
1557 __in efx_nic_t *enp,
1558 __in efx_vswitch_id_t vswitch_id,
1559 __in efx_vport_id_t vport_id);
1562 extern __checkReturn efx_rc_t
1563 ef10_evb_vport_assign(
1564 __in efx_nic_t *enp,
1565 __in efx_vswitch_id_t vswitch_id,
1566 __in efx_vport_id_t vport_id,
1567 __in uint32_t vf_index);
1570 extern __checkReturn efx_rc_t
1571 ef10_evb_vport_reconfigure(
1572 __in efx_nic_t *enp,
1573 __in efx_vswitch_id_t vswitch_id,
1574 __in efx_vport_id_t vport_id,
1575 __in_opt uint16_t *vidp,
1576 __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
1577 __out_opt boolean_t *fn_resetp);
1580 extern __checkReturn efx_rc_t
1581 ef10_evb_vport_stats(
1582 __in efx_nic_t *enp,
1583 __in efx_vswitch_id_t vswitch_id,
1584 __in efx_vport_id_t vport_id,
1585 __out efsys_mem_t *esmp);
1587 #endif /* EFSYS_OPT_EVB */
1589 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
1591 extern __checkReturn efx_rc_t
1592 ef10_proxy_auth_init(
1593 __in efx_nic_t *enp);
1597 ef10_proxy_auth_fini(
1598 __in efx_nic_t *enp);
1601 extern __checkReturn efx_rc_t
1602 ef10_proxy_auth_mc_config(
1603 __in efx_nic_t *enp,
1604 __in efsys_mem_t *request_bufferp,
1605 __in efsys_mem_t *response_bufferp,
1606 __in efsys_mem_t *status_bufferp,
1607 __in uint32_t block_cnt,
1608 __in_ecount(op_count) uint32_t *op_listp,
1609 __in size_t op_count);
1612 extern __checkReturn efx_rc_t
1613 ef10_proxy_auth_disable(
1614 __in efx_nic_t *enp);
1617 extern __checkReturn efx_rc_t
1618 ef10_proxy_auth_privilege_modify(
1619 __in efx_nic_t *enp,
1620 __in uint32_t fn_group,
1621 __in uint32_t pf_index,
1622 __in uint32_t vf_index,
1623 __in uint32_t add_privileges_mask,
1624 __in uint32_t remove_privileges_mask);
1627 extern __checkReturn efx_rc_t
1628 ef10_proxy_auth_set_privilege_mask(
1629 __in efx_nic_t *enp,
1630 __in uint32_t vf_index,
1632 __in uint32_t value);
1635 extern __checkReturn efx_rc_t
1636 ef10_proxy_auth_complete_request(
1637 __in efx_nic_t *enp,
1638 __in uint32_t fn_index,
1639 __in uint32_t proxy_result,
1640 __in uint32_t handle);
1643 extern __checkReturn efx_rc_t
1644 ef10_proxy_auth_exec_cmd(
1645 __in efx_nic_t *enp,
1646 __inout efx_proxy_cmd_params_t *paramsp);
1649 extern __checkReturn efx_rc_t
1650 ef10_proxy_auth_get_privilege_mask(
1651 __in efx_nic_t *enp,
1652 __in uint32_t pf_index,
1653 __in uint32_t vf_index,
1654 __out uint32_t *maskp);
1656 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
1658 #if EFSYS_OPT_RX_PACKED_STREAM
1660 /* Data space per credit in packed stream mode */
1661 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1664 * Received packets are always aligned at this boundary. Also there always
1665 * exists a gap of this size between packets.
1666 * (see SF-112241-TC, 4.5)
1668 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1671 * Size of a pseudo-header prepended to received packets
1672 * in packed stream mode
1674 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1676 /* Minimum space for packet in packed stream mode */
1677 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1678 EFX_P2ROUNDUP(size_t, \
1679 EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1681 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1682 EFX_RX_PACKED_STREAM_ALIGNMENT)
1684 /* Maximum number of credits */
1685 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1687 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1689 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1692 * Maximum DMA length and buffer stride alignment.
1693 * (see SF-119419-TC, 3.2)
1695 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1703 #endif /* _SYS_EF10_IMPL_H */