1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
20 #define EF10_TXQ_MINNDESCS 512
22 #define EF10_EVQ_DESC_SIZE (sizeof (efx_qword_t))
23 #define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t))
24 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
26 /* Number of hardware EVQ buffers (for compile-time resource dimensions) */
27 #define EF10_EVQ_MAXNBUFS (64)
29 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
30 #define EF10_TXQ_MAXNBUFS 8
32 #if EFSYS_OPT_HUNTINGTON
33 # if (EF10_EVQ_MAXNBUFS < HUNT_EVQ_MAXNBUFS)
34 # error "EF10_EVQ_MAXNBUFS too small"
36 #endif /* EFSYS_OPT_HUNTINGTON */
38 # if (EF10_EVQ_MAXNBUFS < MEDFORD_EVQ_MAXNBUFS)
39 # error "EF10_EVQ_MAXNBUFS too small"
41 #endif /* EFSYS_OPT_MEDFORD */
42 #if EFSYS_OPT_MEDFORD2
43 # if (EF10_EVQ_MAXNBUFS < MEDFORD2_EVQ_MAXNBUFS)
44 # error "EF10_EVQ_MAXNBUFS too small"
46 #endif /* EFSYS_OPT_MEDFORD2 */
48 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
49 #define EF10_MAX_PIOBUF_NBUFS (16)
51 #if EFSYS_OPT_HUNTINGTON
52 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
53 # error "EF10_MAX_PIOBUF_NBUFS too small"
55 #endif /* EFSYS_OPT_HUNTINGTON */
57 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
58 # error "EF10_MAX_PIOBUF_NBUFS too small"
60 #endif /* EFSYS_OPT_MEDFORD */
61 #if EFSYS_OPT_MEDFORD2
62 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
63 # error "EF10_MAX_PIOBUF_NBUFS too small"
65 #endif /* EFSYS_OPT_MEDFORD2 */
70 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
71 * possibly be increased, or the write size reported by newer firmware used
74 #define EF10_NVRAM_CHUNK 0x80
77 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
78 * to an 8 descriptor boundary.
80 #define EF10_RX_WPTR_ALIGN 8
83 * Max byte offset into the packet the TCP header must start for the hardware
84 * to be able to parse the packet correctly.
86 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
88 /* Invalid RSS context handle */
89 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
95 extern __checkReturn efx_rc_t
102 __in efx_nic_t *enp);
105 extern __checkReturn efx_rc_t
108 __in unsigned int index,
109 __in efsys_mem_t *esmp,
114 __in efx_evq_t *eep);
119 __in efx_evq_t *eep);
122 extern __checkReturn efx_rc_t
125 __in unsigned int count);
134 extern __checkReturn efx_rc_t
137 __in unsigned int us);
142 ef10_ev_qstats_update(
144 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
145 #endif /* EFSYS_OPT_QSTATS */
149 ef10_ev_rxlabel_init(
152 __in unsigned int label,
153 __in efx_rxq_type_t type);
157 ef10_ev_rxlabel_fini(
159 __in unsigned int label);
162 extern __checkReturn boolean_t
165 __in efx_qword_t *eqp,
166 __in const efx_ev_callbacks_t *eecp,
172 extern __checkReturn efx_rc_t
175 __in efx_intr_type_t type,
176 __in efsys_mem_t *esmp);
181 __in efx_nic_t *enp);
186 __in efx_nic_t *enp);
190 ef10_intr_disable_unlocked(
191 __in efx_nic_t *enp);
194 extern __checkReturn efx_rc_t
197 __in unsigned int level);
201 ef10_intr_status_line(
203 __out boolean_t *fatalp,
204 __out uint32_t *qmaskp);
208 ef10_intr_status_message(
210 __in unsigned int message,
211 __out boolean_t *fatalp);
216 __in efx_nic_t *enp);
221 __in efx_nic_t *enp);
226 extern __checkReturn efx_rc_t
227 efx_mcdi_vadaptor_alloc(
229 __in uint32_t port_id);
232 extern __checkReturn efx_rc_t
233 efx_mcdi_vadaptor_free(
235 __in uint32_t port_id);
238 extern __checkReturn efx_rc_t
239 ef10_upstream_port_vadaptor_alloc(
240 __in efx_nic_t *enp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
248 extern __checkReturn efx_rc_t
249 ef10_nic_set_drv_limits(
250 __inout efx_nic_t *enp,
251 __in efx_drv_limits_t *edlp);
254 extern __checkReturn efx_rc_t
255 ef10_nic_get_vi_pool(
257 __out uint32_t *vi_countp);
260 extern __checkReturn efx_rc_t
261 ef10_nic_get_bar_region(
263 __in efx_nic_region_t region,
264 __out uint32_t *offsetp,
265 __out size_t *sizep);
268 extern __checkReturn efx_rc_t
270 __in efx_nic_t *enp);
273 extern __checkReturn efx_rc_t
275 __in efx_nic_t *enp);
278 extern __checkReturn boolean_t
279 ef10_nic_hw_unavailable(
280 __in efx_nic_t *enp);
284 ef10_nic_set_hw_unavailable(
285 __in efx_nic_t *enp);
290 extern __checkReturn efx_rc_t
291 ef10_nic_register_test(
292 __in efx_nic_t *enp);
294 #endif /* EFSYS_OPT_DIAG */
299 __in efx_nic_t *enp);
304 __in efx_nic_t *enp);
310 extern __checkReturn efx_rc_t
313 __out efx_link_mode_t *link_modep);
316 extern __checkReturn efx_rc_t
319 __out boolean_t *mac_upp);
322 extern __checkReturn efx_rc_t
324 __in efx_nic_t *enp);
327 extern __checkReturn efx_rc_t
329 __in efx_nic_t *enp);
332 extern __checkReturn efx_rc_t
338 extern __checkReturn efx_rc_t
339 ef10_mac_reconfigure(
340 __in efx_nic_t *enp);
343 extern __checkReturn efx_rc_t
344 ef10_mac_multicast_list_set(
345 __in efx_nic_t *enp);
348 extern __checkReturn efx_rc_t
349 ef10_mac_filter_default_rxq_set(
352 __in boolean_t using_rss);
356 ef10_mac_filter_default_rxq_clear(
357 __in efx_nic_t *enp);
359 #if EFSYS_OPT_LOOPBACK
362 extern __checkReturn efx_rc_t
363 ef10_mac_loopback_set(
365 __in efx_link_mode_t link_mode,
366 __in efx_loopback_type_t loopback_type);
368 #endif /* EFSYS_OPT_LOOPBACK */
370 #if EFSYS_OPT_MAC_STATS
373 extern __checkReturn efx_rc_t
374 ef10_mac_stats_get_mask(
376 __inout_bcount(mask_size) uint32_t *maskp,
377 __in size_t mask_size);
380 extern __checkReturn efx_rc_t
381 ef10_mac_stats_update(
383 __in efsys_mem_t *esmp,
384 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
385 __inout_opt uint32_t *generationp);
387 #endif /* EFSYS_OPT_MAC_STATS */
395 extern __checkReturn efx_rc_t
398 __in const efx_mcdi_transport_t *mtp);
403 __in efx_nic_t *enp);
407 ef10_mcdi_send_request(
409 __in_bcount(hdr_len) void *hdrp,
411 __in_bcount(sdu_len) void *sdup,
412 __in size_t sdu_len);
415 extern __checkReturn boolean_t
416 ef10_mcdi_poll_response(
417 __in efx_nic_t *enp);
421 ef10_mcdi_read_response(
423 __out_bcount(length) void *bufferp,
429 ef10_mcdi_poll_reboot(
430 __in efx_nic_t *enp);
433 extern __checkReturn efx_rc_t
434 ef10_mcdi_feature_supported(
436 __in efx_mcdi_feature_id_t id,
437 __out boolean_t *supportedp);
441 ef10_mcdi_get_timeout(
443 __in efx_mcdi_req_t *emrp,
444 __out uint32_t *timeoutp);
446 #endif /* EFSYS_OPT_MCDI */
450 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
453 extern __checkReturn efx_rc_t
454 ef10_nvram_buf_read_tlv(
456 __in_bcount(max_seg_size) caddr_t seg_data,
457 __in size_t max_seg_size,
459 __deref_out_bcount_opt(*sizep) caddr_t *datap,
460 __out size_t *sizep);
463 extern __checkReturn efx_rc_t
464 ef10_nvram_buf_write_tlv(
465 __inout_bcount(partn_size) caddr_t partn_data,
466 __in size_t partn_size,
468 __in_bcount(tag_size) caddr_t tag_data,
469 __in size_t tag_size,
470 __out size_t *total_lengthp);
473 extern __checkReturn efx_rc_t
474 ef10_nvram_partn_read_tlv(
478 __deref_out_bcount_opt(*sizep) caddr_t *datap,
479 __out size_t *sizep);
482 extern __checkReturn efx_rc_t
483 ef10_nvram_partn_write_tlv(
487 __in_bcount(size) caddr_t data,
491 extern __checkReturn efx_rc_t
492 ef10_nvram_partn_write_segment_tlv(
496 __in_bcount(size) caddr_t data,
498 __in boolean_t all_segments);
501 extern __checkReturn efx_rc_t
502 ef10_nvram_partn_lock(
504 __in uint32_t partn);
507 extern __checkReturn efx_rc_t
508 ef10_nvram_partn_unlock(
511 __out_opt uint32_t *resultp);
513 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
520 extern __checkReturn efx_rc_t
522 __in efx_nic_t *enp);
524 #endif /* EFSYS_OPT_DIAG */
527 extern __checkReturn efx_rc_t
528 ef10_nvram_type_to_partn(
530 __in efx_nvram_type_t type,
531 __out uint32_t *partnp);
534 extern __checkReturn efx_rc_t
535 ef10_nvram_partn_size(
538 __out size_t *sizep);
541 extern __checkReturn efx_rc_t
542 ef10_nvram_partn_info(
545 __out efx_nvram_info_t * enip);
548 extern __checkReturn efx_rc_t
549 ef10_nvram_partn_rw_start(
552 __out size_t *chunk_sizep);
555 extern __checkReturn efx_rc_t
556 ef10_nvram_partn_read_mode(
559 __in unsigned int offset,
560 __out_bcount(size) caddr_t data,
565 extern __checkReturn efx_rc_t
566 ef10_nvram_partn_read(
569 __in unsigned int offset,
570 __out_bcount(size) caddr_t data,
574 extern __checkReturn efx_rc_t
575 ef10_nvram_partn_read_backup(
578 __in unsigned int offset,
579 __out_bcount(size) caddr_t data,
583 extern __checkReturn efx_rc_t
584 ef10_nvram_partn_erase(
587 __in unsigned int offset,
591 extern __checkReturn efx_rc_t
592 ef10_nvram_partn_write(
595 __in unsigned int offset,
596 __in_bcount(size) caddr_t data,
600 extern __checkReturn efx_rc_t
601 ef10_nvram_partn_rw_finish(
604 __out_opt uint32_t *verify_resultp);
607 extern __checkReturn efx_rc_t
608 ef10_nvram_partn_get_version(
611 __out uint32_t *subtypep,
612 __out_ecount(4) uint16_t version[4]);
615 extern __checkReturn efx_rc_t
616 ef10_nvram_partn_set_version(
619 __in_ecount(4) uint16_t version[4]);
622 extern __checkReturn efx_rc_t
623 ef10_nvram_buffer_validate(
625 __in_bcount(buffer_size)
627 __in size_t buffer_size);
631 ef10_nvram_buffer_init(
632 __out_bcount(buffer_size)
634 __in size_t buffer_size);
637 extern __checkReturn efx_rc_t
638 ef10_nvram_buffer_create(
639 __in uint32_t partn_type,
640 __out_bcount(buffer_size)
642 __in size_t buffer_size);
645 extern __checkReturn efx_rc_t
646 ef10_nvram_buffer_find_item_start(
647 __in_bcount(buffer_size)
649 __in size_t buffer_size,
650 __out uint32_t *startp);
653 extern __checkReturn efx_rc_t
654 ef10_nvram_buffer_find_end(
655 __in_bcount(buffer_size)
657 __in size_t buffer_size,
658 __in uint32_t offset,
659 __out uint32_t *endp);
662 extern __checkReturn __success(return != B_FALSE) boolean_t
663 ef10_nvram_buffer_find_item(
664 __in_bcount(buffer_size)
666 __in size_t buffer_size,
667 __in uint32_t offset,
668 __out uint32_t *startp,
669 __out uint32_t *lengthp);
672 extern __checkReturn efx_rc_t
673 ef10_nvram_buffer_peek_item(
674 __in_bcount(buffer_size)
676 __in size_t buffer_size,
677 __in uint32_t offset,
678 __out uint32_t *tagp,
679 __out uint32_t *lengthp,
680 __out uint32_t *value_offsetp);
683 extern __checkReturn efx_rc_t
684 ef10_nvram_buffer_get_item(
685 __in_bcount(buffer_size)
687 __in size_t buffer_size,
688 __in uint32_t offset,
689 __in uint32_t length,
690 __out uint32_t *tagp,
691 __out_bcount_part(value_max_size, *lengthp)
693 __in size_t value_max_size,
694 __out uint32_t *lengthp);
697 extern __checkReturn efx_rc_t
698 ef10_nvram_buffer_insert_item(
699 __in_bcount(buffer_size)
701 __in size_t buffer_size,
702 __in uint32_t offset,
704 __in_bcount(length) caddr_t valuep,
705 __in uint32_t length,
706 __out uint32_t *lengthp);
709 extern __checkReturn efx_rc_t
710 ef10_nvram_buffer_modify_item(
711 __in_bcount(buffer_size)
713 __in size_t buffer_size,
714 __in uint32_t offset,
716 __in_bcount(length) caddr_t valuep,
717 __in uint32_t length,
718 __out uint32_t *lengthp);
721 extern __checkReturn efx_rc_t
722 ef10_nvram_buffer_delete_item(
723 __in_bcount(buffer_size)
725 __in size_t buffer_size,
726 __in uint32_t offset,
727 __in uint32_t length,
731 extern __checkReturn efx_rc_t
732 ef10_nvram_buffer_finish(
733 __in_bcount(buffer_size)
735 __in size_t buffer_size);
737 #endif /* EFSYS_OPT_NVRAM */
742 typedef struct ef10_link_state_s {
743 efx_phy_link_state_t epls;
744 #if EFSYS_OPT_LOOPBACK
745 efx_loopback_type_t els_loopback;
747 boolean_t els_mac_up;
754 __in efx_qword_t *eqp,
755 __out efx_link_mode_t *link_modep);
758 extern __checkReturn efx_rc_t
761 __out ef10_link_state_t *elsp);
764 extern __checkReturn efx_rc_t
770 extern __checkReturn efx_rc_t
771 ef10_phy_reconfigure(
772 __in efx_nic_t *enp);
775 extern __checkReturn efx_rc_t
777 __in efx_nic_t *enp);
780 extern __checkReturn efx_rc_t
783 __out uint32_t *ouip);
786 extern __checkReturn efx_rc_t
787 ef10_phy_link_state_get(
789 __out efx_phy_link_state_t *eplsp);
791 #if EFSYS_OPT_PHY_STATS
794 extern __checkReturn efx_rc_t
795 ef10_phy_stats_update(
797 __in efsys_mem_t *esmp,
798 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
800 #endif /* EFSYS_OPT_PHY_STATS */
805 extern __checkReturn efx_rc_t
806 ef10_bist_enable_offline(
807 __in efx_nic_t *enp);
810 extern __checkReturn efx_rc_t
813 __in efx_bist_type_t type);
816 extern __checkReturn efx_rc_t
819 __in efx_bist_type_t type,
820 __out efx_bist_result_t *resultp,
821 __out_opt __drv_when(count > 0, __notnull)
822 uint32_t *value_maskp,
823 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
824 unsigned long *valuesp,
831 __in efx_bist_type_t type);
833 #endif /* EFSYS_OPT_BIST */
838 extern __checkReturn efx_rc_t
840 __in efx_nic_t *enp);
845 __in efx_nic_t *enp);
848 extern __checkReturn efx_rc_t
851 __in unsigned int index,
852 __in unsigned int label,
853 __in efsys_mem_t *esmp,
859 __out unsigned int *addedp);
864 __in efx_txq_t *etp);
867 extern __checkReturn efx_rc_t
870 __in_ecount(ndescs) efx_buffer_t *ebp,
871 __in unsigned int ndescs,
872 __in unsigned int completed,
873 __inout unsigned int *addedp);
879 __in unsigned int added,
880 __in unsigned int pushed);
882 #if EFSYS_OPT_RX_PACKED_STREAM
885 ef10_rx_qpush_ps_credits(
886 __in efx_rxq_t *erp);
889 extern __checkReturn uint8_t *
890 ef10_rx_qps_packet_info(
892 __in uint8_t *buffer,
893 __in uint32_t buffer_length,
894 __in uint32_t current_offset,
895 __out uint16_t *lengthp,
896 __out uint32_t *next_offsetp,
897 __out uint32_t *timestamp);
901 extern __checkReturn efx_rc_t
904 __in unsigned int ns);
907 extern __checkReturn efx_rc_t
909 __in efx_txq_t *etp);
914 __in efx_txq_t *etp);
917 extern __checkReturn efx_rc_t
919 __in efx_txq_t *etp);
923 ef10_tx_qpio_disable(
924 __in efx_txq_t *etp);
927 extern __checkReturn efx_rc_t
930 __in_ecount(buf_length) uint8_t *buffer,
931 __in size_t buf_length,
932 __in size_t pio_buf_offset);
935 extern __checkReturn efx_rc_t
938 __in size_t pkt_length,
939 __in unsigned int completed,
940 __inout unsigned int *addedp);
943 extern __checkReturn efx_rc_t
946 __in_ecount(n) efx_desc_t *ed,
948 __in unsigned int completed,
949 __inout unsigned int *addedp);
953 ef10_tx_qdesc_dma_create(
955 __in efsys_dma_addr_t addr,
958 __out efx_desc_t *edp);
962 ef10_tx_qdesc_tso_create(
964 __in uint16_t ipv4_id,
965 __in uint32_t tcp_seq,
966 __in uint8_t tcp_flags,
967 __out efx_desc_t *edp);
971 ef10_tx_qdesc_tso2_create(
973 __in uint16_t ipv4_id,
974 __in uint16_t outer_ipv4_id,
975 __in uint32_t tcp_seq,
976 __in uint16_t tcp_mss,
977 __out_ecount(count) efx_desc_t *edp,
982 ef10_tx_qdesc_vlantci_create(
984 __in uint16_t vlan_tci,
985 __out efx_desc_t *edp);
989 ef10_tx_qdesc_checksum_create(
992 __out efx_desc_t *edp);
998 ef10_tx_qstats_update(
1000 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1002 #endif /* EFSYS_OPT_QSTATS */
1004 typedef uint32_t efx_piobuf_handle_t;
1006 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
1009 extern __checkReturn efx_rc_t
1011 __inout efx_nic_t *enp,
1012 __out uint32_t *bufnump,
1013 __out efx_piobuf_handle_t *handlep,
1014 __out uint32_t *blknump,
1015 __out uint32_t *offsetp,
1016 __out size_t *sizep);
1019 extern __checkReturn efx_rc_t
1021 __inout efx_nic_t *enp,
1022 __in uint32_t bufnum,
1023 __in uint32_t blknum);
1026 extern __checkReturn efx_rc_t
1028 __inout efx_nic_t *enp,
1029 __in uint32_t vi_index,
1030 __in efx_piobuf_handle_t handle);
1033 extern __checkReturn efx_rc_t
1034 ef10_nic_pio_unlink(
1035 __inout efx_nic_t *enp,
1036 __in uint32_t vi_index);
1044 extern __checkReturn efx_rc_t
1046 __in efx_nic_t *enp);
1049 extern __checkReturn efx_rc_t
1051 __in efx_nic_t *enp,
1052 __out size_t *sizep);
1055 extern __checkReturn efx_rc_t
1057 __in efx_nic_t *enp,
1058 __out_bcount(size) caddr_t data,
1062 extern __checkReturn efx_rc_t
1064 __in efx_nic_t *enp,
1065 __in_bcount(size) caddr_t data,
1069 extern __checkReturn efx_rc_t
1071 __in efx_nic_t *enp,
1072 __in_bcount(size) caddr_t data,
1076 extern __checkReturn efx_rc_t
1078 __in efx_nic_t *enp,
1079 __in_bcount(size) caddr_t data,
1081 __inout efx_vpd_value_t *evvp);
1084 extern __checkReturn efx_rc_t
1086 __in efx_nic_t *enp,
1087 __in_bcount(size) caddr_t data,
1089 __in efx_vpd_value_t *evvp);
1092 extern __checkReturn efx_rc_t
1094 __in efx_nic_t *enp,
1095 __in_bcount(size) caddr_t data,
1097 __out efx_vpd_value_t *evvp,
1098 __inout unsigned int *contp);
1101 extern __checkReturn efx_rc_t
1103 __in efx_nic_t *enp,
1104 __in_bcount(size) caddr_t data,
1110 __in efx_nic_t *enp);
1112 #endif /* EFSYS_OPT_VPD */
1118 extern __checkReturn efx_rc_t
1120 __in efx_nic_t *enp);
1122 #if EFSYS_OPT_RX_SCATTER
1124 extern __checkReturn efx_rc_t
1125 ef10_rx_scatter_enable(
1126 __in efx_nic_t *enp,
1127 __in unsigned int buf_size);
1128 #endif /* EFSYS_OPT_RX_SCATTER */
1131 #if EFSYS_OPT_RX_SCALE
1134 extern __checkReturn efx_rc_t
1135 ef10_rx_scale_context_alloc(
1136 __in efx_nic_t *enp,
1137 __in efx_rx_scale_context_type_t type,
1138 __in uint32_t num_queues,
1139 __out uint32_t *rss_contextp);
1142 extern __checkReturn efx_rc_t
1143 ef10_rx_scale_context_free(
1144 __in efx_nic_t *enp,
1145 __in uint32_t rss_context);
1148 extern __checkReturn efx_rc_t
1149 ef10_rx_scale_mode_set(
1150 __in efx_nic_t *enp,
1151 __in uint32_t rss_context,
1152 __in efx_rx_hash_alg_t alg,
1153 __in efx_rx_hash_type_t type,
1154 __in boolean_t insert);
1157 extern __checkReturn efx_rc_t
1158 ef10_rx_scale_key_set(
1159 __in efx_nic_t *enp,
1160 __in uint32_t rss_context,
1161 __in_ecount(n) uint8_t *key,
1165 extern __checkReturn efx_rc_t
1166 ef10_rx_scale_tbl_set(
1167 __in efx_nic_t *enp,
1168 __in uint32_t rss_context,
1169 __in_ecount(n) unsigned int *table,
1173 extern __checkReturn uint32_t
1174 ef10_rx_prefix_hash(
1175 __in efx_nic_t *enp,
1176 __in efx_rx_hash_alg_t func,
1177 __in uint8_t *buffer);
1179 #endif /* EFSYS_OPT_RX_SCALE */
1182 extern __checkReturn efx_rc_t
1183 ef10_rx_prefix_pktlen(
1184 __in efx_nic_t *enp,
1185 __in uint8_t *buffer,
1186 __out uint16_t *lengthp);
1191 __in efx_rxq_t *erp,
1192 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1194 __in unsigned int ndescs,
1195 __in unsigned int completed,
1196 __in unsigned int added);
1201 __in efx_rxq_t *erp,
1202 __in unsigned int added,
1203 __inout unsigned int *pushedp);
1206 extern __checkReturn efx_rc_t
1208 __in efx_rxq_t *erp);
1213 __in efx_rxq_t *erp);
1215 union efx_rxq_type_data_u;
1218 extern __checkReturn efx_rc_t
1220 __in efx_nic_t *enp,
1221 __in unsigned int index,
1222 __in unsigned int label,
1223 __in efx_rxq_type_t type,
1224 __in_opt const union efx_rxq_type_data_u *type_data,
1225 __in efsys_mem_t *esmp,
1228 __in unsigned int flags,
1229 __in efx_evq_t *eep,
1230 __in efx_rxq_t *erp);
1235 __in efx_rxq_t *erp);
1240 __in efx_nic_t *enp);
1242 #if EFSYS_OPT_FILTER
1244 enum efx_filter_replacement_policy_e;
1246 typedef struct ef10_filter_handle_s {
1249 } ef10_filter_handle_t;
1251 typedef struct ef10_filter_entry_s {
1252 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1253 ef10_filter_handle_t efe_handle;
1254 } ef10_filter_entry_t;
1257 * BUSY flag indicates that an update is in progress.
1258 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1260 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1261 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1262 #define EFX_EF10_FILTER_FLAGS 3U
1265 * Size of the hash table used by the driver. Doesn't need to be the
1266 * same size as the hardware's table.
1268 #define EFX_EF10_FILTER_TBL_ROWS 8192
1270 /* Only need to allow for one directed and one unknown unicast filter */
1271 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1273 /* Allow for the broadcast address to be added to the multicast list */
1274 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1277 * For encapsulated packets, there is one filter each for each combination of
1278 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1279 * multicast inner frames.
1281 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1283 typedef struct ef10_filter_table_s {
1284 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1285 efx_rxq_t *eft_default_rxq;
1286 boolean_t eft_using_rss;
1287 uint32_t eft_unicst_filter_indexes[
1288 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1289 uint32_t eft_unicst_filter_count;
1290 uint32_t eft_mulcst_filter_indexes[
1291 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1292 uint32_t eft_mulcst_filter_count;
1293 boolean_t eft_using_all_mulcst;
1294 uint32_t eft_encap_filter_indexes[
1295 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1296 uint32_t eft_encap_filter_count;
1297 } ef10_filter_table_t;
1300 extern __checkReturn efx_rc_t
1302 __in efx_nic_t *enp);
1307 __in efx_nic_t *enp);
1310 extern __checkReturn efx_rc_t
1311 ef10_filter_restore(
1312 __in efx_nic_t *enp);
1315 extern __checkReturn efx_rc_t
1317 __in efx_nic_t *enp,
1318 __inout efx_filter_spec_t *spec,
1319 __in enum efx_filter_replacement_policy_e policy);
1322 extern __checkReturn efx_rc_t
1324 __in efx_nic_t *enp,
1325 __inout efx_filter_spec_t *spec);
1328 extern __checkReturn efx_rc_t
1329 ef10_filter_supported_filters(
1330 __in efx_nic_t *enp,
1331 __out_ecount(buffer_length) uint32_t *buffer,
1332 __in size_t buffer_length,
1333 __out size_t *list_lengthp);
1336 extern __checkReturn efx_rc_t
1337 ef10_filter_reconfigure(
1338 __in efx_nic_t *enp,
1339 __in_ecount(6) uint8_t const *mac_addr,
1340 __in boolean_t all_unicst,
1341 __in boolean_t mulcst,
1342 __in boolean_t all_mulcst,
1343 __in boolean_t brdcst,
1344 __in_ecount(6*count) uint8_t const *addrs,
1345 __in uint32_t count);
1349 ef10_filter_get_default_rxq(
1350 __in efx_nic_t *enp,
1351 __out efx_rxq_t **erpp,
1352 __out boolean_t *using_rss);
1356 ef10_filter_default_rxq_set(
1357 __in efx_nic_t *enp,
1358 __in efx_rxq_t *erp,
1359 __in boolean_t using_rss);
1363 ef10_filter_default_rxq_clear(
1364 __in efx_nic_t *enp);
1367 #endif /* EFSYS_OPT_FILTER */
1370 extern __checkReturn efx_rc_t
1371 efx_mcdi_get_function_info(
1372 __in efx_nic_t *enp,
1373 __out uint32_t *pfp,
1374 __out_opt uint32_t *vfp);
1377 extern __checkReturn efx_rc_t
1378 efx_mcdi_privilege_mask(
1379 __in efx_nic_t *enp,
1382 __out uint32_t *maskp);
1385 extern __checkReturn efx_rc_t
1386 efx_mcdi_get_port_assignment(
1387 __in efx_nic_t *enp,
1388 __out uint32_t *portp);
1391 extern __checkReturn efx_rc_t
1392 efx_mcdi_get_port_modes(
1393 __in efx_nic_t *enp,
1394 __out uint32_t *modesp,
1395 __out_opt uint32_t *current_modep,
1396 __out_opt uint32_t *default_modep);
1399 extern __checkReturn efx_rc_t
1400 ef10_nic_get_port_mode_bandwidth(
1401 __in efx_nic_t *enp,
1402 __out uint32_t *bandwidth_mbpsp);
1405 extern __checkReturn efx_rc_t
1406 efx_mcdi_get_mac_address_pf(
1407 __in efx_nic_t *enp,
1408 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1411 extern __checkReturn efx_rc_t
1412 efx_mcdi_get_mac_address_vf(
1413 __in efx_nic_t *enp,
1414 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1417 extern __checkReturn efx_rc_t
1419 __in efx_nic_t *enp,
1420 __out uint32_t *sys_freqp,
1421 __out uint32_t *dpcpu_freqp);
1425 extern __checkReturn efx_rc_t
1426 efx_mcdi_get_rxdp_config(
1427 __in efx_nic_t *enp,
1428 __out uint32_t *end_paddingp);
1431 extern __checkReturn efx_rc_t
1432 efx_mcdi_get_vector_cfg(
1433 __in efx_nic_t *enp,
1434 __out_opt uint32_t *vec_basep,
1435 __out_opt uint32_t *pf_nvecp,
1436 __out_opt uint32_t *vf_nvecp);
1439 extern __checkReturn efx_rc_t
1441 __in efx_nic_t *enp,
1442 __in uint32_t min_vi_count,
1443 __in uint32_t max_vi_count,
1444 __out uint32_t *vi_basep,
1445 __out uint32_t *vi_countp,
1446 __out uint32_t *vi_shiftp);
1449 extern __checkReturn efx_rc_t
1451 __in efx_nic_t *enp);
1454 extern __checkReturn efx_rc_t
1455 ef10_get_privilege_mask(
1456 __in efx_nic_t *enp,
1457 __out uint32_t *maskp);
1460 extern __checkReturn efx_rc_t
1461 efx_mcdi_nic_board_cfg(
1462 __in efx_nic_t *enp);
1465 extern __checkReturn efx_rc_t
1466 efx_mcdi_entity_reset(
1467 __in efx_nic_t *enp);
1469 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1472 extern __checkReturn efx_rc_t
1473 efx_mcdi_get_nic_global(
1474 __in efx_nic_t *enp,
1476 __out uint32_t *valuep);
1479 extern __checkReturn efx_rc_t
1480 efx_mcdi_set_nic_global(
1481 __in efx_nic_t *enp,
1483 __in uint32_t value);
1485 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1489 extern __checkReturn efx_rc_t
1491 __in efx_nic_t *enp);
1496 __in efx_nic_t *enp);
1499 extern __checkReturn efx_rc_t
1500 ef10_evb_vswitch_alloc(
1501 __in efx_nic_t *enp,
1502 __out efx_vswitch_id_t *vswitch_idp);
1506 extern __checkReturn efx_rc_t
1507 ef10_evb_vswitch_free(
1508 __in efx_nic_t *enp,
1509 __in efx_vswitch_id_t vswitch_id);
1512 extern __checkReturn efx_rc_t
1513 ef10_evb_vport_alloc(
1514 __in efx_nic_t *enp,
1515 __in efx_vswitch_id_t vswitch_id,
1516 __in efx_vport_type_t vport_type,
1518 __in boolean_t vlan_restrict,
1519 __out efx_vport_id_t *vport_idp);
1523 extern __checkReturn efx_rc_t
1524 ef10_evb_vport_free(
1525 __in efx_nic_t *enp,
1526 __in efx_vswitch_id_t vswitch_id,
1527 __in efx_vport_id_t vport_id);
1530 extern __checkReturn efx_rc_t
1531 ef10_evb_vport_mac_addr_add(
1532 __in efx_nic_t *enp,
1533 __in efx_vswitch_id_t vswitch_id,
1534 __in efx_vport_id_t vport_id,
1535 __in_ecount(6) uint8_t *addrp);
1538 extern __checkReturn efx_rc_t
1539 ef10_evb_vport_mac_addr_del(
1540 __in efx_nic_t *enp,
1541 __in efx_vswitch_id_t vswitch_id,
1542 __in efx_vport_id_t vport_id,
1543 __in_ecount(6) uint8_t *addrp);
1546 extern __checkReturn efx_rc_t
1547 ef10_evb_vadaptor_alloc(
1548 __in efx_nic_t *enp,
1549 __in efx_vswitch_id_t vswitch_id,
1550 __in efx_vport_id_t vport_id);
1554 extern __checkReturn efx_rc_t
1555 ef10_evb_vadaptor_free(
1556 __in efx_nic_t *enp,
1557 __in efx_vswitch_id_t vswitch_id,
1558 __in efx_vport_id_t vport_id);
1561 extern __checkReturn efx_rc_t
1562 ef10_evb_vport_assign(
1563 __in efx_nic_t *enp,
1564 __in efx_vswitch_id_t vswitch_id,
1565 __in efx_vport_id_t vport_id,
1566 __in uint32_t vf_index);
1569 extern __checkReturn efx_rc_t
1570 ef10_evb_vport_reconfigure(
1571 __in efx_nic_t *enp,
1572 __in efx_vswitch_id_t vswitch_id,
1573 __in efx_vport_id_t vport_id,
1574 __in_opt uint16_t *vidp,
1575 __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
1576 __out_opt boolean_t *fn_resetp);
1579 extern __checkReturn efx_rc_t
1580 ef10_evb_vport_stats(
1581 __in efx_nic_t *enp,
1582 __in efx_vswitch_id_t vswitch_id,
1583 __in efx_vport_id_t vport_id,
1584 __out efsys_mem_t *esmp);
1586 #endif /* EFSYS_OPT_EVB */
1588 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
1590 extern __checkReturn efx_rc_t
1591 ef10_proxy_auth_init(
1592 __in efx_nic_t *enp);
1596 ef10_proxy_auth_fini(
1597 __in efx_nic_t *enp);
1600 extern __checkReturn efx_rc_t
1601 ef10_proxy_auth_mc_config(
1602 __in efx_nic_t *enp,
1603 __in efsys_mem_t *request_bufferp,
1604 __in efsys_mem_t *response_bufferp,
1605 __in efsys_mem_t *status_bufferp,
1606 __in uint32_t block_cnt,
1607 __in_ecount(op_count) uint32_t *op_listp,
1608 __in size_t op_count);
1611 extern __checkReturn efx_rc_t
1612 ef10_proxy_auth_disable(
1613 __in efx_nic_t *enp);
1616 extern __checkReturn efx_rc_t
1617 ef10_proxy_auth_privilege_modify(
1618 __in efx_nic_t *enp,
1619 __in uint32_t fn_group,
1620 __in uint32_t pf_index,
1621 __in uint32_t vf_index,
1622 __in uint32_t add_privileges_mask,
1623 __in uint32_t remove_privileges_mask);
1626 extern __checkReturn efx_rc_t
1627 ef10_proxy_auth_set_privilege_mask(
1628 __in efx_nic_t *enp,
1629 __in uint32_t vf_index,
1631 __in uint32_t value);
1634 extern __checkReturn efx_rc_t
1635 ef10_proxy_auth_complete_request(
1636 __in efx_nic_t *enp,
1637 __in uint32_t fn_index,
1638 __in uint32_t proxy_result,
1639 __in uint32_t handle);
1642 extern __checkReturn efx_rc_t
1643 ef10_proxy_auth_exec_cmd(
1644 __in efx_nic_t *enp,
1645 __inout efx_proxy_cmd_params_t *paramsp);
1648 extern __checkReturn efx_rc_t
1649 ef10_proxy_auth_get_privilege_mask(
1650 __in efx_nic_t *enp,
1651 __in uint32_t pf_index,
1652 __in uint32_t vf_index,
1653 __out uint32_t *maskp);
1655 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
1657 #if EFSYS_OPT_RX_PACKED_STREAM
1659 /* Data space per credit in packed stream mode */
1660 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1663 * Received packets are always aligned at this boundary. Also there always
1664 * exists a gap of this size between packets.
1665 * (see SF-112241-TC, 4.5)
1667 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1670 * Size of a pseudo-header prepended to received packets
1671 * in packed stream mode
1673 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1675 /* Minimum space for packet in packed stream mode */
1676 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1677 EFX_P2ROUNDUP(size_t, \
1678 EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1680 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1681 EFX_RX_PACKED_STREAM_ALIGNMENT)
1683 /* Maximum number of credits */
1684 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1686 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1688 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1691 * Maximum DMA length and buffer stride alignment.
1692 * (see SF-119419-TC, 3.2)
1694 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1702 #endif /* _SYS_EF10_IMPL_H */