1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
20 #define EF10_TXQ_MINNDESCS 512
22 #define EF10_EVQ_DESC_SIZE (sizeof (efx_qword_t))
23 #define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t))
24 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
26 /* Number of hardware EVQ buffers (for compile-time resource dimensions) */
27 #define EF10_EVQ_MAXNBUFS (64)
29 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
30 #define EF10_TXQ_MAXNBUFS 8
32 #if EFSYS_OPT_HUNTINGTON
33 # if (EF10_EVQ_MAXNBUFS < HUNT_EVQ_MAXNBUFS)
34 # error "EF10_EVQ_MAXNBUFS too small"
36 #endif /* EFSYS_OPT_HUNTINGTON */
38 # if (EF10_EVQ_MAXNBUFS < MEDFORD_EVQ_MAXNBUFS)
39 # error "EF10_EVQ_MAXNBUFS too small"
41 #endif /* EFSYS_OPT_MEDFORD */
42 #if EFSYS_OPT_MEDFORD2
43 # if (EF10_EVQ_MAXNBUFS < MEDFORD2_EVQ_MAXNBUFS)
44 # error "EF10_EVQ_MAXNBUFS too small"
46 #endif /* EFSYS_OPT_MEDFORD2 */
48 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
49 #define EF10_MAX_PIOBUF_NBUFS (16)
51 #if EFSYS_OPT_HUNTINGTON
52 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
53 # error "EF10_MAX_PIOBUF_NBUFS too small"
55 #endif /* EFSYS_OPT_HUNTINGTON */
57 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
58 # error "EF10_MAX_PIOBUF_NBUFS too small"
60 #endif /* EFSYS_OPT_MEDFORD */
61 #if EFSYS_OPT_MEDFORD2
62 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
63 # error "EF10_MAX_PIOBUF_NBUFS too small"
65 #endif /* EFSYS_OPT_MEDFORD2 */
70 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
71 * possibly be increased, or the write size reported by newer firmware used
74 #define EF10_NVRAM_CHUNK 0x80
77 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
78 * to an 8 descriptor boundary.
80 #define EF10_RX_WPTR_ALIGN 8
83 * Max byte offset into the packet the TCP header must start for the hardware
84 * to be able to parse the packet correctly.
86 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
88 /* Invalid RSS context handle */
89 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
95 extern __checkReturn efx_rc_t
102 __in efx_nic_t *enp);
105 extern __checkReturn efx_rc_t
108 __in unsigned int index,
109 __in efsys_mem_t *esmp,
114 __in efx_evq_t *eep);
119 __in efx_evq_t *eep);
122 extern __checkReturn efx_rc_t
125 __in unsigned int count);
134 extern __checkReturn efx_rc_t
137 __in unsigned int us);
142 ef10_ev_qstats_update(
144 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
145 #endif /* EFSYS_OPT_QSTATS */
149 ef10_ev_rxlabel_init(
152 __in unsigned int label,
153 __in efx_rxq_type_t type);
157 ef10_ev_rxlabel_fini(
159 __in unsigned int label);
162 extern __checkReturn boolean_t
165 __in efx_qword_t *eqp,
166 __in const efx_ev_callbacks_t *eecp,
172 extern __checkReturn efx_rc_t
175 __in efx_intr_type_t type,
176 __in efsys_mem_t *esmp);
181 __in efx_nic_t *enp);
186 __in efx_nic_t *enp);
190 ef10_intr_disable_unlocked(
191 __in efx_nic_t *enp);
194 extern __checkReturn efx_rc_t
197 __in unsigned int level);
201 ef10_intr_status_line(
203 __out boolean_t *fatalp,
204 __out uint32_t *qmaskp);
208 ef10_intr_status_message(
210 __in unsigned int message,
211 __out boolean_t *fatalp);
216 __in efx_nic_t *enp);
221 __in efx_nic_t *enp);
226 extern __checkReturn efx_rc_t
227 efx_mcdi_vadaptor_alloc(
229 __in uint32_t port_id);
232 extern __checkReturn efx_rc_t
233 efx_mcdi_vadaptor_free(
235 __in uint32_t port_id);
238 extern __checkReturn efx_rc_t
240 __in efx_nic_t *enp);
243 extern __checkReturn efx_rc_t
244 ef10_nic_set_drv_limits(
245 __inout efx_nic_t *enp,
246 __in efx_drv_limits_t *edlp);
249 extern __checkReturn efx_rc_t
250 ef10_nic_get_vi_pool(
252 __out uint32_t *vi_countp);
255 extern __checkReturn efx_rc_t
256 ef10_nic_get_bar_region(
258 __in efx_nic_region_t region,
259 __out uint32_t *offsetp,
260 __out size_t *sizep);
263 extern __checkReturn efx_rc_t
265 __in efx_nic_t *enp);
268 extern __checkReturn efx_rc_t
270 __in efx_nic_t *enp);
273 extern __checkReturn boolean_t
274 ef10_nic_hw_unavailable(
275 __in efx_nic_t *enp);
279 ef10_nic_set_hw_unavailable(
280 __in efx_nic_t *enp);
285 extern __checkReturn efx_rc_t
286 ef10_nic_register_test(
287 __in efx_nic_t *enp);
289 #endif /* EFSYS_OPT_DIAG */
294 __in efx_nic_t *enp);
299 __in efx_nic_t *enp);
305 extern __checkReturn efx_rc_t
308 __out efx_link_mode_t *link_modep);
311 extern __checkReturn efx_rc_t
314 __out boolean_t *mac_upp);
317 extern __checkReturn efx_rc_t
319 __in efx_nic_t *enp);
322 extern __checkReturn efx_rc_t
324 __in efx_nic_t *enp);
327 extern __checkReturn efx_rc_t
333 extern __checkReturn efx_rc_t
334 ef10_mac_reconfigure(
335 __in efx_nic_t *enp);
338 extern __checkReturn efx_rc_t
339 ef10_mac_multicast_list_set(
340 __in efx_nic_t *enp);
343 extern __checkReturn efx_rc_t
344 ef10_mac_filter_default_rxq_set(
347 __in boolean_t using_rss);
351 ef10_mac_filter_default_rxq_clear(
352 __in efx_nic_t *enp);
354 #if EFSYS_OPT_LOOPBACK
357 extern __checkReturn efx_rc_t
358 ef10_mac_loopback_set(
360 __in efx_link_mode_t link_mode,
361 __in efx_loopback_type_t loopback_type);
363 #endif /* EFSYS_OPT_LOOPBACK */
365 #if EFSYS_OPT_MAC_STATS
368 extern __checkReturn efx_rc_t
369 ef10_mac_stats_get_mask(
371 __inout_bcount(mask_size) uint32_t *maskp,
372 __in size_t mask_size);
375 extern __checkReturn efx_rc_t
376 ef10_mac_stats_update(
378 __in efsys_mem_t *esmp,
379 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
380 __inout_opt uint32_t *generationp);
382 #endif /* EFSYS_OPT_MAC_STATS */
390 extern __checkReturn efx_rc_t
393 __in const efx_mcdi_transport_t *mtp);
398 __in efx_nic_t *enp);
402 ef10_mcdi_send_request(
404 __in_bcount(hdr_len) void *hdrp,
406 __in_bcount(sdu_len) void *sdup,
407 __in size_t sdu_len);
410 extern __checkReturn boolean_t
411 ef10_mcdi_poll_response(
412 __in efx_nic_t *enp);
416 ef10_mcdi_read_response(
418 __out_bcount(length) void *bufferp,
424 ef10_mcdi_poll_reboot(
425 __in efx_nic_t *enp);
428 extern __checkReturn efx_rc_t
429 ef10_mcdi_feature_supported(
431 __in efx_mcdi_feature_id_t id,
432 __out boolean_t *supportedp);
436 ef10_mcdi_get_timeout(
438 __in efx_mcdi_req_t *emrp,
439 __out uint32_t *timeoutp);
441 #endif /* EFSYS_OPT_MCDI */
445 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
448 extern __checkReturn efx_rc_t
449 ef10_nvram_buf_read_tlv(
451 __in_bcount(max_seg_size) caddr_t seg_data,
452 __in size_t max_seg_size,
454 __deref_out_bcount_opt(*sizep) caddr_t *datap,
455 __out size_t *sizep);
458 extern __checkReturn efx_rc_t
459 ef10_nvram_buf_write_tlv(
460 __inout_bcount(partn_size) caddr_t partn_data,
461 __in size_t partn_size,
463 __in_bcount(tag_size) caddr_t tag_data,
464 __in size_t tag_size,
465 __out size_t *total_lengthp);
468 extern __checkReturn efx_rc_t
469 ef10_nvram_partn_read_tlv(
473 __deref_out_bcount_opt(*sizep) caddr_t *datap,
474 __out size_t *sizep);
477 extern __checkReturn efx_rc_t
478 ef10_nvram_partn_write_tlv(
482 __in_bcount(size) caddr_t data,
486 extern __checkReturn efx_rc_t
487 ef10_nvram_partn_write_segment_tlv(
491 __in_bcount(size) caddr_t data,
493 __in boolean_t all_segments);
496 extern __checkReturn efx_rc_t
497 ef10_nvram_partn_lock(
499 __in uint32_t partn);
502 extern __checkReturn efx_rc_t
503 ef10_nvram_partn_unlock(
506 __out_opt uint32_t *resultp);
508 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
515 extern __checkReturn efx_rc_t
517 __in efx_nic_t *enp);
519 #endif /* EFSYS_OPT_DIAG */
522 extern __checkReturn efx_rc_t
523 ef10_nvram_type_to_partn(
525 __in efx_nvram_type_t type,
526 __out uint32_t *partnp);
529 extern __checkReturn efx_rc_t
530 ef10_nvram_partn_size(
533 __out size_t *sizep);
536 extern __checkReturn efx_rc_t
537 ef10_nvram_partn_info(
540 __out efx_nvram_info_t * enip);
543 extern __checkReturn efx_rc_t
544 ef10_nvram_partn_rw_start(
547 __out size_t *chunk_sizep);
550 extern __checkReturn efx_rc_t
551 ef10_nvram_partn_read_mode(
554 __in unsigned int offset,
555 __out_bcount(size) caddr_t data,
560 extern __checkReturn efx_rc_t
561 ef10_nvram_partn_read(
564 __in unsigned int offset,
565 __out_bcount(size) caddr_t data,
569 extern __checkReturn efx_rc_t
570 ef10_nvram_partn_read_backup(
573 __in unsigned int offset,
574 __out_bcount(size) caddr_t data,
578 extern __checkReturn efx_rc_t
579 ef10_nvram_partn_erase(
582 __in unsigned int offset,
586 extern __checkReturn efx_rc_t
587 ef10_nvram_partn_write(
590 __in unsigned int offset,
591 __in_bcount(size) caddr_t data,
595 extern __checkReturn efx_rc_t
596 ef10_nvram_partn_rw_finish(
599 __out_opt uint32_t *verify_resultp);
602 extern __checkReturn efx_rc_t
603 ef10_nvram_partn_get_version(
606 __out uint32_t *subtypep,
607 __out_ecount(4) uint16_t version[4]);
610 extern __checkReturn efx_rc_t
611 ef10_nvram_partn_set_version(
614 __in_ecount(4) uint16_t version[4]);
617 extern __checkReturn efx_rc_t
618 ef10_nvram_buffer_validate(
620 __in_bcount(buffer_size)
622 __in size_t buffer_size);
626 ef10_nvram_buffer_init(
627 __out_bcount(buffer_size)
629 __in size_t buffer_size);
632 extern __checkReturn efx_rc_t
633 ef10_nvram_buffer_create(
634 __in uint32_t partn_type,
635 __out_bcount(buffer_size)
637 __in size_t buffer_size);
640 extern __checkReturn efx_rc_t
641 ef10_nvram_buffer_find_item_start(
642 __in_bcount(buffer_size)
644 __in size_t buffer_size,
645 __out uint32_t *startp);
648 extern __checkReturn efx_rc_t
649 ef10_nvram_buffer_find_end(
650 __in_bcount(buffer_size)
652 __in size_t buffer_size,
653 __in uint32_t offset,
654 __out uint32_t *endp);
657 extern __checkReturn __success(return != B_FALSE) boolean_t
658 ef10_nvram_buffer_find_item(
659 __in_bcount(buffer_size)
661 __in size_t buffer_size,
662 __in uint32_t offset,
663 __out uint32_t *startp,
664 __out uint32_t *lengthp);
667 extern __checkReturn efx_rc_t
668 ef10_nvram_buffer_peek_item(
669 __in_bcount(buffer_size)
671 __in size_t buffer_size,
672 __in uint32_t offset,
673 __out uint32_t *tagp,
674 __out uint32_t *lengthp,
675 __out uint32_t *value_offsetp);
678 extern __checkReturn efx_rc_t
679 ef10_nvram_buffer_get_item(
680 __in_bcount(buffer_size)
682 __in size_t buffer_size,
683 __in uint32_t offset,
684 __in uint32_t length,
685 __out uint32_t *tagp,
686 __out_bcount_part(value_max_size, *lengthp)
688 __in size_t value_max_size,
689 __out uint32_t *lengthp);
692 extern __checkReturn efx_rc_t
693 ef10_nvram_buffer_insert_item(
694 __in_bcount(buffer_size)
696 __in size_t buffer_size,
697 __in uint32_t offset,
699 __in_bcount(length) caddr_t valuep,
700 __in uint32_t length,
701 __out uint32_t *lengthp);
704 extern __checkReturn efx_rc_t
705 ef10_nvram_buffer_modify_item(
706 __in_bcount(buffer_size)
708 __in size_t buffer_size,
709 __in uint32_t offset,
711 __in_bcount(length) caddr_t valuep,
712 __in uint32_t length,
713 __out uint32_t *lengthp);
716 extern __checkReturn efx_rc_t
717 ef10_nvram_buffer_delete_item(
718 __in_bcount(buffer_size)
720 __in size_t buffer_size,
721 __in uint32_t offset,
722 __in uint32_t length,
726 extern __checkReturn efx_rc_t
727 ef10_nvram_buffer_finish(
728 __in_bcount(buffer_size)
730 __in size_t buffer_size);
732 #endif /* EFSYS_OPT_NVRAM */
737 typedef struct ef10_link_state_s {
738 efx_phy_link_state_t epls;
739 #if EFSYS_OPT_LOOPBACK
740 efx_loopback_type_t els_loopback;
742 boolean_t els_mac_up;
749 __in efx_qword_t *eqp,
750 __out efx_link_mode_t *link_modep);
753 extern __checkReturn efx_rc_t
756 __out ef10_link_state_t *elsp);
759 extern __checkReturn efx_rc_t
765 extern __checkReturn efx_rc_t
766 ef10_phy_reconfigure(
767 __in efx_nic_t *enp);
770 extern __checkReturn efx_rc_t
772 __in efx_nic_t *enp);
775 extern __checkReturn efx_rc_t
778 __out uint32_t *ouip);
781 extern __checkReturn efx_rc_t
782 ef10_phy_link_state_get(
784 __out efx_phy_link_state_t *eplsp);
786 #if EFSYS_OPT_PHY_STATS
789 extern __checkReturn efx_rc_t
790 ef10_phy_stats_update(
792 __in efsys_mem_t *esmp,
793 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
795 #endif /* EFSYS_OPT_PHY_STATS */
800 extern __checkReturn efx_rc_t
801 ef10_bist_enable_offline(
802 __in efx_nic_t *enp);
805 extern __checkReturn efx_rc_t
808 __in efx_bist_type_t type);
811 extern __checkReturn efx_rc_t
814 __in efx_bist_type_t type,
815 __out efx_bist_result_t *resultp,
816 __out_opt __drv_when(count > 0, __notnull)
817 uint32_t *value_maskp,
818 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
819 unsigned long *valuesp,
826 __in efx_bist_type_t type);
828 #endif /* EFSYS_OPT_BIST */
833 extern __checkReturn efx_rc_t
835 __in efx_nic_t *enp);
840 __in efx_nic_t *enp);
843 extern __checkReturn efx_rc_t
846 __in unsigned int index,
847 __in unsigned int label,
848 __in efsys_mem_t *esmp,
854 __out unsigned int *addedp);
859 __in efx_txq_t *etp);
862 extern __checkReturn efx_rc_t
865 __in_ecount(ndescs) efx_buffer_t *ebp,
866 __in unsigned int ndescs,
867 __in unsigned int completed,
868 __inout unsigned int *addedp);
874 __in unsigned int added,
875 __in unsigned int pushed);
877 #if EFSYS_OPT_RX_PACKED_STREAM
880 ef10_rx_qpush_ps_credits(
881 __in efx_rxq_t *erp);
884 extern __checkReturn uint8_t *
885 ef10_rx_qps_packet_info(
887 __in uint8_t *buffer,
888 __in uint32_t buffer_length,
889 __in uint32_t current_offset,
890 __out uint16_t *lengthp,
891 __out uint32_t *next_offsetp,
892 __out uint32_t *timestamp);
896 extern __checkReturn efx_rc_t
899 __in unsigned int ns);
902 extern __checkReturn efx_rc_t
904 __in efx_txq_t *etp);
909 __in efx_txq_t *etp);
912 extern __checkReturn efx_rc_t
914 __in efx_txq_t *etp);
918 ef10_tx_qpio_disable(
919 __in efx_txq_t *etp);
922 extern __checkReturn efx_rc_t
925 __in_ecount(buf_length) uint8_t *buffer,
926 __in size_t buf_length,
927 __in size_t pio_buf_offset);
930 extern __checkReturn efx_rc_t
933 __in size_t pkt_length,
934 __in unsigned int completed,
935 __inout unsigned int *addedp);
938 extern __checkReturn efx_rc_t
941 __in_ecount(n) efx_desc_t *ed,
943 __in unsigned int completed,
944 __inout unsigned int *addedp);
948 ef10_tx_qdesc_dma_create(
950 __in efsys_dma_addr_t addr,
953 __out efx_desc_t *edp);
957 ef10_tx_qdesc_tso_create(
959 __in uint16_t ipv4_id,
960 __in uint32_t tcp_seq,
961 __in uint8_t tcp_flags,
962 __out efx_desc_t *edp);
966 ef10_tx_qdesc_tso2_create(
968 __in uint16_t ipv4_id,
969 __in uint16_t outer_ipv4_id,
970 __in uint32_t tcp_seq,
971 __in uint16_t tcp_mss,
972 __out_ecount(count) efx_desc_t *edp,
977 ef10_tx_qdesc_vlantci_create(
979 __in uint16_t vlan_tci,
980 __out efx_desc_t *edp);
984 ef10_tx_qdesc_checksum_create(
987 __out efx_desc_t *edp);
993 ef10_tx_qstats_update(
995 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
997 #endif /* EFSYS_OPT_QSTATS */
999 typedef uint32_t efx_piobuf_handle_t;
1001 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
1004 extern __checkReturn efx_rc_t
1006 __inout efx_nic_t *enp,
1007 __out uint32_t *bufnump,
1008 __out efx_piobuf_handle_t *handlep,
1009 __out uint32_t *blknump,
1010 __out uint32_t *offsetp,
1011 __out size_t *sizep);
1014 extern __checkReturn efx_rc_t
1016 __inout efx_nic_t *enp,
1017 __in uint32_t bufnum,
1018 __in uint32_t blknum);
1021 extern __checkReturn efx_rc_t
1023 __inout efx_nic_t *enp,
1024 __in uint32_t vi_index,
1025 __in efx_piobuf_handle_t handle);
1028 extern __checkReturn efx_rc_t
1029 ef10_nic_pio_unlink(
1030 __inout efx_nic_t *enp,
1031 __in uint32_t vi_index);
1039 extern __checkReturn efx_rc_t
1041 __in efx_nic_t *enp);
1044 extern __checkReturn efx_rc_t
1046 __in efx_nic_t *enp,
1047 __out size_t *sizep);
1050 extern __checkReturn efx_rc_t
1052 __in efx_nic_t *enp,
1053 __out_bcount(size) caddr_t data,
1057 extern __checkReturn efx_rc_t
1059 __in efx_nic_t *enp,
1060 __in_bcount(size) caddr_t data,
1064 extern __checkReturn efx_rc_t
1066 __in efx_nic_t *enp,
1067 __in_bcount(size) caddr_t data,
1071 extern __checkReturn efx_rc_t
1073 __in efx_nic_t *enp,
1074 __in_bcount(size) caddr_t data,
1076 __inout efx_vpd_value_t *evvp);
1079 extern __checkReturn efx_rc_t
1081 __in efx_nic_t *enp,
1082 __in_bcount(size) caddr_t data,
1084 __in efx_vpd_value_t *evvp);
1087 extern __checkReturn efx_rc_t
1089 __in efx_nic_t *enp,
1090 __in_bcount(size) caddr_t data,
1092 __out efx_vpd_value_t *evvp,
1093 __inout unsigned int *contp);
1096 extern __checkReturn efx_rc_t
1098 __in efx_nic_t *enp,
1099 __in_bcount(size) caddr_t data,
1105 __in efx_nic_t *enp);
1107 #endif /* EFSYS_OPT_VPD */
1113 extern __checkReturn efx_rc_t
1115 __in efx_nic_t *enp);
1117 #if EFSYS_OPT_RX_SCATTER
1119 extern __checkReturn efx_rc_t
1120 ef10_rx_scatter_enable(
1121 __in efx_nic_t *enp,
1122 __in unsigned int buf_size);
1123 #endif /* EFSYS_OPT_RX_SCATTER */
1126 #if EFSYS_OPT_RX_SCALE
1129 extern __checkReturn efx_rc_t
1130 ef10_rx_scale_context_alloc(
1131 __in efx_nic_t *enp,
1132 __in efx_rx_scale_context_type_t type,
1133 __in uint32_t num_queues,
1134 __out uint32_t *rss_contextp);
1137 extern __checkReturn efx_rc_t
1138 ef10_rx_scale_context_free(
1139 __in efx_nic_t *enp,
1140 __in uint32_t rss_context);
1143 extern __checkReturn efx_rc_t
1144 ef10_rx_scale_mode_set(
1145 __in efx_nic_t *enp,
1146 __in uint32_t rss_context,
1147 __in efx_rx_hash_alg_t alg,
1148 __in efx_rx_hash_type_t type,
1149 __in boolean_t insert);
1152 extern __checkReturn efx_rc_t
1153 ef10_rx_scale_key_set(
1154 __in efx_nic_t *enp,
1155 __in uint32_t rss_context,
1156 __in_ecount(n) uint8_t *key,
1160 extern __checkReturn efx_rc_t
1161 ef10_rx_scale_tbl_set(
1162 __in efx_nic_t *enp,
1163 __in uint32_t rss_context,
1164 __in_ecount(n) unsigned int *table,
1168 extern __checkReturn uint32_t
1169 ef10_rx_prefix_hash(
1170 __in efx_nic_t *enp,
1171 __in efx_rx_hash_alg_t func,
1172 __in uint8_t *buffer);
1174 #endif /* EFSYS_OPT_RX_SCALE */
1177 extern __checkReturn efx_rc_t
1178 ef10_rx_prefix_pktlen(
1179 __in efx_nic_t *enp,
1180 __in uint8_t *buffer,
1181 __out uint16_t *lengthp);
1186 __in efx_rxq_t *erp,
1187 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1189 __in unsigned int ndescs,
1190 __in unsigned int completed,
1191 __in unsigned int added);
1196 __in efx_rxq_t *erp,
1197 __in unsigned int added,
1198 __inout unsigned int *pushedp);
1201 extern __checkReturn efx_rc_t
1203 __in efx_rxq_t *erp);
1208 __in efx_rxq_t *erp);
1210 union efx_rxq_type_data_u;
1213 extern __checkReturn efx_rc_t
1215 __in efx_nic_t *enp,
1216 __in unsigned int index,
1217 __in unsigned int label,
1218 __in efx_rxq_type_t type,
1219 __in_opt const union efx_rxq_type_data_u *type_data,
1220 __in efsys_mem_t *esmp,
1223 __in unsigned int flags,
1224 __in efx_evq_t *eep,
1225 __in efx_rxq_t *erp);
1230 __in efx_rxq_t *erp);
1235 __in efx_nic_t *enp);
1237 #if EFSYS_OPT_FILTER
1239 enum efx_filter_replacement_policy_e;
1241 typedef struct ef10_filter_handle_s {
1244 } ef10_filter_handle_t;
1246 typedef struct ef10_filter_entry_s {
1247 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1248 ef10_filter_handle_t efe_handle;
1249 } ef10_filter_entry_t;
1252 * BUSY flag indicates that an update is in progress.
1253 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1255 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1256 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1257 #define EFX_EF10_FILTER_FLAGS 3U
1260 * Size of the hash table used by the driver. Doesn't need to be the
1261 * same size as the hardware's table.
1263 #define EFX_EF10_FILTER_TBL_ROWS 8192
1265 /* Only need to allow for one directed and one unknown unicast filter */
1266 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1268 /* Allow for the broadcast address to be added to the multicast list */
1269 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1272 * For encapsulated packets, there is one filter each for each combination of
1273 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1274 * multicast inner frames.
1276 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1278 typedef struct ef10_filter_table_s {
1279 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1280 efx_rxq_t *eft_default_rxq;
1281 boolean_t eft_using_rss;
1282 uint32_t eft_unicst_filter_indexes[
1283 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1284 uint32_t eft_unicst_filter_count;
1285 uint32_t eft_mulcst_filter_indexes[
1286 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1287 uint32_t eft_mulcst_filter_count;
1288 boolean_t eft_using_all_mulcst;
1289 uint32_t eft_encap_filter_indexes[
1290 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1291 uint32_t eft_encap_filter_count;
1292 } ef10_filter_table_t;
1295 extern __checkReturn efx_rc_t
1297 __in efx_nic_t *enp);
1302 __in efx_nic_t *enp);
1305 extern __checkReturn efx_rc_t
1306 ef10_filter_restore(
1307 __in efx_nic_t *enp);
1310 extern __checkReturn efx_rc_t
1312 __in efx_nic_t *enp,
1313 __inout efx_filter_spec_t *spec,
1314 __in enum efx_filter_replacement_policy_e policy);
1317 extern __checkReturn efx_rc_t
1319 __in efx_nic_t *enp,
1320 __inout efx_filter_spec_t *spec);
1323 extern __checkReturn efx_rc_t
1324 ef10_filter_supported_filters(
1325 __in efx_nic_t *enp,
1326 __out_ecount(buffer_length) uint32_t *buffer,
1327 __in size_t buffer_length,
1328 __out size_t *list_lengthp);
1331 extern __checkReturn efx_rc_t
1332 ef10_filter_reconfigure(
1333 __in efx_nic_t *enp,
1334 __in_ecount(6) uint8_t const *mac_addr,
1335 __in boolean_t all_unicst,
1336 __in boolean_t mulcst,
1337 __in boolean_t all_mulcst,
1338 __in boolean_t brdcst,
1339 __in_ecount(6*count) uint8_t const *addrs,
1340 __in uint32_t count);
1344 ef10_filter_get_default_rxq(
1345 __in efx_nic_t *enp,
1346 __out efx_rxq_t **erpp,
1347 __out boolean_t *using_rss);
1351 ef10_filter_default_rxq_set(
1352 __in efx_nic_t *enp,
1353 __in efx_rxq_t *erp,
1354 __in boolean_t using_rss);
1358 ef10_filter_default_rxq_clear(
1359 __in efx_nic_t *enp);
1362 #endif /* EFSYS_OPT_FILTER */
1365 extern __checkReturn efx_rc_t
1366 efx_mcdi_get_function_info(
1367 __in efx_nic_t *enp,
1368 __out uint32_t *pfp,
1369 __out_opt uint32_t *vfp);
1372 extern __checkReturn efx_rc_t
1373 efx_mcdi_privilege_mask(
1374 __in efx_nic_t *enp,
1377 __out uint32_t *maskp);
1380 extern __checkReturn efx_rc_t
1381 efx_mcdi_get_port_assignment(
1382 __in efx_nic_t *enp,
1383 __out uint32_t *portp);
1386 extern __checkReturn efx_rc_t
1387 efx_mcdi_get_port_modes(
1388 __in efx_nic_t *enp,
1389 __out uint32_t *modesp,
1390 __out_opt uint32_t *current_modep,
1391 __out_opt uint32_t *default_modep);
1394 extern __checkReturn efx_rc_t
1395 ef10_nic_get_port_mode_bandwidth(
1396 __in efx_nic_t *enp,
1397 __out uint32_t *bandwidth_mbpsp);
1400 extern __checkReturn efx_rc_t
1401 efx_mcdi_get_mac_address_pf(
1402 __in efx_nic_t *enp,
1403 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1406 extern __checkReturn efx_rc_t
1407 efx_mcdi_get_mac_address_vf(
1408 __in efx_nic_t *enp,
1409 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1412 extern __checkReturn efx_rc_t
1414 __in efx_nic_t *enp,
1415 __out uint32_t *sys_freqp,
1416 __out uint32_t *dpcpu_freqp);
1420 extern __checkReturn efx_rc_t
1421 efx_mcdi_get_rxdp_config(
1422 __in efx_nic_t *enp,
1423 __out uint32_t *end_paddingp);
1426 extern __checkReturn efx_rc_t
1427 efx_mcdi_get_vector_cfg(
1428 __in efx_nic_t *enp,
1429 __out_opt uint32_t *vec_basep,
1430 __out_opt uint32_t *pf_nvecp,
1431 __out_opt uint32_t *vf_nvecp);
1434 extern __checkReturn efx_rc_t
1436 __in efx_nic_t *enp,
1437 __in uint32_t min_vi_count,
1438 __in uint32_t max_vi_count,
1439 __out uint32_t *vi_basep,
1440 __out uint32_t *vi_countp,
1441 __out uint32_t *vi_shiftp);
1444 extern __checkReturn efx_rc_t
1446 __in efx_nic_t *enp);
1449 extern __checkReturn efx_rc_t
1450 ef10_get_privilege_mask(
1451 __in efx_nic_t *enp,
1452 __out uint32_t *maskp);
1455 extern __checkReturn efx_rc_t
1456 efx_mcdi_nic_board_cfg(
1457 __in efx_nic_t *enp);
1460 extern __checkReturn efx_rc_t
1461 efx_mcdi_entity_reset(
1462 __in efx_nic_t *enp);
1464 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1467 extern __checkReturn efx_rc_t
1468 efx_mcdi_get_nic_global(
1469 __in efx_nic_t *enp,
1471 __out uint32_t *valuep);
1474 extern __checkReturn efx_rc_t
1475 efx_mcdi_set_nic_global(
1476 __in efx_nic_t *enp,
1478 __in uint32_t value);
1480 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1484 extern __checkReturn efx_rc_t
1486 __in efx_nic_t *enp);
1491 __in efx_nic_t *enp);
1494 extern __checkReturn efx_rc_t
1495 ef10_evb_vswitch_alloc(
1496 __in efx_nic_t *enp,
1497 __out efx_vswitch_id_t *vswitch_idp);
1501 extern __checkReturn efx_rc_t
1502 ef10_evb_vswitch_free(
1503 __in efx_nic_t *enp,
1504 __in efx_vswitch_id_t vswitch_id);
1507 extern __checkReturn efx_rc_t
1508 ef10_evb_vport_alloc(
1509 __in efx_nic_t *enp,
1510 __in efx_vswitch_id_t vswitch_id,
1511 __in efx_vport_type_t vport_type,
1513 __in boolean_t vlan_restrict,
1514 __out efx_vport_id_t *vport_idp);
1518 extern __checkReturn efx_rc_t
1519 ef10_evb_vport_free(
1520 __in efx_nic_t *enp,
1521 __in efx_vswitch_id_t vswitch_id,
1522 __in efx_vport_id_t vport_id);
1525 extern __checkReturn efx_rc_t
1526 ef10_evb_vport_mac_addr_add(
1527 __in efx_nic_t *enp,
1528 __in efx_vswitch_id_t vswitch_id,
1529 __in efx_vport_id_t vport_id,
1530 __in_ecount(6) uint8_t *addrp);
1533 extern __checkReturn efx_rc_t
1534 ef10_evb_vport_mac_addr_del(
1535 __in efx_nic_t *enp,
1536 __in efx_vswitch_id_t vswitch_id,
1537 __in efx_vport_id_t vport_id,
1538 __in_ecount(6) uint8_t *addrp);
1541 extern __checkReturn efx_rc_t
1542 ef10_evb_vadaptor_alloc(
1543 __in efx_nic_t *enp,
1544 __in efx_vswitch_id_t vswitch_id,
1545 __in efx_vport_id_t vport_id);
1549 extern __checkReturn efx_rc_t
1550 ef10_evb_vadaptor_free(
1551 __in efx_nic_t *enp,
1552 __in efx_vswitch_id_t vswitch_id,
1553 __in efx_vport_id_t vport_id);
1556 extern __checkReturn efx_rc_t
1557 ef10_evb_vport_assign(
1558 __in efx_nic_t *enp,
1559 __in efx_vswitch_id_t vswitch_id,
1560 __in efx_vport_id_t vport_id,
1561 __in uint32_t vf_index);
1564 extern __checkReturn efx_rc_t
1565 ef10_evb_vport_reconfigure(
1566 __in efx_nic_t *enp,
1567 __in efx_vswitch_id_t vswitch_id,
1568 __in efx_vport_id_t vport_id,
1569 __in_opt uint16_t *vidp,
1570 __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
1571 __out_opt boolean_t *fn_resetp);
1574 extern __checkReturn efx_rc_t
1575 ef10_evb_vport_stats(
1576 __in efx_nic_t *enp,
1577 __in efx_vswitch_id_t vswitch_id,
1578 __in efx_vport_id_t vport_id,
1579 __out efsys_mem_t *esmp);
1581 #endif /* EFSYS_OPT_EVB */
1583 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
1585 extern __checkReturn efx_rc_t
1586 ef10_proxy_auth_init(
1587 __in efx_nic_t *enp);
1591 ef10_proxy_auth_fini(
1592 __in efx_nic_t *enp);
1595 extern __checkReturn efx_rc_t
1596 ef10_proxy_auth_mc_config(
1597 __in efx_nic_t *enp,
1598 __in efsys_mem_t *request_bufferp,
1599 __in efsys_mem_t *response_bufferp,
1600 __in efsys_mem_t *status_bufferp,
1601 __in uint32_t block_cnt,
1602 __in_ecount(op_count) uint32_t *op_listp,
1603 __in size_t op_count);
1606 extern __checkReturn efx_rc_t
1607 ef10_proxy_auth_disable(
1608 __in efx_nic_t *enp);
1611 extern __checkReturn efx_rc_t
1612 ef10_proxy_auth_privilege_modify(
1613 __in efx_nic_t *enp,
1614 __in uint32_t fn_group,
1615 __in uint32_t pf_index,
1616 __in uint32_t vf_index,
1617 __in uint32_t add_privileges_mask,
1618 __in uint32_t remove_privileges_mask);
1621 extern __checkReturn efx_rc_t
1622 ef10_proxy_auth_set_privilege_mask(
1623 __in efx_nic_t *enp,
1624 __in uint32_t vf_index,
1626 __in uint32_t value);
1629 extern __checkReturn efx_rc_t
1630 ef10_proxy_auth_complete_request(
1631 __in efx_nic_t *enp,
1632 __in uint32_t fn_index,
1633 __in uint32_t proxy_result,
1634 __in uint32_t handle);
1637 extern __checkReturn efx_rc_t
1638 ef10_proxy_auth_exec_cmd(
1639 __in efx_nic_t *enp,
1640 __inout efx_proxy_cmd_params_t *paramsp);
1643 extern __checkReturn efx_rc_t
1644 ef10_proxy_auth_get_privilege_mask(
1645 __in efx_nic_t *enp,
1646 __in uint32_t pf_index,
1647 __in uint32_t vf_index,
1648 __out uint32_t *maskp);
1650 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
1652 #if EFSYS_OPT_RX_PACKED_STREAM
1654 /* Data space per credit in packed stream mode */
1655 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1658 * Received packets are always aligned at this boundary. Also there always
1659 * exists a gap of this size between packets.
1660 * (see SF-112241-TC, 4.5)
1662 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1665 * Size of a pseudo-header prepended to received packets
1666 * in packed stream mode
1668 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1670 /* Minimum space for packet in packed stream mode */
1671 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1672 EFX_P2ROUNDUP(size_t, \
1673 EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1675 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1676 EFX_RX_PACKED_STREAM_ALIGNMENT)
1678 /* Maximum number of credits */
1679 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1681 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1683 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1686 * Maximum DMA length and buffer stride alignment.
1687 * (see SF-119419-TC, 3.2)
1689 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1697 #endif /* _SYS_EF10_IMPL_H */