1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
20 #define EF10_TXQ_MINNDESCS 512
22 #define EF10_EVQ_DESC_SIZE (sizeof (efx_qword_t))
23 #define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t))
24 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
26 /* Number of hardware EVQ buffers (for compile-time resource dimensions) */
27 #define EF10_EVQ_MAXNBUFS (64)
29 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
30 #define EF10_TXQ_MAXNBUFS 8
32 #if EFSYS_OPT_HUNTINGTON
33 # if (EF10_EVQ_MAXNBUFS < HUNT_EVQ_MAXNBUFS)
34 # error "EF10_EVQ_MAXNBUFS too small"
36 #endif /* EFSYS_OPT_HUNTINGTON */
38 # if (EF10_EVQ_MAXNBUFS < MEDFORD_EVQ_MAXNBUFS)
39 # error "EF10_EVQ_MAXNBUFS too small"
41 #endif /* EFSYS_OPT_MEDFORD */
42 #if EFSYS_OPT_MEDFORD2
43 # if (EF10_EVQ_MAXNBUFS < MEDFORD2_EVQ_MAXNBUFS)
44 # error "EF10_EVQ_MAXNBUFS too small"
46 #endif /* EFSYS_OPT_MEDFORD2 */
48 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
49 #define EF10_MAX_PIOBUF_NBUFS (16)
51 #if EFSYS_OPT_HUNTINGTON
52 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
53 # error "EF10_MAX_PIOBUF_NBUFS too small"
55 #endif /* EFSYS_OPT_HUNTINGTON */
57 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
58 # error "EF10_MAX_PIOBUF_NBUFS too small"
60 #endif /* EFSYS_OPT_MEDFORD */
61 #if EFSYS_OPT_MEDFORD2
62 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
63 # error "EF10_MAX_PIOBUF_NBUFS too small"
65 #endif /* EFSYS_OPT_MEDFORD2 */
70 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
71 * possibly be increased, or the write size reported by newer firmware used
74 #define EF10_NVRAM_CHUNK 0x80
77 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
78 * to an 8 descriptor boundary.
80 #define EF10_RX_WPTR_ALIGN 8
83 * Max byte offset into the packet the TCP header must start for the hardware
84 * to be able to parse the packet correctly.
86 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
88 /* Invalid RSS context handle */
89 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
95 extern __checkReturn efx_rc_t
102 __in efx_nic_t *enp);
105 extern __checkReturn efx_rc_t
108 __in unsigned int index,
109 __in efsys_mem_t *esmp,
114 __in efx_evq_t *eep);
119 __in efx_evq_t *eep);
122 extern __checkReturn efx_rc_t
125 __in unsigned int count);
134 extern __checkReturn efx_rc_t
137 __in unsigned int us);
142 ef10_ev_qstats_update(
144 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
145 #endif /* EFSYS_OPT_QSTATS */
149 ef10_ev_rxlabel_init(
152 __in unsigned int label,
153 __in efx_rxq_type_t type);
157 ef10_ev_rxlabel_fini(
159 __in unsigned int label);
164 extern __checkReturn efx_rc_t
167 __in efx_intr_type_t type,
168 __in efsys_mem_t *esmp);
173 __in efx_nic_t *enp);
178 __in efx_nic_t *enp);
182 ef10_intr_disable_unlocked(
183 __in efx_nic_t *enp);
186 extern __checkReturn efx_rc_t
189 __in unsigned int level);
193 ef10_intr_status_line(
195 __out boolean_t *fatalp,
196 __out uint32_t *qmaskp);
200 ef10_intr_status_message(
202 __in unsigned int message,
203 __out boolean_t *fatalp);
208 __in efx_nic_t *enp);
213 __in efx_nic_t *enp);
218 extern __checkReturn efx_rc_t
219 efx_mcdi_vadaptor_alloc(
221 __in uint32_t port_id);
224 extern __checkReturn efx_rc_t
225 efx_mcdi_vadaptor_free(
227 __in uint32_t port_id);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
235 extern __checkReturn efx_rc_t
236 ef10_nic_set_drv_limits(
237 __inout efx_nic_t *enp,
238 __in efx_drv_limits_t *edlp);
241 extern __checkReturn efx_rc_t
242 ef10_nic_get_vi_pool(
244 __out uint32_t *vi_countp);
247 extern __checkReturn efx_rc_t
248 ef10_nic_get_bar_region(
250 __in efx_nic_region_t region,
251 __out uint32_t *offsetp,
252 __out size_t *sizep);
255 extern __checkReturn efx_rc_t
257 __in efx_nic_t *enp);
260 extern __checkReturn efx_rc_t
262 __in efx_nic_t *enp);
265 extern __checkReturn boolean_t
266 ef10_nic_hw_unavailable(
267 __in efx_nic_t *enp);
271 ef10_nic_set_hw_unavailable(
272 __in efx_nic_t *enp);
277 extern __checkReturn efx_rc_t
278 ef10_nic_register_test(
279 __in efx_nic_t *enp);
281 #endif /* EFSYS_OPT_DIAG */
286 __in efx_nic_t *enp);
291 __in efx_nic_t *enp);
297 extern __checkReturn efx_rc_t
300 __out efx_link_mode_t *link_modep);
303 extern __checkReturn efx_rc_t
306 __out boolean_t *mac_upp);
309 extern __checkReturn efx_rc_t
311 __in efx_nic_t *enp);
314 extern __checkReturn efx_rc_t
316 __in efx_nic_t *enp);
319 extern __checkReturn efx_rc_t
325 extern __checkReturn efx_rc_t
326 ef10_mac_reconfigure(
327 __in efx_nic_t *enp);
330 extern __checkReturn efx_rc_t
331 ef10_mac_multicast_list_set(
332 __in efx_nic_t *enp);
335 extern __checkReturn efx_rc_t
336 ef10_mac_filter_default_rxq_set(
339 __in boolean_t using_rss);
343 ef10_mac_filter_default_rxq_clear(
344 __in efx_nic_t *enp);
346 #if EFSYS_OPT_LOOPBACK
349 extern __checkReturn efx_rc_t
350 ef10_mac_loopback_set(
352 __in efx_link_mode_t link_mode,
353 __in efx_loopback_type_t loopback_type);
355 #endif /* EFSYS_OPT_LOOPBACK */
357 #if EFSYS_OPT_MAC_STATS
360 extern __checkReturn efx_rc_t
361 ef10_mac_stats_get_mask(
363 __inout_bcount(mask_size) uint32_t *maskp,
364 __in size_t mask_size);
367 extern __checkReturn efx_rc_t
368 ef10_mac_stats_update(
370 __in efsys_mem_t *esmp,
371 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
372 __inout_opt uint32_t *generationp);
374 #endif /* EFSYS_OPT_MAC_STATS */
382 extern __checkReturn efx_rc_t
385 __in const efx_mcdi_transport_t *mtp);
390 __in efx_nic_t *enp);
394 ef10_mcdi_send_request(
396 __in_bcount(hdr_len) void *hdrp,
398 __in_bcount(sdu_len) void *sdup,
399 __in size_t sdu_len);
402 extern __checkReturn boolean_t
403 ef10_mcdi_poll_response(
404 __in efx_nic_t *enp);
408 ef10_mcdi_read_response(
410 __out_bcount(length) void *bufferp,
416 ef10_mcdi_poll_reboot(
417 __in efx_nic_t *enp);
420 extern __checkReturn efx_rc_t
421 ef10_mcdi_feature_supported(
423 __in efx_mcdi_feature_id_t id,
424 __out boolean_t *supportedp);
428 ef10_mcdi_get_timeout(
430 __in efx_mcdi_req_t *emrp,
431 __out uint32_t *timeoutp);
433 #endif /* EFSYS_OPT_MCDI */
437 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
440 extern __checkReturn efx_rc_t
441 ef10_nvram_buf_read_tlv(
443 __in_bcount(max_seg_size) caddr_t seg_data,
444 __in size_t max_seg_size,
446 __deref_out_bcount_opt(*sizep) caddr_t *datap,
447 __out size_t *sizep);
450 extern __checkReturn efx_rc_t
451 ef10_nvram_buf_write_tlv(
452 __inout_bcount(partn_size) caddr_t partn_data,
453 __in size_t partn_size,
455 __in_bcount(tag_size) caddr_t tag_data,
456 __in size_t tag_size,
457 __out size_t *total_lengthp);
460 extern __checkReturn efx_rc_t
461 ef10_nvram_partn_read_tlv(
465 __deref_out_bcount_opt(*sizep) caddr_t *datap,
466 __out size_t *sizep);
469 extern __checkReturn efx_rc_t
470 ef10_nvram_partn_write_tlv(
474 __in_bcount(size) caddr_t data,
478 extern __checkReturn efx_rc_t
479 ef10_nvram_partn_write_segment_tlv(
483 __in_bcount(size) caddr_t data,
485 __in boolean_t all_segments);
488 extern __checkReturn efx_rc_t
489 ef10_nvram_partn_lock(
491 __in uint32_t partn);
494 extern __checkReturn efx_rc_t
495 ef10_nvram_partn_unlock(
498 __out_opt uint32_t *resultp);
500 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
507 extern __checkReturn efx_rc_t
509 __in efx_nic_t *enp);
511 #endif /* EFSYS_OPT_DIAG */
514 extern __checkReturn efx_rc_t
515 ef10_nvram_type_to_partn(
517 __in efx_nvram_type_t type,
518 __out uint32_t *partnp);
521 extern __checkReturn efx_rc_t
522 ef10_nvram_partn_size(
525 __out size_t *sizep);
528 extern __checkReturn efx_rc_t
529 ef10_nvram_partn_info(
532 __out efx_nvram_info_t * enip);
535 extern __checkReturn efx_rc_t
536 ef10_nvram_partn_rw_start(
539 __out size_t *chunk_sizep);
542 extern __checkReturn efx_rc_t
543 ef10_nvram_partn_read_mode(
546 __in unsigned int offset,
547 __out_bcount(size) caddr_t data,
552 extern __checkReturn efx_rc_t
553 ef10_nvram_partn_read(
556 __in unsigned int offset,
557 __out_bcount(size) caddr_t data,
561 extern __checkReturn efx_rc_t
562 ef10_nvram_partn_read_backup(
565 __in unsigned int offset,
566 __out_bcount(size) caddr_t data,
570 extern __checkReturn efx_rc_t
571 ef10_nvram_partn_erase(
574 __in unsigned int offset,
578 extern __checkReturn efx_rc_t
579 ef10_nvram_partn_write(
582 __in unsigned int offset,
583 __in_bcount(size) caddr_t data,
587 extern __checkReturn efx_rc_t
588 ef10_nvram_partn_rw_finish(
591 __out_opt uint32_t *verify_resultp);
594 extern __checkReturn efx_rc_t
595 ef10_nvram_partn_get_version(
598 __out uint32_t *subtypep,
599 __out_ecount(4) uint16_t version[4]);
602 extern __checkReturn efx_rc_t
603 ef10_nvram_partn_set_version(
606 __in_ecount(4) uint16_t version[4]);
609 extern __checkReturn efx_rc_t
610 ef10_nvram_buffer_validate(
612 __in_bcount(buffer_size)
614 __in size_t buffer_size);
618 ef10_nvram_buffer_init(
619 __out_bcount(buffer_size)
621 __in size_t buffer_size);
624 extern __checkReturn efx_rc_t
625 ef10_nvram_buffer_create(
626 __in uint32_t partn_type,
627 __out_bcount(buffer_size)
629 __in size_t buffer_size);
632 extern __checkReturn efx_rc_t
633 ef10_nvram_buffer_find_item_start(
634 __in_bcount(buffer_size)
636 __in size_t buffer_size,
637 __out uint32_t *startp);
640 extern __checkReturn efx_rc_t
641 ef10_nvram_buffer_find_end(
642 __in_bcount(buffer_size)
644 __in size_t buffer_size,
645 __in uint32_t offset,
646 __out uint32_t *endp);
649 extern __checkReturn __success(return != B_FALSE) boolean_t
650 ef10_nvram_buffer_find_item(
651 __in_bcount(buffer_size)
653 __in size_t buffer_size,
654 __in uint32_t offset,
655 __out uint32_t *startp,
656 __out uint32_t *lengthp);
659 extern __checkReturn efx_rc_t
660 ef10_nvram_buffer_peek_item(
661 __in_bcount(buffer_size)
663 __in size_t buffer_size,
664 __in uint32_t offset,
665 __out uint32_t *tagp,
666 __out uint32_t *lengthp,
667 __out uint32_t *value_offsetp);
670 extern __checkReturn efx_rc_t
671 ef10_nvram_buffer_get_item(
672 __in_bcount(buffer_size)
674 __in size_t buffer_size,
675 __in uint32_t offset,
676 __in uint32_t length,
677 __out uint32_t *tagp,
678 __out_bcount_part(value_max_size, *lengthp)
680 __in size_t value_max_size,
681 __out uint32_t *lengthp);
684 extern __checkReturn efx_rc_t
685 ef10_nvram_buffer_insert_item(
686 __in_bcount(buffer_size)
688 __in size_t buffer_size,
689 __in uint32_t offset,
691 __in_bcount(length) caddr_t valuep,
692 __in uint32_t length,
693 __out uint32_t *lengthp);
696 extern __checkReturn efx_rc_t
697 ef10_nvram_buffer_modify_item(
698 __in_bcount(buffer_size)
700 __in size_t buffer_size,
701 __in uint32_t offset,
703 __in_bcount(length) caddr_t valuep,
704 __in uint32_t length,
705 __out uint32_t *lengthp);
708 extern __checkReturn efx_rc_t
709 ef10_nvram_buffer_delete_item(
710 __in_bcount(buffer_size)
712 __in size_t buffer_size,
713 __in uint32_t offset,
714 __in uint32_t length,
718 extern __checkReturn efx_rc_t
719 ef10_nvram_buffer_finish(
720 __in_bcount(buffer_size)
722 __in size_t buffer_size);
724 #endif /* EFSYS_OPT_NVRAM */
729 typedef struct ef10_link_state_s {
730 efx_phy_link_state_t epls;
731 #if EFSYS_OPT_LOOPBACK
732 efx_loopback_type_t els_loopback;
734 boolean_t els_mac_up;
741 __in efx_qword_t *eqp,
742 __out efx_link_mode_t *link_modep);
745 extern __checkReturn efx_rc_t
748 __out ef10_link_state_t *elsp);
751 extern __checkReturn efx_rc_t
757 extern __checkReturn efx_rc_t
758 ef10_phy_reconfigure(
759 __in efx_nic_t *enp);
762 extern __checkReturn efx_rc_t
764 __in efx_nic_t *enp);
767 extern __checkReturn efx_rc_t
770 __out uint32_t *ouip);
773 extern __checkReturn efx_rc_t
774 ef10_phy_link_state_get(
776 __out efx_phy_link_state_t *eplsp);
778 #if EFSYS_OPT_PHY_STATS
781 extern __checkReturn efx_rc_t
782 ef10_phy_stats_update(
784 __in efsys_mem_t *esmp,
785 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
787 #endif /* EFSYS_OPT_PHY_STATS */
792 extern __checkReturn efx_rc_t
793 ef10_bist_enable_offline(
794 __in efx_nic_t *enp);
797 extern __checkReturn efx_rc_t
800 __in efx_bist_type_t type);
803 extern __checkReturn efx_rc_t
806 __in efx_bist_type_t type,
807 __out efx_bist_result_t *resultp,
808 __out_opt __drv_when(count > 0, __notnull)
809 uint32_t *value_maskp,
810 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
811 unsigned long *valuesp,
818 __in efx_bist_type_t type);
820 #endif /* EFSYS_OPT_BIST */
825 extern __checkReturn efx_rc_t
827 __in efx_nic_t *enp);
832 __in efx_nic_t *enp);
835 extern __checkReturn efx_rc_t
838 __in unsigned int index,
839 __in unsigned int label,
840 __in efsys_mem_t *esmp,
846 __out unsigned int *addedp);
851 __in efx_txq_t *etp);
854 extern __checkReturn efx_rc_t
857 __in_ecount(ndescs) efx_buffer_t *ebp,
858 __in unsigned int ndescs,
859 __in unsigned int completed,
860 __inout unsigned int *addedp);
866 __in unsigned int added,
867 __in unsigned int pushed);
869 #if EFSYS_OPT_RX_PACKED_STREAM
872 ef10_rx_qpush_ps_credits(
873 __in efx_rxq_t *erp);
876 extern __checkReturn uint8_t *
877 ef10_rx_qps_packet_info(
879 __in uint8_t *buffer,
880 __in uint32_t buffer_length,
881 __in uint32_t current_offset,
882 __out uint16_t *lengthp,
883 __out uint32_t *next_offsetp,
884 __out uint32_t *timestamp);
888 extern __checkReturn efx_rc_t
891 __in unsigned int ns);
894 extern __checkReturn efx_rc_t
896 __in efx_txq_t *etp);
901 __in efx_txq_t *etp);
904 extern __checkReturn efx_rc_t
906 __in efx_txq_t *etp);
910 ef10_tx_qpio_disable(
911 __in efx_txq_t *etp);
914 extern __checkReturn efx_rc_t
917 __in_ecount(buf_length) uint8_t *buffer,
918 __in size_t buf_length,
919 __in size_t pio_buf_offset);
922 extern __checkReturn efx_rc_t
925 __in size_t pkt_length,
926 __in unsigned int completed,
927 __inout unsigned int *addedp);
930 extern __checkReturn efx_rc_t
933 __in_ecount(n) efx_desc_t *ed,
935 __in unsigned int completed,
936 __inout unsigned int *addedp);
940 ef10_tx_qdesc_dma_create(
942 __in efsys_dma_addr_t addr,
945 __out efx_desc_t *edp);
949 ef10_tx_qdesc_tso_create(
951 __in uint16_t ipv4_id,
952 __in uint32_t tcp_seq,
953 __in uint8_t tcp_flags,
954 __out efx_desc_t *edp);
958 ef10_tx_qdesc_tso2_create(
960 __in uint16_t ipv4_id,
961 __in uint16_t outer_ipv4_id,
962 __in uint32_t tcp_seq,
963 __in uint16_t tcp_mss,
964 __out_ecount(count) efx_desc_t *edp,
969 ef10_tx_qdesc_vlantci_create(
971 __in uint16_t vlan_tci,
972 __out efx_desc_t *edp);
976 ef10_tx_qdesc_checksum_create(
979 __out efx_desc_t *edp);
985 ef10_tx_qstats_update(
987 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
989 #endif /* EFSYS_OPT_QSTATS */
991 typedef uint32_t efx_piobuf_handle_t;
993 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
996 extern __checkReturn efx_rc_t
998 __inout efx_nic_t *enp,
999 __out uint32_t *bufnump,
1000 __out efx_piobuf_handle_t *handlep,
1001 __out uint32_t *blknump,
1002 __out uint32_t *offsetp,
1003 __out size_t *sizep);
1006 extern __checkReturn efx_rc_t
1008 __inout efx_nic_t *enp,
1009 __in uint32_t bufnum,
1010 __in uint32_t blknum);
1013 extern __checkReturn efx_rc_t
1015 __inout efx_nic_t *enp,
1016 __in uint32_t vi_index,
1017 __in efx_piobuf_handle_t handle);
1020 extern __checkReturn efx_rc_t
1021 ef10_nic_pio_unlink(
1022 __inout efx_nic_t *enp,
1023 __in uint32_t vi_index);
1031 extern __checkReturn efx_rc_t
1033 __in efx_nic_t *enp);
1036 extern __checkReturn efx_rc_t
1038 __in efx_nic_t *enp,
1039 __out size_t *sizep);
1042 extern __checkReturn efx_rc_t
1044 __in efx_nic_t *enp,
1045 __out_bcount(size) caddr_t data,
1049 extern __checkReturn efx_rc_t
1051 __in efx_nic_t *enp,
1052 __in_bcount(size) caddr_t data,
1056 extern __checkReturn efx_rc_t
1058 __in efx_nic_t *enp,
1059 __in_bcount(size) caddr_t data,
1063 extern __checkReturn efx_rc_t
1065 __in efx_nic_t *enp,
1066 __in_bcount(size) caddr_t data,
1068 __inout efx_vpd_value_t *evvp);
1071 extern __checkReturn efx_rc_t
1073 __in efx_nic_t *enp,
1074 __in_bcount(size) caddr_t data,
1076 __in efx_vpd_value_t *evvp);
1079 extern __checkReturn efx_rc_t
1081 __in efx_nic_t *enp,
1082 __in_bcount(size) caddr_t data,
1084 __out efx_vpd_value_t *evvp,
1085 __inout unsigned int *contp);
1088 extern __checkReturn efx_rc_t
1090 __in efx_nic_t *enp,
1091 __in_bcount(size) caddr_t data,
1097 __in efx_nic_t *enp);
1099 #endif /* EFSYS_OPT_VPD */
1105 extern __checkReturn efx_rc_t
1107 __in efx_nic_t *enp);
1109 #if EFSYS_OPT_RX_SCATTER
1111 extern __checkReturn efx_rc_t
1112 ef10_rx_scatter_enable(
1113 __in efx_nic_t *enp,
1114 __in unsigned int buf_size);
1115 #endif /* EFSYS_OPT_RX_SCATTER */
1118 #if EFSYS_OPT_RX_SCALE
1121 extern __checkReturn efx_rc_t
1122 ef10_rx_scale_context_alloc(
1123 __in efx_nic_t *enp,
1124 __in efx_rx_scale_context_type_t type,
1125 __in uint32_t num_queues,
1126 __out uint32_t *rss_contextp);
1129 extern __checkReturn efx_rc_t
1130 ef10_rx_scale_context_free(
1131 __in efx_nic_t *enp,
1132 __in uint32_t rss_context);
1135 extern __checkReturn efx_rc_t
1136 ef10_rx_scale_mode_set(
1137 __in efx_nic_t *enp,
1138 __in uint32_t rss_context,
1139 __in efx_rx_hash_alg_t alg,
1140 __in efx_rx_hash_type_t type,
1141 __in boolean_t insert);
1144 extern __checkReturn efx_rc_t
1145 ef10_rx_scale_key_set(
1146 __in efx_nic_t *enp,
1147 __in uint32_t rss_context,
1148 __in_ecount(n) uint8_t *key,
1152 extern __checkReturn efx_rc_t
1153 ef10_rx_scale_tbl_set(
1154 __in efx_nic_t *enp,
1155 __in uint32_t rss_context,
1156 __in_ecount(n) unsigned int *table,
1160 extern __checkReturn uint32_t
1161 ef10_rx_prefix_hash(
1162 __in efx_nic_t *enp,
1163 __in efx_rx_hash_alg_t func,
1164 __in uint8_t *buffer);
1166 #endif /* EFSYS_OPT_RX_SCALE */
1169 extern __checkReturn efx_rc_t
1170 ef10_rx_prefix_pktlen(
1171 __in efx_nic_t *enp,
1172 __in uint8_t *buffer,
1173 __out uint16_t *lengthp);
1178 __in efx_rxq_t *erp,
1179 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1181 __in unsigned int ndescs,
1182 __in unsigned int completed,
1183 __in unsigned int added);
1188 __in efx_rxq_t *erp,
1189 __in unsigned int added,
1190 __inout unsigned int *pushedp);
1193 extern __checkReturn efx_rc_t
1195 __in efx_rxq_t *erp);
1200 __in efx_rxq_t *erp);
1202 union efx_rxq_type_data_u;
1205 extern __checkReturn efx_rc_t
1207 __in efx_nic_t *enp,
1208 __in unsigned int index,
1209 __in unsigned int label,
1210 __in efx_rxq_type_t type,
1211 __in_opt const union efx_rxq_type_data_u *type_data,
1212 __in efsys_mem_t *esmp,
1215 __in unsigned int flags,
1216 __in efx_evq_t *eep,
1217 __in efx_rxq_t *erp);
1222 __in efx_rxq_t *erp);
1227 __in efx_nic_t *enp);
1229 #if EFSYS_OPT_FILTER
1231 enum efx_filter_replacement_policy_e;
1233 typedef struct ef10_filter_handle_s {
1236 } ef10_filter_handle_t;
1238 typedef struct ef10_filter_entry_s {
1239 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1240 ef10_filter_handle_t efe_handle;
1241 } ef10_filter_entry_t;
1244 * BUSY flag indicates that an update is in progress.
1245 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1247 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1248 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1249 #define EFX_EF10_FILTER_FLAGS 3U
1252 * Size of the hash table used by the driver. Doesn't need to be the
1253 * same size as the hardware's table.
1255 #define EFX_EF10_FILTER_TBL_ROWS 8192
1257 /* Only need to allow for one directed and one unknown unicast filter */
1258 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1260 /* Allow for the broadcast address to be added to the multicast list */
1261 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1264 * For encapsulated packets, there is one filter each for each combination of
1265 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1266 * multicast inner frames.
1268 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1270 typedef struct ef10_filter_table_s {
1271 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1272 efx_rxq_t *eft_default_rxq;
1273 boolean_t eft_using_rss;
1274 uint32_t eft_unicst_filter_indexes[
1275 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1276 uint32_t eft_unicst_filter_count;
1277 uint32_t eft_mulcst_filter_indexes[
1278 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1279 uint32_t eft_mulcst_filter_count;
1280 boolean_t eft_using_all_mulcst;
1281 uint32_t eft_encap_filter_indexes[
1282 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1283 uint32_t eft_encap_filter_count;
1284 } ef10_filter_table_t;
1287 extern __checkReturn efx_rc_t
1289 __in efx_nic_t *enp);
1294 __in efx_nic_t *enp);
1297 extern __checkReturn efx_rc_t
1298 ef10_filter_restore(
1299 __in efx_nic_t *enp);
1302 extern __checkReturn efx_rc_t
1304 __in efx_nic_t *enp,
1305 __inout efx_filter_spec_t *spec,
1306 __in enum efx_filter_replacement_policy_e policy);
1309 extern __checkReturn efx_rc_t
1311 __in efx_nic_t *enp,
1312 __inout efx_filter_spec_t *spec);
1315 extern __checkReturn efx_rc_t
1316 ef10_filter_supported_filters(
1317 __in efx_nic_t *enp,
1318 __out_ecount(buffer_length) uint32_t *buffer,
1319 __in size_t buffer_length,
1320 __out size_t *list_lengthp);
1323 extern __checkReturn efx_rc_t
1324 ef10_filter_reconfigure(
1325 __in efx_nic_t *enp,
1326 __in_ecount(6) uint8_t const *mac_addr,
1327 __in boolean_t all_unicst,
1328 __in boolean_t mulcst,
1329 __in boolean_t all_mulcst,
1330 __in boolean_t brdcst,
1331 __in_ecount(6*count) uint8_t const *addrs,
1332 __in uint32_t count);
1336 ef10_filter_get_default_rxq(
1337 __in efx_nic_t *enp,
1338 __out efx_rxq_t **erpp,
1339 __out boolean_t *using_rss);
1343 ef10_filter_default_rxq_set(
1344 __in efx_nic_t *enp,
1345 __in efx_rxq_t *erp,
1346 __in boolean_t using_rss);
1350 ef10_filter_default_rxq_clear(
1351 __in efx_nic_t *enp);
1354 #endif /* EFSYS_OPT_FILTER */
1357 extern __checkReturn efx_rc_t
1358 efx_mcdi_get_function_info(
1359 __in efx_nic_t *enp,
1360 __out uint32_t *pfp,
1361 __out_opt uint32_t *vfp);
1364 extern __checkReturn efx_rc_t
1365 efx_mcdi_privilege_mask(
1366 __in efx_nic_t *enp,
1369 __out uint32_t *maskp);
1372 extern __checkReturn efx_rc_t
1373 efx_mcdi_get_port_assignment(
1374 __in efx_nic_t *enp,
1375 __out uint32_t *portp);
1378 extern __checkReturn efx_rc_t
1379 efx_mcdi_get_port_modes(
1380 __in efx_nic_t *enp,
1381 __out uint32_t *modesp,
1382 __out_opt uint32_t *current_modep,
1383 __out_opt uint32_t *default_modep);
1386 extern __checkReturn efx_rc_t
1387 ef10_nic_get_port_mode_bandwidth(
1388 __in efx_nic_t *enp,
1389 __out uint32_t *bandwidth_mbpsp);
1392 extern __checkReturn efx_rc_t
1393 efx_mcdi_get_mac_address_pf(
1394 __in efx_nic_t *enp,
1395 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1398 extern __checkReturn efx_rc_t
1399 efx_mcdi_get_mac_address_vf(
1400 __in efx_nic_t *enp,
1401 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1404 extern __checkReturn efx_rc_t
1406 __in efx_nic_t *enp,
1407 __out uint32_t *sys_freqp,
1408 __out uint32_t *dpcpu_freqp);
1412 extern __checkReturn efx_rc_t
1413 efx_mcdi_get_rxdp_config(
1414 __in efx_nic_t *enp,
1415 __out uint32_t *end_paddingp);
1418 extern __checkReturn efx_rc_t
1419 efx_mcdi_get_vector_cfg(
1420 __in efx_nic_t *enp,
1421 __out_opt uint32_t *vec_basep,
1422 __out_opt uint32_t *pf_nvecp,
1423 __out_opt uint32_t *vf_nvecp);
1426 extern __checkReturn efx_rc_t
1428 __in efx_nic_t *enp,
1429 __in uint32_t min_vi_count,
1430 __in uint32_t max_vi_count,
1431 __out uint32_t *vi_basep,
1432 __out uint32_t *vi_countp,
1433 __out uint32_t *vi_shiftp);
1436 extern __checkReturn efx_rc_t
1438 __in efx_nic_t *enp);
1441 extern __checkReturn efx_rc_t
1442 ef10_get_privilege_mask(
1443 __in efx_nic_t *enp,
1444 __out uint32_t *maskp);
1447 extern __checkReturn efx_rc_t
1448 efx_mcdi_nic_board_cfg(
1449 __in efx_nic_t *enp);
1452 extern __checkReturn efx_rc_t
1453 efx_mcdi_entity_reset(
1454 __in efx_nic_t *enp);
1456 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1459 extern __checkReturn efx_rc_t
1460 efx_mcdi_get_nic_global(
1461 __in efx_nic_t *enp,
1463 __out uint32_t *valuep);
1466 extern __checkReturn efx_rc_t
1467 efx_mcdi_set_nic_global(
1468 __in efx_nic_t *enp,
1470 __in uint32_t value);
1472 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1476 extern __checkReturn efx_rc_t
1478 __in efx_nic_t *enp);
1483 __in efx_nic_t *enp);
1486 extern __checkReturn efx_rc_t
1487 ef10_evb_vswitch_alloc(
1488 __in efx_nic_t *enp,
1489 __out efx_vswitch_id_t *vswitch_idp);
1493 extern __checkReturn efx_rc_t
1494 ef10_evb_vswitch_free(
1495 __in efx_nic_t *enp,
1496 __in efx_vswitch_id_t vswitch_id);
1499 extern __checkReturn efx_rc_t
1500 ef10_evb_vport_alloc(
1501 __in efx_nic_t *enp,
1502 __in efx_vswitch_id_t vswitch_id,
1503 __in efx_vport_type_t vport_type,
1505 __in boolean_t vlan_restrict,
1506 __out efx_vport_id_t *vport_idp);
1510 extern __checkReturn efx_rc_t
1511 ef10_evb_vport_free(
1512 __in efx_nic_t *enp,
1513 __in efx_vswitch_id_t vswitch_id,
1514 __in efx_vport_id_t vport_id);
1517 extern __checkReturn efx_rc_t
1518 ef10_evb_vport_mac_addr_add(
1519 __in efx_nic_t *enp,
1520 __in efx_vswitch_id_t vswitch_id,
1521 __in efx_vport_id_t vport_id,
1522 __in_ecount(6) uint8_t *addrp);
1525 extern __checkReturn efx_rc_t
1526 ef10_evb_vport_mac_addr_del(
1527 __in efx_nic_t *enp,
1528 __in efx_vswitch_id_t vswitch_id,
1529 __in efx_vport_id_t vport_id,
1530 __in_ecount(6) uint8_t *addrp);
1533 extern __checkReturn efx_rc_t
1534 ef10_evb_vadaptor_alloc(
1535 __in efx_nic_t *enp,
1536 __in efx_vswitch_id_t vswitch_id,
1537 __in efx_vport_id_t vport_id);
1541 extern __checkReturn efx_rc_t
1542 ef10_evb_vadaptor_free(
1543 __in efx_nic_t *enp,
1544 __in efx_vswitch_id_t vswitch_id,
1545 __in efx_vport_id_t vport_id);
1548 extern __checkReturn efx_rc_t
1549 ef10_evb_vport_assign(
1550 __in efx_nic_t *enp,
1551 __in efx_vswitch_id_t vswitch_id,
1552 __in efx_vport_id_t vport_id,
1553 __in uint32_t vf_index);
1556 extern __checkReturn efx_rc_t
1557 ef10_evb_vport_reconfigure(
1558 __in efx_nic_t *enp,
1559 __in efx_vswitch_id_t vswitch_id,
1560 __in efx_vport_id_t vport_id,
1561 __in_opt uint16_t *vidp,
1562 __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
1563 __out_opt boolean_t *fn_resetp);
1566 extern __checkReturn efx_rc_t
1567 ef10_evb_vport_stats(
1568 __in efx_nic_t *enp,
1569 __in efx_vswitch_id_t vswitch_id,
1570 __in efx_vport_id_t vport_id,
1571 __out efsys_mem_t *esmp);
1573 #endif /* EFSYS_OPT_EVB */
1575 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
1577 extern __checkReturn efx_rc_t
1578 ef10_proxy_auth_init(
1579 __in efx_nic_t *enp);
1583 ef10_proxy_auth_fini(
1584 __in efx_nic_t *enp);
1587 extern __checkReturn efx_rc_t
1588 ef10_proxy_auth_mc_config(
1589 __in efx_nic_t *enp,
1590 __in efsys_mem_t *request_bufferp,
1591 __in efsys_mem_t *response_bufferp,
1592 __in efsys_mem_t *status_bufferp,
1593 __in uint32_t block_cnt,
1594 __in_ecount(op_count) uint32_t *op_listp,
1595 __in size_t op_count);
1598 extern __checkReturn efx_rc_t
1599 ef10_proxy_auth_disable(
1600 __in efx_nic_t *enp);
1603 extern __checkReturn efx_rc_t
1604 ef10_proxy_auth_privilege_modify(
1605 __in efx_nic_t *enp,
1606 __in uint32_t fn_group,
1607 __in uint32_t pf_index,
1608 __in uint32_t vf_index,
1609 __in uint32_t add_privileges_mask,
1610 __in uint32_t remove_privileges_mask);
1613 extern __checkReturn efx_rc_t
1614 ef10_proxy_auth_set_privilege_mask(
1615 __in efx_nic_t *enp,
1616 __in uint32_t vf_index,
1618 __in uint32_t value);
1621 extern __checkReturn efx_rc_t
1622 ef10_proxy_auth_complete_request(
1623 __in efx_nic_t *enp,
1624 __in uint32_t fn_index,
1625 __in uint32_t proxy_result,
1626 __in uint32_t handle);
1629 extern __checkReturn efx_rc_t
1630 ef10_proxy_auth_exec_cmd(
1631 __in efx_nic_t *enp,
1632 __inout efx_proxy_cmd_params_t *paramsp);
1635 extern __checkReturn efx_rc_t
1636 ef10_proxy_auth_get_privilege_mask(
1637 __in efx_nic_t *enp,
1638 __in uint32_t pf_index,
1639 __in uint32_t vf_index,
1640 __out uint32_t *maskp);
1642 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
1644 #if EFSYS_OPT_RX_PACKED_STREAM
1646 /* Data space per credit in packed stream mode */
1647 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1650 * Received packets are always aligned at this boundary. Also there always
1651 * exists a gap of this size between packets.
1652 * (see SF-112241-TC, 4.5)
1654 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1657 * Size of a pseudo-header prepended to received packets
1658 * in packed stream mode
1660 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1662 /* Minimum space for packet in packed stream mode */
1663 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1664 EFX_P2ROUNDUP(size_t, \
1665 EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1667 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1668 EFX_RX_PACKED_STREAM_ALIGNMENT)
1670 /* Maximum number of credits */
1671 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1673 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1675 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1678 * Maximum DMA length and buffer stride alignment.
1679 * (see SF-119419-TC, 3.2)
1681 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1689 #endif /* _SYS_EF10_IMPL_H */