1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
11 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
16 #error "WITH_MCDI_V2 required for EF10 MCDIv2 commands."
20 __checkReturn efx_rc_t
23 __in const efx_mcdi_transport_t *emtp)
25 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
26 efsys_mem_t *esmp = emtp->emt_dma_mem;
30 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
31 EFSYS_ASSERT(enp->en_features & EFX_FEATURE_MCDI_DMA);
34 * All EF10 firmware supports MCDIv2 and MCDIv1.
35 * Medford BootROM supports MCDIv2 and MCDIv1.
36 * Huntington BootROM supports MCDIv1 only.
38 emip->emi_max_version = 2;
40 /* A host DMA buffer is required for EF10 MCDI */
47 * Ensure that the MC doorbell is in a known state before issuing MCDI
48 * commands. The recovery algorithm requires that the MC command buffer
49 * must be 256 byte aligned. See bug24769.
51 if ((EFSYS_MEM_ADDR(esmp) & 0xFF) != 0) {
55 EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, 1);
56 switch (enp->en_family) {
57 #if EFSYS_OPT_RIVERHEAD
58 case EFX_FAMILY_RIVERHEAD:
59 EFX_BAR_FCW_WRITED(enp, ER_GZ_MC_DB_HWRD_REG, &dword);
61 #endif /* EFSYS_OPT_RIVERHEAD */
63 EFX_BAR_WRITED(enp, ER_DZ_MC_DB_HWRD_REG, &dword, B_FALSE);
67 /* Save initial MC reboot status */
68 (void) ef10_mcdi_poll_reboot(enp);
70 /* Start a new epoch (allow fresh MCDI requests to succeed) */
71 efx_mcdi_new_epoch(enp);
78 EFSYS_PROBE1(fail1, efx_rc_t, rc);
87 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
89 emip->emi_new_epoch = B_FALSE;
93 * In older firmware all commands are processed in a single thread, so a long
94 * running command for one PCIe function can block processing for another
95 * function (see bug 61269).
97 * In newer firmware that supports multithreaded MCDI processing, we can extend
98 * the timeout for long-running requests which we know firmware may choose to
99 * process in a background thread.
101 #define EF10_MCDI_CMD_TIMEOUT_US (10 * 1000 * 1000)
102 #define EF10_MCDI_CMD_LONG_TIMEOUT_US (60 * 1000 * 1000)
105 ef10_mcdi_get_timeout(
107 __in efx_mcdi_req_t *emrp,
108 __out uint32_t *timeoutp)
110 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
112 switch (emrp->emr_cmd) {
113 case MC_CMD_POLL_BIST:
114 case MC_CMD_NVRAM_ERASE:
115 case MC_CMD_LICENSING_V3:
116 case MC_CMD_NVRAM_UPDATE_FINISH:
117 if (encp->enc_nvram_update_verify_result_supported != B_FALSE) {
119 * Potentially longer running commands, which firmware
120 * may choose to process in a background thread.
122 *timeoutp = EF10_MCDI_CMD_LONG_TIMEOUT_US;
127 *timeoutp = EF10_MCDI_CMD_TIMEOUT_US;
133 ef10_mcdi_send_request(
135 __in_bcount(hdr_len) void *hdrp,
137 __in_bcount(sdu_len) void *sdup,
140 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
141 efsys_mem_t *esmp = emtp->emt_dma_mem;
145 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
147 /* Write the header */
148 for (pos = 0; pos < hdr_len; pos += sizeof (efx_dword_t)) {
149 dword = *(efx_dword_t *)((uint8_t *)hdrp + pos);
150 EFSYS_MEM_WRITED(esmp, pos, &dword);
153 /* Write the payload */
154 for (pos = 0; pos < sdu_len; pos += sizeof (efx_dword_t)) {
155 dword = *(efx_dword_t *)((uint8_t *)sdup + pos);
156 EFSYS_MEM_WRITED(esmp, hdr_len + pos, &dword);
159 /* Guarantee ordering of memory (MCDI request) and PIO (MC doorbell) */
160 EFSYS_DMA_SYNC_FOR_DEVICE(esmp, 0, hdr_len + sdu_len);
161 EFSYS_PIO_WRITE_BARRIER();
163 /* Ring the doorbell to post the command DMA address to the MC */
164 EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0,
165 EFSYS_MEM_ADDR(esmp) >> 32);
166 switch (enp->en_family) {
167 #if EFSYS_OPT_RIVERHEAD
168 case EFX_FAMILY_RIVERHEAD:
169 EFX_BAR_FCW_WRITED(enp, ER_GZ_MC_DB_LWRD_REG, &dword);
171 #endif /* EFSYS_OPT_RIVERHEAD */
173 EFX_BAR_WRITED(enp, ER_DZ_MC_DB_LWRD_REG, &dword, B_FALSE);
177 EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0,
178 EFSYS_MEM_ADDR(esmp) & 0xffffffff);
179 switch (enp->en_family) {
180 #if EFSYS_OPT_RIVERHEAD
181 case EFX_FAMILY_RIVERHEAD:
182 EFX_BAR_FCW_WRITED(enp, ER_GZ_MC_DB_HWRD_REG, &dword);
184 #endif /* EFSYS_OPT_RIVERHEAD */
186 EFX_BAR_WRITED(enp, ER_DZ_MC_DB_HWRD_REG, &dword, B_FALSE);
191 __checkReturn boolean_t
192 ef10_mcdi_poll_response(
195 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
196 efsys_mem_t *esmp = emtp->emt_dma_mem;
199 EFSYS_MEM_READD(esmp, 0, &hdr);
200 EFSYS_MEM_READ_BARRIER();
202 return (EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE) ? B_TRUE : B_FALSE);
206 ef10_mcdi_read_response(
208 __out_bcount(length) void *bufferp,
212 const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
213 efsys_mem_t *esmp = emtp->emt_dma_mem;
214 unsigned int pos = 0;
216 size_t remaining = length;
218 while (remaining > 0) {
219 size_t chunk = MIN(remaining, sizeof (data));
221 EFSYS_MEM_READD(esmp, offset + pos, &data);
222 memcpy((uint8_t *)bufferp + pos, &data, chunk);
229 ef10_mcdi_poll_reboot(
232 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
238 old_status = emip->emi_mc_reboot_status;
240 /* Update MC reboot status word */
241 switch (enp->en_family) {
242 #if EFSYS_OPT_RIVERHEAD
243 case EFX_FAMILY_RIVERHEAD:
244 EFX_BAR_FCW_READD(enp, ER_GZ_MC_SFT_STATUS, &dword);
246 #endif /* EFSYS_OPT_RIVERHEAD */
248 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG,
252 new_status = dword.ed_u32[0];
254 /* MC has rebooted if the value has changed */
255 if (new_status != old_status) {
256 emip->emi_mc_reboot_status = new_status;
259 * FIXME: Ignore detected MC REBOOT for now.
261 * The Siena support for checking for MC reboot from status
262 * flags is broken - see comments in siena_mcdi_poll_reboot().
263 * As the generic MCDI code is shared the EF10 reboot
264 * detection suffers similar problems.
266 * Do not report an error when the boot status changes until
267 * this can be handled by common code drivers (and reworked to
268 * support Siena too).
270 _NOTE(CONSTANTCONDITION)
280 EFSYS_PROBE1(fail1, efx_rc_t, rc);
285 __checkReturn efx_rc_t
286 ef10_mcdi_feature_supported(
288 __in efx_mcdi_feature_id_t id,
289 __out boolean_t *supportedp)
291 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
292 uint32_t privilege_mask = encp->enc_privilege_mask;
295 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
298 * Use privilege mask state at MCDI attach.
302 case EFX_MCDI_FEATURE_FW_UPDATE:
304 * Admin privilege must be used prior to introduction of
308 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, ADMIN);
310 case EFX_MCDI_FEATURE_LINK_CONTROL:
312 * Admin privilege used prior to introduction of
316 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, LINK) ||
317 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, ADMIN);
319 case EFX_MCDI_FEATURE_MACADDR_CHANGE:
321 * Admin privilege must be used prior to introduction of
322 * mac spoofing privilege (at v4.6), which is used up to
323 * introduction of change mac spoofing privilege (at v4.7)
326 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, CHANGE_MAC) ||
327 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, MAC_SPOOFING) ||
328 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, ADMIN);
330 case EFX_MCDI_FEATURE_MAC_SPOOFING:
332 * Admin privilege must be used prior to introduction of
333 * mac spoofing privilege (at v4.6), which is used up to
334 * introduction of mac spoofing TX privilege (at v4.7)
337 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, MAC_SPOOFING_TX) ||
338 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, MAC_SPOOFING) ||
339 EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, ADMIN);
349 EFSYS_PROBE1(fail1, efx_rc_t, rc);
354 #endif /* EFSYS_OPT_MCDI */
356 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */