1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
13 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
27 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
29 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
30 req.emr_in_buf = payload;
31 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
32 req.emr_out_buf = payload;
33 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
35 efx_mcdi_execute(enp, &req);
37 if (req.emr_rc != 0) {
42 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
47 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
54 EFSYS_PROBE1(fail1, efx_rc_t, rc);
59 __checkReturn efx_rc_t
60 efx_mcdi_get_port_modes(
62 __out uint32_t *modesp,
63 __out_opt uint32_t *current_modep,
64 __out_opt uint32_t *default_modep)
67 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
68 MC_CMD_GET_PORT_MODES_OUT_LEN);
71 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
73 req.emr_cmd = MC_CMD_GET_PORT_MODES;
74 req.emr_in_buf = payload;
75 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
76 req.emr_out_buf = payload;
77 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
79 efx_mcdi_execute(enp, &req);
81 if (req.emr_rc != 0) {
87 * Require only Modes and DefaultMode fields, unless the current mode
88 * was requested (CurrentMode field was added for Medford).
90 if (req.emr_out_length_used <
91 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
95 if ((current_modep != NULL) && (req.emr_out_length_used <
96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
101 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
103 if (current_modep != NULL) {
104 *current_modep = MCDI_OUT_DWORD(req,
105 GET_PORT_MODES_OUT_CURRENT_MODE);
108 if (default_modep != NULL) {
109 *default_modep = MCDI_OUT_DWORD(req,
110 GET_PORT_MODES_OUT_DEFAULT_MODE);
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
125 __checkReturn efx_rc_t
126 ef10_nic_get_port_mode_bandwidth(
128 __out uint32_t *bandwidth_mbpsp)
131 uint32_t current_mode;
132 efx_port_t *epp = &(enp->en_port);
134 uint32_t single_lane;
140 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
141 ¤t_mode, NULL)) != 0) {
142 /* No port mode info available. */
146 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX))
151 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX))
156 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX))
161 switch (current_mode) {
162 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
163 bandwidth = single_lane;
165 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
166 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
167 bandwidth = dual_lane;
169 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
170 bandwidth = single_lane + single_lane;
172 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
173 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
174 bandwidth = 4 * single_lane;
176 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
177 bandwidth = (2 * single_lane) + (2 * single_lane);
179 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
180 bandwidth = dual_lane + dual_lane;
182 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
183 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
184 bandwidth = dual_lane + (2 * single_lane);
186 /* Legacy Medford-only mode. Do not use (see bug63270) */
187 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
188 bandwidth = 4 * single_lane;
190 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
191 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
192 bandwidth = quad_lane;
194 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
195 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
196 bandwidth = 2 * dual_lane;
198 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
199 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
200 bandwidth = quad_lane + (2 * single_lane);
202 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
203 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
204 bandwidth = quad_lane + dual_lane;
206 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
207 bandwidth = quad_lane + quad_lane;
214 *bandwidth_mbpsp = bandwidth;
221 EFSYS_PROBE1(fail1, efx_rc_t, rc);
226 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
230 __checkReturn efx_rc_t
231 efx_mcdi_vadaptor_alloc(
233 __in uint32_t port_id)
236 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
237 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
240 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
241 req.emr_in_buf = payload;
242 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
243 req.emr_out_buf = payload;
244 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
246 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
247 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
248 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
249 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
251 efx_mcdi_execute(enp, &req);
253 if (req.emr_rc != 0) {
261 EFSYS_PROBE1(fail1, efx_rc_t, rc);
266 __checkReturn efx_rc_t
267 efx_mcdi_vadaptor_free(
269 __in uint32_t port_id)
272 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
273 MC_CMD_VADAPTOR_FREE_OUT_LEN);
276 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
277 req.emr_in_buf = payload;
278 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
279 req.emr_out_buf = payload;
280 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
282 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
284 efx_mcdi_execute(enp, &req);
286 if (req.emr_rc != 0) {
294 EFSYS_PROBE1(fail1, efx_rc_t, rc);
299 #endif /* EFX_OPTS_EF10() */
301 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
303 __checkReturn efx_rc_t
304 efx_mcdi_get_mac_address_pf(
306 __out_ecount_opt(6) uint8_t mac_addrp[6])
309 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
310 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
313 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
315 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
316 req.emr_in_buf = payload;
317 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
318 req.emr_out_buf = payload;
319 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
321 efx_mcdi_execute(enp, &req);
323 if (req.emr_rc != 0) {
328 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
333 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
338 if (mac_addrp != NULL) {
341 addrp = MCDI_OUT2(req, uint8_t,
342 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
344 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
354 EFSYS_PROBE1(fail1, efx_rc_t, rc);
359 __checkReturn efx_rc_t
360 efx_mcdi_get_mac_address_vf(
362 __out_ecount_opt(6) uint8_t mac_addrp[6])
365 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
366 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
369 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
371 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
372 req.emr_in_buf = payload;
373 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
374 req.emr_out_buf = payload;
375 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
377 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
378 EVB_PORT_ID_ASSIGNED);
380 efx_mcdi_execute(enp, &req);
382 if (req.emr_rc != 0) {
387 if (req.emr_out_length_used <
388 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
393 if (MCDI_OUT_DWORD(req,
394 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
399 if (mac_addrp != NULL) {
402 addrp = MCDI_OUT2(req, uint8_t,
403 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
405 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
415 EFSYS_PROBE1(fail1, efx_rc_t, rc);
420 __checkReturn efx_rc_t
423 __out uint32_t *sys_freqp,
424 __out uint32_t *dpcpu_freqp)
427 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
428 MC_CMD_GET_CLOCK_OUT_LEN);
431 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
433 req.emr_cmd = MC_CMD_GET_CLOCK;
434 req.emr_in_buf = payload;
435 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
436 req.emr_out_buf = payload;
437 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
439 efx_mcdi_execute(enp, &req);
441 if (req.emr_rc != 0) {
446 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
451 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
452 if (*sys_freqp == 0) {
456 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
457 if (*dpcpu_freqp == 0) {
471 EFSYS_PROBE1(fail1, efx_rc_t, rc);
476 __checkReturn efx_rc_t
477 efx_mcdi_get_rxdp_config(
479 __out uint32_t *end_paddingp)
482 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
483 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
484 uint32_t end_padding;
487 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
488 req.emr_in_buf = payload;
489 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
490 req.emr_out_buf = payload;
491 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
493 efx_mcdi_execute(enp, &req);
495 if (req.emr_rc != 0) {
500 if (req.emr_out_length_used < MC_CMD_GET_RXDP_CONFIG_OUT_LEN) {
505 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
506 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
507 /* RX DMA end padding is disabled */
510 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
511 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
512 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
515 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
518 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
527 *end_paddingp = end_padding;
536 EFSYS_PROBE1(fail1, efx_rc_t, rc);
541 __checkReturn efx_rc_t
542 efx_mcdi_get_vector_cfg(
544 __out_opt uint32_t *vec_basep,
545 __out_opt uint32_t *pf_nvecp,
546 __out_opt uint32_t *vf_nvecp)
549 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
550 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
553 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
554 req.emr_in_buf = payload;
555 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
556 req.emr_out_buf = payload;
557 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
559 efx_mcdi_execute(enp, &req);
561 if (req.emr_rc != 0) {
566 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
571 if (vec_basep != NULL)
572 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
573 if (pf_nvecp != NULL)
574 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
575 if (vf_nvecp != NULL)
576 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
583 EFSYS_PROBE1(fail1, efx_rc_t, rc);
588 __checkReturn efx_rc_t
591 __in uint32_t min_vi_count,
592 __in uint32_t max_vi_count,
593 __out uint32_t *vi_basep,
594 __out uint32_t *vi_countp,
595 __out uint32_t *vi_shiftp)
598 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
599 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
602 if (vi_countp == NULL) {
607 req.emr_cmd = MC_CMD_ALLOC_VIS;
608 req.emr_in_buf = payload;
609 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
610 req.emr_out_buf = payload;
611 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
613 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
614 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
616 efx_mcdi_execute(enp, &req);
618 if (req.emr_rc != 0) {
623 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
628 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
629 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
631 /* Report VI_SHIFT if available (always zero for Huntington) */
632 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
635 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
644 EFSYS_PROBE1(fail1, efx_rc_t, rc);
650 __checkReturn efx_rc_t
657 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
658 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
660 req.emr_cmd = MC_CMD_FREE_VIS;
661 req.emr_in_buf = NULL;
662 req.emr_in_length = 0;
663 req.emr_out_buf = NULL;
664 req.emr_out_length = 0;
666 efx_mcdi_execute_quiet(enp, &req);
668 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
669 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
677 EFSYS_PROBE1(fail1, efx_rc_t, rc);
682 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
686 static __checkReturn efx_rc_t
687 efx_mcdi_alloc_piobuf(
689 __out efx_piobuf_handle_t *handlep)
692 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
693 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
696 if (handlep == NULL) {
701 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
702 req.emr_in_buf = payload;
703 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
704 req.emr_out_buf = payload;
705 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
707 efx_mcdi_execute_quiet(enp, &req);
709 if (req.emr_rc != 0) {
714 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
719 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
728 EFSYS_PROBE1(fail1, efx_rc_t, rc);
733 static __checkReturn efx_rc_t
734 efx_mcdi_free_piobuf(
736 __in efx_piobuf_handle_t handle)
739 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
740 MC_CMD_FREE_PIOBUF_OUT_LEN);
743 req.emr_cmd = MC_CMD_FREE_PIOBUF;
744 req.emr_in_buf = payload;
745 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
746 req.emr_out_buf = payload;
747 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
749 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
751 efx_mcdi_execute_quiet(enp, &req);
753 if (req.emr_rc != 0) {
761 EFSYS_PROBE1(fail1, efx_rc_t, rc);
766 static __checkReturn efx_rc_t
767 efx_mcdi_link_piobuf(
769 __in uint32_t vi_index,
770 __in efx_piobuf_handle_t handle)
773 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
774 MC_CMD_LINK_PIOBUF_OUT_LEN);
777 req.emr_cmd = MC_CMD_LINK_PIOBUF;
778 req.emr_in_buf = payload;
779 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
780 req.emr_out_buf = payload;
781 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
783 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
784 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
786 efx_mcdi_execute(enp, &req);
788 if (req.emr_rc != 0) {
796 EFSYS_PROBE1(fail1, efx_rc_t, rc);
801 static __checkReturn efx_rc_t
802 efx_mcdi_unlink_piobuf(
804 __in uint32_t vi_index)
807 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
808 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
811 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
812 req.emr_in_buf = payload;
813 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
814 req.emr_out_buf = payload;
815 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
817 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
819 efx_mcdi_execute_quiet(enp, &req);
821 if (req.emr_rc != 0) {
829 EFSYS_PROBE1(fail1, efx_rc_t, rc);
835 ef10_nic_alloc_piobufs(
837 __in uint32_t max_piobuf_count)
839 efx_piobuf_handle_t *handlep;
842 EFSYS_ASSERT3U(max_piobuf_count, <=,
843 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
845 enp->en_arch.ef10.ena_piobuf_count = 0;
847 for (i = 0; i < max_piobuf_count; i++) {
848 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
850 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
853 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
854 enp->en_arch.ef10.ena_piobuf_count++;
860 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
861 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
863 (void) efx_mcdi_free_piobuf(enp, *handlep);
864 *handlep = EFX_PIOBUF_HANDLE_INVALID;
866 enp->en_arch.ef10.ena_piobuf_count = 0;
871 ef10_nic_free_piobufs(
874 efx_piobuf_handle_t *handlep;
877 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
878 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
880 (void) efx_mcdi_free_piobuf(enp, *handlep);
881 *handlep = EFX_PIOBUF_HANDLE_INVALID;
883 enp->en_arch.ef10.ena_piobuf_count = 0;
886 /* Sub-allocate a block from a piobuf */
887 __checkReturn efx_rc_t
889 __inout efx_nic_t *enp,
890 __out uint32_t *bufnump,
891 __out efx_piobuf_handle_t *handlep,
892 __out uint32_t *blknump,
893 __out uint32_t *offsetp,
896 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
897 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
898 uint32_t blk_per_buf;
902 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
903 EFSYS_ASSERT(bufnump);
904 EFSYS_ASSERT(handlep);
905 EFSYS_ASSERT(blknump);
906 EFSYS_ASSERT(offsetp);
909 if ((edcp->edc_pio_alloc_size == 0) ||
910 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
914 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
916 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
917 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
922 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
923 for (blk = 0; blk < blk_per_buf; blk++) {
924 if ((*map & (1u << blk)) == 0) {
934 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
937 *sizep = edcp->edc_pio_alloc_size;
938 *offsetp = blk * (*sizep);
945 EFSYS_PROBE1(fail1, efx_rc_t, rc);
950 /* Free a piobuf sub-allocated block */
951 __checkReturn efx_rc_t
953 __inout efx_nic_t *enp,
954 __in uint32_t bufnum,
955 __in uint32_t blknum)
960 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
961 (blknum >= (8 * sizeof (*map)))) {
966 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
967 if ((*map & (1u << blknum)) == 0) {
971 *map &= ~(1u << blknum);
978 EFSYS_PROBE1(fail1, efx_rc_t, rc);
983 __checkReturn efx_rc_t
985 __inout efx_nic_t *enp,
986 __in uint32_t vi_index,
987 __in efx_piobuf_handle_t handle)
989 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
992 __checkReturn efx_rc_t
994 __inout efx_nic_t *enp,
995 __in uint32_t vi_index)
997 return (efx_mcdi_unlink_piobuf(enp, vi_index));
1000 #endif /* EFX_OPTS_EF10() */
1002 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1004 static __checkReturn efx_rc_t
1005 ef10_mcdi_get_pf_count(
1006 __in efx_nic_t *enp,
1007 __out uint32_t *pf_countp)
1010 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
1011 MC_CMD_GET_PF_COUNT_OUT_LEN);
1014 req.emr_cmd = MC_CMD_GET_PF_COUNT;
1015 req.emr_in_buf = payload;
1016 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
1017 req.emr_out_buf = payload;
1018 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
1020 efx_mcdi_execute(enp, &req);
1022 if (req.emr_rc != 0) {
1027 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1032 *pf_countp = *MCDI_OUT(req, uint8_t,
1033 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1035 EFSYS_ASSERT(*pf_countp != 0);
1042 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1047 static __checkReturn efx_rc_t
1048 ef10_get_datapath_caps(
1049 __in efx_nic_t *enp)
1051 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1053 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1054 MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
1057 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1058 req.emr_in_buf = payload;
1059 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1060 req.emr_out_buf = payload;
1061 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V7_OUT_LEN;
1063 efx_mcdi_execute_quiet(enp, &req);
1065 if (req.emr_rc != 0) {
1070 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1075 #define CAP_FLAGS1(_req, _flag) \
1076 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1077 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1079 #define CAP_FLAGS2(_req, _flag) \
1080 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1081 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1082 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1084 #define CAP_FLAGS3(_req, _flag) \
1085 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) && \
1086 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V7_OUT_FLAGS3) & \
1087 (1u << (MC_CMD_GET_CAPABILITIES_V7_OUT_ ## _flag ## _LBN))))
1089 /* Check if RXDP firmware inserts 14 byte prefix */
1090 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14))
1091 encp->enc_rx_prefix_size = 14;
1093 encp->enc_rx_prefix_size = 0;
1095 #if EFSYS_OPT_RX_SCALE
1096 /* Check if the firmware supports additional RSS modes */
1097 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1098 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1100 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1101 #endif /* EFSYS_OPT_RX_SCALE */
1103 /* Check if the firmware supports TSO */
1104 if (CAP_FLAGS1(req, TX_TSO))
1105 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1107 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1109 /* Check if the firmware supports FATSOv2 */
1110 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1111 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1112 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1113 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1115 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1116 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1119 /* Check if the firmware supports FATSOv2 encap */
1120 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1121 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1123 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1125 /* Check if TSOv3 is supported */
1126 if (CAP_FLAGS2(req, TX_TSO_V3))
1127 encp->enc_tso_v3_enabled = B_TRUE;
1129 encp->enc_tso_v3_enabled = B_FALSE;
1131 /* Check if the firmware has vadapter/vport/vswitch support */
1132 if (CAP_FLAGS1(req, EVB))
1133 encp->enc_datapath_cap_evb = B_TRUE;
1135 encp->enc_datapath_cap_evb = B_FALSE;
1137 /* Check if the firmware supports vport reconfiguration */
1138 if (CAP_FLAGS1(req, VPORT_RECONFIGURE))
1139 encp->enc_vport_reconfigure_supported = B_TRUE;
1141 encp->enc_vport_reconfigure_supported = B_FALSE;
1143 /* Check if the firmware supports VLAN insertion */
1144 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1145 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1147 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1149 /* Check if the firmware supports RX event batching */
1150 if (CAP_FLAGS1(req, RX_BATCHING))
1151 encp->enc_rx_batching_enabled = B_TRUE;
1153 encp->enc_rx_batching_enabled = B_FALSE;
1156 * Even if batching isn't reported as supported, we may still get
1157 * batched events (see bug61153).
1159 encp->enc_rx_batch_max = 16;
1161 /* Check if the firmware supports disabling scatter on RXQs */
1162 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1163 encp->enc_rx_disable_scatter_supported = B_TRUE;
1165 encp->enc_rx_disable_scatter_supported = B_FALSE;
1167 /* No limit on maximum number of Rx scatter elements per packet. */
1168 encp->enc_rx_scatter_max = -1;
1170 /* Check if the firmware supports packed stream mode */
1171 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1172 encp->enc_rx_packed_stream_supported = B_TRUE;
1174 encp->enc_rx_packed_stream_supported = B_FALSE;
1177 * Check if the firmware supports configurable buffer sizes
1178 * for packed stream mode (otherwise buffer size is 1Mbyte)
1180 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1181 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1183 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1185 /* Check if the firmware supports equal stride super-buffer mode */
1186 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1187 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1189 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1191 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1192 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1193 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1195 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1197 /* Check if the firmware supports set mac with running filters */
1198 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1199 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1201 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1204 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1205 * specifying which parameters to configure.
1207 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1208 encp->enc_enhanced_set_mac_supported = B_TRUE;
1210 encp->enc_enhanced_set_mac_supported = B_FALSE;
1213 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1214 * us to let the firmware choose the settings to use on an EVQ.
1216 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1217 encp->enc_init_evq_v2_supported = B_TRUE;
1219 encp->enc_init_evq_v2_supported = B_FALSE;
1222 * Check if firmware supports extended width event queues, which have
1223 * a different event descriptor layout.
1225 if (CAP_FLAGS3(req, EXTENDED_WIDTH_EVQS_SUPPORTED))
1226 encp->enc_init_evq_extended_width_supported = B_TRUE;
1228 encp->enc_init_evq_extended_width_supported = B_FALSE;
1231 * Check if the NO_CONT_EV mode for RX events is supported.
1233 if (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV))
1234 encp->enc_no_cont_ev_mode_supported = B_TRUE;
1236 encp->enc_no_cont_ev_mode_supported = B_FALSE;
1239 * Check if buffer size may and must be specified on INIT_RXQ.
1240 * It may be always specified to efx_rx_qcreate(), but will be
1241 * just kept libefx internal if MCDI does not support it.
1243 if (CAP_FLAGS2(req, INIT_RXQ_WITH_BUFFER_SIZE))
1244 encp->enc_init_rxq_with_buffer_size = B_TRUE;
1246 encp->enc_init_rxq_with_buffer_size = B_FALSE;
1249 * Check if firmware-verified NVRAM updates must be used.
1251 * The firmware trusted installer requires all NVRAM updates to use
1252 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1253 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1254 * partition and report the result).
1256 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1257 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1259 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1261 if (CAP_FLAGS2(req, NVRAM_UPDATE_POLL_VERIFY_RESULT))
1262 encp->enc_nvram_update_poll_verify_result_supported = B_TRUE;
1264 encp->enc_nvram_update_poll_verify_result_supported = B_FALSE;
1267 * Check if firmware update via the BUNDLE partition is supported
1269 if (CAP_FLAGS2(req, BUNDLE_UPDATE))
1270 encp->enc_nvram_bundle_update_supported = B_TRUE;
1272 encp->enc_nvram_bundle_update_supported = B_FALSE;
1275 * Check if firmware provides packet memory and Rx datapath
1278 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1279 encp->enc_pm_and_rxdp_counters = B_TRUE;
1281 encp->enc_pm_and_rxdp_counters = B_FALSE;
1284 * Check if the 40G MAC hardware is capable of reporting
1285 * statistics for Tx size bins.
1287 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1288 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1290 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1293 * Check if firmware supports VXLAN and NVGRE tunnels.
1294 * The capability indicates Geneve protocol support as well.
1296 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1297 encp->enc_tunnel_encapsulations_supported =
1298 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1299 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1300 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1302 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1303 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1304 encp->enc_tunnel_config_udp_entries_max =
1305 EFX_TUNNEL_MAXNENTRIES;
1307 encp->enc_tunnel_config_udp_entries_max = 0;
1311 * Check if firmware reports the VI window mode.
1312 * Medford2 has a variable VI window size (8K, 16K or 64K).
1313 * Medford and Huntington have a fixed 8K VI window size.
1315 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1317 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1320 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1321 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1323 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1324 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1326 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1327 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1330 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1333 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1334 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1335 /* Huntington and Medford have fixed 8K window size */
1336 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1338 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1341 /* Check if firmware supports extended MAC stats. */
1342 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1343 /* Extended stats buffer supported */
1344 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1345 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1347 /* Use Siena-compatible legacy MAC stats */
1348 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1351 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1352 encp->enc_fec_counters = B_TRUE;
1354 encp->enc_fec_counters = B_FALSE;
1356 /* Check if the firmware provides head-of-line blocking counters */
1357 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1358 encp->enc_hlb_counters = B_TRUE;
1360 encp->enc_hlb_counters = B_FALSE;
1362 #if EFSYS_OPT_RX_SCALE
1363 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1364 /* Only one exclusive RSS context is available per port. */
1365 encp->enc_rx_scale_max_exclusive_contexts = 1;
1367 switch (enp->en_family) {
1368 case EFX_FAMILY_MEDFORD2:
1369 encp->enc_rx_scale_hash_alg_mask =
1370 (1U << EFX_RX_HASHALG_TOEPLITZ);
1373 case EFX_FAMILY_MEDFORD:
1374 case EFX_FAMILY_HUNTINGTON:
1376 * Packed stream firmware variant maintains a
1377 * non-standard algorithm for hash computation.
1378 * It implies explicit XORing together
1379 * source + destination IP addresses (or last
1380 * four bytes in the case of IPv6) and using the
1381 * resulting value as the input to a Toeplitz hash.
1383 encp->enc_rx_scale_hash_alg_mask =
1384 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1392 /* Port numbers cannot contribute to the hash value */
1393 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1396 * Maximum number of exclusive RSS contexts.
1397 * EF10 hardware supports 64 in total, but 6 are reserved
1398 * for shared contexts. They are a global resource so
1399 * not all may be available.
1401 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1403 encp->enc_rx_scale_hash_alg_mask =
1404 (1U << EFX_RX_HASHALG_TOEPLITZ);
1407 * It is possible to use port numbers as
1408 * the input data for hash computation.
1410 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1412 #endif /* EFSYS_OPT_RX_SCALE */
1414 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1415 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1416 encp->enc_filter_action_flag_supported = B_TRUE;
1418 encp->enc_filter_action_flag_supported = B_FALSE;
1420 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1421 encp->enc_filter_action_mark_supported = B_TRUE;
1423 encp->enc_filter_action_mark_supported = B_FALSE;
1425 /* Get maximum supported value for "MARK" filter action */
1426 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1427 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1428 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1430 encp->enc_filter_action_mark_max = 0;
1434 * Check support for EF100 Match Action Engine (MAE).
1435 * MAE hardware is present on Riverhead boards (from R2),
1436 * and on Keystone, and requires support in firmware.
1438 * MAE control operations require MAE control privilege,
1439 * which is not available for VFs.
1441 * Privileges can change dynamically at runtime: we assume
1442 * MAE support requires the privilege is granted initially,
1443 * and ignore later dynamic changes.
1445 if (CAP_FLAGS3(req, MAE_SUPPORTED) &&
1446 EFX_MCDI_HAVE_PRIVILEGE(encp->enc_privilege_mask, MAE))
1447 encp->enc_mae_supported = B_TRUE;
1449 encp->enc_mae_supported = B_FALSE;
1451 encp->enc_mae_supported = B_FALSE;
1452 #endif /* EFSYS_OPT_MAE */
1460 #if EFSYS_OPT_RX_SCALE
1463 #endif /* EFSYS_OPT_RX_SCALE */
1467 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1473 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1474 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1475 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1476 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1477 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1478 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1479 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1480 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1481 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1482 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1483 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1484 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1486 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1489 __checkReturn efx_rc_t
1490 ef10_get_privilege_mask(
1491 __in efx_nic_t *enp,
1492 __out uint32_t *maskp)
1494 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1498 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1503 /* Fallback for old firmware without privilege mask support */
1504 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1505 /* Assume PF has admin privilege */
1506 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1508 /* VF is always unprivileged by default */
1509 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1518 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1524 #define EFX_EXT_PORT_MAX 4
1525 #define EFX_EXT_PORT_NA 0xFF
1528 * Table of mapping schemes from port number to external number.
1530 * Each port number ultimately corresponds to a connector: either as part of
1531 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1532 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1533 * "Salina"). In general:
1535 * Port number (0-based)
1537 * port mapping (n:1)
1540 * External port number (1-based)
1542 * fixed (1:1) or cable assembly (1:m)
1547 * The external numbering refers to the cages or magjacks on the board,
1548 * as visibly annotated on the board or back panel. This table describes
1549 * how to determine which external cage/magjack corresponds to the port
1550 * numbers used by the driver.
1552 * The count of consecutive port numbers that map to each external number,
1553 * is determined by the chip family and the current port mode.
1555 * For the Huntington family, the current port mode cannot be discovered,
1556 * but a single mapping is used by all modes for a given chip variant,
1557 * so the mapping used is instead the last match in the table to the full
1558 * set of port modes to which the NIC can be configured. Therefore the
1559 * ordering of entries in the mapping table is significant.
1561 static struct ef10_external_port_map_s {
1562 efx_family_t family;
1563 uint32_t modes_mask;
1564 uint8_t base_port[EFX_EXT_PORT_MAX];
1565 } __ef10_external_port_mappings[] = {
1567 * Modes used by Huntington family controllers where each port
1568 * number maps to a separate cage.
1569 * SFN7x22F (Torino):
1579 EFX_FAMILY_HUNTINGTON,
1580 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1581 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1582 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1586 * Modes which for Huntington identify a chip variant where 2
1587 * adjacent port numbers map to each cage.
1595 EFX_FAMILY_HUNTINGTON,
1596 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1597 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1598 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1599 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1600 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1603 * Modes that on Medford allocate each port number to a separate
1612 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1613 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1614 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1618 * Modes that on Medford allocate 2 adjacent port numbers to each
1627 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1628 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1629 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1630 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1631 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1632 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1633 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1636 * Modes that on Medford allocate 4 adjacent port numbers to
1645 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1646 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1647 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1650 * Modes that on Medford allocate 4 adjacent port numbers to
1659 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1660 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1663 * Modes that on Medford2 allocate each port number to a separate
1671 EFX_FAMILY_MEDFORD2,
1672 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1673 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1674 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1675 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1676 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1677 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1678 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1679 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1683 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1690 EFX_FAMILY_MEDFORD2,
1691 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */
1692 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */
1693 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1696 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1
1697 * and the rest to cage 2.
1704 EFX_FAMILY_MEDFORD2,
1705 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1706 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1707 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1708 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1709 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1712 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1720 EFX_FAMILY_MEDFORD2,
1721 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1722 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1725 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1733 EFX_FAMILY_MEDFORD2,
1734 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1735 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */
1736 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1737 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1740 * Modes that on Riverhead allocate each port number to a separate
1746 EFX_FAMILY_RIVERHEAD,
1747 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1748 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1749 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1750 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1754 static __checkReturn efx_rc_t
1755 ef10_external_port_mapping(
1756 __in efx_nic_t *enp,
1758 __out uint8_t *external_portp)
1762 uint32_t port_modes;
1765 struct ef10_external_port_map_s *mapp = NULL;
1766 int ext_index = port; /* Default 1-1 mapping */
1768 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1771 * No current port mode information (i.e. Huntington)
1772 * - infer mapping from available modes
1774 if ((rc = efx_mcdi_get_port_modes(enp,
1775 &port_modes, NULL, NULL)) != 0) {
1777 * No port mode information available
1778 * - use default mapping
1783 /* Only need to scan the current mode */
1784 port_modes = 1 << current;
1788 * Infer the internal port -> external number mapping from
1789 * the possible port modes for this NIC.
1791 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1792 struct ef10_external_port_map_s *eepmp =
1793 &__ef10_external_port_mappings[i];
1794 if (eepmp->family != enp->en_family)
1796 matches = (eepmp->modes_mask & port_modes);
1799 * Some modes match. For some Huntington boards
1800 * there will be multiple matches. The mapping on the
1801 * last match is used.
1804 port_modes &= ~matches;
1808 if (port_modes != 0) {
1809 /* Some advertised modes are not supported */
1817 * External ports are assigned a sequence of consecutive
1818 * port numbers, so find the one with the closest base_port.
1820 uint32_t delta = EFX_EXT_PORT_NA;
1822 for (i = 0; i < EFX_EXT_PORT_MAX; i++) {
1823 uint32_t base = mapp->base_port[i];
1824 if ((base != EFX_EXT_PORT_NA) && (base <= port)) {
1825 if ((port - base) < delta) {
1826 delta = (port - base);
1832 *external_portp = (uint8_t)(ext_index + 1);
1837 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1842 __checkReturn efx_rc_t
1843 efx_mcdi_nic_board_cfg(
1844 __in efx_nic_t *enp)
1846 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1847 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1848 ef10_link_state_t els;
1849 efx_port_t *epp = &(enp->en_port);
1850 efx_pcie_interface_t intf;
1851 uint32_t board_type = 0;
1852 uint32_t base, nvec;
1857 uint8_t mac_addr[6] = { 0 };
1860 /* Get the (zero-based) MCDI port number */
1861 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1864 /* EFX MCDI interface uses one-based port numbers */
1865 emip->emi_port = port + 1;
1867 encp->enc_assigned_port = port;
1869 if ((rc = ef10_external_port_mapping(enp, port,
1870 &encp->enc_external_port)) != 0)
1874 * Get PCIe function number from firmware (used for
1875 * per-function privilege and dynamic config info).
1876 * - PCIe PF: pf = PF number, vf = 0xffff.
1877 * - PCIe VF: pf = parent PF, vf = VF number.
1879 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf, &intf)) != 0)
1884 encp->enc_intf = intf;
1886 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1889 /* MAC address for this function */
1890 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1891 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1892 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1894 * Disable static config checking, ONLY for manufacturing test
1895 * and setup at the factory, to allow the static config to be
1898 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1899 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1901 * If the static config does not include a global MAC
1902 * address pool then the board may return a locally
1903 * administered MAC address (this should only happen on
1904 * incorrectly programmed boards).
1908 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1910 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1915 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1918 * Get the current privilege mask. Note that this may be modified
1919 * dynamically, so for most cases the value is informational only.
1920 * If the privilege being discovered can't be granted dynamically,
1921 * it's fine to rely on the value. In all other cases, DO NOT use
1922 * the privilege mask to check for sufficient privileges, as that
1923 * can result in time-of-check/time-of-use bugs.
1925 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1927 encp->enc_privilege_mask = mask;
1929 /* Board configuration (legacy) */
1930 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1932 /* Unprivileged functions may not be able to read board cfg */
1939 encp->enc_board_type = board_type;
1941 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1942 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1946 * Firmware with support for *_FEC capability bits does not
1947 * report that the corresponding *_FEC_REQUESTED bits are supported.
1948 * Add them here so that drivers understand that they are supported.
1950 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1951 epp->ep_phy_cap_mask |=
1952 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1953 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1954 epp->ep_phy_cap_mask |=
1955 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1956 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1957 epp->ep_phy_cap_mask |=
1958 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1960 /* Obtain the default PHY advertised capabilities */
1961 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1963 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
1964 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
1966 /* Check capabilities of running datapath firmware */
1967 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1970 /* Get interrupt vector limits */
1971 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1972 if (EFX_PCI_FUNCTION_IS_PF(encp))
1975 /* Ignore error (cannot query vector limits from a VF). */
1979 encp->enc_intr_vec_base = base;
1980 encp->enc_intr_limit = nvec;
1985 EFSYS_PROBE(fail11);
1987 EFSYS_PROBE(fail10);
2005 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2010 __checkReturn efx_rc_t
2011 efx_mcdi_entity_reset(
2012 __in efx_nic_t *enp)
2015 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
2016 MC_CMD_ENTITY_RESET_OUT_LEN);
2019 req.emr_cmd = MC_CMD_ENTITY_RESET;
2020 req.emr_in_buf = payload;
2021 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2022 req.emr_out_buf = payload;
2023 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2025 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2026 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2028 efx_mcdi_execute(enp, &req);
2030 if (req.emr_rc != 0) {
2038 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2043 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
2047 static __checkReturn efx_rc_t
2048 ef10_set_workaround_bug26807(
2049 __in efx_nic_t *enp)
2051 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2056 * If the bug26807 workaround is enabled, then firmware has enabled
2057 * support for chained multicast filters. Firmware will reset (FLR)
2058 * functions which have filters in the hardware filter table when the
2059 * workaround is enabled/disabled.
2061 * We must recheck if the workaround is enabled after inserting the
2062 * first hardware filter, in case it has been changed since this check.
2064 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
2067 encp->enc_bug26807_workaround = B_TRUE;
2068 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
2070 * Other functions had installed filters before the
2071 * workaround was enabled, and they have been reset
2074 EFSYS_PROBE(bug26807_workaround_flr_done);
2075 /* FIXME: bump MC warm boot count ? */
2077 } else if (rc == EACCES) {
2079 * Unprivileged functions cannot enable the workaround in older
2082 encp->enc_bug26807_workaround = B_FALSE;
2083 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
2084 encp->enc_bug26807_workaround = B_FALSE;
2092 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2097 static __checkReturn efx_rc_t
2099 __in efx_nic_t *enp)
2101 const efx_nic_ops_t *enop = enp->en_enop;
2102 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2105 if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0)
2109 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
2110 * We only support the 14 byte prefix here.
2112 if (encp->enc_rx_prefix_size != 14) {
2117 encp->enc_clk_mult = 1; /* not used for EF10 */
2119 /* Alignment for WPTR updates */
2120 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
2122 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
2123 /* No boundary crossing limits */
2124 encp->enc_tx_dma_desc_boundary = 0;
2127 * Maximum number of bytes into the frame the TCP header can start for
2128 * firmware assisted TSO to work.
2130 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
2132 /* EF10 TSO engine demands that packet header be contiguous. */
2133 encp->enc_tx_tso_max_header_ndescs = 1;
2135 /* The overall TSO header length is not limited. */
2136 encp->enc_tx_tso_max_header_length = UINT32_MAX;
2139 * There are no specific limitations on the number of
2140 * TSO payload descriptors.
2142 encp->enc_tx_tso_max_payload_ndescs = UINT32_MAX;
2144 /* TSO superframe payload length is not limited. */
2145 encp->enc_tx_tso_max_payload_length = UINT32_MAX;
2148 * Limitation on the maximum number of outgoing packets per
2149 * TSO transaction described in SF-108452-SW.
2151 encp->enc_tx_tso_max_nframes = 32767;
2154 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
2155 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
2156 * resources (allocated to this PCIe function), which is zero until
2157 * after we have allocated VIs.
2159 encp->enc_evq_limit = 1024;
2160 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
2161 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
2163 encp->enc_buftbl_limit = UINT32_MAX;
2165 if ((rc = ef10_set_workaround_bug26807(enp)) != 0)
2168 /* Get remaining controller-specific board config */
2169 if ((rc = enop->eno_board_cfg(enp)) != 0)
2182 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2187 __checkReturn efx_rc_t
2189 __in efx_nic_t *enp)
2191 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2192 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2195 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2197 /* Read and clear any assertion state */
2198 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2201 /* Exit the assertion handler */
2202 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2206 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
2209 if ((rc = ef10_nic_board_cfg(enp)) != 0)
2213 * Set default driver config limits (based on board config).
2215 * FIXME: For now allocate a fixed number of VIs which is likely to be
2216 * sufficient and small enough to allow multiple functions on the same
2219 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
2220 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
2222 /* The client driver must configure and enable PIO buffer support */
2223 edcp->edc_max_piobuf_count = 0;
2224 edcp->edc_pio_alloc_size = 0;
2226 #if EFSYS_OPT_MAC_STATS
2227 /* Wipe the MAC statistics */
2228 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
2232 #if EFSYS_OPT_LOOPBACK
2233 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
2237 #if EFSYS_OPT_MON_STATS
2238 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
2239 /* Unprivileged functions do not have access to sensors */
2247 #if EFSYS_OPT_MON_STATS
2251 #if EFSYS_OPT_LOOPBACK
2255 #if EFSYS_OPT_MAC_STATS
2266 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2271 __checkReturn efx_rc_t
2272 ef10_nic_set_drv_limits(
2273 __inout efx_nic_t *enp,
2274 __in efx_drv_limits_t *edlp)
2276 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2277 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2278 uint32_t min_evq_count, max_evq_count;
2279 uint32_t min_rxq_count, max_rxq_count;
2280 uint32_t min_txq_count, max_txq_count;
2288 /* Get minimum required and maximum usable VI limits */
2289 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2290 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2291 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2293 edcp->edc_min_vi_count =
2294 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2296 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2297 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2298 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2300 edcp->edc_max_vi_count =
2301 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2304 * Check limits for sub-allocated piobuf blocks.
2305 * PIO is optional, so don't fail if the limits are incorrect.
2307 if ((encp->enc_piobuf_size == 0) ||
2308 (encp->enc_piobuf_limit == 0) ||
2309 (edlp->edl_min_pio_alloc_size == 0) ||
2310 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2312 edcp->edc_max_piobuf_count = 0;
2313 edcp->edc_pio_alloc_size = 0;
2315 uint32_t blk_size, blk_count, blks_per_piobuf;
2318 MAX(edlp->edl_min_pio_alloc_size,
2319 encp->enc_piobuf_min_alloc_size);
2321 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2322 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2324 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2326 /* A zero max pio alloc count means unlimited */
2327 if ((edlp->edl_max_pio_alloc_count > 0) &&
2328 (edlp->edl_max_pio_alloc_count < blk_count)) {
2329 blk_count = edlp->edl_max_pio_alloc_count;
2332 edcp->edc_pio_alloc_size = blk_size;
2333 edcp->edc_max_piobuf_count =
2334 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2340 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2346 __checkReturn efx_rc_t
2348 __in efx_nic_t *enp)
2352 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2353 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2355 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2358 if ((rc = efx_mcdi_entity_reset(enp)) != 0)
2361 /* Clear RX/TX DMA queue errors */
2362 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2371 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2376 #endif /* EFX_OPTS_EF10() */
2378 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
2380 __checkReturn efx_rc_t
2381 ef10_upstream_port_vadaptor_alloc(
2382 __in efx_nic_t *enp)
2389 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2390 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2391 * retry the request several times after waiting a while. The wait time
2392 * between retries starts small (10ms) and exponentially increases.
2393 * Total wait time is a little over two seconds. Retry logic in the
2394 * client driver may mean this whole loop is repeated if it continues to
2399 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2400 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2403 * Do not retry alloc for PF, or for other errors on
2409 /* VF startup before PF is ready. Retry allocation. */
2411 /* Too many attempts */
2415 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2416 EFSYS_SLEEP(delay_us);
2418 if (delay_us < 500000)
2427 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2432 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
2436 __checkReturn efx_rc_t
2438 __in efx_nic_t *enp)
2440 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2441 uint32_t min_vi_count, max_vi_count;
2442 uint32_t vi_count, vi_base, vi_shift;
2444 uint32_t vi_window_size;
2446 boolean_t alloc_vadaptor = B_TRUE;
2448 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2450 /* Enable reporting of some events (e.g. link change) */
2451 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2454 /* Allocate (optional) on-chip PIO buffers */
2455 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2458 * For best performance, PIO writes should use a write-combined
2459 * (WC) memory mapping. Using a separate WC mapping for the PIO
2460 * aperture of each VI would be a burden to drivers (and not
2461 * possible if the host page size is >4Kbyte).
2463 * To avoid this we use a single uncached (UC) mapping for VI
2464 * register access, and a single WC mapping for extra VIs used
2467 * Each piobuf must be linked to a VI in the WC mapping, and to
2468 * each VI that is using a sub-allocated block from the piobuf.
2470 min_vi_count = edcp->edc_min_vi_count;
2472 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2474 /* Ensure that the previously attached driver's VIs are freed */
2475 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2479 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2480 * fails then retrying the request for fewer VI resources may succeed.
2483 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2484 &vi_base, &vi_count, &vi_shift)) != 0)
2487 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2489 if (vi_count < min_vi_count) {
2494 enp->en_arch.ef10.ena_vi_base = vi_base;
2495 enp->en_arch.ef10.ena_vi_count = vi_count;
2496 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2498 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2499 /* Not enough extra VIs to map piobufs */
2500 ef10_nic_free_piobufs(enp);
2503 enp->en_arch.ef10.ena_pio_write_vi_base =
2504 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2506 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2507 EFX_VI_WINDOW_SHIFT_INVALID);
2508 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2509 EFX_VI_WINDOW_SHIFT_64K);
2510 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2512 /* Save UC memory mapping details */
2513 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2514 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2515 enp->en_arch.ef10.ena_uc_mem_map_size =
2517 enp->en_arch.ef10.ena_pio_write_vi_base);
2519 enp->en_arch.ef10.ena_uc_mem_map_size =
2521 enp->en_arch.ef10.ena_vi_count);
2524 /* Save WC memory mapping details */
2525 enp->en_arch.ef10.ena_wc_mem_map_offset =
2526 enp->en_arch.ef10.ena_uc_mem_map_offset +
2527 enp->en_arch.ef10.ena_uc_mem_map_size;
2529 enp->en_arch.ef10.ena_wc_mem_map_size =
2531 enp->en_arch.ef10.ena_piobuf_count);
2533 /* Link piobufs to extra VIs in WC mapping */
2534 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2535 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2536 rc = efx_mcdi_link_piobuf(enp,
2537 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2538 enp->en_arch.ef10.ena_piobuf_handle[i]);
2545 * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs
2546 * during NIC initialization when vSwitch is created and vports are
2547 * allocated. Hence, skip vAdaptor allocation for EVB and update vport
2548 * id in NIC structure with the one allocated for PF.
2551 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2553 if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) {
2554 /* For EVB use vport allocated on vswitch */
2555 enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id;
2556 alloc_vadaptor = B_FALSE;
2559 if (alloc_vadaptor != B_FALSE) {
2560 /* Allocate a vAdaptor attached to our upstream vPort/pPort */
2561 if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0)
2564 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2577 ef10_nic_free_piobufs(enp);
2580 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2585 __checkReturn efx_rc_t
2586 ef10_nic_get_vi_pool(
2587 __in efx_nic_t *enp,
2588 __out uint32_t *vi_countp)
2590 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2593 * Report VIs that the client driver can use.
2594 * Do not include VIs used for PIO buffer writes.
2596 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2601 __checkReturn efx_rc_t
2602 ef10_nic_get_bar_region(
2603 __in efx_nic_t *enp,
2604 __in efx_nic_region_t region,
2605 __out uint32_t *offsetp,
2606 __out size_t *sizep)
2610 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2613 * TODO: Specify host memory mapping alignment and granularity
2614 * in efx_drv_limits_t so that they can be taken into account
2615 * when allocating extra VIs for PIO writes.
2619 /* UC mapped memory BAR region for VI registers */
2620 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2621 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2624 case EFX_REGION_PIO_WRITE_VI:
2625 /* WC mapped memory BAR region for piobuf writes */
2626 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2627 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2638 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2643 __checkReturn boolean_t
2644 ef10_nic_hw_unavailable(
2645 __in efx_nic_t *enp)
2649 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2652 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2653 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2659 ef10_nic_set_hw_unavailable(enp);
2665 ef10_nic_set_hw_unavailable(
2666 __in efx_nic_t *enp)
2668 EFSYS_PROBE(hw_unavail);
2669 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2675 __in efx_nic_t *enp)
2679 boolean_t do_vadaptor_free = B_TRUE;
2682 if (enp->en_vswitchp != NULL) {
2684 * For SR-IOV the vAdaptor is freed with the vswitch,
2685 * so do not free it here.
2687 do_vadaptor_free = B_FALSE;
2690 if (do_vadaptor_free != B_FALSE) {
2691 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2692 enp->en_vport_id = EVB_PORT_ID_NULL;
2695 /* Unlink piobufs from extra VIs in WC mapping */
2696 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2697 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2698 rc = efx_mcdi_unlink_piobuf(enp,
2699 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2705 ef10_nic_free_piobufs(enp);
2707 (void) efx_mcdi_free_vis(enp);
2708 enp->en_arch.ef10.ena_vi_count = 0;
2713 __in efx_nic_t *enp)
2715 #if EFSYS_OPT_MON_STATS
2716 mcdi_mon_cfg_free(enp);
2717 #endif /* EFSYS_OPT_MON_STATS */
2718 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2723 __checkReturn efx_rc_t
2724 ef10_nic_register_test(
2725 __in efx_nic_t *enp)
2730 _NOTE(ARGUNUSED(enp))
2731 _NOTE(CONSTANTCONDITION)
2741 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2746 #endif /* EFSYS_OPT_DIAG */
2748 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2750 __checkReturn efx_rc_t
2751 efx_mcdi_get_nic_global(
2752 __in efx_nic_t *enp,
2754 __out uint32_t *valuep)
2757 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2758 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2761 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2762 req.emr_in_buf = payload;
2763 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2764 req.emr_out_buf = payload;
2765 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2767 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2769 efx_mcdi_execute(enp, &req);
2771 if (req.emr_rc != 0) {
2776 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2781 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2788 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2793 __checkReturn efx_rc_t
2794 efx_mcdi_set_nic_global(
2795 __in efx_nic_t *enp,
2797 __in uint32_t value)
2800 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2803 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2804 req.emr_in_buf = payload;
2805 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2806 req.emr_out_buf = NULL;
2807 req.emr_out_length = 0;
2809 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2810 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2812 efx_mcdi_execute(enp, &req);
2814 if (req.emr_rc != 0) {
2822 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2827 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2829 #endif /* EFX_OPTS_EF10() */