1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
27 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
29 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
30 req.emr_in_buf = payload;
31 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
32 req.emr_out_buf = payload;
33 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
35 efx_mcdi_execute(enp, &req);
37 if (req.emr_rc != 0) {
42 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
47 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
54 EFSYS_PROBE1(fail1, efx_rc_t, rc);
59 __checkReturn efx_rc_t
60 efx_mcdi_get_port_modes(
62 __out uint32_t *modesp,
63 __out_opt uint32_t *current_modep,
64 __out_opt uint32_t *default_modep)
67 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
68 MC_CMD_GET_PORT_MODES_OUT_LEN);
71 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
73 req.emr_cmd = MC_CMD_GET_PORT_MODES;
74 req.emr_in_buf = payload;
75 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
76 req.emr_out_buf = payload;
77 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
79 efx_mcdi_execute(enp, &req);
81 if (req.emr_rc != 0) {
87 * Require only Modes and DefaultMode fields, unless the current mode
88 * was requested (CurrentMode field was added for Medford).
90 if (req.emr_out_length_used <
91 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
95 if ((current_modep != NULL) && (req.emr_out_length_used <
96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
101 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
103 if (current_modep != NULL) {
104 *current_modep = MCDI_OUT_DWORD(req,
105 GET_PORT_MODES_OUT_CURRENT_MODE);
108 if (default_modep != NULL) {
109 *default_modep = MCDI_OUT_DWORD(req,
110 GET_PORT_MODES_OUT_DEFAULT_MODE);
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
125 __checkReturn efx_rc_t
126 ef10_nic_get_port_mode_bandwidth(
128 __out uint32_t *bandwidth_mbpsp)
131 uint32_t current_mode;
132 efx_port_t *epp = &(enp->en_port);
134 uint32_t single_lane;
140 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
141 ¤t_mode, NULL)) != 0) {
142 /* No port mode info available. */
146 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX))
151 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX))
156 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX))
161 switch (current_mode) {
162 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
163 bandwidth = single_lane;
165 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
166 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
167 bandwidth = dual_lane;
169 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
170 bandwidth = single_lane + single_lane;
172 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
173 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
174 bandwidth = 4 * single_lane;
176 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
177 bandwidth = (2 * single_lane) + (2 * single_lane);
179 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
180 bandwidth = dual_lane + dual_lane;
182 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
183 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
184 bandwidth = dual_lane + (2 * single_lane);
186 /* Legacy Medford-only mode. Do not use (see bug63270) */
187 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
188 bandwidth = 4 * single_lane;
190 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
191 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
192 bandwidth = quad_lane;
194 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
195 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
196 bandwidth = 2 * dual_lane;
198 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
199 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
200 bandwidth = quad_lane + (2 * single_lane);
202 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
203 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
204 bandwidth = quad_lane + dual_lane;
206 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
207 bandwidth = quad_lane + quad_lane;
214 *bandwidth_mbpsp = bandwidth;
221 EFSYS_PROBE1(fail1, efx_rc_t, rc);
226 __checkReturn efx_rc_t
227 efx_mcdi_vadaptor_alloc(
229 __in uint32_t port_id)
232 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
233 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
236 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
237 req.emr_in_buf = payload;
238 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
239 req.emr_out_buf = payload;
240 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
242 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
243 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
244 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
245 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
247 efx_mcdi_execute(enp, &req);
249 if (req.emr_rc != 0) {
257 EFSYS_PROBE1(fail1, efx_rc_t, rc);
262 __checkReturn efx_rc_t
263 efx_mcdi_vadaptor_free(
265 __in uint32_t port_id)
268 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
269 MC_CMD_VADAPTOR_FREE_OUT_LEN);
272 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
273 req.emr_in_buf = payload;
274 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
275 req.emr_out_buf = payload;
276 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
278 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
280 efx_mcdi_execute(enp, &req);
282 if (req.emr_rc != 0) {
290 EFSYS_PROBE1(fail1, efx_rc_t, rc);
295 __checkReturn efx_rc_t
296 efx_mcdi_get_mac_address_pf(
298 __out_ecount_opt(6) uint8_t mac_addrp[6])
301 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
302 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
305 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
307 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
308 req.emr_in_buf = payload;
309 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
310 req.emr_out_buf = payload;
311 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
313 efx_mcdi_execute(enp, &req);
315 if (req.emr_rc != 0) {
320 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
325 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
330 if (mac_addrp != NULL) {
333 addrp = MCDI_OUT2(req, uint8_t,
334 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
336 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
346 EFSYS_PROBE1(fail1, efx_rc_t, rc);
351 __checkReturn efx_rc_t
352 efx_mcdi_get_mac_address_vf(
354 __out_ecount_opt(6) uint8_t mac_addrp[6])
357 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
358 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
361 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
363 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
364 req.emr_in_buf = payload;
365 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
366 req.emr_out_buf = payload;
367 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
369 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
370 EVB_PORT_ID_ASSIGNED);
372 efx_mcdi_execute(enp, &req);
374 if (req.emr_rc != 0) {
379 if (req.emr_out_length_used <
380 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
385 if (MCDI_OUT_DWORD(req,
386 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
391 if (mac_addrp != NULL) {
394 addrp = MCDI_OUT2(req, uint8_t,
395 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
397 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
407 EFSYS_PROBE1(fail1, efx_rc_t, rc);
412 __checkReturn efx_rc_t
415 __out uint32_t *sys_freqp,
416 __out uint32_t *dpcpu_freqp)
419 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
420 MC_CMD_GET_CLOCK_OUT_LEN);
423 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
425 req.emr_cmd = MC_CMD_GET_CLOCK;
426 req.emr_in_buf = payload;
427 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
428 req.emr_out_buf = payload;
429 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
431 efx_mcdi_execute(enp, &req);
433 if (req.emr_rc != 0) {
438 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
443 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
444 if (*sys_freqp == 0) {
448 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
449 if (*dpcpu_freqp == 0) {
463 EFSYS_PROBE1(fail1, efx_rc_t, rc);
468 __checkReturn efx_rc_t
469 efx_mcdi_get_rxdp_config(
471 __out uint32_t *end_paddingp)
474 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
475 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
476 uint32_t end_padding;
479 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
480 req.emr_in_buf = payload;
481 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
482 req.emr_out_buf = payload;
483 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
485 efx_mcdi_execute(enp, &req);
486 if (req.emr_rc != 0) {
491 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
492 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
493 /* RX DMA end padding is disabled */
496 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
497 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
498 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
501 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
504 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
513 *end_paddingp = end_padding;
520 EFSYS_PROBE1(fail1, efx_rc_t, rc);
525 __checkReturn efx_rc_t
526 efx_mcdi_get_vector_cfg(
528 __out_opt uint32_t *vec_basep,
529 __out_opt uint32_t *pf_nvecp,
530 __out_opt uint32_t *vf_nvecp)
533 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
534 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
537 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
538 req.emr_in_buf = payload;
539 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
540 req.emr_out_buf = payload;
541 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
543 efx_mcdi_execute(enp, &req);
545 if (req.emr_rc != 0) {
550 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
555 if (vec_basep != NULL)
556 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
557 if (pf_nvecp != NULL)
558 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
559 if (vf_nvecp != NULL)
560 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
567 EFSYS_PROBE1(fail1, efx_rc_t, rc);
572 static __checkReturn efx_rc_t
575 __in uint32_t min_vi_count,
576 __in uint32_t max_vi_count,
577 __out uint32_t *vi_basep,
578 __out uint32_t *vi_countp,
579 __out uint32_t *vi_shiftp)
582 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
583 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
586 if (vi_countp == NULL) {
591 req.emr_cmd = MC_CMD_ALLOC_VIS;
592 req.emr_in_buf = payload;
593 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
594 req.emr_out_buf = payload;
595 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
597 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
598 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
600 efx_mcdi_execute(enp, &req);
602 if (req.emr_rc != 0) {
607 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
612 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
613 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
615 /* Report VI_SHIFT if available (always zero for Huntington) */
616 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
619 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
628 EFSYS_PROBE1(fail1, efx_rc_t, rc);
634 static __checkReturn efx_rc_t
641 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
642 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
644 req.emr_cmd = MC_CMD_FREE_VIS;
645 req.emr_in_buf = NULL;
646 req.emr_in_length = 0;
647 req.emr_out_buf = NULL;
648 req.emr_out_length = 0;
650 efx_mcdi_execute_quiet(enp, &req);
652 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
653 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
661 EFSYS_PROBE1(fail1, efx_rc_t, rc);
667 static __checkReturn efx_rc_t
668 efx_mcdi_alloc_piobuf(
670 __out efx_piobuf_handle_t *handlep)
673 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
674 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
677 if (handlep == NULL) {
682 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
683 req.emr_in_buf = payload;
684 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
685 req.emr_out_buf = payload;
686 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
688 efx_mcdi_execute_quiet(enp, &req);
690 if (req.emr_rc != 0) {
695 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
700 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
709 EFSYS_PROBE1(fail1, efx_rc_t, rc);
714 static __checkReturn efx_rc_t
715 efx_mcdi_free_piobuf(
717 __in efx_piobuf_handle_t handle)
720 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
721 MC_CMD_FREE_PIOBUF_OUT_LEN);
724 req.emr_cmd = MC_CMD_FREE_PIOBUF;
725 req.emr_in_buf = payload;
726 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
727 req.emr_out_buf = payload;
728 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
730 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
732 efx_mcdi_execute_quiet(enp, &req);
734 if (req.emr_rc != 0) {
742 EFSYS_PROBE1(fail1, efx_rc_t, rc);
747 static __checkReturn efx_rc_t
748 efx_mcdi_link_piobuf(
750 __in uint32_t vi_index,
751 __in efx_piobuf_handle_t handle)
754 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
755 MC_CMD_LINK_PIOBUF_OUT_LEN);
758 req.emr_cmd = MC_CMD_LINK_PIOBUF;
759 req.emr_in_buf = payload;
760 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
761 req.emr_out_buf = payload;
762 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
764 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
765 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
767 efx_mcdi_execute(enp, &req);
769 if (req.emr_rc != 0) {
777 EFSYS_PROBE1(fail1, efx_rc_t, rc);
782 static __checkReturn efx_rc_t
783 efx_mcdi_unlink_piobuf(
785 __in uint32_t vi_index)
788 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
789 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
792 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
793 req.emr_in_buf = payload;
794 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
795 req.emr_out_buf = payload;
796 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
798 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
800 efx_mcdi_execute_quiet(enp, &req);
802 if (req.emr_rc != 0) {
810 EFSYS_PROBE1(fail1, efx_rc_t, rc);
816 ef10_nic_alloc_piobufs(
818 __in uint32_t max_piobuf_count)
820 efx_piobuf_handle_t *handlep;
823 EFSYS_ASSERT3U(max_piobuf_count, <=,
824 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
826 enp->en_arch.ef10.ena_piobuf_count = 0;
828 for (i = 0; i < max_piobuf_count; i++) {
829 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
831 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
834 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
835 enp->en_arch.ef10.ena_piobuf_count++;
841 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
842 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
844 (void) efx_mcdi_free_piobuf(enp, *handlep);
845 *handlep = EFX_PIOBUF_HANDLE_INVALID;
847 enp->en_arch.ef10.ena_piobuf_count = 0;
852 ef10_nic_free_piobufs(
855 efx_piobuf_handle_t *handlep;
858 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
859 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
861 (void) efx_mcdi_free_piobuf(enp, *handlep);
862 *handlep = EFX_PIOBUF_HANDLE_INVALID;
864 enp->en_arch.ef10.ena_piobuf_count = 0;
867 /* Sub-allocate a block from a piobuf */
868 __checkReturn efx_rc_t
870 __inout efx_nic_t *enp,
871 __out uint32_t *bufnump,
872 __out efx_piobuf_handle_t *handlep,
873 __out uint32_t *blknump,
874 __out uint32_t *offsetp,
877 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
878 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
879 uint32_t blk_per_buf;
883 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
884 EFSYS_ASSERT(bufnump);
885 EFSYS_ASSERT(handlep);
886 EFSYS_ASSERT(blknump);
887 EFSYS_ASSERT(offsetp);
890 if ((edcp->edc_pio_alloc_size == 0) ||
891 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
895 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
897 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
898 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
903 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
904 for (blk = 0; blk < blk_per_buf; blk++) {
905 if ((*map & (1u << blk)) == 0) {
915 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
918 *sizep = edcp->edc_pio_alloc_size;
919 *offsetp = blk * (*sizep);
926 EFSYS_PROBE1(fail1, efx_rc_t, rc);
931 /* Free a piobuf sub-allocated block */
932 __checkReturn efx_rc_t
934 __inout efx_nic_t *enp,
935 __in uint32_t bufnum,
936 __in uint32_t blknum)
941 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
942 (blknum >= (8 * sizeof (*map)))) {
947 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
948 if ((*map & (1u << blknum)) == 0) {
952 *map &= ~(1u << blknum);
959 EFSYS_PROBE1(fail1, efx_rc_t, rc);
964 __checkReturn efx_rc_t
966 __inout efx_nic_t *enp,
967 __in uint32_t vi_index,
968 __in efx_piobuf_handle_t handle)
970 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
973 __checkReturn efx_rc_t
975 __inout efx_nic_t *enp,
976 __in uint32_t vi_index)
978 return (efx_mcdi_unlink_piobuf(enp, vi_index));
981 static __checkReturn efx_rc_t
982 ef10_mcdi_get_pf_count(
984 __out uint32_t *pf_countp)
987 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
988 MC_CMD_GET_PF_COUNT_OUT_LEN);
991 req.emr_cmd = MC_CMD_GET_PF_COUNT;
992 req.emr_in_buf = payload;
993 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
994 req.emr_out_buf = payload;
995 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
997 efx_mcdi_execute(enp, &req);
999 if (req.emr_rc != 0) {
1004 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1009 *pf_countp = *MCDI_OUT(req, uint8_t,
1010 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1012 EFSYS_ASSERT(*pf_countp != 0);
1019 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1024 static __checkReturn efx_rc_t
1025 ef10_get_datapath_caps(
1026 __in efx_nic_t *enp)
1028 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1030 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1031 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN);
1034 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1035 req.emr_in_buf = payload;
1036 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1037 req.emr_out_buf = payload;
1038 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1040 efx_mcdi_execute_quiet(enp, &req);
1042 if (req.emr_rc != 0) {
1047 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1052 #define CAP_FLAGS1(_req, _flag) \
1053 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1054 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1056 #define CAP_FLAGS2(_req, _flag) \
1057 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1058 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1059 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1061 /* Check if RXDP firmware inserts 14 byte prefix */
1062 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14))
1063 encp->enc_rx_prefix_size = 14;
1065 encp->enc_rx_prefix_size = 0;
1067 #if EFSYS_OPT_RX_SCALE
1068 /* Check if the firmware supports additional RSS modes */
1069 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1070 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1072 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1073 #endif /* EFSYS_OPT_RX_SCALE */
1075 /* Check if the firmware supports TSO */
1076 if (CAP_FLAGS1(req, TX_TSO))
1077 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1079 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1081 /* Check if the firmware supports FATSOv2 */
1082 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1083 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1084 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1085 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1087 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1088 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1091 /* Check if the firmware supports FATSOv2 encap */
1092 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1093 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1095 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1097 /* Check if the firmware has vadapter/vport/vswitch support */
1098 if (CAP_FLAGS1(req, EVB))
1099 encp->enc_datapath_cap_evb = B_TRUE;
1101 encp->enc_datapath_cap_evb = B_FALSE;
1103 /* Check if the firmware supports vport reconfiguration */
1104 if (CAP_FLAGS1(req, VPORT_RECONFIGURE))
1105 encp->enc_vport_reconfigure_supported = B_TRUE;
1107 encp->enc_vport_reconfigure_supported = B_FALSE;
1109 /* Check if the firmware supports VLAN insertion */
1110 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1111 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1113 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1115 /* Check if the firmware supports RX event batching */
1116 if (CAP_FLAGS1(req, RX_BATCHING))
1117 encp->enc_rx_batching_enabled = B_TRUE;
1119 encp->enc_rx_batching_enabled = B_FALSE;
1122 * Even if batching isn't reported as supported, we may still get
1123 * batched events (see bug61153).
1125 encp->enc_rx_batch_max = 16;
1127 /* Check if the firmware supports disabling scatter on RXQs */
1128 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1129 encp->enc_rx_disable_scatter_supported = B_TRUE;
1131 encp->enc_rx_disable_scatter_supported = B_FALSE;
1133 /* Check if the firmware supports packed stream mode */
1134 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1135 encp->enc_rx_packed_stream_supported = B_TRUE;
1137 encp->enc_rx_packed_stream_supported = B_FALSE;
1140 * Check if the firmware supports configurable buffer sizes
1141 * for packed stream mode (otherwise buffer size is 1Mbyte)
1143 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1144 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1146 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1148 /* Check if the firmware supports equal stride super-buffer mode */
1149 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1150 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1152 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1154 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1155 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1156 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1158 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1160 /* Check if the firmware supports set mac with running filters */
1161 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1162 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1164 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1167 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1168 * specifying which parameters to configure.
1170 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1171 encp->enc_enhanced_set_mac_supported = B_TRUE;
1173 encp->enc_enhanced_set_mac_supported = B_FALSE;
1176 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1177 * us to let the firmware choose the settings to use on an EVQ.
1179 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1180 encp->enc_init_evq_v2_supported = B_TRUE;
1182 encp->enc_init_evq_v2_supported = B_FALSE;
1185 * Check if the NO_CONT_EV mode for RX events is supported.
1187 if (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV))
1188 encp->enc_no_cont_ev_mode_supported = B_TRUE;
1190 encp->enc_no_cont_ev_mode_supported = B_FALSE;
1193 * Check if buffer size may and must be specified on INIT_RXQ.
1194 * It may be always specified to efx_rx_qcreate(), but will be
1195 * just kept libefx internal if MCDI does not support it.
1197 if (CAP_FLAGS2(req, INIT_RXQ_WITH_BUFFER_SIZE))
1198 encp->enc_init_rxq_with_buffer_size = B_TRUE;
1200 encp->enc_init_rxq_with_buffer_size = B_FALSE;
1203 * Check if firmware-verified NVRAM updates must be used.
1205 * The firmware trusted installer requires all NVRAM updates to use
1206 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1207 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1208 * partition and report the result).
1210 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1211 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1213 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1215 if (CAP_FLAGS2(req, NVRAM_UPDATE_POLL_VERIFY_RESULT))
1216 encp->enc_nvram_update_poll_verify_result_supported = B_TRUE;
1218 encp->enc_nvram_update_poll_verify_result_supported = B_FALSE;
1221 * Check if firmware update via the BUNDLE partition is supported
1223 if (CAP_FLAGS2(req, BUNDLE_UPDATE))
1224 encp->enc_nvram_bundle_update_supported = B_TRUE;
1226 encp->enc_nvram_bundle_update_supported = B_FALSE;
1229 * Check if firmware provides packet memory and Rx datapath
1232 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1233 encp->enc_pm_and_rxdp_counters = B_TRUE;
1235 encp->enc_pm_and_rxdp_counters = B_FALSE;
1238 * Check if the 40G MAC hardware is capable of reporting
1239 * statistics for Tx size bins.
1241 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1242 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1244 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1247 * Check if firmware supports VXLAN and NVGRE tunnels.
1248 * The capability indicates Geneve protocol support as well.
1250 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1251 encp->enc_tunnel_encapsulations_supported =
1252 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1253 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1254 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1256 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1257 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1258 encp->enc_tunnel_config_udp_entries_max =
1259 EFX_TUNNEL_MAXNENTRIES;
1261 encp->enc_tunnel_config_udp_entries_max = 0;
1265 * Check if firmware reports the VI window mode.
1266 * Medford2 has a variable VI window size (8K, 16K or 64K).
1267 * Medford and Huntington have a fixed 8K VI window size.
1269 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1271 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1274 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1275 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1277 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1278 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1280 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1281 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1284 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1287 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1288 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1289 /* Huntington and Medford have fixed 8K window size */
1290 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1292 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1295 /* Check if firmware supports extended MAC stats. */
1296 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1297 /* Extended stats buffer supported */
1298 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1299 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1301 /* Use Siena-compatible legacy MAC stats */
1302 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1305 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1306 encp->enc_fec_counters = B_TRUE;
1308 encp->enc_fec_counters = B_FALSE;
1310 /* Check if the firmware provides head-of-line blocking counters */
1311 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1312 encp->enc_hlb_counters = B_TRUE;
1314 encp->enc_hlb_counters = B_FALSE;
1316 #if EFSYS_OPT_RX_SCALE
1317 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1318 /* Only one exclusive RSS context is available per port. */
1319 encp->enc_rx_scale_max_exclusive_contexts = 1;
1321 switch (enp->en_family) {
1322 case EFX_FAMILY_MEDFORD2:
1323 encp->enc_rx_scale_hash_alg_mask =
1324 (1U << EFX_RX_HASHALG_TOEPLITZ);
1327 case EFX_FAMILY_MEDFORD:
1328 case EFX_FAMILY_HUNTINGTON:
1330 * Packed stream firmware variant maintains a
1331 * non-standard algorithm for hash computation.
1332 * It implies explicit XORing together
1333 * source + destination IP addresses (or last
1334 * four bytes in the case of IPv6) and using the
1335 * resulting value as the input to a Toeplitz hash.
1337 encp->enc_rx_scale_hash_alg_mask =
1338 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1346 /* Port numbers cannot contribute to the hash value */
1347 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1350 * Maximum number of exclusive RSS contexts.
1351 * EF10 hardware supports 64 in total, but 6 are reserved
1352 * for shared contexts. They are a global resource so
1353 * not all may be available.
1355 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1357 encp->enc_rx_scale_hash_alg_mask =
1358 (1U << EFX_RX_HASHALG_TOEPLITZ);
1361 * It is possible to use port numbers as
1362 * the input data for hash computation.
1364 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1366 #endif /* EFSYS_OPT_RX_SCALE */
1368 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1369 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1370 encp->enc_filter_action_flag_supported = B_TRUE;
1372 encp->enc_filter_action_flag_supported = B_FALSE;
1374 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1375 encp->enc_filter_action_mark_supported = B_TRUE;
1377 encp->enc_filter_action_mark_supported = B_FALSE;
1379 /* Get maximum supported value for "MARK" filter action */
1380 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1381 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1382 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1384 encp->enc_filter_action_mark_max = 0;
1391 #if EFSYS_OPT_RX_SCALE
1394 #endif /* EFSYS_OPT_RX_SCALE */
1398 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1404 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1405 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1406 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1407 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1408 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1409 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1410 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1411 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1412 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1413 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1414 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1415 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1417 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1420 __checkReturn efx_rc_t
1421 ef10_get_privilege_mask(
1422 __in efx_nic_t *enp,
1423 __out uint32_t *maskp)
1425 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1429 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1434 /* Fallback for old firmware without privilege mask support */
1435 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1436 /* Assume PF has admin privilege */
1437 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1439 /* VF is always unprivileged by default */
1440 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1449 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1455 #define EFX_EXT_PORT_MAX 4
1456 #define EFX_EXT_PORT_NA 0xFF
1459 * Table of mapping schemes from port number to external number.
1461 * Each port number ultimately corresponds to a connector: either as part of
1462 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1463 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1464 * "Salina"). In general:
1466 * Port number (0-based)
1468 * port mapping (n:1)
1471 * External port number (1-based)
1473 * fixed (1:1) or cable assembly (1:m)
1478 * The external numbering refers to the cages or magjacks on the board,
1479 * as visibly annotated on the board or back panel. This table describes
1480 * how to determine which external cage/magjack corresponds to the port
1481 * numbers used by the driver.
1483 * The count of consecutive port numbers that map to each external number,
1484 * is determined by the chip family and the current port mode.
1486 * For the Huntington family, the current port mode cannot be discovered,
1487 * but a single mapping is used by all modes for a given chip variant,
1488 * so the mapping used is instead the last match in the table to the full
1489 * set of port modes to which the NIC can be configured. Therefore the
1490 * ordering of entries in the mapping table is significant.
1492 static struct ef10_external_port_map_s {
1493 efx_family_t family;
1494 uint32_t modes_mask;
1495 uint8_t base_port[EFX_EXT_PORT_MAX];
1496 } __ef10_external_port_mappings[] = {
1498 * Modes used by Huntington family controllers where each port
1499 * number maps to a separate cage.
1500 * SFN7x22F (Torino):
1510 EFX_FAMILY_HUNTINGTON,
1511 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1512 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1513 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1517 * Modes which for Huntington identify a chip variant where 2
1518 * adjacent port numbers map to each cage.
1526 EFX_FAMILY_HUNTINGTON,
1527 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1528 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1529 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1530 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1531 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1534 * Modes that on Medford allocate each port number to a separate
1543 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1544 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1545 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1549 * Modes that on Medford allocate 2 adjacent port numbers to each
1558 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1559 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1560 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1561 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1562 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1563 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1564 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1567 * Modes that on Medford allocate 4 adjacent port numbers to
1576 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1577 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1578 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1581 * Modes that on Medford allocate 4 adjacent port numbers to
1590 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1591 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1594 * Modes that on Medford2 allocate each port number to a separate
1602 EFX_FAMILY_MEDFORD2,
1603 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1604 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1605 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1606 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1607 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1608 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1609 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1610 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1614 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1621 EFX_FAMILY_MEDFORD2,
1622 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */
1623 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */
1624 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1627 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1
1628 * and the rest to cage 2.
1635 EFX_FAMILY_MEDFORD2,
1636 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1637 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1638 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1639 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1640 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1643 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1651 EFX_FAMILY_MEDFORD2,
1652 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1653 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1656 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1664 EFX_FAMILY_MEDFORD2,
1665 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1666 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */
1667 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1668 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1672 static __checkReturn efx_rc_t
1673 ef10_external_port_mapping(
1674 __in efx_nic_t *enp,
1676 __out uint8_t *external_portp)
1680 uint32_t port_modes;
1683 struct ef10_external_port_map_s *mapp = NULL;
1684 int ext_index = port; /* Default 1-1 mapping */
1686 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1689 * No current port mode information (i.e. Huntington)
1690 * - infer mapping from available modes
1692 if ((rc = efx_mcdi_get_port_modes(enp,
1693 &port_modes, NULL, NULL)) != 0) {
1695 * No port mode information available
1696 * - use default mapping
1701 /* Only need to scan the current mode */
1702 port_modes = 1 << current;
1706 * Infer the internal port -> external number mapping from
1707 * the possible port modes for this NIC.
1709 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1710 struct ef10_external_port_map_s *eepmp =
1711 &__ef10_external_port_mappings[i];
1712 if (eepmp->family != enp->en_family)
1714 matches = (eepmp->modes_mask & port_modes);
1717 * Some modes match. For some Huntington boards
1718 * there will be multiple matches. The mapping on the
1719 * last match is used.
1722 port_modes &= ~matches;
1726 if (port_modes != 0) {
1727 /* Some advertised modes are not supported */
1735 * External ports are assigned a sequence of consecutive
1736 * port numbers, so find the one with the closest base_port.
1738 uint32_t delta = EFX_EXT_PORT_NA;
1740 for (i = 0; i < EFX_EXT_PORT_MAX; i++) {
1741 uint32_t base = mapp->base_port[i];
1742 if ((base != EFX_EXT_PORT_NA) && (base <= port)) {
1743 if ((port - base) < delta) {
1744 delta = (port - base);
1750 *external_portp = (uint8_t)(ext_index + 1);
1755 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1760 static __checkReturn efx_rc_t
1761 efx_mcdi_nic_board_cfg(
1762 __in efx_nic_t *enp)
1764 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1765 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1766 ef10_link_state_t els;
1767 efx_port_t *epp = &(enp->en_port);
1768 uint32_t board_type = 0;
1769 uint32_t base, nvec;
1774 uint8_t mac_addr[6] = { 0 };
1777 /* Get the (zero-based) MCDI port number */
1778 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1781 /* EFX MCDI interface uses one-based port numbers */
1782 emip->emi_port = port + 1;
1784 encp->enc_assigned_port = port;
1786 if ((rc = ef10_external_port_mapping(enp, port,
1787 &encp->enc_external_port)) != 0)
1791 * Get PCIe function number from firmware (used for
1792 * per-function privilege and dynamic config info).
1793 * - PCIe PF: pf = PF number, vf = 0xffff.
1794 * - PCIe VF: pf = parent PF, vf = VF number.
1796 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1802 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1805 /* MAC address for this function */
1806 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1807 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1808 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1810 * Disable static config checking, ONLY for manufacturing test
1811 * and setup at the factory, to allow the static config to be
1814 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1815 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1817 * If the static config does not include a global MAC
1818 * address pool then the board may return a locally
1819 * administered MAC address (this should only happen on
1820 * incorrectly programmed boards).
1824 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1826 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1831 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1833 /* Board configuration (legacy) */
1834 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1836 /* Unprivileged functions may not be able to read board cfg */
1843 encp->enc_board_type = board_type;
1845 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1846 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1850 * Firmware with support for *_FEC capability bits does not
1851 * report that the corresponding *_FEC_REQUESTED bits are supported.
1852 * Add them here so that drivers understand that they are supported.
1854 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1855 epp->ep_phy_cap_mask |=
1856 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1857 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1858 epp->ep_phy_cap_mask |=
1859 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1860 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1861 epp->ep_phy_cap_mask |=
1862 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1864 /* Obtain the default PHY advertised capabilities */
1865 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1867 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
1868 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
1870 /* Check capabilities of running datapath firmware */
1871 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1874 /* Get interrupt vector limits */
1875 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1876 if (EFX_PCI_FUNCTION_IS_PF(encp))
1879 /* Ignore error (cannot query vector limits from a VF). */
1883 encp->enc_intr_vec_base = base;
1884 encp->enc_intr_limit = nvec;
1887 * Get the current privilege mask. Note that this may be modified
1888 * dynamically, so this value is informational only. DO NOT use
1889 * the privilege mask to check for sufficient privileges, as that
1890 * can result in time-of-check/time-of-use bugs.
1892 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1894 encp->enc_privilege_mask = mask;
1899 EFSYS_PROBE(fail11);
1901 EFSYS_PROBE(fail10);
1919 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1924 static __checkReturn efx_rc_t
1925 ef10_set_workaround_bug26807(
1926 __in efx_nic_t *enp)
1928 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1933 * If the bug26807 workaround is enabled, then firmware has enabled
1934 * support for chained multicast filters. Firmware will reset (FLR)
1935 * functions which have filters in the hardware filter table when the
1936 * workaround is enabled/disabled.
1938 * We must recheck if the workaround is enabled after inserting the
1939 * first hardware filter, in case it has been changed since this check.
1941 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
1944 encp->enc_bug26807_workaround = B_TRUE;
1945 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
1947 * Other functions had installed filters before the
1948 * workaround was enabled, and they have been reset
1951 EFSYS_PROBE(bug26807_workaround_flr_done);
1952 /* FIXME: bump MC warm boot count ? */
1954 } else if (rc == EACCES) {
1956 * Unprivileged functions cannot enable the workaround in older
1959 encp->enc_bug26807_workaround = B_FALSE;
1960 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1961 encp->enc_bug26807_workaround = B_FALSE;
1969 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1974 static __checkReturn efx_rc_t
1976 __in efx_nic_t *enp)
1978 const efx_nic_ops_t *enop = enp->en_enop;
1979 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1982 if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0)
1986 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1987 * We only support the 14 byte prefix here.
1989 if (encp->enc_rx_prefix_size != 14) {
1994 encp->enc_clk_mult = 1; /* not used for EF10 */
1996 /* Alignment for WPTR updates */
1997 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1999 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
2000 /* No boundary crossing limits */
2001 encp->enc_tx_dma_desc_boundary = 0;
2004 * Maximum number of bytes into the frame the TCP header can start for
2005 * firmware assisted TSO to work.
2007 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
2010 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
2011 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
2012 * resources (allocated to this PCIe function), which is zero until
2013 * after we have allocated VIs.
2015 encp->enc_evq_limit = 1024;
2016 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
2017 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
2019 encp->enc_buftbl_limit = UINT32_MAX;
2021 if ((rc = ef10_set_workaround_bug26807(enp)) != 0)
2024 /* Get remaining controller-specific board config */
2025 if ((rc = enop->eno_board_cfg(enp)) != 0)
2038 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2043 __checkReturn efx_rc_t
2045 __in efx_nic_t *enp)
2047 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2048 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2051 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2053 /* Read and clear any assertion state */
2054 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2057 /* Exit the assertion handler */
2058 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2062 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
2065 if ((rc = ef10_nic_board_cfg(enp)) != 0)
2069 * Set default driver config limits (based on board config).
2071 * FIXME: For now allocate a fixed number of VIs which is likely to be
2072 * sufficient and small enough to allow multiple functions on the same
2075 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
2076 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
2078 /* The client driver must configure and enable PIO buffer support */
2079 edcp->edc_max_piobuf_count = 0;
2080 edcp->edc_pio_alloc_size = 0;
2082 #if EFSYS_OPT_MAC_STATS
2083 /* Wipe the MAC statistics */
2084 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
2088 #if EFSYS_OPT_LOOPBACK
2089 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
2093 #if EFSYS_OPT_MON_STATS
2094 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
2095 /* Unprivileged functions do not have access to sensors */
2101 encp->enc_features = enp->en_features;
2105 #if EFSYS_OPT_MON_STATS
2109 #if EFSYS_OPT_LOOPBACK
2113 #if EFSYS_OPT_MAC_STATS
2124 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2129 __checkReturn efx_rc_t
2130 ef10_nic_set_drv_limits(
2131 __inout efx_nic_t *enp,
2132 __in efx_drv_limits_t *edlp)
2134 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2135 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2136 uint32_t min_evq_count, max_evq_count;
2137 uint32_t min_rxq_count, max_rxq_count;
2138 uint32_t min_txq_count, max_txq_count;
2146 /* Get minimum required and maximum usable VI limits */
2147 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2148 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2149 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2151 edcp->edc_min_vi_count =
2152 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2154 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2155 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2156 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2158 edcp->edc_max_vi_count =
2159 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2162 * Check limits for sub-allocated piobuf blocks.
2163 * PIO is optional, so don't fail if the limits are incorrect.
2165 if ((encp->enc_piobuf_size == 0) ||
2166 (encp->enc_piobuf_limit == 0) ||
2167 (edlp->edl_min_pio_alloc_size == 0) ||
2168 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2170 edcp->edc_max_piobuf_count = 0;
2171 edcp->edc_pio_alloc_size = 0;
2173 uint32_t blk_size, blk_count, blks_per_piobuf;
2176 MAX(edlp->edl_min_pio_alloc_size,
2177 encp->enc_piobuf_min_alloc_size);
2179 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2180 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2182 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2184 /* A zero max pio alloc count means unlimited */
2185 if ((edlp->edl_max_pio_alloc_count > 0) &&
2186 (edlp->edl_max_pio_alloc_count < blk_count)) {
2187 blk_count = edlp->edl_max_pio_alloc_count;
2190 edcp->edc_pio_alloc_size = blk_size;
2191 edcp->edc_max_piobuf_count =
2192 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2198 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2204 __checkReturn efx_rc_t
2206 __in efx_nic_t *enp)
2209 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
2210 MC_CMD_ENTITY_RESET_OUT_LEN);
2213 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2214 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2216 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2219 req.emr_cmd = MC_CMD_ENTITY_RESET;
2220 req.emr_in_buf = payload;
2221 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
2222 req.emr_out_buf = payload;
2223 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
2225 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
2226 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
2228 efx_mcdi_execute(enp, &req);
2230 if (req.emr_rc != 0) {
2235 /* Clear RX/TX DMA queue errors */
2236 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2245 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2250 static __checkReturn efx_rc_t
2251 ef10_upstream_port_vadaptor_alloc(
2252 __in efx_nic_t *enp)
2259 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2260 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2261 * retry the request several times after waiting a while. The wait time
2262 * between retries starts small (10ms) and exponentially increases.
2263 * Total wait time is a little over two seconds. Retry logic in the
2264 * client driver may mean this whole loop is repeated if it continues to
2269 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2270 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2273 * Do not retry alloc for PF, or for other errors on
2279 /* VF startup before PF is ready. Retry allocation. */
2281 /* Too many attempts */
2285 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2286 EFSYS_SLEEP(delay_us);
2288 if (delay_us < 500000)
2297 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2302 __checkReturn efx_rc_t
2304 __in efx_nic_t *enp)
2306 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2307 uint32_t min_vi_count, max_vi_count;
2308 uint32_t vi_count, vi_base, vi_shift;
2310 uint32_t vi_window_size;
2312 boolean_t alloc_vadaptor = B_TRUE;
2314 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2316 /* Enable reporting of some events (e.g. link change) */
2317 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2320 /* Allocate (optional) on-chip PIO buffers */
2321 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2324 * For best performance, PIO writes should use a write-combined
2325 * (WC) memory mapping. Using a separate WC mapping for the PIO
2326 * aperture of each VI would be a burden to drivers (and not
2327 * possible if the host page size is >4Kbyte).
2329 * To avoid this we use a single uncached (UC) mapping for VI
2330 * register access, and a single WC mapping for extra VIs used
2333 * Each piobuf must be linked to a VI in the WC mapping, and to
2334 * each VI that is using a sub-allocated block from the piobuf.
2336 min_vi_count = edcp->edc_min_vi_count;
2338 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2340 /* Ensure that the previously attached driver's VIs are freed */
2341 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2345 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2346 * fails then retrying the request for fewer VI resources may succeed.
2349 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2350 &vi_base, &vi_count, &vi_shift)) != 0)
2353 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2355 if (vi_count < min_vi_count) {
2360 enp->en_arch.ef10.ena_vi_base = vi_base;
2361 enp->en_arch.ef10.ena_vi_count = vi_count;
2362 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2364 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2365 /* Not enough extra VIs to map piobufs */
2366 ef10_nic_free_piobufs(enp);
2369 enp->en_arch.ef10.ena_pio_write_vi_base =
2370 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2372 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2373 EFX_VI_WINDOW_SHIFT_INVALID);
2374 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2375 EFX_VI_WINDOW_SHIFT_64K);
2376 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2378 /* Save UC memory mapping details */
2379 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2380 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2381 enp->en_arch.ef10.ena_uc_mem_map_size =
2383 enp->en_arch.ef10.ena_pio_write_vi_base);
2385 enp->en_arch.ef10.ena_uc_mem_map_size =
2387 enp->en_arch.ef10.ena_vi_count);
2390 /* Save WC memory mapping details */
2391 enp->en_arch.ef10.ena_wc_mem_map_offset =
2392 enp->en_arch.ef10.ena_uc_mem_map_offset +
2393 enp->en_arch.ef10.ena_uc_mem_map_size;
2395 enp->en_arch.ef10.ena_wc_mem_map_size =
2397 enp->en_arch.ef10.ena_piobuf_count);
2399 /* Link piobufs to extra VIs in WC mapping */
2400 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2401 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2402 rc = efx_mcdi_link_piobuf(enp,
2403 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2404 enp->en_arch.ef10.ena_piobuf_handle[i]);
2411 * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs
2412 * during NIC initialization when vSwitch is created and vports are
2413 * allocated. Hence, skip vAdaptor allocation for EVB and update vport
2414 * id in NIC structure with the one allocated for PF.
2417 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2419 if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) {
2420 /* For EVB use vport allocated on vswitch */
2421 enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id;
2422 alloc_vadaptor = B_FALSE;
2425 if (alloc_vadaptor != B_FALSE) {
2426 /* Allocate a vAdaptor attached to our upstream vPort/pPort */
2427 if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0)
2430 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2443 ef10_nic_free_piobufs(enp);
2446 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2451 __checkReturn efx_rc_t
2452 ef10_nic_get_vi_pool(
2453 __in efx_nic_t *enp,
2454 __out uint32_t *vi_countp)
2456 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2459 * Report VIs that the client driver can use.
2460 * Do not include VIs used for PIO buffer writes.
2462 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2467 __checkReturn efx_rc_t
2468 ef10_nic_get_bar_region(
2469 __in efx_nic_t *enp,
2470 __in efx_nic_region_t region,
2471 __out uint32_t *offsetp,
2472 __out size_t *sizep)
2476 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2479 * TODO: Specify host memory mapping alignment and granularity
2480 * in efx_drv_limits_t so that they can be taken into account
2481 * when allocating extra VIs for PIO writes.
2485 /* UC mapped memory BAR region for VI registers */
2486 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2487 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2490 case EFX_REGION_PIO_WRITE_VI:
2491 /* WC mapped memory BAR region for piobuf writes */
2492 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2493 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2504 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2509 __checkReturn boolean_t
2510 ef10_nic_hw_unavailable(
2511 __in efx_nic_t *enp)
2515 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2518 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2519 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2525 ef10_nic_set_hw_unavailable(enp);
2531 ef10_nic_set_hw_unavailable(
2532 __in efx_nic_t *enp)
2534 EFSYS_PROBE(hw_unavail);
2535 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2541 __in efx_nic_t *enp)
2545 boolean_t do_vadaptor_free = B_TRUE;
2548 if (enp->en_vswitchp != NULL) {
2550 * For SR-IOV the vAdaptor is freed with the vswitch,
2551 * so do not free it here.
2553 do_vadaptor_free = B_FALSE;
2556 if (do_vadaptor_free != B_FALSE) {
2557 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2558 enp->en_vport_id = EVB_PORT_ID_NULL;
2561 /* Unlink piobufs from extra VIs in WC mapping */
2562 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2563 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2564 rc = efx_mcdi_unlink_piobuf(enp,
2565 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2571 ef10_nic_free_piobufs(enp);
2573 (void) efx_mcdi_free_vis(enp);
2574 enp->en_arch.ef10.ena_vi_count = 0;
2579 __in efx_nic_t *enp)
2581 #if EFSYS_OPT_MON_STATS
2582 mcdi_mon_cfg_free(enp);
2583 #endif /* EFSYS_OPT_MON_STATS */
2584 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2589 __checkReturn efx_rc_t
2590 ef10_nic_register_test(
2591 __in efx_nic_t *enp)
2596 _NOTE(ARGUNUSED(enp))
2597 _NOTE(CONSTANTCONDITION)
2607 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2612 #endif /* EFSYS_OPT_DIAG */
2614 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2616 __checkReturn efx_rc_t
2617 efx_mcdi_get_nic_global(
2618 __in efx_nic_t *enp,
2620 __out uint32_t *valuep)
2623 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2624 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2627 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2628 req.emr_in_buf = payload;
2629 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2630 req.emr_out_buf = payload;
2631 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2633 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2635 efx_mcdi_execute(enp, &req);
2637 if (req.emr_rc != 0) {
2642 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2647 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2654 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2659 __checkReturn efx_rc_t
2660 efx_mcdi_set_nic_global(
2661 __in efx_nic_t *enp,
2663 __in uint32_t value)
2666 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2669 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2670 req.emr_in_buf = payload;
2671 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2672 req.emr_out_buf = NULL;
2673 req.emr_out_length = 0;
2675 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2676 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2678 efx_mcdi_execute(enp, &req);
2680 if (req.emr_rc != 0) {
2688 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2693 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2695 #endif /* EFX_OPTS_EF10() */