1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
13 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
15 #include "ef10_tlv_layout.h"
17 __checkReturn efx_rc_t
18 efx_mcdi_get_port_assignment(
20 __out uint32_t *portp)
23 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
24 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN);
27 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
29 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
30 req.emr_in_buf = payload;
31 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
32 req.emr_out_buf = payload;
33 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
35 efx_mcdi_execute(enp, &req);
37 if (req.emr_rc != 0) {
42 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
47 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
54 EFSYS_PROBE1(fail1, efx_rc_t, rc);
59 __checkReturn efx_rc_t
60 efx_mcdi_get_port_modes(
62 __out uint32_t *modesp,
63 __out_opt uint32_t *current_modep,
64 __out_opt uint32_t *default_modep)
67 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PORT_MODES_IN_LEN,
68 MC_CMD_GET_PORT_MODES_OUT_LEN);
71 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
73 req.emr_cmd = MC_CMD_GET_PORT_MODES;
74 req.emr_in_buf = payload;
75 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
76 req.emr_out_buf = payload;
77 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
79 efx_mcdi_execute(enp, &req);
81 if (req.emr_rc != 0) {
87 * Require only Modes and DefaultMode fields, unless the current mode
88 * was requested (CurrentMode field was added for Medford).
90 if (req.emr_out_length_used <
91 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
95 if ((current_modep != NULL) && (req.emr_out_length_used <
96 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
101 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
103 if (current_modep != NULL) {
104 *current_modep = MCDI_OUT_DWORD(req,
105 GET_PORT_MODES_OUT_CURRENT_MODE);
108 if (default_modep != NULL) {
109 *default_modep = MCDI_OUT_DWORD(req,
110 GET_PORT_MODES_OUT_DEFAULT_MODE);
120 EFSYS_PROBE1(fail1, efx_rc_t, rc);
125 __checkReturn efx_rc_t
126 ef10_nic_get_port_mode_bandwidth(
128 __out uint32_t *bandwidth_mbpsp)
131 uint32_t current_mode;
132 efx_port_t *epp = &(enp->en_port);
134 uint32_t single_lane;
140 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
141 ¤t_mode, NULL)) != 0) {
142 /* No port mode info available. */
146 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_25000FDX))
151 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_50000FDX))
156 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_100000FDX))
161 switch (current_mode) {
162 case TLV_PORT_MODE_1x1_NA: /* mode 0 */
163 bandwidth = single_lane;
165 case TLV_PORT_MODE_1x2_NA: /* mode 10 */
166 case TLV_PORT_MODE_NA_1x2: /* mode 11 */
167 bandwidth = dual_lane;
169 case TLV_PORT_MODE_1x1_1x1: /* mode 2 */
170 bandwidth = single_lane + single_lane;
172 case TLV_PORT_MODE_4x1_NA: /* mode 4 */
173 case TLV_PORT_MODE_NA_4x1: /* mode 8 */
174 bandwidth = 4 * single_lane;
176 case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
177 bandwidth = (2 * single_lane) + (2 * single_lane);
179 case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
180 bandwidth = dual_lane + dual_lane;
182 case TLV_PORT_MODE_1x2_2x1: /* mode 17 */
183 case TLV_PORT_MODE_2x1_1x2: /* mode 18 */
184 bandwidth = dual_lane + (2 * single_lane);
186 /* Legacy Medford-only mode. Do not use (see bug63270) */
187 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */
188 bandwidth = 4 * single_lane;
190 case TLV_PORT_MODE_1x4_NA: /* mode 1 */
191 case TLV_PORT_MODE_NA_1x4: /* mode 22 */
192 bandwidth = quad_lane;
194 case TLV_PORT_MODE_2x2_NA: /* mode 13 */
195 case TLV_PORT_MODE_NA_2x2: /* mode 14 */
196 bandwidth = 2 * dual_lane;
198 case TLV_PORT_MODE_1x4_2x1: /* mode 6 */
199 case TLV_PORT_MODE_2x1_1x4: /* mode 7 */
200 bandwidth = quad_lane + (2 * single_lane);
202 case TLV_PORT_MODE_1x4_1x2: /* mode 15 */
203 case TLV_PORT_MODE_1x2_1x4: /* mode 16 */
204 bandwidth = quad_lane + dual_lane;
206 case TLV_PORT_MODE_1x4_1x4: /* mode 3 */
207 bandwidth = quad_lane + quad_lane;
214 *bandwidth_mbpsp = bandwidth;
221 EFSYS_PROBE1(fail1, efx_rc_t, rc);
226 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
230 __checkReturn efx_rc_t
231 efx_mcdi_vadaptor_alloc(
233 __in uint32_t port_id)
236 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_ALLOC_IN_LEN,
237 MC_CMD_VADAPTOR_ALLOC_OUT_LEN);
240 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
241 req.emr_in_buf = payload;
242 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
243 req.emr_out_buf = payload;
244 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
246 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
247 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
248 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
249 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
251 efx_mcdi_execute(enp, &req);
253 if (req.emr_rc != 0) {
261 EFSYS_PROBE1(fail1, efx_rc_t, rc);
266 __checkReturn efx_rc_t
267 efx_mcdi_vadaptor_free(
269 __in uint32_t port_id)
272 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_FREE_IN_LEN,
273 MC_CMD_VADAPTOR_FREE_OUT_LEN);
276 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
277 req.emr_in_buf = payload;
278 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
279 req.emr_out_buf = payload;
280 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
282 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
284 efx_mcdi_execute(enp, &req);
286 if (req.emr_rc != 0) {
294 EFSYS_PROBE1(fail1, efx_rc_t, rc);
299 #endif /* EFX_OPTS_EF10() */
301 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
303 __checkReturn efx_rc_t
304 efx_mcdi_get_mac_address_pf(
306 __out_ecount_opt(6) uint8_t mac_addrp[6])
309 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
310 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
313 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
315 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
316 req.emr_in_buf = payload;
317 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
318 req.emr_out_buf = payload;
319 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
321 efx_mcdi_execute(enp, &req);
323 if (req.emr_rc != 0) {
328 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
333 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
338 if (mac_addrp != NULL) {
341 addrp = MCDI_OUT2(req, uint8_t,
342 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
344 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
354 EFSYS_PROBE1(fail1, efx_rc_t, rc);
359 __checkReturn efx_rc_t
360 efx_mcdi_get_mac_address_vf(
362 __out_ecount_opt(6) uint8_t mac_addrp[6])
365 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
366 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
369 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
371 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
372 req.emr_in_buf = payload;
373 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
374 req.emr_out_buf = payload;
375 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
377 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
378 EVB_PORT_ID_ASSIGNED);
380 efx_mcdi_execute(enp, &req);
382 if (req.emr_rc != 0) {
387 if (req.emr_out_length_used <
388 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
393 if (MCDI_OUT_DWORD(req,
394 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
399 if (mac_addrp != NULL) {
402 addrp = MCDI_OUT2(req, uint8_t,
403 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
405 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
415 EFSYS_PROBE1(fail1, efx_rc_t, rc);
420 __checkReturn efx_rc_t
423 __out uint32_t *sys_freqp,
424 __out uint32_t *dpcpu_freqp)
427 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CLOCK_IN_LEN,
428 MC_CMD_GET_CLOCK_OUT_LEN);
431 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
433 req.emr_cmd = MC_CMD_GET_CLOCK;
434 req.emr_in_buf = payload;
435 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
436 req.emr_out_buf = payload;
437 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
439 efx_mcdi_execute(enp, &req);
441 if (req.emr_rc != 0) {
446 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
451 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
452 if (*sys_freqp == 0) {
456 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
457 if (*dpcpu_freqp == 0) {
471 EFSYS_PROBE1(fail1, efx_rc_t, rc);
476 __checkReturn efx_rc_t
477 efx_mcdi_get_rxdp_config(
479 __out uint32_t *end_paddingp)
482 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
483 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
484 uint32_t end_padding;
487 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
488 req.emr_in_buf = payload;
489 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
490 req.emr_out_buf = payload;
491 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
493 efx_mcdi_execute(enp, &req);
494 if (req.emr_rc != 0) {
499 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
500 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
501 /* RX DMA end padding is disabled */
504 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
505 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
506 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
509 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
512 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
521 *end_paddingp = end_padding;
528 EFSYS_PROBE1(fail1, efx_rc_t, rc);
533 __checkReturn efx_rc_t
534 efx_mcdi_get_vector_cfg(
536 __out_opt uint32_t *vec_basep,
537 __out_opt uint32_t *pf_nvecp,
538 __out_opt uint32_t *vf_nvecp)
541 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_VECTOR_CFG_IN_LEN,
542 MC_CMD_GET_VECTOR_CFG_OUT_LEN);
545 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
546 req.emr_in_buf = payload;
547 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
548 req.emr_out_buf = payload;
549 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
551 efx_mcdi_execute(enp, &req);
553 if (req.emr_rc != 0) {
558 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
563 if (vec_basep != NULL)
564 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
565 if (pf_nvecp != NULL)
566 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
567 if (vf_nvecp != NULL)
568 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
575 EFSYS_PROBE1(fail1, efx_rc_t, rc);
580 __checkReturn efx_rc_t
583 __in uint32_t min_vi_count,
584 __in uint32_t max_vi_count,
585 __out uint32_t *vi_basep,
586 __out uint32_t *vi_countp,
587 __out uint32_t *vi_shiftp)
590 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_VIS_IN_LEN,
591 MC_CMD_ALLOC_VIS_EXT_OUT_LEN);
594 if (vi_countp == NULL) {
599 req.emr_cmd = MC_CMD_ALLOC_VIS;
600 req.emr_in_buf = payload;
601 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
602 req.emr_out_buf = payload;
603 req.emr_out_length = MC_CMD_ALLOC_VIS_EXT_OUT_LEN;
605 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
606 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
608 efx_mcdi_execute(enp, &req);
610 if (req.emr_rc != 0) {
615 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
620 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
621 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
623 /* Report VI_SHIFT if available (always zero for Huntington) */
624 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
627 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
636 EFSYS_PROBE1(fail1, efx_rc_t, rc);
642 __checkReturn efx_rc_t
649 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
650 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
652 req.emr_cmd = MC_CMD_FREE_VIS;
653 req.emr_in_buf = NULL;
654 req.emr_in_length = 0;
655 req.emr_out_buf = NULL;
656 req.emr_out_length = 0;
658 efx_mcdi_execute_quiet(enp, &req);
660 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
661 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
669 EFSYS_PROBE1(fail1, efx_rc_t, rc);
674 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
678 static __checkReturn efx_rc_t
679 efx_mcdi_alloc_piobuf(
681 __out efx_piobuf_handle_t *handlep)
684 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ALLOC_PIOBUF_IN_LEN,
685 MC_CMD_ALLOC_PIOBUF_OUT_LEN);
688 if (handlep == NULL) {
693 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
694 req.emr_in_buf = payload;
695 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
696 req.emr_out_buf = payload;
697 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
699 efx_mcdi_execute_quiet(enp, &req);
701 if (req.emr_rc != 0) {
706 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
711 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
720 EFSYS_PROBE1(fail1, efx_rc_t, rc);
725 static __checkReturn efx_rc_t
726 efx_mcdi_free_piobuf(
728 __in efx_piobuf_handle_t handle)
731 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FREE_PIOBUF_IN_LEN,
732 MC_CMD_FREE_PIOBUF_OUT_LEN);
735 req.emr_cmd = MC_CMD_FREE_PIOBUF;
736 req.emr_in_buf = payload;
737 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
738 req.emr_out_buf = payload;
739 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
741 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
743 efx_mcdi_execute_quiet(enp, &req);
745 if (req.emr_rc != 0) {
753 EFSYS_PROBE1(fail1, efx_rc_t, rc);
758 static __checkReturn efx_rc_t
759 efx_mcdi_link_piobuf(
761 __in uint32_t vi_index,
762 __in efx_piobuf_handle_t handle)
765 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_LINK_PIOBUF_IN_LEN,
766 MC_CMD_LINK_PIOBUF_OUT_LEN);
769 req.emr_cmd = MC_CMD_LINK_PIOBUF;
770 req.emr_in_buf = payload;
771 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
772 req.emr_out_buf = payload;
773 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
775 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
776 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
778 efx_mcdi_execute(enp, &req);
780 if (req.emr_rc != 0) {
788 EFSYS_PROBE1(fail1, efx_rc_t, rc);
793 static __checkReturn efx_rc_t
794 efx_mcdi_unlink_piobuf(
796 __in uint32_t vi_index)
799 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_UNLINK_PIOBUF_IN_LEN,
800 MC_CMD_UNLINK_PIOBUF_OUT_LEN);
803 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
804 req.emr_in_buf = payload;
805 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
806 req.emr_out_buf = payload;
807 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
809 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
811 efx_mcdi_execute_quiet(enp, &req);
813 if (req.emr_rc != 0) {
821 EFSYS_PROBE1(fail1, efx_rc_t, rc);
827 ef10_nic_alloc_piobufs(
829 __in uint32_t max_piobuf_count)
831 efx_piobuf_handle_t *handlep;
834 EFSYS_ASSERT3U(max_piobuf_count, <=,
835 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
837 enp->en_arch.ef10.ena_piobuf_count = 0;
839 for (i = 0; i < max_piobuf_count; i++) {
840 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
842 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
845 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
846 enp->en_arch.ef10.ena_piobuf_count++;
852 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
853 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
855 (void) efx_mcdi_free_piobuf(enp, *handlep);
856 *handlep = EFX_PIOBUF_HANDLE_INVALID;
858 enp->en_arch.ef10.ena_piobuf_count = 0;
863 ef10_nic_free_piobufs(
866 efx_piobuf_handle_t *handlep;
869 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
870 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
872 (void) efx_mcdi_free_piobuf(enp, *handlep);
873 *handlep = EFX_PIOBUF_HANDLE_INVALID;
875 enp->en_arch.ef10.ena_piobuf_count = 0;
878 /* Sub-allocate a block from a piobuf */
879 __checkReturn efx_rc_t
881 __inout efx_nic_t *enp,
882 __out uint32_t *bufnump,
883 __out efx_piobuf_handle_t *handlep,
884 __out uint32_t *blknump,
885 __out uint32_t *offsetp,
888 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
889 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
890 uint32_t blk_per_buf;
894 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
895 EFSYS_ASSERT(bufnump);
896 EFSYS_ASSERT(handlep);
897 EFSYS_ASSERT(blknump);
898 EFSYS_ASSERT(offsetp);
901 if ((edcp->edc_pio_alloc_size == 0) ||
902 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
906 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
908 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
909 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
914 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
915 for (blk = 0; blk < blk_per_buf; blk++) {
916 if ((*map & (1u << blk)) == 0) {
926 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
929 *sizep = edcp->edc_pio_alloc_size;
930 *offsetp = blk * (*sizep);
937 EFSYS_PROBE1(fail1, efx_rc_t, rc);
942 /* Free a piobuf sub-allocated block */
943 __checkReturn efx_rc_t
945 __inout efx_nic_t *enp,
946 __in uint32_t bufnum,
947 __in uint32_t blknum)
952 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
953 (blknum >= (8 * sizeof (*map)))) {
958 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
959 if ((*map & (1u << blknum)) == 0) {
963 *map &= ~(1u << blknum);
970 EFSYS_PROBE1(fail1, efx_rc_t, rc);
975 __checkReturn efx_rc_t
977 __inout efx_nic_t *enp,
978 __in uint32_t vi_index,
979 __in efx_piobuf_handle_t handle)
981 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
984 __checkReturn efx_rc_t
986 __inout efx_nic_t *enp,
987 __in uint32_t vi_index)
989 return (efx_mcdi_unlink_piobuf(enp, vi_index));
992 #endif /* EFX_OPTS_EF10() */
994 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
996 static __checkReturn efx_rc_t
997 ef10_mcdi_get_pf_count(
999 __out uint32_t *pf_countp)
1002 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PF_COUNT_IN_LEN,
1003 MC_CMD_GET_PF_COUNT_OUT_LEN);
1006 req.emr_cmd = MC_CMD_GET_PF_COUNT;
1007 req.emr_in_buf = payload;
1008 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
1009 req.emr_out_buf = payload;
1010 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
1012 efx_mcdi_execute(enp, &req);
1014 if (req.emr_rc != 0) {
1019 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
1024 *pf_countp = *MCDI_OUT(req, uint8_t,
1025 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
1027 EFSYS_ASSERT(*pf_countp != 0);
1034 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1039 static __checkReturn efx_rc_t
1040 ef10_get_datapath_caps(
1041 __in efx_nic_t *enp)
1043 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1045 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_CAPABILITIES_IN_LEN,
1046 MC_CMD_GET_CAPABILITIES_V5_OUT_LEN);
1049 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
1050 req.emr_in_buf = payload;
1051 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
1052 req.emr_out_buf = payload;
1053 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V5_OUT_LEN;
1055 efx_mcdi_execute_quiet(enp, &req);
1057 if (req.emr_rc != 0) {
1062 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
1067 #define CAP_FLAGS1(_req, _flag) \
1068 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_OUT_FLAGS1) & \
1069 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN)))
1071 #define CAP_FLAGS2(_req, _flag) \
1072 (((_req).emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) && \
1073 (MCDI_OUT_DWORD((_req), GET_CAPABILITIES_V2_OUT_FLAGS2) & \
1074 (1u << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## _flag ## _LBN))))
1076 /* Check if RXDP firmware inserts 14 byte prefix */
1077 if (CAP_FLAGS1(req, RX_PREFIX_LEN_14))
1078 encp->enc_rx_prefix_size = 14;
1080 encp->enc_rx_prefix_size = 0;
1082 #if EFSYS_OPT_RX_SCALE
1083 /* Check if the firmware supports additional RSS modes */
1084 if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES))
1085 encp->enc_rx_scale_additional_modes_supported = B_TRUE;
1087 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
1088 #endif /* EFSYS_OPT_RX_SCALE */
1090 /* Check if the firmware supports TSO */
1091 if (CAP_FLAGS1(req, TX_TSO))
1092 encp->enc_fw_assisted_tso_enabled = B_TRUE;
1094 encp->enc_fw_assisted_tso_enabled = B_FALSE;
1096 /* Check if the firmware supports FATSOv2 */
1097 if (CAP_FLAGS2(req, TX_TSO_V2)) {
1098 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
1099 encp->enc_fw_assisted_tso_v2_n_contexts = MCDI_OUT_WORD(req,
1100 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
1102 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
1103 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
1106 /* Check if the firmware supports FATSOv2 encap */
1107 if (CAP_FLAGS2(req, TX_TSO_V2_ENCAP))
1108 encp->enc_fw_assisted_tso_v2_encap_enabled = B_TRUE;
1110 encp->enc_fw_assisted_tso_v2_encap_enabled = B_FALSE;
1112 /* Check if TSOv3 is supported */
1113 if (CAP_FLAGS2(req, TX_TSO_V3))
1114 encp->enc_tso_v3_enabled = B_TRUE;
1116 encp->enc_tso_v3_enabled = B_FALSE;
1118 /* Check if the firmware has vadapter/vport/vswitch support */
1119 if (CAP_FLAGS1(req, EVB))
1120 encp->enc_datapath_cap_evb = B_TRUE;
1122 encp->enc_datapath_cap_evb = B_FALSE;
1124 /* Check if the firmware supports vport reconfiguration */
1125 if (CAP_FLAGS1(req, VPORT_RECONFIGURE))
1126 encp->enc_vport_reconfigure_supported = B_TRUE;
1128 encp->enc_vport_reconfigure_supported = B_FALSE;
1130 /* Check if the firmware supports VLAN insertion */
1131 if (CAP_FLAGS1(req, TX_VLAN_INSERTION))
1132 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
1134 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
1136 /* Check if the firmware supports RX event batching */
1137 if (CAP_FLAGS1(req, RX_BATCHING))
1138 encp->enc_rx_batching_enabled = B_TRUE;
1140 encp->enc_rx_batching_enabled = B_FALSE;
1143 * Even if batching isn't reported as supported, we may still get
1144 * batched events (see bug61153).
1146 encp->enc_rx_batch_max = 16;
1148 /* Check if the firmware supports disabling scatter on RXQs */
1149 if (CAP_FLAGS1(req, RX_DISABLE_SCATTER))
1150 encp->enc_rx_disable_scatter_supported = B_TRUE;
1152 encp->enc_rx_disable_scatter_supported = B_FALSE;
1154 /* Check if the firmware supports packed stream mode */
1155 if (CAP_FLAGS1(req, RX_PACKED_STREAM))
1156 encp->enc_rx_packed_stream_supported = B_TRUE;
1158 encp->enc_rx_packed_stream_supported = B_FALSE;
1161 * Check if the firmware supports configurable buffer sizes
1162 * for packed stream mode (otherwise buffer size is 1Mbyte)
1164 if (CAP_FLAGS1(req, RX_PACKED_STREAM_VAR_BUFFERS))
1165 encp->enc_rx_var_packed_stream_supported = B_TRUE;
1167 encp->enc_rx_var_packed_stream_supported = B_FALSE;
1169 /* Check if the firmware supports equal stride super-buffer mode */
1170 if (CAP_FLAGS2(req, EQUAL_STRIDE_SUPER_BUFFER))
1171 encp->enc_rx_es_super_buffer_supported = B_TRUE;
1173 encp->enc_rx_es_super_buffer_supported = B_FALSE;
1175 /* Check if the firmware supports FW subvariant w/o Tx checksumming */
1176 if (CAP_FLAGS2(req, FW_SUBVARIANT_NO_TX_CSUM))
1177 encp->enc_fw_subvariant_no_tx_csum_supported = B_TRUE;
1179 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
1181 /* Check if the firmware supports set mac with running filters */
1182 if (CAP_FLAGS1(req, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED))
1183 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
1185 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
1188 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1189 * specifying which parameters to configure.
1191 if (CAP_FLAGS1(req, SET_MAC_ENHANCED))
1192 encp->enc_enhanced_set_mac_supported = B_TRUE;
1194 encp->enc_enhanced_set_mac_supported = B_FALSE;
1197 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1198 * us to let the firmware choose the settings to use on an EVQ.
1200 if (CAP_FLAGS2(req, INIT_EVQ_V2))
1201 encp->enc_init_evq_v2_supported = B_TRUE;
1203 encp->enc_init_evq_v2_supported = B_FALSE;
1206 * Check if the NO_CONT_EV mode for RX events is supported.
1208 if (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV))
1209 encp->enc_no_cont_ev_mode_supported = B_TRUE;
1211 encp->enc_no_cont_ev_mode_supported = B_FALSE;
1214 * Check if buffer size may and must be specified on INIT_RXQ.
1215 * It may be always specified to efx_rx_qcreate(), but will be
1216 * just kept libefx internal if MCDI does not support it.
1218 if (CAP_FLAGS2(req, INIT_RXQ_WITH_BUFFER_SIZE))
1219 encp->enc_init_rxq_with_buffer_size = B_TRUE;
1221 encp->enc_init_rxq_with_buffer_size = B_FALSE;
1224 * Check if firmware-verified NVRAM updates must be used.
1226 * The firmware trusted installer requires all NVRAM updates to use
1227 * version 2 of MC_CMD_NVRAM_UPDATE_START (to enable verified update)
1228 * and version 2 of MC_CMD_NVRAM_UPDATE_FINISH (to verify the updated
1229 * partition and report the result).
1231 if (CAP_FLAGS2(req, NVRAM_UPDATE_REPORT_VERIFY_RESULT))
1232 encp->enc_nvram_update_verify_result_supported = B_TRUE;
1234 encp->enc_nvram_update_verify_result_supported = B_FALSE;
1236 if (CAP_FLAGS2(req, NVRAM_UPDATE_POLL_VERIFY_RESULT))
1237 encp->enc_nvram_update_poll_verify_result_supported = B_TRUE;
1239 encp->enc_nvram_update_poll_verify_result_supported = B_FALSE;
1242 * Check if firmware update via the BUNDLE partition is supported
1244 if (CAP_FLAGS2(req, BUNDLE_UPDATE))
1245 encp->enc_nvram_bundle_update_supported = B_TRUE;
1247 encp->enc_nvram_bundle_update_supported = B_FALSE;
1250 * Check if firmware provides packet memory and Rx datapath
1253 if (CAP_FLAGS1(req, PM_AND_RXDP_COUNTERS))
1254 encp->enc_pm_and_rxdp_counters = B_TRUE;
1256 encp->enc_pm_and_rxdp_counters = B_FALSE;
1259 * Check if the 40G MAC hardware is capable of reporting
1260 * statistics for Tx size bins.
1262 if (CAP_FLAGS2(req, MAC_STATS_40G_TX_SIZE_BINS))
1263 encp->enc_mac_stats_40g_tx_size_bins = B_TRUE;
1265 encp->enc_mac_stats_40g_tx_size_bins = B_FALSE;
1268 * Check if firmware supports VXLAN and NVGRE tunnels.
1269 * The capability indicates Geneve protocol support as well.
1271 if (CAP_FLAGS1(req, VXLAN_NVGRE)) {
1272 encp->enc_tunnel_encapsulations_supported =
1273 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
1274 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
1275 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
1277 EFX_STATIC_ASSERT(EFX_TUNNEL_MAXNENTRIES ==
1278 MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MAXNUM);
1279 encp->enc_tunnel_config_udp_entries_max =
1280 EFX_TUNNEL_MAXNENTRIES;
1282 encp->enc_tunnel_config_udp_entries_max = 0;
1286 * Check if firmware reports the VI window mode.
1287 * Medford2 has a variable VI window size (8K, 16K or 64K).
1288 * Medford and Huntington have a fixed 8K VI window size.
1290 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V3_OUT_LEN) {
1292 MCDI_OUT_BYTE(req, GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
1295 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K:
1296 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1298 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K:
1299 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_16K;
1301 case MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K:
1302 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_64K;
1305 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1308 } else if ((enp->en_family == EFX_FAMILY_HUNTINGTON) ||
1309 (enp->en_family == EFX_FAMILY_MEDFORD)) {
1310 /* Huntington and Medford have fixed 8K window size */
1311 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
1313 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_INVALID;
1316 /* Check if firmware supports extended MAC stats. */
1317 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
1318 /* Extended stats buffer supported */
1319 encp->enc_mac_stats_nstats = MCDI_OUT_WORD(req,
1320 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
1322 /* Use Siena-compatible legacy MAC stats */
1323 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
1326 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V2)
1327 encp->enc_fec_counters = B_TRUE;
1329 encp->enc_fec_counters = B_FALSE;
1331 /* Check if the firmware provides head-of-line blocking counters */
1332 if (CAP_FLAGS2(req, RXDP_HLB_IDLE))
1333 encp->enc_hlb_counters = B_TRUE;
1335 encp->enc_hlb_counters = B_FALSE;
1337 #if EFSYS_OPT_RX_SCALE
1338 if (CAP_FLAGS1(req, RX_RSS_LIMITED)) {
1339 /* Only one exclusive RSS context is available per port. */
1340 encp->enc_rx_scale_max_exclusive_contexts = 1;
1342 switch (enp->en_family) {
1343 case EFX_FAMILY_MEDFORD2:
1344 encp->enc_rx_scale_hash_alg_mask =
1345 (1U << EFX_RX_HASHALG_TOEPLITZ);
1348 case EFX_FAMILY_MEDFORD:
1349 case EFX_FAMILY_HUNTINGTON:
1351 * Packed stream firmware variant maintains a
1352 * non-standard algorithm for hash computation.
1353 * It implies explicit XORing together
1354 * source + destination IP addresses (or last
1355 * four bytes in the case of IPv6) and using the
1356 * resulting value as the input to a Toeplitz hash.
1358 encp->enc_rx_scale_hash_alg_mask =
1359 (1U << EFX_RX_HASHALG_PACKED_STREAM);
1367 /* Port numbers cannot contribute to the hash value */
1368 encp->enc_rx_scale_l4_hash_supported = B_FALSE;
1371 * Maximum number of exclusive RSS contexts.
1372 * EF10 hardware supports 64 in total, but 6 are reserved
1373 * for shared contexts. They are a global resource so
1374 * not all may be available.
1376 encp->enc_rx_scale_max_exclusive_contexts = 64 - 6;
1378 encp->enc_rx_scale_hash_alg_mask =
1379 (1U << EFX_RX_HASHALG_TOEPLITZ);
1382 * It is possible to use port numbers as
1383 * the input data for hash computation.
1385 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
1387 #endif /* EFSYS_OPT_RX_SCALE */
1389 /* Check if the firmware supports "FLAG" and "MARK" filter actions */
1390 if (CAP_FLAGS2(req, FILTER_ACTION_FLAG))
1391 encp->enc_filter_action_flag_supported = B_TRUE;
1393 encp->enc_filter_action_flag_supported = B_FALSE;
1395 if (CAP_FLAGS2(req, FILTER_ACTION_MARK))
1396 encp->enc_filter_action_mark_supported = B_TRUE;
1398 encp->enc_filter_action_mark_supported = B_FALSE;
1400 /* Get maximum supported value for "MARK" filter action */
1401 if (req.emr_out_length_used >= MC_CMD_GET_CAPABILITIES_V5_OUT_LEN)
1402 encp->enc_filter_action_mark_max = MCDI_OUT_DWORD(req,
1403 GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX);
1405 encp->enc_filter_action_mark_max = 0;
1412 #if EFSYS_OPT_RX_SCALE
1415 #endif /* EFSYS_OPT_RX_SCALE */
1419 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1425 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1426 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1427 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1428 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1429 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1430 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1431 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1432 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1433 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1434 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1435 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1436 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1438 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1441 __checkReturn efx_rc_t
1442 ef10_get_privilege_mask(
1443 __in efx_nic_t *enp,
1444 __out uint32_t *maskp)
1446 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1450 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1455 /* Fallback for old firmware without privilege mask support */
1456 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1457 /* Assume PF has admin privilege */
1458 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1460 /* VF is always unprivileged by default */
1461 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1470 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1476 #define EFX_EXT_PORT_MAX 4
1477 #define EFX_EXT_PORT_NA 0xFF
1480 * Table of mapping schemes from port number to external number.
1482 * Each port number ultimately corresponds to a connector: either as part of
1483 * a cable assembly attached to a module inserted in an SFP+/QSFP+ cage on
1484 * the board, or fixed to the board (e.g. 10GBASE-T magjack on SFN5121T
1485 * "Salina"). In general:
1487 * Port number (0-based)
1489 * port mapping (n:1)
1492 * External port number (1-based)
1494 * fixed (1:1) or cable assembly (1:m)
1499 * The external numbering refers to the cages or magjacks on the board,
1500 * as visibly annotated on the board or back panel. This table describes
1501 * how to determine which external cage/magjack corresponds to the port
1502 * numbers used by the driver.
1504 * The count of consecutive port numbers that map to each external number,
1505 * is determined by the chip family and the current port mode.
1507 * For the Huntington family, the current port mode cannot be discovered,
1508 * but a single mapping is used by all modes for a given chip variant,
1509 * so the mapping used is instead the last match in the table to the full
1510 * set of port modes to which the NIC can be configured. Therefore the
1511 * ordering of entries in the mapping table is significant.
1513 static struct ef10_external_port_map_s {
1514 efx_family_t family;
1515 uint32_t modes_mask;
1516 uint8_t base_port[EFX_EXT_PORT_MAX];
1517 } __ef10_external_port_mappings[] = {
1519 * Modes used by Huntington family controllers where each port
1520 * number maps to a separate cage.
1521 * SFN7x22F (Torino):
1531 EFX_FAMILY_HUNTINGTON,
1532 (1U << TLV_PORT_MODE_10G) | /* mode 0 */
1533 (1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
1534 (1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1538 * Modes which for Huntington identify a chip variant where 2
1539 * adjacent port numbers map to each cage.
1547 EFX_FAMILY_HUNTINGTON,
1548 (1U << TLV_PORT_MODE_40G) | /* mode 1 */
1549 (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
1550 (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
1551 (1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
1552 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1555 * Modes that on Medford allocate each port number to a separate
1564 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1565 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1566 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1570 * Modes that on Medford allocate 2 adjacent port numbers to each
1579 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1580 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */
1581 (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */
1582 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1583 /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
1584 (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
1585 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1588 * Modes that on Medford allocate 4 adjacent port numbers to
1597 /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
1598 (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
1599 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1602 * Modes that on Medford allocate 4 adjacent port numbers to
1611 (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */
1612 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1615 * Modes that on Medford2 allocate each port number to a separate
1623 EFX_FAMILY_MEDFORD2,
1624 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1625 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1626 (1U << TLV_PORT_MODE_1x1_1x1) | /* mode 2 */
1627 (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */
1628 (1U << TLV_PORT_MODE_1x2_NA) | /* mode 10 */
1629 (1U << TLV_PORT_MODE_1x2_1x2) | /* mode 12 */
1630 (1U << TLV_PORT_MODE_1x4_1x2) | /* mode 15 */
1631 (1U << TLV_PORT_MODE_1x2_1x4), /* mode 16 */
1635 * Modes that on Medford2 allocate 1 port to cage 1 and the rest
1642 EFX_FAMILY_MEDFORD2,
1643 (1U << TLV_PORT_MODE_1x2_2x1) | /* mode 17 */
1644 (1U << TLV_PORT_MODE_1x4_2x1), /* mode 6 */
1645 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1648 * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1
1649 * and the rest to cage 2.
1656 EFX_FAMILY_MEDFORD2,
1657 (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 4 */
1658 (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */
1659 (1U << TLV_PORT_MODE_2x2_NA) | /* mode 13 */
1660 (1U << TLV_PORT_MODE_2x1_1x2), /* mode 18 */
1661 { 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1664 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1672 EFX_FAMILY_MEDFORD2,
1673 (1U << TLV_PORT_MODE_4x1_NA), /* mode 5 */
1674 { 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1677 * Modes that on Medford2 allocate up to 4 adjacent port numbers
1685 EFX_FAMILY_MEDFORD2,
1686 (1U << TLV_PORT_MODE_NA_4x1) | /* mode 8 */
1687 (1U << TLV_PORT_MODE_NA_1x2) | /* mode 11 */
1688 (1U << TLV_PORT_MODE_NA_2x2), /* mode 14 */
1689 { EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1692 * Modes that on Riverhead allocate each port number to a separate
1698 EFX_FAMILY_RIVERHEAD,
1699 (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */
1700 (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */
1701 (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */
1702 { 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
1706 static __checkReturn efx_rc_t
1707 ef10_external_port_mapping(
1708 __in efx_nic_t *enp,
1710 __out uint8_t *external_portp)
1714 uint32_t port_modes;
1717 struct ef10_external_port_map_s *mapp = NULL;
1718 int ext_index = port; /* Default 1-1 mapping */
1720 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,
1723 * No current port mode information (i.e. Huntington)
1724 * - infer mapping from available modes
1726 if ((rc = efx_mcdi_get_port_modes(enp,
1727 &port_modes, NULL, NULL)) != 0) {
1729 * No port mode information available
1730 * - use default mapping
1735 /* Only need to scan the current mode */
1736 port_modes = 1 << current;
1740 * Infer the internal port -> external number mapping from
1741 * the possible port modes for this NIC.
1743 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1744 struct ef10_external_port_map_s *eepmp =
1745 &__ef10_external_port_mappings[i];
1746 if (eepmp->family != enp->en_family)
1748 matches = (eepmp->modes_mask & port_modes);
1751 * Some modes match. For some Huntington boards
1752 * there will be multiple matches. The mapping on the
1753 * last match is used.
1756 port_modes &= ~matches;
1760 if (port_modes != 0) {
1761 /* Some advertised modes are not supported */
1769 * External ports are assigned a sequence of consecutive
1770 * port numbers, so find the one with the closest base_port.
1772 uint32_t delta = EFX_EXT_PORT_NA;
1774 for (i = 0; i < EFX_EXT_PORT_MAX; i++) {
1775 uint32_t base = mapp->base_port[i];
1776 if ((base != EFX_EXT_PORT_NA) && (base <= port)) {
1777 if ((port - base) < delta) {
1778 delta = (port - base);
1784 *external_portp = (uint8_t)(ext_index + 1);
1789 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1794 __checkReturn efx_rc_t
1795 efx_mcdi_nic_board_cfg(
1796 __in efx_nic_t *enp)
1798 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1799 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1800 ef10_link_state_t els;
1801 efx_port_t *epp = &(enp->en_port);
1802 uint32_t board_type = 0;
1803 uint32_t base, nvec;
1808 uint8_t mac_addr[6] = { 0 };
1811 /* Get the (zero-based) MCDI port number */
1812 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1815 /* EFX MCDI interface uses one-based port numbers */
1816 emip->emi_port = port + 1;
1818 encp->enc_assigned_port = port;
1820 if ((rc = ef10_external_port_mapping(enp, port,
1821 &encp->enc_external_port)) != 0)
1825 * Get PCIe function number from firmware (used for
1826 * per-function privilege and dynamic config info).
1827 * - PCIe PF: pf = PF number, vf = 0xffff.
1828 * - PCIe VF: pf = parent PF, vf = VF number.
1830 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1836 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1839 /* MAC address for this function */
1840 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1841 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1842 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
1844 * Disable static config checking, ONLY for manufacturing test
1845 * and setup at the factory, to allow the static config to be
1848 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1849 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1851 * If the static config does not include a global MAC
1852 * address pool then the board may return a locally
1853 * administered MAC address (this should only happen on
1854 * incorrectly programmed boards).
1858 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
1860 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1865 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1867 /* Board configuration (legacy) */
1868 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1870 /* Unprivileged functions may not be able to read board cfg */
1877 encp->enc_board_type = board_type;
1879 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1880 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1884 * Firmware with support for *_FEC capability bits does not
1885 * report that the corresponding *_FEC_REQUESTED bits are supported.
1886 * Add them here so that drivers understand that they are supported.
1888 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC))
1889 epp->ep_phy_cap_mask |=
1890 (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED);
1891 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC))
1892 epp->ep_phy_cap_mask |=
1893 (1u << EFX_PHY_CAP_RS_FEC_REQUESTED);
1894 if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC))
1895 epp->ep_phy_cap_mask |=
1896 (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
1898 /* Obtain the default PHY advertised capabilities */
1899 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
1901 epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
1902 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
1904 /* Check capabilities of running datapath firmware */
1905 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1908 /* Get interrupt vector limits */
1909 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1910 if (EFX_PCI_FUNCTION_IS_PF(encp))
1913 /* Ignore error (cannot query vector limits from a VF). */
1917 encp->enc_intr_vec_base = base;
1918 encp->enc_intr_limit = nvec;
1921 * Get the current privilege mask. Note that this may be modified
1922 * dynamically, so this value is informational only. DO NOT use
1923 * the privilege mask to check for sufficient privileges, as that
1924 * can result in time-of-check/time-of-use bugs.
1926 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
1928 encp->enc_privilege_mask = mask;
1933 EFSYS_PROBE(fail11);
1935 EFSYS_PROBE(fail10);
1953 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1958 __checkReturn efx_rc_t
1959 efx_mcdi_entity_reset(
1960 __in efx_nic_t *enp)
1963 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_ENTITY_RESET_IN_LEN,
1964 MC_CMD_ENTITY_RESET_OUT_LEN);
1967 req.emr_cmd = MC_CMD_ENTITY_RESET;
1968 req.emr_in_buf = payload;
1969 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1970 req.emr_out_buf = payload;
1971 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1973 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1974 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1976 efx_mcdi_execute(enp, &req);
1978 if (req.emr_rc != 0) {
1986 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1991 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1995 static __checkReturn efx_rc_t
1996 ef10_set_workaround_bug26807(
1997 __in efx_nic_t *enp)
1999 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2004 * If the bug26807 workaround is enabled, then firmware has enabled
2005 * support for chained multicast filters. Firmware will reset (FLR)
2006 * functions which have filters in the hardware filter table when the
2007 * workaround is enabled/disabled.
2009 * We must recheck if the workaround is enabled after inserting the
2010 * first hardware filter, in case it has been changed since this check.
2012 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
2015 encp->enc_bug26807_workaround = B_TRUE;
2016 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
2018 * Other functions had installed filters before the
2019 * workaround was enabled, and they have been reset
2022 EFSYS_PROBE(bug26807_workaround_flr_done);
2023 /* FIXME: bump MC warm boot count ? */
2025 } else if (rc == EACCES) {
2027 * Unprivileged functions cannot enable the workaround in older
2030 encp->enc_bug26807_workaround = B_FALSE;
2031 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
2032 encp->enc_bug26807_workaround = B_FALSE;
2040 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2045 static __checkReturn efx_rc_t
2047 __in efx_nic_t *enp)
2049 const efx_nic_ops_t *enop = enp->en_enop;
2050 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2053 if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0)
2057 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
2058 * We only support the 14 byte prefix here.
2060 if (encp->enc_rx_prefix_size != 14) {
2065 encp->enc_clk_mult = 1; /* not used for EF10 */
2067 /* Alignment for WPTR updates */
2068 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
2070 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
2071 /* No boundary crossing limits */
2072 encp->enc_tx_dma_desc_boundary = 0;
2075 * Maximum number of bytes into the frame the TCP header can start for
2076 * firmware assisted TSO to work.
2078 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
2080 /* EF10 TSO engine demands that packet header be contiguous. */
2081 encp->enc_tx_tso_max_header_ndescs = 1;
2083 /* The overall TSO header length is not limited. */
2084 encp->enc_tx_tso_max_header_length = UINT32_MAX;
2087 * There are no specific limitations on the number of
2088 * TSO payload descriptors.
2090 encp->enc_tx_tso_max_payload_ndescs = UINT32_MAX;
2092 /* TSO superframe payload length is not limited. */
2093 encp->enc_tx_tso_max_payload_length = UINT32_MAX;
2096 * Limitation on the maximum number of outgoing packets per
2097 * TSO transaction described in SF-108452-SW.
2099 encp->enc_tx_tso_max_nframes = 32767;
2102 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
2103 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
2104 * resources (allocated to this PCIe function), which is zero until
2105 * after we have allocated VIs.
2107 encp->enc_evq_limit = 1024;
2108 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
2109 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
2111 encp->enc_buftbl_limit = UINT32_MAX;
2113 if ((rc = ef10_set_workaround_bug26807(enp)) != 0)
2116 /* Get remaining controller-specific board config */
2117 if ((rc = enop->eno_board_cfg(enp)) != 0)
2130 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2135 __checkReturn efx_rc_t
2137 __in efx_nic_t *enp)
2139 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2140 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2143 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2145 /* Read and clear any assertion state */
2146 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2149 /* Exit the assertion handler */
2150 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2154 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
2157 if ((rc = ef10_nic_board_cfg(enp)) != 0)
2161 * Set default driver config limits (based on board config).
2163 * FIXME: For now allocate a fixed number of VIs which is likely to be
2164 * sufficient and small enough to allow multiple functions on the same
2167 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
2168 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
2170 /* The client driver must configure and enable PIO buffer support */
2171 edcp->edc_max_piobuf_count = 0;
2172 edcp->edc_pio_alloc_size = 0;
2174 #if EFSYS_OPT_MAC_STATS
2175 /* Wipe the MAC statistics */
2176 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
2180 #if EFSYS_OPT_LOOPBACK
2181 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
2185 #if EFSYS_OPT_MON_STATS
2186 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
2187 /* Unprivileged functions do not have access to sensors */
2195 #if EFSYS_OPT_MON_STATS
2199 #if EFSYS_OPT_LOOPBACK
2203 #if EFSYS_OPT_MAC_STATS
2214 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2219 __checkReturn efx_rc_t
2220 ef10_nic_set_drv_limits(
2221 __inout efx_nic_t *enp,
2222 __in efx_drv_limits_t *edlp)
2224 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
2225 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2226 uint32_t min_evq_count, max_evq_count;
2227 uint32_t min_rxq_count, max_rxq_count;
2228 uint32_t min_txq_count, max_txq_count;
2236 /* Get minimum required and maximum usable VI limits */
2237 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
2238 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
2239 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
2241 edcp->edc_min_vi_count =
2242 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
2244 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
2245 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
2246 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
2248 edcp->edc_max_vi_count =
2249 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
2252 * Check limits for sub-allocated piobuf blocks.
2253 * PIO is optional, so don't fail if the limits are incorrect.
2255 if ((encp->enc_piobuf_size == 0) ||
2256 (encp->enc_piobuf_limit == 0) ||
2257 (edlp->edl_min_pio_alloc_size == 0) ||
2258 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
2260 edcp->edc_max_piobuf_count = 0;
2261 edcp->edc_pio_alloc_size = 0;
2263 uint32_t blk_size, blk_count, blks_per_piobuf;
2266 MAX(edlp->edl_min_pio_alloc_size,
2267 encp->enc_piobuf_min_alloc_size);
2269 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
2270 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
2272 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
2274 /* A zero max pio alloc count means unlimited */
2275 if ((edlp->edl_max_pio_alloc_count > 0) &&
2276 (edlp->edl_max_pio_alloc_count < blk_count)) {
2277 blk_count = edlp->edl_max_pio_alloc_count;
2280 edcp->edc_pio_alloc_size = blk_size;
2281 edcp->edc_max_piobuf_count =
2282 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
2288 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2294 __checkReturn efx_rc_t
2296 __in efx_nic_t *enp)
2300 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
2301 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
2303 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
2306 if ((rc = efx_mcdi_entity_reset(enp)) != 0)
2309 /* Clear RX/TX DMA queue errors */
2310 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
2319 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2324 static __checkReturn efx_rc_t
2325 ef10_upstream_port_vadaptor_alloc(
2326 __in efx_nic_t *enp)
2333 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
2334 * driver has yet to bring up the EVB port. See bug 56147. In this case,
2335 * retry the request several times after waiting a while. The wait time
2336 * between retries starts small (10ms) and exponentially increases.
2337 * Total wait time is a little over two seconds. Retry logic in the
2338 * client driver may mean this whole loop is repeated if it continues to
2343 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
2344 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
2347 * Do not retry alloc for PF, or for other errors on
2353 /* VF startup before PF is ready. Retry allocation. */
2355 /* Too many attempts */
2359 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
2360 EFSYS_SLEEP(delay_us);
2362 if (delay_us < 500000)
2371 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2376 __checkReturn efx_rc_t
2378 __in efx_nic_t *enp)
2380 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
2381 uint32_t min_vi_count, max_vi_count;
2382 uint32_t vi_count, vi_base, vi_shift;
2384 uint32_t vi_window_size;
2386 boolean_t alloc_vadaptor = B_TRUE;
2388 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2390 /* Enable reporting of some events (e.g. link change) */
2391 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
2394 /* Allocate (optional) on-chip PIO buffers */
2395 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
2398 * For best performance, PIO writes should use a write-combined
2399 * (WC) memory mapping. Using a separate WC mapping for the PIO
2400 * aperture of each VI would be a burden to drivers (and not
2401 * possible if the host page size is >4Kbyte).
2403 * To avoid this we use a single uncached (UC) mapping for VI
2404 * register access, and a single WC mapping for extra VIs used
2407 * Each piobuf must be linked to a VI in the WC mapping, and to
2408 * each VI that is using a sub-allocated block from the piobuf.
2410 min_vi_count = edcp->edc_min_vi_count;
2412 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
2414 /* Ensure that the previously attached driver's VIs are freed */
2415 if ((rc = efx_mcdi_free_vis(enp)) != 0)
2419 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
2420 * fails then retrying the request for fewer VI resources may succeed.
2423 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
2424 &vi_base, &vi_count, &vi_shift)) != 0)
2427 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
2429 if (vi_count < min_vi_count) {
2434 enp->en_arch.ef10.ena_vi_base = vi_base;
2435 enp->en_arch.ef10.ena_vi_count = vi_count;
2436 enp->en_arch.ef10.ena_vi_shift = vi_shift;
2438 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
2439 /* Not enough extra VIs to map piobufs */
2440 ef10_nic_free_piobufs(enp);
2443 enp->en_arch.ef10.ena_pio_write_vi_base =
2444 vi_count - enp->en_arch.ef10.ena_piobuf_count;
2446 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
2447 EFX_VI_WINDOW_SHIFT_INVALID);
2448 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
2449 EFX_VI_WINDOW_SHIFT_64K);
2450 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
2452 /* Save UC memory mapping details */
2453 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
2454 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2455 enp->en_arch.ef10.ena_uc_mem_map_size =
2457 enp->en_arch.ef10.ena_pio_write_vi_base);
2459 enp->en_arch.ef10.ena_uc_mem_map_size =
2461 enp->en_arch.ef10.ena_vi_count);
2464 /* Save WC memory mapping details */
2465 enp->en_arch.ef10.ena_wc_mem_map_offset =
2466 enp->en_arch.ef10.ena_uc_mem_map_offset +
2467 enp->en_arch.ef10.ena_uc_mem_map_size;
2469 enp->en_arch.ef10.ena_wc_mem_map_size =
2471 enp->en_arch.ef10.ena_piobuf_count);
2473 /* Link piobufs to extra VIs in WC mapping */
2474 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2475 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2476 rc = efx_mcdi_link_piobuf(enp,
2477 enp->en_arch.ef10.ena_pio_write_vi_base + i,
2478 enp->en_arch.ef10.ena_piobuf_handle[i]);
2485 * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs
2486 * during NIC initialization when vSwitch is created and vports are
2487 * allocated. Hence, skip vAdaptor allocation for EVB and update vport
2488 * id in NIC structure with the one allocated for PF.
2491 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
2493 if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) {
2494 /* For EVB use vport allocated on vswitch */
2495 enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id;
2496 alloc_vadaptor = B_FALSE;
2499 if (alloc_vadaptor != B_FALSE) {
2500 /* Allocate a vAdaptor attached to our upstream vPort/pPort */
2501 if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0)
2504 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
2517 ef10_nic_free_piobufs(enp);
2520 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2525 __checkReturn efx_rc_t
2526 ef10_nic_get_vi_pool(
2527 __in efx_nic_t *enp,
2528 __out uint32_t *vi_countp)
2530 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2533 * Report VIs that the client driver can use.
2534 * Do not include VIs used for PIO buffer writes.
2536 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
2541 __checkReturn efx_rc_t
2542 ef10_nic_get_bar_region(
2543 __in efx_nic_t *enp,
2544 __in efx_nic_region_t region,
2545 __out uint32_t *offsetp,
2546 __out size_t *sizep)
2550 EFSYS_ASSERT(EFX_FAMILY_IS_EF10(enp));
2553 * TODO: Specify host memory mapping alignment and granularity
2554 * in efx_drv_limits_t so that they can be taken into account
2555 * when allocating extra VIs for PIO writes.
2559 /* UC mapped memory BAR region for VI registers */
2560 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
2561 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
2564 case EFX_REGION_PIO_WRITE_VI:
2565 /* WC mapped memory BAR region for piobuf writes */
2566 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
2567 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
2578 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2583 __checkReturn boolean_t
2584 ef10_nic_hw_unavailable(
2585 __in efx_nic_t *enp)
2589 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
2592 EFX_BAR_READD(enp, ER_DZ_BIU_MC_SFT_STATUS_REG, &dword, B_FALSE);
2593 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
2599 ef10_nic_set_hw_unavailable(enp);
2605 ef10_nic_set_hw_unavailable(
2606 __in efx_nic_t *enp)
2608 EFSYS_PROBE(hw_unavail);
2609 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
2615 __in efx_nic_t *enp)
2619 boolean_t do_vadaptor_free = B_TRUE;
2622 if (enp->en_vswitchp != NULL) {
2624 * For SR-IOV the vAdaptor is freed with the vswitch,
2625 * so do not free it here.
2627 do_vadaptor_free = B_FALSE;
2630 if (do_vadaptor_free != B_FALSE) {
2631 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
2632 enp->en_vport_id = EVB_PORT_ID_NULL;
2635 /* Unlink piobufs from extra VIs in WC mapping */
2636 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
2637 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
2638 rc = efx_mcdi_unlink_piobuf(enp,
2639 enp->en_arch.ef10.ena_pio_write_vi_base + i);
2645 ef10_nic_free_piobufs(enp);
2647 (void) efx_mcdi_free_vis(enp);
2648 enp->en_arch.ef10.ena_vi_count = 0;
2653 __in efx_nic_t *enp)
2655 #if EFSYS_OPT_MON_STATS
2656 mcdi_mon_cfg_free(enp);
2657 #endif /* EFSYS_OPT_MON_STATS */
2658 (void) efx_mcdi_drv_attach(enp, B_FALSE);
2663 __checkReturn efx_rc_t
2664 ef10_nic_register_test(
2665 __in efx_nic_t *enp)
2670 _NOTE(ARGUNUSED(enp))
2671 _NOTE(CONSTANTCONDITION)
2681 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2686 #endif /* EFSYS_OPT_DIAG */
2688 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
2690 __checkReturn efx_rc_t
2691 efx_mcdi_get_nic_global(
2692 __in efx_nic_t *enp,
2694 __out uint32_t *valuep)
2697 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_NIC_GLOBAL_IN_LEN,
2698 MC_CMD_GET_NIC_GLOBAL_OUT_LEN);
2701 req.emr_cmd = MC_CMD_GET_NIC_GLOBAL;
2702 req.emr_in_buf = payload;
2703 req.emr_in_length = MC_CMD_GET_NIC_GLOBAL_IN_LEN;
2704 req.emr_out_buf = payload;
2705 req.emr_out_length = MC_CMD_GET_NIC_GLOBAL_OUT_LEN;
2707 MCDI_IN_SET_DWORD(req, GET_NIC_GLOBAL_IN_KEY, key);
2709 efx_mcdi_execute(enp, &req);
2711 if (req.emr_rc != 0) {
2716 if (req.emr_out_length_used != MC_CMD_GET_NIC_GLOBAL_OUT_LEN) {
2721 *valuep = MCDI_OUT_DWORD(req, GET_NIC_GLOBAL_OUT_VALUE);
2728 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2733 __checkReturn efx_rc_t
2734 efx_mcdi_set_nic_global(
2735 __in efx_nic_t *enp,
2737 __in uint32_t value)
2740 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_NIC_GLOBAL_IN_LEN, 0);
2743 req.emr_cmd = MC_CMD_SET_NIC_GLOBAL;
2744 req.emr_in_buf = payload;
2745 req.emr_in_length = MC_CMD_SET_NIC_GLOBAL_IN_LEN;
2746 req.emr_out_buf = NULL;
2747 req.emr_out_length = 0;
2749 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_KEY, key);
2750 MCDI_IN_SET_DWORD(req, SET_NIC_GLOBAL_IN_VALUE, value);
2752 efx_mcdi_execute(enp, &req);
2754 if (req.emr_rc != 0) {
2762 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2767 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
2769 #endif /* EFX_OPTS_EF10() */