1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
10 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
14 __in uint32_t mcdi_cap,
15 __out uint32_t *maskp)
19 #define CHECK_CAP(_cap) \
20 EFX_STATIC_ASSERT(EFX_PHY_CAP_##_cap == MC_CMD_PHY_CAP_##_cap##_LBN)
38 CHECK_CAP(BASER_FEC_REQUESTED);
40 CHECK_CAP(RS_FEC_REQUESTED);
41 CHECK_CAP(25G_BASER_FEC);
42 CHECK_CAP(25G_BASER_FEC_REQUESTED);
46 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN))
47 mask |= (1 << EFX_PHY_CAP_10HDX);
48 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN))
49 mask |= (1 << EFX_PHY_CAP_10FDX);
50 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN))
51 mask |= (1 << EFX_PHY_CAP_100HDX);
52 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN))
53 mask |= (1 << EFX_PHY_CAP_100FDX);
54 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN))
55 mask |= (1 << EFX_PHY_CAP_1000HDX);
56 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN))
57 mask |= (1 << EFX_PHY_CAP_1000FDX);
58 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN))
59 mask |= (1 << EFX_PHY_CAP_10000FDX);
60 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25000FDX_LBN))
61 mask |= (1 << EFX_PHY_CAP_25000FDX);
62 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
63 mask |= (1 << EFX_PHY_CAP_40000FDX);
64 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_50000FDX_LBN))
65 mask |= (1 << EFX_PHY_CAP_50000FDX);
66 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100000FDX_LBN))
67 mask |= (1 << EFX_PHY_CAP_100000FDX);
69 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN))
70 mask |= (1 << EFX_PHY_CAP_PAUSE);
71 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN))
72 mask |= (1 << EFX_PHY_CAP_ASYM);
73 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
74 mask |= (1 << EFX_PHY_CAP_AN);
76 /* FEC caps (supported on Medford2 and later) */
77 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_LBN))
78 mask |= (1 << EFX_PHY_CAP_BASER_FEC);
79 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_BASER_FEC_REQUESTED_LBN))
80 mask |= (1 << EFX_PHY_CAP_BASER_FEC_REQUESTED);
82 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_LBN))
83 mask |= (1 << EFX_PHY_CAP_RS_FEC);
84 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_RS_FEC_REQUESTED_LBN))
85 mask |= (1 << EFX_PHY_CAP_RS_FEC_REQUESTED);
87 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_LBN))
88 mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC);
89 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_25G_BASER_FEC_REQUESTED_LBN))
90 mask |= (1 << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED);
96 mcdi_phy_decode_link_mode(
98 __in uint32_t link_flags,
99 __in unsigned int speed,
100 __in unsigned int fcntl,
102 __out efx_link_mode_t *link_modep,
103 __out unsigned int *fcntlp,
104 __out efx_phy_fec_type_t *fecp)
106 boolean_t fd = !!(link_flags &
107 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
108 boolean_t up = !!(link_flags &
109 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
111 _NOTE(ARGUNUSED(enp))
114 *link_modep = EFX_LINK_DOWN;
115 else if (speed == 100000 && fd)
116 *link_modep = EFX_LINK_100000FDX;
117 else if (speed == 50000 && fd)
118 *link_modep = EFX_LINK_50000FDX;
119 else if (speed == 40000 && fd)
120 *link_modep = EFX_LINK_40000FDX;
121 else if (speed == 25000 && fd)
122 *link_modep = EFX_LINK_25000FDX;
123 else if (speed == 10000 && fd)
124 *link_modep = EFX_LINK_10000FDX;
125 else if (speed == 1000)
126 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX;
127 else if (speed == 100)
128 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX;
129 else if (speed == 10)
130 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX;
132 *link_modep = EFX_LINK_UNKNOWN;
134 if (fcntl == MC_CMD_FCNTL_OFF)
136 else if (fcntl == MC_CMD_FCNTL_RESPOND)
137 *fcntlp = EFX_FCNTL_RESPOND;
138 else if (fcntl == MC_CMD_FCNTL_GENERATE)
139 *fcntlp = EFX_FCNTL_GENERATE;
140 else if (fcntl == MC_CMD_FCNTL_BIDIR)
141 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
143 EFSYS_PROBE1(mc_pcol_error, int, fcntl);
148 case MC_CMD_FEC_NONE:
149 *fecp = EFX_PHY_FEC_NONE;
151 case MC_CMD_FEC_BASER:
152 *fecp = EFX_PHY_FEC_BASER;
155 *fecp = EFX_PHY_FEC_RS;
158 EFSYS_PROBE1(mc_pcol_error, int, fec);
159 *fecp = EFX_PHY_FEC_NONE;
168 __in efx_qword_t *eqp,
169 __out efx_link_mode_t *link_modep)
171 efx_port_t *epp = &(enp->en_port);
172 unsigned int link_flags;
175 efx_phy_fec_type_t fec = MC_CMD_FEC_NONE;
176 efx_link_mode_t link_mode;
177 uint32_t lp_cap_mask;
180 * Convert the LINKCHANGE speed enumeration into mbit/s, in the
181 * same way as GET_LINK encodes the speed
183 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) {
184 case MCDI_EVENT_LINKCHANGE_SPEED_100M:
187 case MCDI_EVENT_LINKCHANGE_SPEED_1G:
190 case MCDI_EVENT_LINKCHANGE_SPEED_10G:
193 case MCDI_EVENT_LINKCHANGE_SPEED_25G:
196 case MCDI_EVENT_LINKCHANGE_SPEED_40G:
199 case MCDI_EVENT_LINKCHANGE_SPEED_50G:
202 case MCDI_EVENT_LINKCHANGE_SPEED_100G:
210 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);
211 mcdi_phy_decode_link_mode(enp, link_flags, speed,
212 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),
213 MC_CMD_FEC_NONE, &link_mode,
215 mcdi_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),
219 * It's safe to update ep_lp_cap_mask without the driver's port lock
220 * because presumably any concurrently running efx_port_poll() is
221 * only going to arrive at the same value.
223 * ep_fcntl has two meanings. It's either the link common fcntl
224 * (if the PHY supports AN), or it's the forced link state. If
225 * the former, it's safe to update the value for the same reason as
226 * for ep_lp_cap_mask. If the latter, then just ignore the value,
227 * because we can race with efx_mac_fcntl_set().
229 epp->ep_lp_cap_mask = lp_cap_mask;
230 epp->ep_fcntl = fcntl;
232 *link_modep = link_mode;
235 __checkReturn efx_rc_t
238 __in boolean_t power)
245 /* Check if the PHY is a zombie */
246 if ((rc = ef10_phy_verify(enp)) != 0)
249 enp->en_reset_flags |= EFX_RESET_PHY;
254 EFSYS_PROBE1(fail1, efx_rc_t, rc);
259 __checkReturn efx_rc_t
262 __out ef10_link_state_t *elsp)
266 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LINK_IN_LEN,
267 MC_CMD_GET_LINK_OUT_V2_LEN);
270 req.emr_cmd = MC_CMD_GET_LINK;
271 req.emr_in_buf = payload;
272 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN;
273 req.emr_out_buf = payload;
274 req.emr_out_length = MC_CMD_GET_LINK_OUT_V2_LEN;
276 efx_mcdi_execute(enp, &req);
278 if (req.emr_rc != 0) {
283 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) {
288 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP),
289 &elsp->epls.epls_adv_cap_mask);
290 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),
291 &elsp->epls.epls_lp_cap_mask);
293 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN)
294 fec = MC_CMD_FEC_NONE;
296 fec = MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_FEC_TYPE);
298 mcdi_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
299 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
300 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
301 fec, &elsp->epls.epls_link_mode,
302 &elsp->epls.epls_fcntl, &elsp->epls.epls_fec);
304 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_V2_LEN) {
305 elsp->epls.epls_ld_cap_mask = 0;
307 mcdi_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_V2_LD_CAP),
308 &elsp->epls.epls_ld_cap_mask);
312 #if EFSYS_OPT_LOOPBACK
314 * MC_CMD_LOOPBACK and EFX_LOOPBACK names are equivalent, so use the
315 * MCDI value directly. Agreement is checked in efx_loopback_mask().
317 elsp->els_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE);
318 #endif /* EFSYS_OPT_LOOPBACK */
320 elsp->els_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;
327 EFSYS_PROBE1(fail1, efx_rc_t, rc);
332 static __checkReturn efx_rc_t
333 efx_mcdi_phy_set_link(
335 __in uint32_t cap_mask,
336 __in efx_loopback_type_t loopback_type,
337 __in efx_link_mode_t loopback_link_mode,
338 __in uint32_t phy_flags)
341 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_LINK_IN_LEN,
342 MC_CMD_SET_LINK_OUT_LEN);
346 req.emr_cmd = MC_CMD_SET_LINK;
347 req.emr_in_buf = payload;
348 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN;
349 req.emr_out_buf = payload;
350 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN;
352 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP,
353 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1,
354 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1,
355 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1,
356 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1,
357 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1,
358 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1,
359 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1,
360 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1,
361 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,
362 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);
363 /* Too many fields for for POPULATE macros, so insert this afterwards */
364 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
365 PHY_CAP_25000FDX, (cap_mask >> EFX_PHY_CAP_25000FDX) & 0x1);
366 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
367 PHY_CAP_40000FDX, (cap_mask >> EFX_PHY_CAP_40000FDX) & 0x1);
368 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
369 PHY_CAP_50000FDX, (cap_mask >> EFX_PHY_CAP_50000FDX) & 0x1);
370 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
371 PHY_CAP_100000FDX, (cap_mask >> EFX_PHY_CAP_100000FDX) & 0x1);
373 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
374 PHY_CAP_BASER_FEC, (cap_mask >> EFX_PHY_CAP_BASER_FEC) & 0x1);
375 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
376 PHY_CAP_BASER_FEC_REQUESTED,
377 (cap_mask >> EFX_PHY_CAP_BASER_FEC_REQUESTED) & 0x1);
379 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
380 PHY_CAP_RS_FEC, (cap_mask >> EFX_PHY_CAP_RS_FEC) & 0x1);
381 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
382 PHY_CAP_RS_FEC_REQUESTED,
383 (cap_mask >> EFX_PHY_CAP_RS_FEC_REQUESTED) & 0x1);
385 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
386 PHY_CAP_25G_BASER_FEC,
387 (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC) & 0x1);
388 MCDI_IN_SET_DWORD_FIELD(req, SET_LINK_IN_CAP,
389 PHY_CAP_25G_BASER_FEC_REQUESTED,
390 (cap_mask >> EFX_PHY_CAP_25G_BASER_FEC_REQUESTED) & 0x1);
392 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, loopback_type);
394 switch (loopback_link_mode) {
395 case EFX_LINK_100FDX:
398 case EFX_LINK_1000FDX:
401 case EFX_LINK_10000FDX:
404 case EFX_LINK_25000FDX:
407 case EFX_LINK_40000FDX:
410 case EFX_LINK_50000FDX:
413 case EFX_LINK_100000FDX:
420 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed);
422 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, phy_flags);
424 efx_mcdi_execute(enp, &req);
426 if (req.emr_rc != 0) {
434 EFSYS_PROBE1(fail1, efx_rc_t, rc);
439 static __checkReturn efx_rc_t
440 efx_mcdi_phy_set_led(
442 __in efx_phy_led_mode_t phy_led_mode)
445 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_ID_LED_IN_LEN,
446 MC_CMD_SET_ID_LED_OUT_LEN);
447 unsigned int led_mode;
450 req.emr_cmd = MC_CMD_SET_ID_LED;
451 req.emr_in_buf = payload;
452 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN;
453 req.emr_out_buf = payload;
454 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;
456 switch (phy_led_mode) {
457 case EFX_PHY_LED_DEFAULT:
458 led_mode = MC_CMD_LED_DEFAULT;
460 case EFX_PHY_LED_OFF:
461 led_mode = MC_CMD_LED_OFF;
464 led_mode = MC_CMD_LED_ON;
468 led_mode = MC_CMD_LED_DEFAULT;
472 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);
474 efx_mcdi_execute(enp, &req);
476 if (req.emr_rc != 0) {
484 EFSYS_PROBE1(fail1, efx_rc_t, rc);
489 __checkReturn efx_rc_t
490 ef10_phy_reconfigure(
493 efx_port_t *epp = &(enp->en_port);
494 efx_loopback_type_t loopback_type;
495 efx_link_mode_t loopback_link_mode;
497 efx_phy_led_mode_t phy_led_mode;
501 if ((rc = efx_mcdi_link_control_supported(enp, &supported)) != 0)
503 if (supported == B_FALSE)
506 #if EFSYS_OPT_LOOPBACK
507 loopback_type = epp->ep_loopback_type;
508 loopback_link_mode = epp->ep_loopback_link_mode;
510 loopback_type = EFX_LOOPBACK_OFF;
511 loopback_link_mode = EFX_LINK_UNKNOWN;
513 #if EFSYS_OPT_PHY_FLAGS
514 phy_flags = epp->ep_phy_flags;
519 rc = efx_mcdi_phy_set_link(enp, epp->ep_adv_cap_mask,
520 loopback_type, loopback_link_mode, phy_flags);
524 /* And set the blink mode */
526 #if EFSYS_OPT_PHY_LED_CONTROL
527 phy_led_mode = epp->ep_phy_led_mode;
529 phy_led_mode = EFX_PHY_LED_DEFAULT;
532 rc = efx_mcdi_phy_set_led(enp, phy_led_mode);
535 * If LED control is not supported by firmware, we can
536 * silently ignore default mode set failure
537 * (see FWRIVERHD-198).
539 if (rc == EOPNOTSUPP && phy_led_mode == EFX_PHY_LED_DEFAULT)
552 EFSYS_PROBE1(fail1, efx_rc_t, rc);
557 __checkReturn efx_rc_t
562 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_PHY_STATE_IN_LEN,
563 MC_CMD_GET_PHY_STATE_OUT_LEN);
567 req.emr_cmd = MC_CMD_GET_PHY_STATE;
568 req.emr_in_buf = payload;
569 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN;
570 req.emr_out_buf = payload;
571 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN;
573 efx_mcdi_execute(enp, &req);
575 if (req.emr_rc != 0) {
580 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) {
585 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE);
586 if (state != MC_CMD_PHY_STATE_OK) {
587 if (state != MC_CMD_PHY_STATE_ZOMBIE)
588 EFSYS_PROBE1(mc_pcol_error, int, state);
600 EFSYS_PROBE1(fail1, efx_rc_t, rc);
605 __checkReturn efx_rc_t
608 __out uint32_t *ouip)
610 _NOTE(ARGUNUSED(enp, ouip))
615 __checkReturn efx_rc_t
616 ef10_phy_link_state_get(
618 __out efx_phy_link_state_t *eplsp)
621 ef10_link_state_t els;
623 /* Obtain the active link state */
624 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
632 EFSYS_PROBE1(fail1, efx_rc_t, rc);
638 #if EFSYS_OPT_PHY_STATS
640 __checkReturn efx_rc_t
641 ef10_phy_stats_update(
643 __in efsys_mem_t *esmp,
644 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
646 /* TBD: no stats support in firmware yet */
647 _NOTE(ARGUNUSED(enp, esmp))
648 memset(stat, 0, EFX_PHY_NSTATS * sizeof (*stat));
653 #endif /* EFSYS_OPT_PHY_STATS */
657 __checkReturn efx_rc_t
658 ef10_bist_enable_offline(
663 if ((rc = efx_mcdi_bist_enable_offline(enp)) != 0)
669 EFSYS_PROBE1(fail1, efx_rc_t, rc);
674 __checkReturn efx_rc_t
677 __in efx_bist_type_t type)
681 if ((rc = efx_mcdi_bist_start(enp, type)) != 0)
687 EFSYS_PROBE1(fail1, efx_rc_t, rc);
692 __checkReturn efx_rc_t
695 __in efx_bist_type_t type,
696 __out efx_bist_result_t *resultp,
697 __out_opt __drv_when(count > 0, __notnull)
698 uint32_t *value_maskp,
699 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
700 unsigned long *valuesp,
704 * MCDI_CTL_SDU_LEN_MAX_V1 is large enough cover all BIST results,
705 * whilst not wasting stack.
707 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_POLL_BIST_IN_LEN,
708 MCDI_CTL_SDU_LEN_MAX_V1);
709 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
711 uint32_t value_mask = 0;
715 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_LEN <=
716 MCDI_CTL_SDU_LEN_MAX_V1);
717 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_SFT9001_LEN <=
718 MCDI_CTL_SDU_LEN_MAX_V1);
719 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MRSFP_LEN <=
720 MCDI_CTL_SDU_LEN_MAX_V1);
721 EFX_STATIC_ASSERT(MC_CMD_POLL_BIST_OUT_MEM_LEN <=
722 MCDI_CTL_SDU_LEN_MAX_V1);
724 _NOTE(ARGUNUSED(type))
726 req.emr_cmd = MC_CMD_POLL_BIST;
727 req.emr_in_buf = payload;
728 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN;
729 req.emr_out_buf = payload;
730 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX_V1;
732 efx_mcdi_execute(enp, &req);
734 if (req.emr_rc != 0) {
739 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) {
745 (void) memset(valuesp, '\0', count * sizeof (unsigned long));
747 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT);
749 if (result == MC_CMD_POLL_BIST_FAILED &&
750 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MEM_LEN &&
751 count > EFX_BIST_MEM_ECC_FATAL) {
752 if (valuesp != NULL) {
753 valuesp[EFX_BIST_MEM_TEST] =
754 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_TEST);
755 valuesp[EFX_BIST_MEM_ADDR] =
756 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ADDR);
757 valuesp[EFX_BIST_MEM_BUS] =
758 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_BUS);
759 valuesp[EFX_BIST_MEM_EXPECT] =
760 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_EXPECT);
761 valuesp[EFX_BIST_MEM_ACTUAL] =
762 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ACTUAL);
763 valuesp[EFX_BIST_MEM_ECC] =
764 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC);
765 valuesp[EFX_BIST_MEM_ECC_PARITY] =
766 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC_PARITY);
767 valuesp[EFX_BIST_MEM_ECC_FATAL] =
768 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MEM_ECC_FATAL);
770 value_mask |= (1 << EFX_BIST_MEM_TEST) |
771 (1 << EFX_BIST_MEM_ADDR) |
772 (1 << EFX_BIST_MEM_BUS) |
773 (1 << EFX_BIST_MEM_EXPECT) |
774 (1 << EFX_BIST_MEM_ACTUAL) |
775 (1 << EFX_BIST_MEM_ECC) |
776 (1 << EFX_BIST_MEM_ECC_PARITY) |
777 (1 << EFX_BIST_MEM_ECC_FATAL);
778 } else if (result == MC_CMD_POLL_BIST_FAILED &&
779 encp->enc_phy_type == EFX_PHY_XFI_FARMI &&
780 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN &&
781 count > EFX_BIST_FAULT_CODE) {
783 valuesp[EFX_BIST_FAULT_CODE] =
784 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST);
785 value_mask |= 1 << EFX_BIST_FAULT_CODE;
788 if (value_maskp != NULL)
789 *value_maskp = value_mask;
791 EFSYS_ASSERT(resultp != NULL);
792 if (result == MC_CMD_POLL_BIST_RUNNING)
793 *resultp = EFX_BIST_RESULT_RUNNING;
794 else if (result == MC_CMD_POLL_BIST_PASSED)
795 *resultp = EFX_BIST_RESULT_PASSED;
797 *resultp = EFX_BIST_RESULT_FAILED;
804 EFSYS_PROBE1(fail1, efx_rc_t, rc);
812 __in efx_bist_type_t type)
814 /* There is no way to stop BIST on EF10. */
815 _NOTE(ARGUNUSED(enp, type))
818 #endif /* EFSYS_OPT_BIST */
820 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */