1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
13 #if EFSYS_OPT_RX_SCALE
14 static __checkReturn efx_rc_t
15 efx_mcdi_rss_context_alloc(
17 __in efx_rx_scale_context_type_t type,
18 __in uint32_t num_queues,
19 __out uint32_t *rss_contextp)
22 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
23 MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
25 uint32_t context_type;
28 if (num_queues > EFX_MAXRSS) {
34 case EFX_RX_SCALE_EXCLUSIVE:
35 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
37 case EFX_RX_SCALE_SHARED:
38 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
45 req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
46 req.emr_in_buf = payload;
47 req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN;
48 req.emr_out_buf = payload;
49 req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
51 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
53 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
56 * For exclusive contexts, NUM_QUEUES is only used to validate
57 * indirection table offsets.
58 * For shared contexts, the provided context will spread traffic over
59 * NUM_QUEUES many queues.
61 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
63 efx_mcdi_execute(enp, &req);
65 if (req.emr_rc != 0) {
70 if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
75 rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
76 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
81 *rss_contextp = rss_context;
94 EFSYS_PROBE1(fail1, efx_rc_t, rc);
98 #endif /* EFSYS_OPT_RX_SCALE */
100 #if EFSYS_OPT_RX_SCALE
102 efx_mcdi_rss_context_free(
104 __in uint32_t rss_context)
107 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_FREE_IN_LEN,
108 MC_CMD_RSS_CONTEXT_FREE_OUT_LEN);
111 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
116 req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE;
117 req.emr_in_buf = payload;
118 req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN;
119 req.emr_out_buf = payload;
120 req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN;
122 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context);
124 efx_mcdi_execute_quiet(enp, &req);
126 if (req.emr_rc != 0) {
136 EFSYS_PROBE1(fail1, efx_rc_t, rc);
140 #endif /* EFSYS_OPT_RX_SCALE */
142 #if EFSYS_OPT_RX_SCALE
144 efx_mcdi_rss_context_set_flags(
146 __in uint32_t rss_context,
147 __in efx_rx_hash_type_t type)
149 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
151 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN,
152 MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN);
155 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
156 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN);
157 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
158 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH);
159 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
160 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN);
161 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
162 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH);
163 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
164 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN);
165 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
166 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH);
167 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
168 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN);
169 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
170 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH);
172 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
177 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS;
178 req.emr_in_buf = payload;
179 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN;
180 req.emr_out_buf = payload;
181 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN;
183 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
187 * If the firmware lacks support for additional modes, RSS_MODE
188 * fields must contain zeros, otherwise the operation will fail.
190 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE)
191 type &= EFX_RX_HASH_LEGACY_MASK;
193 MCDI_IN_POPULATE_DWORD_10(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS,
194 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN,
195 (type & EFX_RX_HASH_IPV4) ? 1 : 0,
196 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN,
197 (type & EFX_RX_HASH_TCPIPV4) ? 1 : 0,
198 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN,
199 (type & EFX_RX_HASH_IPV6) ? 1 : 0,
200 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN,
201 (type & EFX_RX_HASH_TCPIPV6) ? 1 : 0,
202 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE,
203 (type >> EFX_RX_CLASS_IPV4_TCP_LBN) &
204 EFX_MASK32(EFX_RX_CLASS_IPV4_TCP),
205 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE,
206 (type >> EFX_RX_CLASS_IPV4_UDP_LBN) &
207 EFX_MASK32(EFX_RX_CLASS_IPV4_UDP),
208 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE,
209 (type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4),
210 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE,
211 (type >> EFX_RX_CLASS_IPV6_TCP_LBN) &
212 EFX_MASK32(EFX_RX_CLASS_IPV6_TCP),
213 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE,
214 (type >> EFX_RX_CLASS_IPV6_UDP_LBN) &
215 EFX_MASK32(EFX_RX_CLASS_IPV6_UDP),
216 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE,
217 (type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6));
219 efx_mcdi_execute(enp, &req);
221 if (req.emr_rc != 0) {
231 EFSYS_PROBE1(fail1, efx_rc_t, rc);
235 #endif /* EFSYS_OPT_RX_SCALE */
237 #if EFSYS_OPT_RX_SCALE
239 efx_mcdi_rss_context_set_key(
241 __in uint32_t rss_context,
242 __in_ecount(n) uint8_t *key,
246 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN,
247 MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN);
250 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
255 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY;
256 req.emr_in_buf = payload;
257 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN;
258 req.emr_out_buf = payload;
259 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN;
261 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
264 EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
265 if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) {
270 memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY),
273 efx_mcdi_execute(enp, &req);
275 if (req.emr_rc != 0) {
287 EFSYS_PROBE1(fail1, efx_rc_t, rc);
291 #endif /* EFSYS_OPT_RX_SCALE */
293 #if EFSYS_OPT_RX_SCALE
295 efx_mcdi_rss_context_set_table(
297 __in uint32_t rss_context,
298 __in_ecount(n) unsigned int *table,
302 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN,
303 MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN);
307 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
312 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE;
313 req.emr_in_buf = payload;
314 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN;
315 req.emr_out_buf = payload;
316 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN;
318 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
322 MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE);
325 i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN;
327 req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0;
330 efx_mcdi_execute(enp, &req);
332 if (req.emr_rc != 0) {
342 EFSYS_PROBE1(fail1, efx_rc_t, rc);
346 #endif /* EFSYS_OPT_RX_SCALE */
349 __checkReturn efx_rc_t
353 #if EFSYS_OPT_RX_SCALE
355 if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
356 &enp->en_rss_context) == 0) {
358 * Allocated an exclusive RSS context, which allows both the
359 * indirection table and key to be modified.
361 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
362 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
365 * Failed to allocate an exclusive RSS context. Continue
366 * operation without support for RSS. The pseudo-header in
367 * received packets will not contain a Toeplitz hash value.
369 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
370 enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE;
373 #endif /* EFSYS_OPT_RX_SCALE */
378 #if EFSYS_OPT_RX_SCATTER
379 __checkReturn efx_rc_t
380 ef10_rx_scatter_enable(
382 __in unsigned int buf_size)
384 _NOTE(ARGUNUSED(enp, buf_size))
387 #endif /* EFSYS_OPT_RX_SCATTER */
389 #if EFSYS_OPT_RX_SCALE
390 __checkReturn efx_rc_t
391 ef10_rx_scale_context_alloc(
393 __in efx_rx_scale_context_type_t type,
394 __in uint32_t num_queues,
395 __out uint32_t *rss_contextp)
399 rc = efx_mcdi_rss_context_alloc(enp, type, num_queues, rss_contextp);
406 EFSYS_PROBE1(fail1, efx_rc_t, rc);
409 #endif /* EFSYS_OPT_RX_SCALE */
411 #if EFSYS_OPT_RX_SCALE
412 __checkReturn efx_rc_t
413 ef10_rx_scale_context_free(
415 __in uint32_t rss_context)
419 rc = efx_mcdi_rss_context_free(enp, rss_context);
426 EFSYS_PROBE1(fail1, efx_rc_t, rc);
429 #endif /* EFSYS_OPT_RX_SCALE */
431 #if EFSYS_OPT_RX_SCALE
432 __checkReturn efx_rc_t
433 ef10_rx_scale_mode_set(
435 __in uint32_t rss_context,
436 __in efx_rx_hash_alg_t alg,
437 __in efx_rx_hash_type_t type,
438 __in boolean_t insert)
440 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
443 EFSYS_ASSERT3U(insert, ==, B_TRUE);
445 if ((encp->enc_rx_scale_hash_alg_mask & (1U << alg)) == 0 ||
451 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
452 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
456 rss_context = enp->en_rss_context;
459 if ((rc = efx_mcdi_rss_context_set_flags(enp,
460 rss_context, type)) != 0)
470 EFSYS_PROBE1(fail1, efx_rc_t, rc);
474 #endif /* EFSYS_OPT_RX_SCALE */
476 #if EFSYS_OPT_RX_SCALE
477 __checkReturn efx_rc_t
478 ef10_rx_scale_key_set(
480 __in uint32_t rss_context,
481 __in_ecount(n) uint8_t *key,
486 EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
487 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
489 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
490 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
494 rss_context = enp->en_rss_context;
497 if ((rc = efx_mcdi_rss_context_set_key(enp, rss_context, key, n)) != 0)
505 EFSYS_PROBE1(fail1, efx_rc_t, rc);
509 #endif /* EFSYS_OPT_RX_SCALE */
511 #if EFSYS_OPT_RX_SCALE
512 __checkReturn efx_rc_t
513 ef10_rx_scale_tbl_set(
515 __in uint32_t rss_context,
516 __in_ecount(n) unsigned int *table,
522 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
523 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
527 rss_context = enp->en_rss_context;
530 if ((rc = efx_mcdi_rss_context_set_table(enp,
531 rss_context, table, n)) != 0)
539 EFSYS_PROBE1(fail1, efx_rc_t, rc);
543 #endif /* EFSYS_OPT_RX_SCALE */
547 * EF10 RX pseudo-header
548 * ---------------------
550 * Receive packets are prefixed by an (optional) 14 byte pseudo-header:
552 * +00: Toeplitz hash value.
553 * (32bit little-endian)
554 * +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag.
556 * +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag.
558 * +08: Packet Length. Zero if the RX datapath was in cut-through mode.
559 * (16bit little-endian)
560 * +10: MAC timestamp. Zero if timestamping is not enabled.
561 * (32bit little-endian)
563 * See "The RX Pseudo-header" in SF-109306-TC.
566 __checkReturn efx_rc_t
567 ef10_rx_prefix_pktlen(
569 __in uint8_t *buffer,
570 __out uint16_t *lengthp)
572 _NOTE(ARGUNUSED(enp))
575 * The RX pseudo-header contains the packet length, excluding the
576 * pseudo-header. If the hardware receive datapath was operating in
577 * cut-through mode then the length in the RX pseudo-header will be
578 * zero, and the packet length must be obtained from the DMA length
579 * reported in the RX event.
581 *lengthp = buffer[8] | (buffer[9] << 8);
585 #if EFSYS_OPT_RX_SCALE
586 __checkReturn uint32_t
589 __in efx_rx_hash_alg_t func,
590 __in uint8_t *buffer)
592 _NOTE(ARGUNUSED(enp))
595 case EFX_RX_HASHALG_PACKED_STREAM:
596 case EFX_RX_HASHALG_TOEPLITZ:
607 #endif /* EFSYS_OPT_RX_SCALE */
609 #if EFSYS_OPT_RX_PACKED_STREAM
611 * Fake length for RXQ descriptors in packed stream mode
612 * to make hardware happy
614 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
620 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
622 __in unsigned int ndescs,
623 __in unsigned int completed,
624 __in unsigned int added)
631 _NOTE(ARGUNUSED(completed))
633 #if EFSYS_OPT_RX_PACKED_STREAM
635 * Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
636 * and equal to 0 after applying mask. Hardware does not like it.
638 if (erp->er_ev_qstate->eers_rx_packed_stream)
639 size = EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE;
642 /* The client driver must not overfill the queue */
643 EFSYS_ASSERT3U(added - completed + ndescs, <=,
644 EFX_RXQ_LIMIT(erp->er_mask + 1));
646 id = added & (erp->er_mask);
647 for (i = 0; i < ndescs; i++) {
648 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
649 unsigned int, id, efsys_dma_addr_t, addrp[i],
652 EFX_POPULATE_QWORD_3(qword,
653 ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size),
654 ESF_DZ_RX_KER_BUF_ADDR_DW0,
655 (uint32_t)(addrp[i] & 0xffffffff),
656 ESF_DZ_RX_KER_BUF_ADDR_DW1,
657 (uint32_t)(addrp[i] >> 32));
659 offset = id * sizeof (efx_qword_t);
660 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
662 id = (id + 1) & (erp->er_mask);
669 __in unsigned int added,
670 __inout unsigned int *pushedp)
672 efx_nic_t *enp = erp->er_enp;
673 unsigned int pushed = *pushedp;
677 /* Hardware has alignment restriction for WPTR */
678 wptr = EFX_P2ALIGN(unsigned int, added, EF10_RX_WPTR_ALIGN);
684 /* Push the populated descriptors out */
685 wptr &= erp->er_mask;
687 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr);
689 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
690 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
691 wptr, pushed & erp->er_mask);
692 EFSYS_PIO_WRITE_BARRIER();
693 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
694 erp->er_index, &dword, B_FALSE);
697 #if EFSYS_OPT_RX_PACKED_STREAM
700 ef10_rx_qpush_ps_credits(
703 efx_nic_t *enp = erp->er_enp;
705 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
708 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
710 if (rxq_state->eers_rx_packed_stream_credits == 0)
714 * It is a bug if we think that FW has utilized more
715 * credits than it is allowed to have (maximum). However,
716 * make sure that we do not credit more than maximum anyway.
718 credits = MIN(rxq_state->eers_rx_packed_stream_credits,
719 EFX_RX_PACKED_STREAM_MAX_CREDITS);
720 EFX_POPULATE_DWORD_3(dword,
721 ERF_DZ_RX_DESC_MAGIC_DOORBELL, 1,
722 ERF_DZ_RX_DESC_MAGIC_CMD,
723 ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS,
724 ERF_DZ_RX_DESC_MAGIC_DATA, credits);
725 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
726 erp->er_index, &dword, B_FALSE);
728 rxq_state->eers_rx_packed_stream_credits = 0;
732 * In accordance with SF-112241-TC the received data has the following layout:
733 * - 8 byte pseudo-header which consist of:
734 * - 4 byte little-endian timestamp
735 * - 2 byte little-endian captured length in bytes
736 * - 2 byte little-endian original packet length in bytes
737 * - captured packet bytes
738 * - optional padding to align to 64 bytes boundary
739 * - 64 bytes scratch space for the host software
741 __checkReturn uint8_t *
742 ef10_rx_qps_packet_info(
744 __in uint8_t *buffer,
745 __in uint32_t buffer_length,
746 __in uint32_t current_offset,
747 __out uint16_t *lengthp,
748 __out uint32_t *next_offsetp,
749 __out uint32_t *timestamp)
754 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
756 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
758 buffer += current_offset;
759 pkt_start = buffer + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE;
761 qwordp = (efx_qword_t *)buffer;
762 *timestamp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_TSTAMP);
763 *lengthp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_ORIG_LEN);
764 buf_len = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_CAP_LEN);
766 buf_len = EFX_P2ROUNDUP(uint16_t,
767 buf_len + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE,
768 EFX_RX_PACKED_STREAM_ALIGNMENT);
770 current_offset + buf_len + EFX_RX_PACKED_STREAM_ALIGNMENT;
772 EFSYS_ASSERT3U(*next_offsetp, <=, buffer_length);
773 EFSYS_ASSERT3U(current_offset + *lengthp, <, *next_offsetp);
775 if ((*next_offsetp ^ current_offset) &
776 EFX_RX_PACKED_STREAM_MEM_PER_CREDIT)
777 rxq_state->eers_rx_packed_stream_credits++;
785 __checkReturn efx_rc_t
789 efx_nic_t *enp = erp->er_enp;
792 if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0)
799 * EALREADY is not an error, but indicates that the MC has rebooted and
800 * that the RXQ has already been destroyed. Callers need to know that
801 * the RXQ flush has completed to avoid waiting until timeout for a
802 * flush done event that will not be delivered.
805 EFSYS_PROBE1(fail1, efx_rc_t, rc);
815 _NOTE(ARGUNUSED(erp))
819 __checkReturn efx_rc_t
822 __in unsigned int index,
823 __in unsigned int label,
824 __in efx_rxq_type_t type,
825 __in_opt const efx_rxq_type_data_t *type_data,
826 __in efsys_mem_t *esmp,
829 __in unsigned int flags,
833 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
835 boolean_t disable_scatter;
836 boolean_t want_inner_classes;
837 unsigned int ps_buf_size;
838 uint32_t es_bufs_per_desc = 0;
839 uint32_t es_max_dma_len = 0;
840 uint32_t es_buf_stride = 0;
841 uint32_t hol_block_timeout = 0;
843 _NOTE(ARGUNUSED(id, erp))
845 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
846 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
849 case EFX_RXQ_TYPE_DEFAULT:
850 if (type_data == NULL) {
854 erp->er_buf_size = type_data->ertd_default.ed_buf_size;
857 #if EFSYS_OPT_RX_PACKED_STREAM
858 case EFX_RXQ_TYPE_PACKED_STREAM:
859 if (type_data == NULL) {
863 switch (type_data->ertd_packed_stream.eps_buf_size) {
864 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
865 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
867 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
868 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
870 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
871 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
873 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
874 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
876 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
877 ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
883 erp->er_buf_size = type_data->ertd_packed_stream.eps_buf_size;
885 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
886 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
887 case EFX_RXQ_TYPE_ES_SUPER_BUFFER:
888 if (type_data == NULL) {
894 type_data->ertd_es_super_buffer.eessb_bufs_per_desc;
896 type_data->ertd_es_super_buffer.eessb_max_dma_len;
898 type_data->ertd_es_super_buffer.eessb_buf_stride;
900 type_data->ertd_es_super_buffer.eessb_hol_block_timeout;
902 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
908 #if EFSYS_OPT_RX_PACKED_STREAM
909 if (ps_buf_size != 0) {
910 /* Check if datapath firmware supports packed stream mode */
911 if (encp->enc_rx_packed_stream_supported == B_FALSE) {
915 /* Check if packed stream allows configurable buffer sizes */
916 if ((ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
917 (encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
922 #else /* EFSYS_OPT_RX_PACKED_STREAM */
923 EFSYS_ASSERT(ps_buf_size == 0);
924 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
926 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
927 if (es_bufs_per_desc > 0) {
928 if (encp->enc_rx_es_super_buffer_supported == B_FALSE) {
932 if (!EFX_IS_P2ALIGNED(uint32_t, es_max_dma_len,
933 EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
937 if (!EFX_IS_P2ALIGNED(uint32_t, es_buf_stride,
938 EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
943 #else /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
944 EFSYS_ASSERT(es_bufs_per_desc == 0);
945 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
947 /* Scatter can only be disabled if the firmware supports doing so */
948 if (flags & EFX_RXQ_FLAG_SCATTER)
949 disable_scatter = B_FALSE;
951 disable_scatter = encp->enc_rx_disable_scatter_supported;
953 if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
954 want_inner_classes = B_TRUE;
956 want_inner_classes = B_FALSE;
958 if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep, label, index,
959 esmp, disable_scatter, want_inner_classes, erp->er_buf_size,
960 ps_buf_size, es_bufs_per_desc, es_max_dma_len,
961 es_buf_stride, hol_block_timeout)) != 0)
965 erp->er_label = label;
967 ef10_ev_rxlabel_init(eep, erp, label, type);
969 erp->er_ev_qstate = &erp->er_eep->ee_rxq_state[label];
975 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
982 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
983 #if EFSYS_OPT_RX_PACKED_STREAM
988 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
991 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
994 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
995 #if EFSYS_OPT_RX_PACKED_STREAM
1000 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1002 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1009 __in efx_rxq_t *erp)
1011 efx_evq_t *eep = erp->er_eep;
1012 unsigned int label = erp->er_label;
1014 ef10_ev_rxlabel_fini(eep, label);
1019 __in efx_nic_t *enp)
1021 #if EFSYS_OPT_RX_SCALE
1022 if (enp->en_rss_context_type != EFX_RX_SCALE_UNAVAILABLE)
1023 (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context);
1024 enp->en_rss_context = 0;
1025 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
1027 _NOTE(ARGUNUSED(enp))
1028 #endif /* EFSYS_OPT_RX_SCALE */
1031 #endif /* EFX_OPTS_EF10() */