1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
11 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
13 #if EFSYS_OPT_RX_SCALE
14 static __checkReturn efx_rc_t
15 efx_mcdi_rss_context_alloc(
17 __in efx_rx_scale_context_type_t type,
18 __in uint32_t num_queues,
19 __out uint32_t *rss_contextp)
22 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN,
23 MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
25 uint32_t context_type;
28 if (num_queues > EFX_MAXRSS) {
34 case EFX_RX_SCALE_EXCLUSIVE:
35 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE;
37 case EFX_RX_SCALE_SHARED:
38 context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
45 req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC;
46 req.emr_in_buf = payload;
47 req.emr_in_length = MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN;
48 req.emr_out_buf = payload;
49 req.emr_out_length = MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN;
51 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
53 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type);
56 * For exclusive contexts, NUM_QUEUES is only used to validate
57 * indirection table offsets.
58 * For shared contexts, the provided context will spread traffic over
59 * NUM_QUEUES many queues.
61 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues);
63 efx_mcdi_execute(enp, &req);
65 if (req.emr_rc != 0) {
70 if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) {
75 rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
76 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
81 *rss_contextp = rss_context;
94 EFSYS_PROBE1(fail1, efx_rc_t, rc);
98 #endif /* EFSYS_OPT_RX_SCALE */
100 #if EFSYS_OPT_RX_SCALE
102 efx_mcdi_rss_context_free(
104 __in uint32_t rss_context)
107 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_FREE_IN_LEN,
108 MC_CMD_RSS_CONTEXT_FREE_OUT_LEN);
111 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
116 req.emr_cmd = MC_CMD_RSS_CONTEXT_FREE;
117 req.emr_in_buf = payload;
118 req.emr_in_length = MC_CMD_RSS_CONTEXT_FREE_IN_LEN;
119 req.emr_out_buf = payload;
120 req.emr_out_length = MC_CMD_RSS_CONTEXT_FREE_OUT_LEN;
122 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, rss_context);
124 efx_mcdi_execute_quiet(enp, &req);
126 if (req.emr_rc != 0) {
136 EFSYS_PROBE1(fail1, efx_rc_t, rc);
140 #endif /* EFSYS_OPT_RX_SCALE */
142 #if EFSYS_OPT_RX_SCALE
144 efx_mcdi_rss_context_set_flags(
146 __in uint32_t rss_context,
147 __in efx_rx_hash_type_t type)
149 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
151 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN,
152 MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN);
155 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_LBN ==
156 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_LBN);
157 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_TCP_WIDTH ==
158 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH);
159 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_LBN ==
160 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_LBN);
161 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV4_WIDTH ==
162 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH);
163 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_LBN ==
164 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_LBN);
165 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_TCP_WIDTH ==
166 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH);
167 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_LBN ==
168 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_LBN);
169 EFX_STATIC_ASSERT(EFX_RX_CLASS_IPV6_WIDTH ==
170 MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH);
172 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
177 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_FLAGS;
178 req.emr_in_buf = payload;
179 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN;
180 req.emr_out_buf = payload;
181 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN;
183 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID,
187 * If the firmware lacks support for additional modes, RSS_MODE
188 * fields must contain zeros, otherwise the operation will fail.
190 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE)
191 type &= EFX_RX_HASH_LEGACY_MASK;
193 MCDI_IN_POPULATE_DWORD_10(req, RSS_CONTEXT_SET_FLAGS_IN_FLAGS,
194 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN,
195 (type & EFX_RX_HASH_IPV4) ? 1 : 0,
196 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN,
197 (type & EFX_RX_HASH_TCPIPV4) ? 1 : 0,
198 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN,
199 (type & EFX_RX_HASH_IPV6) ? 1 : 0,
200 RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN,
201 (type & EFX_RX_HASH_TCPIPV6) ? 1 : 0,
202 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE,
203 (type >> EFX_RX_CLASS_IPV4_TCP_LBN) &
204 EFX_MASK32(EFX_RX_CLASS_IPV4_TCP),
205 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE,
206 (type >> EFX_RX_CLASS_IPV4_UDP_LBN) &
207 EFX_MASK32(EFX_RX_CLASS_IPV4_UDP),
208 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE,
209 (type >> EFX_RX_CLASS_IPV4_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV4),
210 RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE,
211 (type >> EFX_RX_CLASS_IPV6_TCP_LBN) &
212 EFX_MASK32(EFX_RX_CLASS_IPV6_TCP),
213 RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE,
214 (type >> EFX_RX_CLASS_IPV6_UDP_LBN) &
215 EFX_MASK32(EFX_RX_CLASS_IPV6_UDP),
216 RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE,
217 (type >> EFX_RX_CLASS_IPV6_LBN) & EFX_MASK32(EFX_RX_CLASS_IPV6));
219 efx_mcdi_execute(enp, &req);
221 if (req.emr_rc != 0) {
231 EFSYS_PROBE1(fail1, efx_rc_t, rc);
235 #endif /* EFSYS_OPT_RX_SCALE */
237 #if EFSYS_OPT_RX_SCALE
239 efx_mcdi_rss_context_set_key(
241 __in uint32_t rss_context,
242 __in_ecount(n) uint8_t *key,
246 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN,
247 MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN);
250 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
255 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_KEY;
256 req.emr_in_buf = payload;
257 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN;
258 req.emr_out_buf = payload;
259 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN;
261 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
264 EFSYS_ASSERT3U(n, ==, MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
265 if (n != MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN) {
270 memcpy(MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY),
273 efx_mcdi_execute(enp, &req);
275 if (req.emr_rc != 0) {
287 EFSYS_PROBE1(fail1, efx_rc_t, rc);
291 #endif /* EFSYS_OPT_RX_SCALE */
293 #if EFSYS_OPT_RX_SCALE
295 efx_mcdi_rss_context_set_table(
297 __in uint32_t rss_context,
298 __in_ecount(n) unsigned int *table,
302 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN,
303 MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN);
307 if (rss_context == EF10_RSS_CONTEXT_INVALID) {
312 req.emr_cmd = MC_CMD_RSS_CONTEXT_SET_TABLE;
313 req.emr_in_buf = payload;
314 req.emr_in_length = MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN;
315 req.emr_out_buf = payload;
316 req.emr_out_length = MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN;
318 MCDI_IN_SET_DWORD(req, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
322 MCDI_IN2(req, uint8_t, RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE);
325 i < MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN;
327 req_table[i] = (n > 0) ? (uint8_t)table[i % n] : 0;
330 efx_mcdi_execute(enp, &req);
332 if (req.emr_rc != 0) {
342 EFSYS_PROBE1(fail1, efx_rc_t, rc);
346 #endif /* EFSYS_OPT_RX_SCALE */
349 __checkReturn efx_rc_t
353 #if EFSYS_OPT_RX_SCALE
355 if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS,
356 &enp->en_rss_context) == 0) {
358 * Allocated an exclusive RSS context, which allows both the
359 * indirection table and key to be modified.
361 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
362 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
365 * Failed to allocate an exclusive RSS context. Continue
366 * operation without support for RSS. The pseudo-header in
367 * received packets will not contain a Toeplitz hash value.
369 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
370 enp->en_hash_support = EFX_RX_HASH_UNAVAILABLE;
373 #endif /* EFSYS_OPT_RX_SCALE */
380 #if EFSYS_OPT_RX_SCATTER
381 __checkReturn efx_rc_t
382 ef10_rx_scatter_enable(
384 __in unsigned int buf_size)
386 _NOTE(ARGUNUSED(enp, buf_size))
389 #endif /* EFSYS_OPT_RX_SCATTER */
391 #endif /* EFX_OPTS_EF10() */
393 #if EFSYS_OPT_RX_SCALE
394 __checkReturn efx_rc_t
395 ef10_rx_scale_context_alloc(
397 __in efx_rx_scale_context_type_t type,
398 __in uint32_t num_queues,
399 __out uint32_t *rss_contextp)
403 rc = efx_mcdi_rss_context_alloc(enp, type, num_queues, rss_contextp);
410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
413 #endif /* EFSYS_OPT_RX_SCALE */
415 #if EFSYS_OPT_RX_SCALE
416 __checkReturn efx_rc_t
417 ef10_rx_scale_context_free(
419 __in uint32_t rss_context)
423 rc = efx_mcdi_rss_context_free(enp, rss_context);
430 EFSYS_PROBE1(fail1, efx_rc_t, rc);
433 #endif /* EFSYS_OPT_RX_SCALE */
435 #if EFSYS_OPT_RX_SCALE
436 __checkReturn efx_rc_t
437 ef10_rx_scale_mode_set(
439 __in uint32_t rss_context,
440 __in efx_rx_hash_alg_t alg,
441 __in efx_rx_hash_type_t type,
442 __in boolean_t insert)
444 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
447 EFSYS_ASSERT3U(insert, ==, B_TRUE);
449 if ((encp->enc_rx_scale_hash_alg_mask & (1U << alg)) == 0 ||
455 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
456 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
460 rss_context = enp->en_rss_context;
463 if ((rc = efx_mcdi_rss_context_set_flags(enp,
464 rss_context, type)) != 0)
474 EFSYS_PROBE1(fail1, efx_rc_t, rc);
478 #endif /* EFSYS_OPT_RX_SCALE */
480 #if EFSYS_OPT_RX_SCALE
481 __checkReturn efx_rc_t
482 ef10_rx_scale_key_set(
484 __in uint32_t rss_context,
485 __in_ecount(n) uint8_t *key,
490 EFX_STATIC_ASSERT(EFX_RSS_KEY_SIZE ==
491 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
493 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
494 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
498 rss_context = enp->en_rss_context;
501 if ((rc = efx_mcdi_rss_context_set_key(enp, rss_context, key, n)) != 0)
509 EFSYS_PROBE1(fail1, efx_rc_t, rc);
513 #endif /* EFSYS_OPT_RX_SCALE */
515 #if EFSYS_OPT_RX_SCALE
516 __checkReturn efx_rc_t
517 ef10_rx_scale_tbl_set(
519 __in uint32_t rss_context,
520 __in_ecount(n) unsigned int *table,
526 if (rss_context == EFX_RSS_CONTEXT_DEFAULT) {
527 if (enp->en_rss_context_type == EFX_RX_SCALE_UNAVAILABLE) {
531 rss_context = enp->en_rss_context;
534 if ((rc = efx_mcdi_rss_context_set_table(enp,
535 rss_context, table, n)) != 0)
543 EFSYS_PROBE1(fail1, efx_rc_t, rc);
547 #endif /* EFSYS_OPT_RX_SCALE */
552 * EF10 RX pseudo-header (aka Rx prefix)
553 * -------------------------------------
555 * Receive packets are prefixed by an (optional) 14 byte pseudo-header:
557 * +00: Toeplitz hash value.
558 * (32bit little-endian)
559 * +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag.
561 * +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag.
563 * +08: Packet Length. Zero if the RX datapath was in cut-through mode.
564 * (16bit little-endian)
565 * +10: MAC timestamp. Zero if timestamping is not enabled.
566 * (32bit little-endian)
568 * See "The RX Pseudo-header" in SF-109306-TC.
570 * EF10 does not support Rx prefix choice using MC_CMD_GET_RX_PREFIX_ID
571 * and query its layout using MC_CMD_QUERY_RX_PREFIX_ID.
573 static const efx_rx_prefix_layout_t ef10_default_rx_prefix_layout = {
577 [EFX_RX_PREFIX_FIELD_RSS_HASH] =
579 [EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI] =
581 [EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI] =
583 [EFX_RX_PREFIX_FIELD_LENGTH] =
585 [EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP] =
590 #if EFSYS_OPT_RX_PACKED_STREAM
593 * EF10 packed stream Rx prefix layout.
595 * See SF-112241-TC Full speed capture for Huntington and Medford section 4.5.
597 static const efx_rx_prefix_layout_t ef10_packed_stream_rx_prefix_layout = {
601 #define EF10_PS_RX_PREFIX_FIELD(_efx, _ef10) \
602 EFX_RX_PREFIX_FIELD(_efx, ES_DZ_PS_RX_PREFIX_ ## _ef10, B_FALSE)
604 EF10_PS_RX_PREFIX_FIELD(PARTIAL_TSTAMP, TSTAMP),
605 EF10_PS_RX_PREFIX_FIELD(LENGTH, CAP_LEN),
606 EF10_PS_RX_PREFIX_FIELD(ORIG_LENGTH, ORIG_LEN),
608 #undef EF10_PS_RX_PREFIX_FIELD
612 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
614 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
617 * EF10 equal stride super-buffer Rx prefix layout.
619 * See SF-119419-TC DPDK Firmware Driver Interface section 3.4.
621 static const efx_rx_prefix_layout_t ef10_essb_rx_prefix_layout = {
623 .erpl_length = ES_EZ_ESSB_RX_PREFIX_LEN,
625 #define EF10_ESSB_RX_PREFIX_FIELD(_efx, _ef10) \
626 EFX_RX_PREFIX_FIELD(_efx, ES_EZ_ESSB_RX_PREFIX_ ## _ef10, B_FALSE)
628 EF10_ESSB_RX_PREFIX_FIELD(LENGTH, DATA_LEN),
629 EF10_ESSB_RX_PREFIX_FIELD(USER_MARK, MARK),
630 EF10_ESSB_RX_PREFIX_FIELD(RSS_HASH_VALID, HASH_VALID),
631 EF10_ESSB_RX_PREFIX_FIELD(USER_MARK_VALID, MARK_VALID),
632 EF10_ESSB_RX_PREFIX_FIELD(USER_FLAG, MATCH_FLAG),
633 EF10_ESSB_RX_PREFIX_FIELD(RSS_HASH, HASH),
635 #undef EF10_ESSB_RX_PREFIX_FIELD
639 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
641 __checkReturn efx_rc_t
642 ef10_rx_prefix_pktlen(
644 __in uint8_t *buffer,
645 __out uint16_t *lengthp)
647 _NOTE(ARGUNUSED(enp))
650 * The RX pseudo-header contains the packet length, excluding the
651 * pseudo-header. If the hardware receive datapath was operating in
652 * cut-through mode then the length in the RX pseudo-header will be
653 * zero, and the packet length must be obtained from the DMA length
654 * reported in the RX event.
656 *lengthp = buffer[8] | (buffer[9] << 8);
660 #if EFSYS_OPT_RX_SCALE
661 __checkReturn uint32_t
664 __in efx_rx_hash_alg_t func,
665 __in uint8_t *buffer)
667 _NOTE(ARGUNUSED(enp))
670 case EFX_RX_HASHALG_PACKED_STREAM:
671 case EFX_RX_HASHALG_TOEPLITZ:
682 #endif /* EFSYS_OPT_RX_SCALE */
684 #if EFSYS_OPT_RX_PACKED_STREAM
686 * Fake length for RXQ descriptors in packed stream mode
687 * to make hardware happy
689 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
695 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
697 __in unsigned int ndescs,
698 __in unsigned int completed,
699 __in unsigned int added)
706 _NOTE(ARGUNUSED(completed))
708 #if EFSYS_OPT_RX_PACKED_STREAM
710 * Real size of the buffer does not fit into ESF_DZ_RX_KER_BYTE_CNT
711 * and equal to 0 after applying mask. Hardware does not like it.
713 if (erp->er_ev_qstate->eers_rx_packed_stream)
714 size = EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE;
717 /* The client driver must not overfill the queue */
718 EFSYS_ASSERT3U(added - completed + ndescs, <=,
719 EFX_RXQ_LIMIT(erp->er_mask + 1));
721 id = added & (erp->er_mask);
722 for (i = 0; i < ndescs; i++) {
723 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
724 unsigned int, id, efsys_dma_addr_t, addrp[i],
727 EFX_POPULATE_QWORD_3(qword,
728 ESF_DZ_RX_KER_BYTE_CNT, (uint32_t)(size),
729 ESF_DZ_RX_KER_BUF_ADDR_DW0,
730 (uint32_t)(addrp[i] & 0xffffffff),
731 ESF_DZ_RX_KER_BUF_ADDR_DW1,
732 (uint32_t)(addrp[i] >> 32));
734 offset = id * sizeof (efx_qword_t);
735 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
737 id = (id + 1) & (erp->er_mask);
744 __in unsigned int added,
745 __inout unsigned int *pushedp)
747 efx_nic_t *enp = erp->er_enp;
748 unsigned int pushed = *pushedp;
752 /* Hardware has alignment restriction for WPTR */
753 wptr = EFX_P2ALIGN(unsigned int, added, EF10_RX_WPTR_ALIGN);
759 /* Push the populated descriptors out */
760 wptr &= erp->er_mask;
762 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR, wptr);
764 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
765 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
766 EF10_RXQ_DESC_SIZE, wptr, pushed & erp->er_mask);
767 EFSYS_PIO_WRITE_BARRIER();
768 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
769 erp->er_index, &dword, B_FALSE);
772 #if EFSYS_OPT_RX_PACKED_STREAM
775 ef10_rx_qpush_ps_credits(
778 efx_nic_t *enp = erp->er_enp;
780 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
783 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
785 if (rxq_state->eers_rx_packed_stream_credits == 0)
789 * It is a bug if we think that FW has utilized more
790 * credits than it is allowed to have (maximum). However,
791 * make sure that we do not credit more than maximum anyway.
793 credits = MIN(rxq_state->eers_rx_packed_stream_credits,
794 EFX_RX_PACKED_STREAM_MAX_CREDITS);
795 EFX_POPULATE_DWORD_3(dword,
796 ERF_DZ_RX_DESC_MAGIC_DOORBELL, 1,
797 ERF_DZ_RX_DESC_MAGIC_CMD,
798 ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS,
799 ERF_DZ_RX_DESC_MAGIC_DATA, credits);
800 EFX_BAR_VI_WRITED(enp, ER_DZ_RX_DESC_UPD_REG,
801 erp->er_index, &dword, B_FALSE);
803 rxq_state->eers_rx_packed_stream_credits = 0;
807 * In accordance with SF-112241-TC the received data has the following layout:
808 * - 8 byte pseudo-header which consist of:
809 * - 4 byte little-endian timestamp
810 * - 2 byte little-endian captured length in bytes
811 * - 2 byte little-endian original packet length in bytes
812 * - captured packet bytes
813 * - optional padding to align to 64 bytes boundary
814 * - 64 bytes scratch space for the host software
816 __checkReturn uint8_t *
817 ef10_rx_qps_packet_info(
819 __in uint8_t *buffer,
820 __in uint32_t buffer_length,
821 __in uint32_t current_offset,
822 __out uint16_t *lengthp,
823 __out uint32_t *next_offsetp,
824 __out uint32_t *timestamp)
829 efx_evq_rxq_state_t *rxq_state = erp->er_ev_qstate;
831 EFSYS_ASSERT(rxq_state->eers_rx_packed_stream);
833 buffer += current_offset;
834 pkt_start = buffer + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE;
836 qwordp = (efx_qword_t *)buffer;
837 *timestamp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_TSTAMP);
838 *lengthp = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_ORIG_LEN);
839 buf_len = EFX_QWORD_FIELD(*qwordp, ES_DZ_PS_RX_PREFIX_CAP_LEN);
841 buf_len = EFX_P2ROUNDUP(uint16_t,
842 buf_len + EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE,
843 EFX_RX_PACKED_STREAM_ALIGNMENT);
845 current_offset + buf_len + EFX_RX_PACKED_STREAM_ALIGNMENT;
847 EFSYS_ASSERT3U(*next_offsetp, <=, buffer_length);
848 EFSYS_ASSERT3U(current_offset + *lengthp, <, *next_offsetp);
850 if ((*next_offsetp ^ current_offset) &
851 EFX_RX_PACKED_STREAM_MEM_PER_CREDIT)
852 rxq_state->eers_rx_packed_stream_credits++;
860 __checkReturn efx_rc_t
864 efx_nic_t *enp = erp->er_enp;
867 if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0)
874 * EALREADY is not an error, but indicates that the MC has rebooted and
875 * that the RXQ has already been destroyed. Callers need to know that
876 * the RXQ flush has completed to avoid waiting until timeout for a
877 * flush done event that will not be delivered.
880 EFSYS_PROBE1(fail1, efx_rc_t, rc);
890 _NOTE(ARGUNUSED(erp))
894 __checkReturn efx_rc_t
897 __in unsigned int index,
898 __in unsigned int label,
899 __in efx_rxq_type_t type,
900 __in_opt const efx_rxq_type_data_t *type_data,
901 __in efsys_mem_t *esmp,
904 __in unsigned int flags,
908 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
909 efx_mcdi_init_rxq_params_t params;
910 const efx_rx_prefix_layout_t *erpl;
913 _NOTE(ARGUNUSED(id, erp))
915 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << ESF_DZ_RX_QLABEL_WIDTH));
916 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
918 memset(¶ms, 0, sizeof (params));
919 params.buf_size = erp->er_buf_size;
922 case EFX_RXQ_TYPE_DEFAULT:
923 erpl = &ef10_default_rx_prefix_layout;
924 if (type_data == NULL) {
928 erp->er_buf_size = type_data->ertd_default.ed_buf_size;
930 * Ignore EFX_RXQ_FLAG_RSS_HASH since if RSS hash is calculated
931 * it is always delivered from HW in the pseudo-header.
934 #if EFSYS_OPT_RX_PACKED_STREAM
935 case EFX_RXQ_TYPE_PACKED_STREAM:
936 erpl = &ef10_packed_stream_rx_prefix_layout;
937 if (type_data == NULL) {
941 switch (type_data->ertd_packed_stream.eps_buf_size) {
942 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M:
943 params.ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M;
945 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K:
946 params.ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K;
948 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K:
949 params.ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K;
951 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K:
952 params.ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K;
954 case EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K:
955 params.ps_buf_size = MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K;
961 erp->er_buf_size = type_data->ertd_packed_stream.eps_buf_size;
962 /* Packed stream pseudo header does not have RSS hash value */
963 if (flags & EFX_RXQ_FLAG_RSS_HASH) {
968 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
969 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
970 case EFX_RXQ_TYPE_ES_SUPER_BUFFER:
971 erpl = &ef10_essb_rx_prefix_layout;
972 if (type_data == NULL) {
976 params.es_bufs_per_desc =
977 type_data->ertd_es_super_buffer.eessb_bufs_per_desc;
978 params.es_max_dma_len =
979 type_data->ertd_es_super_buffer.eessb_max_dma_len;
980 params.es_buf_stride =
981 type_data->ertd_es_super_buffer.eessb_buf_stride;
982 params.hol_block_timeout =
983 type_data->ertd_es_super_buffer.eessb_hol_block_timeout;
985 * Ignore EFX_RXQ_FLAG_RSS_HASH since if RSS hash is calculated
986 * it is always delivered from HW in the pseudo-header.
989 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
995 #if EFSYS_OPT_RX_PACKED_STREAM
996 if (params.ps_buf_size != 0) {
997 /* Check if datapath firmware supports packed stream mode */
998 if (encp->enc_rx_packed_stream_supported == B_FALSE) {
1002 /* Check if packed stream allows configurable buffer sizes */
1003 if ((params.ps_buf_size != MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M) &&
1004 (encp->enc_rx_var_packed_stream_supported == B_FALSE)) {
1009 #else /* EFSYS_OPT_RX_PACKED_STREAM */
1010 EFSYS_ASSERT(params.ps_buf_size == 0);
1011 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1013 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1014 if (params.es_bufs_per_desc > 0) {
1015 if (encp->enc_rx_es_super_buffer_supported == B_FALSE) {
1019 if (!EFX_IS_P2ALIGNED(uint32_t, params.es_max_dma_len,
1020 EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1024 if (!EFX_IS_P2ALIGNED(uint32_t, params.es_buf_stride,
1025 EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
1030 #else /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1031 EFSYS_ASSERT(params.es_bufs_per_desc == 0);
1032 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1034 if (flags & EFX_RXQ_FLAG_INGRESS_MPORT) {
1039 /* Scatter can only be disabled if the firmware supports doing so */
1040 if (flags & EFX_RXQ_FLAG_SCATTER)
1041 params.disable_scatter = B_FALSE;
1043 params.disable_scatter = encp->enc_rx_disable_scatter_supported;
1045 if (flags & EFX_RXQ_FLAG_INNER_CLASSES)
1046 params.want_inner_classes = B_TRUE;
1048 params.want_inner_classes = B_FALSE;
1050 if ((rc = efx_mcdi_init_rxq(enp, ndescs, eep, label, index,
1051 esmp, ¶ms)) != 0)
1055 erp->er_label = label;
1057 ef10_ev_rxlabel_init(eep, erp, label, type);
1059 erp->er_ev_qstate = &erp->er_eep->ee_rxq_state[label];
1061 erp->er_prefix_layout = *erpl;
1066 EFSYS_PROBE(fail13);
1068 EFSYS_PROBE(fail12);
1069 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1071 EFSYS_PROBE(fail11);
1073 EFSYS_PROBE(fail10);
1076 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1077 #if EFSYS_OPT_RX_PACKED_STREAM
1082 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1085 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1088 #endif /* EFSYS_OPT_RX_ES_SUPER_BUFFER */
1089 #if EFSYS_OPT_RX_PACKED_STREAM
1096 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1098 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1105 __in efx_rxq_t *erp)
1107 efx_evq_t *eep = erp->er_eep;
1108 unsigned int label = erp->er_label;
1110 ef10_ev_rxlabel_fini(eep, label);
1113 #endif /* EFX_OPTS_EF10() */
1117 __in efx_nic_t *enp)
1119 #if EFSYS_OPT_RX_SCALE
1120 if (enp->en_rss_context_type != EFX_RX_SCALE_UNAVAILABLE)
1121 (void) efx_mcdi_rss_context_free(enp, enp->en_rss_context);
1122 enp->en_rss_context = 0;
1123 enp->en_rss_context_type = EFX_RX_SCALE_UNAVAILABLE;
1125 _NOTE(ARGUNUSED(enp))
1126 #endif /* EFSYS_OPT_RX_SCALE */
1129 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */