1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
63 extern __checkReturn efx_rc_t
67 __out efx_family_t *efp,
68 __out unsigned int *membarp);
71 #define EFX_PCI_VENID_SFC 0x1924
72 #define EFX_PCI_VENID_XILINX 0x10EE
74 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
76 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
77 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
78 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
80 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
81 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
82 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
84 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
85 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
87 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
88 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
89 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
91 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
92 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
93 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
95 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
96 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
98 #define EFX_MEM_BAR_SIENA 2
100 #define EFX_MEM_BAR_HUNTINGTON_PF 2
101 #define EFX_MEM_BAR_HUNTINGTON_VF 0
103 #define EFX_MEM_BAR_MEDFORD_PF 2
104 #define EFX_MEM_BAR_MEDFORD_VF 0
106 #define EFX_MEM_BAR_MEDFORD2 0
108 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
109 #define EFX_MEM_BAR_RIVERHEAD 2
117 EFX_ERR_BUFID_DC_OOB,
130 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
132 extern __checkReturn uint32_t
134 __in uint32_t crc_init,
135 __in_ecount(length) uint8_t const *input,
139 /* Type prototypes */
141 typedef struct efx_rxq_s efx_rxq_t;
145 typedef struct efx_nic_s efx_nic_t;
148 extern __checkReturn efx_rc_t
150 __in efx_family_t family,
151 __in efsys_identifier_t *esip,
152 __in efsys_bar_t *esbp,
153 __in efsys_lock_t *eslp,
154 __deref_out efx_nic_t **enpp);
156 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
157 typedef enum efx_fw_variant_e {
158 EFX_FW_VARIANT_FULL_FEATURED,
159 EFX_FW_VARIANT_LOW_LATENCY,
160 EFX_FW_VARIANT_PACKED_STREAM,
161 EFX_FW_VARIANT_HIGH_TX_RATE,
162 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
163 EFX_FW_VARIANT_RULES_ENGINE,
165 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
169 extern __checkReturn efx_rc_t
172 __in efx_fw_variant_t efv);
175 extern __checkReturn efx_rc_t
177 __in efx_nic_t *enp);
180 extern __checkReturn efx_rc_t
182 __in efx_nic_t *enp);
185 extern __checkReturn boolean_t
186 efx_nic_hw_unavailable(
187 __in efx_nic_t *enp);
191 efx_nic_set_hw_unavailable(
192 __in efx_nic_t *enp);
197 extern __checkReturn efx_rc_t
198 efx_nic_register_test(
199 __in efx_nic_t *enp);
201 #endif /* EFSYS_OPT_DIAG */
206 __in efx_nic_t *enp);
211 __in efx_nic_t *enp);
216 __in efx_nic_t *enp);
218 #define EFX_PCIE_LINK_SPEED_GEN1 1
219 #define EFX_PCIE_LINK_SPEED_GEN2 2
220 #define EFX_PCIE_LINK_SPEED_GEN3 3
222 typedef enum efx_pcie_link_performance_e {
223 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
224 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
225 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
226 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
227 } efx_pcie_link_performance_t;
230 extern __checkReturn efx_rc_t
231 efx_nic_calculate_pcie_link_bandwidth(
232 __in uint32_t pcie_link_width,
233 __in uint32_t pcie_link_gen,
234 __out uint32_t *bandwidth_mbpsp);
237 extern __checkReturn efx_rc_t
238 efx_nic_check_pcie_link_speed(
240 __in uint32_t pcie_link_width,
241 __in uint32_t pcie_link_gen,
242 __out efx_pcie_link_performance_t *resultp);
247 /* EF10 architecture NICs require MCDIv2 commands */
248 #define WITH_MCDI_V2 1
251 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
253 typedef enum efx_mcdi_exception_e {
254 EFX_MCDI_EXCEPTION_MC_REBOOT,
255 EFX_MCDI_EXCEPTION_MC_BADASSERT,
256 } efx_mcdi_exception_t;
258 #if EFSYS_OPT_MCDI_LOGGING
259 typedef enum efx_log_msg_e {
261 EFX_LOG_MCDI_REQUEST,
262 EFX_LOG_MCDI_RESPONSE,
264 #endif /* EFSYS_OPT_MCDI_LOGGING */
266 typedef struct efx_mcdi_transport_s {
268 efsys_mem_t *emt_dma_mem;
269 void (*emt_execute)(void *, efx_mcdi_req_t *);
270 void (*emt_ev_cpl)(void *);
271 void (*emt_exception)(void *, efx_mcdi_exception_t);
272 #if EFSYS_OPT_MCDI_LOGGING
273 void (*emt_logger)(void *, efx_log_msg_t,
274 void *, size_t, void *, size_t);
275 #endif /* EFSYS_OPT_MCDI_LOGGING */
276 #if EFSYS_OPT_MCDI_PROXY_AUTH
277 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
278 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
279 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
280 void (*emt_ev_proxy_request)(void *, uint32_t);
281 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
282 } efx_mcdi_transport_t;
285 extern __checkReturn efx_rc_t
288 __in const efx_mcdi_transport_t *mtp);
291 extern __checkReturn efx_rc_t
293 __in efx_nic_t *enp);
298 __in efx_nic_t *enp);
302 efx_mcdi_get_timeout(
304 __in efx_mcdi_req_t *emrp,
305 __out uint32_t *usec_timeoutp);
309 efx_mcdi_request_start(
311 __in efx_mcdi_req_t *emrp,
312 __in boolean_t ev_cpl);
315 extern __checkReturn boolean_t
316 efx_mcdi_request_poll(
317 __in efx_nic_t *enp);
320 extern __checkReturn boolean_t
321 efx_mcdi_request_abort(
322 __in efx_nic_t *enp);
327 __in efx_nic_t *enp);
329 #endif /* EFSYS_OPT_MCDI */
333 #define EFX_NINTR_SIENA 1024
335 typedef enum efx_intr_type_e {
336 EFX_INTR_INVALID = 0,
342 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
345 extern __checkReturn efx_rc_t
348 __in efx_intr_type_t type,
349 __in_opt efsys_mem_t *esmp);
354 __in efx_nic_t *enp);
359 __in efx_nic_t *enp);
363 efx_intr_disable_unlocked(
364 __in efx_nic_t *enp);
366 #define EFX_INTR_NEVQS 32
369 extern __checkReturn efx_rc_t
372 __in unsigned int level);
376 efx_intr_status_line(
378 __out boolean_t *fatalp,
379 __out uint32_t *maskp);
383 efx_intr_status_message(
385 __in unsigned int message,
386 __out boolean_t *fatalp);
391 __in efx_nic_t *enp);
396 __in efx_nic_t *enp);
400 #if EFSYS_OPT_MAC_STATS
402 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
403 typedef enum efx_mac_stat_e {
406 EFX_MAC_RX_UNICST_PKTS,
407 EFX_MAC_RX_MULTICST_PKTS,
408 EFX_MAC_RX_BRDCST_PKTS,
409 EFX_MAC_RX_PAUSE_PKTS,
410 EFX_MAC_RX_LE_64_PKTS,
411 EFX_MAC_RX_65_TO_127_PKTS,
412 EFX_MAC_RX_128_TO_255_PKTS,
413 EFX_MAC_RX_256_TO_511_PKTS,
414 EFX_MAC_RX_512_TO_1023_PKTS,
415 EFX_MAC_RX_1024_TO_15XX_PKTS,
416 EFX_MAC_RX_GE_15XX_PKTS,
418 EFX_MAC_RX_FCS_ERRORS,
419 EFX_MAC_RX_DROP_EVENTS,
420 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
421 EFX_MAC_RX_SYMBOL_ERRORS,
422 EFX_MAC_RX_ALIGN_ERRORS,
423 EFX_MAC_RX_INTERNAL_ERRORS,
424 EFX_MAC_RX_JABBER_PKTS,
425 EFX_MAC_RX_LANE0_CHAR_ERR,
426 EFX_MAC_RX_LANE1_CHAR_ERR,
427 EFX_MAC_RX_LANE2_CHAR_ERR,
428 EFX_MAC_RX_LANE3_CHAR_ERR,
429 EFX_MAC_RX_LANE0_DISP_ERR,
430 EFX_MAC_RX_LANE1_DISP_ERR,
431 EFX_MAC_RX_LANE2_DISP_ERR,
432 EFX_MAC_RX_LANE3_DISP_ERR,
433 EFX_MAC_RX_MATCH_FAULT,
434 EFX_MAC_RX_NODESC_DROP_CNT,
437 EFX_MAC_TX_UNICST_PKTS,
438 EFX_MAC_TX_MULTICST_PKTS,
439 EFX_MAC_TX_BRDCST_PKTS,
440 EFX_MAC_TX_PAUSE_PKTS,
441 EFX_MAC_TX_LE_64_PKTS,
442 EFX_MAC_TX_65_TO_127_PKTS,
443 EFX_MAC_TX_128_TO_255_PKTS,
444 EFX_MAC_TX_256_TO_511_PKTS,
445 EFX_MAC_TX_512_TO_1023_PKTS,
446 EFX_MAC_TX_1024_TO_15XX_PKTS,
447 EFX_MAC_TX_GE_15XX_PKTS,
449 EFX_MAC_TX_SGL_COL_PKTS,
450 EFX_MAC_TX_MULT_COL_PKTS,
451 EFX_MAC_TX_EX_COL_PKTS,
452 EFX_MAC_TX_LATE_COL_PKTS,
454 EFX_MAC_TX_EX_DEF_PKTS,
455 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
456 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
457 EFX_MAC_PM_TRUNC_VFIFO_FULL,
458 EFX_MAC_PM_DISCARD_VFIFO_FULL,
459 EFX_MAC_PM_TRUNC_QBB,
460 EFX_MAC_PM_DISCARD_QBB,
461 EFX_MAC_PM_DISCARD_MAPPING,
462 EFX_MAC_RXDP_Q_DISABLED_PKTS,
463 EFX_MAC_RXDP_DI_DROPPED_PKTS,
464 EFX_MAC_RXDP_STREAMING_PKTS,
465 EFX_MAC_RXDP_HLB_FETCH,
466 EFX_MAC_RXDP_HLB_WAIT,
467 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
468 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
469 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
470 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
471 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
472 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
473 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
474 EFX_MAC_VADAPTER_RX_BAD_BYTES,
475 EFX_MAC_VADAPTER_RX_OVERFLOW,
476 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
477 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
478 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
479 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
480 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
481 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
482 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
483 EFX_MAC_VADAPTER_TX_BAD_BYTES,
484 EFX_MAC_VADAPTER_TX_OVERFLOW,
485 EFX_MAC_FEC_UNCORRECTED_ERRORS,
486 EFX_MAC_FEC_CORRECTED_ERRORS,
487 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
488 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
489 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
490 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
491 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
492 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
493 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
494 EFX_MAC_CTPIO_OVERFLOW_FAIL,
495 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
496 EFX_MAC_CTPIO_TIMEOUT_FAIL,
497 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
498 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
499 EFX_MAC_CTPIO_INVALID_WR_FAIL,
500 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
501 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
502 EFX_MAC_CTPIO_RUNT_FALLBACK,
503 EFX_MAC_CTPIO_SUCCESS,
504 EFX_MAC_CTPIO_FALLBACK,
505 EFX_MAC_CTPIO_POISON,
507 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
508 EFX_MAC_RXDP_HLB_IDLE,
509 EFX_MAC_RXDP_HLB_TIMEOUT,
513 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
515 #endif /* EFSYS_OPT_MAC_STATS */
517 typedef enum efx_link_mode_e {
518 EFX_LINK_UNKNOWN = 0,
534 #define EFX_MAC_ADDR_LEN 6
536 #define EFX_VNI_OR_VSID_LEN 3
538 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
540 #define EFX_MAC_MULTICAST_LIST_MAX 256
542 #define EFX_MAC_SDU_MAX 9202
544 #define EFX_MAC_PDU_ADJUSTMENT \
548 + /* bug16011 */ 16) \
550 #define EFX_MAC_PDU(_sdu) \
551 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
554 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
555 * the SDU rounded up slightly.
557 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
559 #define EFX_MAC_PDU_MIN 60
560 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
563 extern __checkReturn efx_rc_t
569 extern __checkReturn efx_rc_t
575 extern __checkReturn efx_rc_t
581 extern __checkReturn efx_rc_t
584 __in boolean_t all_unicst,
585 __in boolean_t mulcst,
586 __in boolean_t all_mulcst,
587 __in boolean_t brdcst);
591 efx_mac_filter_get_all_ucast_mcast(
593 __out boolean_t *all_unicst,
594 __out boolean_t *all_mulcst);
597 extern __checkReturn efx_rc_t
598 efx_mac_multicast_list_set(
600 __in_ecount(6*count) uint8_t const *addrs,
604 extern __checkReturn efx_rc_t
605 efx_mac_filter_default_rxq_set(
608 __in boolean_t using_rss);
612 efx_mac_filter_default_rxq_clear(
613 __in efx_nic_t *enp);
616 extern __checkReturn efx_rc_t
619 __in boolean_t enabled);
622 extern __checkReturn efx_rc_t
625 __out boolean_t *mac_upp);
627 #define EFX_FCNTL_RESPOND 0x00000001
628 #define EFX_FCNTL_GENERATE 0x00000002
631 extern __checkReturn efx_rc_t
634 __in unsigned int fcntl,
635 __in boolean_t autoneg);
641 __out unsigned int *fcntl_wantedp,
642 __out unsigned int *fcntl_linkp);
645 #if EFSYS_OPT_MAC_STATS
650 extern __checkReturn const char *
653 __in unsigned int id);
655 #endif /* EFSYS_OPT_NAMES */
657 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
659 #define EFX_MAC_STATS_MASK_NPAGES \
660 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
661 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
662 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
665 * Get mask of MAC statistics supported by the hardware.
667 * If mask_size is insufficient to return the mask, EINVAL error is
668 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
669 * (which is sizeof (uint32_t)) is sufficient.
672 extern __checkReturn efx_rc_t
673 efx_mac_stats_get_mask(
675 __out_bcount(mask_size) uint32_t *maskp,
676 __in size_t mask_size);
678 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
679 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
680 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
684 extern __checkReturn efx_rc_t
686 __in efx_nic_t *enp);
689 * Upload mac statistics supported by the hardware into the given buffer.
691 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
692 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
694 * The hardware will only DMA statistics that it understands (of course).
695 * Drivers should not make any assumptions about which statistics are
696 * supported, especially when the statistics are generated by firmware.
698 * Thus, drivers should zero this buffer before use, so that not-understood
699 * statistics read back as zero.
702 extern __checkReturn efx_rc_t
703 efx_mac_stats_upload(
705 __in efsys_mem_t *esmp);
708 extern __checkReturn efx_rc_t
709 efx_mac_stats_periodic(
711 __in efsys_mem_t *esmp,
712 __in uint16_t period_ms,
713 __in boolean_t events);
716 extern __checkReturn efx_rc_t
717 efx_mac_stats_update(
719 __in efsys_mem_t *esmp,
720 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
721 __inout_opt uint32_t *generationp);
723 #endif /* EFSYS_OPT_MAC_STATS */
727 typedef enum efx_mon_type_e {
740 __in efx_nic_t *enp);
742 #endif /* EFSYS_OPT_NAMES */
745 extern __checkReturn efx_rc_t
747 __in efx_nic_t *enp);
749 #if EFSYS_OPT_MON_STATS
751 #define EFX_MON_STATS_PAGE_SIZE 0x100
752 #define EFX_MON_MASK_ELEMENT_SIZE 32
754 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
755 typedef enum efx_mon_stat_e {
756 EFX_MON_STAT_CONTROLLER_TEMP,
757 EFX_MON_STAT_PHY_COMMON_TEMP,
758 EFX_MON_STAT_CONTROLLER_COOLING,
759 EFX_MON_STAT_PHY0_TEMP,
760 EFX_MON_STAT_PHY0_COOLING,
761 EFX_MON_STAT_PHY1_TEMP,
762 EFX_MON_STAT_PHY1_COOLING,
768 EFX_MON_STAT_IN_12V0,
769 EFX_MON_STAT_IN_1V2A,
770 EFX_MON_STAT_IN_VREF,
771 EFX_MON_STAT_OUT_VAOE,
772 EFX_MON_STAT_AOE_TEMP,
773 EFX_MON_STAT_PSU_AOE_TEMP,
774 EFX_MON_STAT_PSU_TEMP,
780 EFX_MON_STAT_IN_VAOE,
781 EFX_MON_STAT_OUT_IAOE,
782 EFX_MON_STAT_IN_IAOE,
783 EFX_MON_STAT_NIC_POWER,
785 EFX_MON_STAT_IN_I0V9,
786 EFX_MON_STAT_IN_I1V2,
787 EFX_MON_STAT_IN_0V9_ADC,
788 EFX_MON_STAT_CONTROLLER_2_TEMP,
789 EFX_MON_STAT_VREG_INTERNAL_TEMP,
790 EFX_MON_STAT_VREG_0V9_TEMP,
791 EFX_MON_STAT_VREG_1V2_TEMP,
792 EFX_MON_STAT_CONTROLLER_VPTAT,
793 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
794 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
795 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
796 EFX_MON_STAT_AMBIENT_TEMP,
797 EFX_MON_STAT_AIRFLOW,
798 EFX_MON_STAT_VDD08D_VSS08D_CSR,
799 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
800 EFX_MON_STAT_HOTPOINT_TEMP,
801 EFX_MON_STAT_PHY_POWER_PORT0,
802 EFX_MON_STAT_PHY_POWER_PORT1,
803 EFX_MON_STAT_MUM_VCC,
804 EFX_MON_STAT_IN_0V9_A,
805 EFX_MON_STAT_IN_I0V9_A,
806 EFX_MON_STAT_VREG_0V9_A_TEMP,
807 EFX_MON_STAT_IN_0V9_B,
808 EFX_MON_STAT_IN_I0V9_B,
809 EFX_MON_STAT_VREG_0V9_B_TEMP,
810 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
811 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
812 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
813 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
814 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
815 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
816 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
817 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
818 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
819 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
820 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
821 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
822 EFX_MON_STAT_SODIMM_VOUT,
823 EFX_MON_STAT_SODIMM_0_TEMP,
824 EFX_MON_STAT_SODIMM_1_TEMP,
825 EFX_MON_STAT_PHY0_VCC,
826 EFX_MON_STAT_PHY1_VCC,
827 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
828 EFX_MON_STAT_BOARD_FRONT_TEMP,
829 EFX_MON_STAT_BOARD_BACK_TEMP,
830 EFX_MON_STAT_IN_I1V8,
831 EFX_MON_STAT_IN_I2V5,
832 EFX_MON_STAT_IN_I3V3,
833 EFX_MON_STAT_IN_I12V0,
835 EFX_MON_STAT_IN_I1V3,
839 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
841 typedef enum efx_mon_stat_state_e {
842 EFX_MON_STAT_STATE_OK = 0,
843 EFX_MON_STAT_STATE_WARNING = 1,
844 EFX_MON_STAT_STATE_FATAL = 2,
845 EFX_MON_STAT_STATE_BROKEN = 3,
846 EFX_MON_STAT_STATE_NO_READING = 4,
847 } efx_mon_stat_state_t;
849 typedef enum efx_mon_stat_unit_e {
850 EFX_MON_STAT_UNIT_UNKNOWN = 0,
851 EFX_MON_STAT_UNIT_BOOL,
852 EFX_MON_STAT_UNIT_TEMP_C,
853 EFX_MON_STAT_UNIT_VOLTAGE_MV,
854 EFX_MON_STAT_UNIT_CURRENT_MA,
855 EFX_MON_STAT_UNIT_POWER_W,
856 EFX_MON_STAT_UNIT_RPM,
858 } efx_mon_stat_unit_t;
860 typedef struct efx_mon_stat_value_s {
862 efx_mon_stat_state_t emsv_state;
863 efx_mon_stat_unit_t emsv_unit;
864 } efx_mon_stat_value_t;
866 typedef struct efx_mon_limit_value_s {
867 uint16_t emlv_warning_min;
868 uint16_t emlv_warning_max;
869 uint16_t emlv_fatal_min;
870 uint16_t emlv_fatal_max;
871 } efx_mon_stat_limits_t;
873 typedef enum efx_mon_stat_portmask_e {
874 EFX_MON_STAT_PORTMAP_NONE = 0,
875 EFX_MON_STAT_PORTMAP_PORT0 = 1,
876 EFX_MON_STAT_PORTMAP_PORT1 = 2,
877 EFX_MON_STAT_PORTMAP_PORT2 = 3,
878 EFX_MON_STAT_PORTMAP_PORT3 = 4,
879 EFX_MON_STAT_PORTMAP_ALL = (-1),
880 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
881 } efx_mon_stat_portmask_t;
889 __in efx_mon_stat_t id);
893 efx_mon_stat_description(
895 __in efx_mon_stat_t id);
897 #endif /* EFSYS_OPT_NAMES */
900 extern __checkReturn boolean_t
901 efx_mon_mcdi_to_efx_stat(
903 __out efx_mon_stat_t *statp);
906 extern __checkReturn boolean_t
907 efx_mon_get_stat_unit(
908 __in efx_mon_stat_t stat,
909 __out efx_mon_stat_unit_t *unitp);
912 extern __checkReturn boolean_t
913 efx_mon_get_stat_portmap(
914 __in efx_mon_stat_t stat,
915 __out efx_mon_stat_portmask_t *maskp);
918 extern __checkReturn efx_rc_t
919 efx_mon_stats_update(
921 __in efsys_mem_t *esmp,
922 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
925 extern __checkReturn efx_rc_t
926 efx_mon_limits_update(
928 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
930 #endif /* EFSYS_OPT_MON_STATS */
935 __in efx_nic_t *enp);
940 extern __checkReturn efx_rc_t
942 __in efx_nic_t *enp);
944 #if EFSYS_OPT_PHY_LED_CONTROL
946 typedef enum efx_phy_led_mode_e {
947 EFX_PHY_LED_DEFAULT = 0,
952 } efx_phy_led_mode_t;
955 extern __checkReturn efx_rc_t
958 __in efx_phy_led_mode_t mode);
960 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
963 extern __checkReturn efx_rc_t
965 __in efx_nic_t *enp);
967 #if EFSYS_OPT_LOOPBACK
969 typedef enum efx_loopback_type_e {
970 EFX_LOOPBACK_OFF = 0,
971 EFX_LOOPBACK_DATA = 1,
972 EFX_LOOPBACK_GMAC = 2,
973 EFX_LOOPBACK_XGMII = 3,
974 EFX_LOOPBACK_XGXS = 4,
975 EFX_LOOPBACK_XAUI = 5,
976 EFX_LOOPBACK_GMII = 6,
977 EFX_LOOPBACK_SGMII = 7,
978 EFX_LOOPBACK_XGBR = 8,
979 EFX_LOOPBACK_XFI = 9,
980 EFX_LOOPBACK_XAUI_FAR = 10,
981 EFX_LOOPBACK_GMII_FAR = 11,
982 EFX_LOOPBACK_SGMII_FAR = 12,
983 EFX_LOOPBACK_XFI_FAR = 13,
984 EFX_LOOPBACK_GPHY = 14,
985 EFX_LOOPBACK_PHY_XS = 15,
986 EFX_LOOPBACK_PCS = 16,
987 EFX_LOOPBACK_PMA_PMD = 17,
988 EFX_LOOPBACK_XPORT = 18,
989 EFX_LOOPBACK_XGMII_WS = 19,
990 EFX_LOOPBACK_XAUI_WS = 20,
991 EFX_LOOPBACK_XAUI_WS_FAR = 21,
992 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
993 EFX_LOOPBACK_GMII_WS = 23,
994 EFX_LOOPBACK_XFI_WS = 24,
995 EFX_LOOPBACK_XFI_WS_FAR = 25,
996 EFX_LOOPBACK_PHYXS_WS = 26,
997 EFX_LOOPBACK_PMA_INT = 27,
998 EFX_LOOPBACK_SD_NEAR = 28,
999 EFX_LOOPBACK_SD_FAR = 29,
1000 EFX_LOOPBACK_PMA_INT_WS = 30,
1001 EFX_LOOPBACK_SD_FEP2_WS = 31,
1002 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1003 EFX_LOOPBACK_SD_FEP_WS = 33,
1004 EFX_LOOPBACK_SD_FES_WS = 34,
1005 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1006 EFX_LOOPBACK_DATA_WS = 36,
1007 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1009 } efx_loopback_type_t;
1011 typedef enum efx_loopback_kind_e {
1012 EFX_LOOPBACK_KIND_OFF = 0,
1013 EFX_LOOPBACK_KIND_ALL,
1014 EFX_LOOPBACK_KIND_MAC,
1015 EFX_LOOPBACK_KIND_PHY,
1017 } efx_loopback_kind_t;
1022 __in efx_loopback_kind_t loopback_kind,
1023 __out efx_qword_t *maskp);
1026 extern __checkReturn efx_rc_t
1027 efx_port_loopback_set(
1028 __in efx_nic_t *enp,
1029 __in efx_link_mode_t link_mode,
1030 __in efx_loopback_type_t type);
1035 extern __checkReturn const char *
1036 efx_loopback_type_name(
1037 __in efx_nic_t *enp,
1038 __in efx_loopback_type_t type);
1040 #endif /* EFSYS_OPT_NAMES */
1042 #endif /* EFSYS_OPT_LOOPBACK */
1045 extern __checkReturn efx_rc_t
1047 __in efx_nic_t *enp,
1048 __out_opt efx_link_mode_t *link_modep);
1053 __in efx_nic_t *enp);
1055 typedef enum efx_phy_cap_type_e {
1056 EFX_PHY_CAP_INVALID = 0,
1061 EFX_PHY_CAP_1000HDX,
1062 EFX_PHY_CAP_1000FDX,
1063 EFX_PHY_CAP_10000FDX,
1067 EFX_PHY_CAP_40000FDX,
1069 EFX_PHY_CAP_100000FDX,
1070 EFX_PHY_CAP_25000FDX,
1071 EFX_PHY_CAP_50000FDX,
1072 EFX_PHY_CAP_BASER_FEC,
1073 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1075 EFX_PHY_CAP_RS_FEC_REQUESTED,
1076 EFX_PHY_CAP_25G_BASER_FEC,
1077 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1079 } efx_phy_cap_type_t;
1082 #define EFX_PHY_CAP_CURRENT 0x00000000
1083 #define EFX_PHY_CAP_DEFAULT 0x00000001
1084 #define EFX_PHY_CAP_PERM 0x00000002
1088 efx_phy_adv_cap_get(
1089 __in efx_nic_t *enp,
1091 __out uint32_t *maskp);
1094 extern __checkReturn efx_rc_t
1095 efx_phy_adv_cap_set(
1096 __in efx_nic_t *enp,
1097 __in uint32_t mask);
1102 __in efx_nic_t *enp,
1103 __out uint32_t *maskp);
1106 extern __checkReturn efx_rc_t
1108 __in efx_nic_t *enp,
1109 __out uint32_t *ouip);
1111 typedef enum efx_phy_media_type_e {
1112 EFX_PHY_MEDIA_INVALID = 0,
1117 EFX_PHY_MEDIA_SFP_PLUS,
1118 EFX_PHY_MEDIA_BASE_T,
1119 EFX_PHY_MEDIA_QSFP_PLUS,
1120 EFX_PHY_MEDIA_NTYPES
1121 } efx_phy_media_type_t;
1124 * Get the type of medium currently used. If the board has ports for
1125 * modules, a module is present, and we recognise the media type of
1126 * the module, then this will be the media type of the module.
1127 * Otherwise it will be the media type of the port.
1131 efx_phy_media_type_get(
1132 __in efx_nic_t *enp,
1133 __out efx_phy_media_type_t *typep);
1136 * 2-wire device address of the base information in accordance with SFF-8472
1137 * Diagnostic Monitoring Interface for Optical Transceivers section
1138 * 4 Memory Organization.
1140 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1143 * 2-wire device address of the digital diagnostics monitoring interface
1144 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1145 * Transceivers section 4 Memory Organization.
1147 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1150 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1151 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1154 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1157 * Maximum accessible data offset for PHY module information.
1159 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1163 extern __checkReturn efx_rc_t
1164 efx_phy_module_get_info(
1165 __in efx_nic_t *enp,
1166 __in uint8_t dev_addr,
1169 __out_bcount(len) uint8_t *data);
1171 #if EFSYS_OPT_PHY_STATS
1173 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1174 typedef enum efx_phy_stat_e {
1176 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1177 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1178 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1179 EFX_PHY_STAT_PMA_PMD_REV_A,
1180 EFX_PHY_STAT_PMA_PMD_REV_B,
1181 EFX_PHY_STAT_PMA_PMD_REV_C,
1182 EFX_PHY_STAT_PMA_PMD_REV_D,
1183 EFX_PHY_STAT_PCS_LINK_UP,
1184 EFX_PHY_STAT_PCS_RX_FAULT,
1185 EFX_PHY_STAT_PCS_TX_FAULT,
1186 EFX_PHY_STAT_PCS_BER,
1187 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1188 EFX_PHY_STAT_PHY_XS_LINK_UP,
1189 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1190 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1191 EFX_PHY_STAT_PHY_XS_ALIGN,
1192 EFX_PHY_STAT_PHY_XS_SYNC_A,
1193 EFX_PHY_STAT_PHY_XS_SYNC_B,
1194 EFX_PHY_STAT_PHY_XS_SYNC_C,
1195 EFX_PHY_STAT_PHY_XS_SYNC_D,
1196 EFX_PHY_STAT_AN_LINK_UP,
1197 EFX_PHY_STAT_AN_MASTER,
1198 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1199 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1200 EFX_PHY_STAT_CL22EXT_LINK_UP,
1205 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1206 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1207 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1208 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1209 EFX_PHY_STAT_AN_COMPLETE,
1210 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1211 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1212 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1213 EFX_PHY_STAT_PCS_FW_VERSION_0,
1214 EFX_PHY_STAT_PCS_FW_VERSION_1,
1215 EFX_PHY_STAT_PCS_FW_VERSION_2,
1216 EFX_PHY_STAT_PCS_FW_VERSION_3,
1217 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1218 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1219 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1220 EFX_PHY_STAT_PCS_OP_MODE,
1224 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1231 __in efx_nic_t *enp,
1232 __in efx_phy_stat_t stat);
1234 #endif /* EFSYS_OPT_NAMES */
1236 #define EFX_PHY_STATS_SIZE 0x100
1239 extern __checkReturn efx_rc_t
1240 efx_phy_stats_update(
1241 __in efx_nic_t *enp,
1242 __in efsys_mem_t *esmp,
1243 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1245 #endif /* EFSYS_OPT_PHY_STATS */
1250 typedef enum efx_bist_type_e {
1251 EFX_BIST_TYPE_UNKNOWN,
1252 EFX_BIST_TYPE_PHY_NORMAL,
1253 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1254 EFX_BIST_TYPE_PHY_CABLE_LONG,
1255 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1256 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1257 EFX_BIST_TYPE_REG, /* Test the register memories */
1258 EFX_BIST_TYPE_NTYPES,
1261 typedef enum efx_bist_result_e {
1262 EFX_BIST_RESULT_UNKNOWN,
1263 EFX_BIST_RESULT_RUNNING,
1264 EFX_BIST_RESULT_PASSED,
1265 EFX_BIST_RESULT_FAILED,
1266 } efx_bist_result_t;
1268 typedef enum efx_phy_cable_status_e {
1269 EFX_PHY_CABLE_STATUS_OK,
1270 EFX_PHY_CABLE_STATUS_INVALID,
1271 EFX_PHY_CABLE_STATUS_OPEN,
1272 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1273 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1274 EFX_PHY_CABLE_STATUS_BUSY,
1275 } efx_phy_cable_status_t;
1277 typedef enum efx_bist_value_e {
1278 EFX_BIST_PHY_CABLE_LENGTH_A,
1279 EFX_BIST_PHY_CABLE_LENGTH_B,
1280 EFX_BIST_PHY_CABLE_LENGTH_C,
1281 EFX_BIST_PHY_CABLE_LENGTH_D,
1282 EFX_BIST_PHY_CABLE_STATUS_A,
1283 EFX_BIST_PHY_CABLE_STATUS_B,
1284 EFX_BIST_PHY_CABLE_STATUS_C,
1285 EFX_BIST_PHY_CABLE_STATUS_D,
1286 EFX_BIST_FAULT_CODE,
1288 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1294 EFX_BIST_MEM_EXPECT,
1295 EFX_BIST_MEM_ACTUAL,
1297 EFX_BIST_MEM_ECC_PARITY,
1298 EFX_BIST_MEM_ECC_FATAL,
1303 extern __checkReturn efx_rc_t
1304 efx_bist_enable_offline(
1305 __in efx_nic_t *enp);
1308 extern __checkReturn efx_rc_t
1310 __in efx_nic_t *enp,
1311 __in efx_bist_type_t type);
1314 extern __checkReturn efx_rc_t
1316 __in efx_nic_t *enp,
1317 __in efx_bist_type_t type,
1318 __out efx_bist_result_t *resultp,
1319 __out_opt uint32_t *value_maskp,
1320 __out_ecount_opt(count) unsigned long *valuesp,
1326 __in efx_nic_t *enp,
1327 __in efx_bist_type_t type);
1329 #endif /* EFSYS_OPT_BIST */
1331 #define EFX_FEATURE_IPV6 0x00000001
1332 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1333 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1334 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1335 #define EFX_FEATURE_MCDI 0x00000020
1336 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1337 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1338 #define EFX_FEATURE_TURBO 0x00000100
1339 #define EFX_FEATURE_MCDI_DMA 0x00000200
1340 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1341 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1342 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1343 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1344 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1345 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1347 typedef enum efx_tunnel_protocol_e {
1348 EFX_TUNNEL_PROTOCOL_NONE = 0,
1349 EFX_TUNNEL_PROTOCOL_VXLAN,
1350 EFX_TUNNEL_PROTOCOL_GENEVE,
1351 EFX_TUNNEL_PROTOCOL_NVGRE,
1353 } efx_tunnel_protocol_t;
1355 typedef enum efx_vi_window_shift_e {
1356 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1357 EFX_VI_WINDOW_SHIFT_8K = 13,
1358 EFX_VI_WINDOW_SHIFT_16K = 14,
1359 EFX_VI_WINDOW_SHIFT_64K = 16,
1360 } efx_vi_window_shift_t;
1362 typedef struct efx_nic_cfg_s {
1363 uint32_t enc_board_type;
1364 uint32_t enc_phy_type;
1366 char enc_phy_name[21];
1368 char enc_phy_revision[21];
1369 efx_mon_type_t enc_mon_type;
1370 #if EFSYS_OPT_MON_STATS
1371 uint32_t enc_mon_stat_dma_buf_size;
1372 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1374 unsigned int enc_features;
1375 efx_vi_window_shift_t enc_vi_window_shift;
1376 uint8_t enc_mac_addr[6];
1377 uint8_t enc_port; /* PHY port number */
1378 uint32_t enc_intr_vec_base;
1379 uint32_t enc_intr_limit;
1380 uint32_t enc_evq_limit;
1381 uint32_t enc_txq_limit;
1382 uint32_t enc_rxq_limit;
1383 uint32_t enc_evq_max_nevs;
1384 uint32_t enc_evq_min_nevs;
1385 uint32_t enc_rxq_max_ndescs;
1386 uint32_t enc_rxq_min_ndescs;
1387 uint32_t enc_txq_max_ndescs;
1388 uint32_t enc_txq_min_ndescs;
1389 uint32_t enc_buftbl_limit;
1390 uint32_t enc_piobuf_limit;
1391 uint32_t enc_piobuf_size;
1392 uint32_t enc_piobuf_min_alloc_size;
1393 uint32_t enc_evq_timer_quantum_ns;
1394 uint32_t enc_evq_timer_max_us;
1395 uint32_t enc_clk_mult;
1396 uint32_t enc_ev_desc_size;
1397 uint32_t enc_rx_desc_size;
1398 uint32_t enc_tx_desc_size;
1399 uint32_t enc_rx_prefix_size;
1400 uint32_t enc_rx_buf_align_start;
1401 uint32_t enc_rx_buf_align_end;
1402 #if EFSYS_OPT_RX_SCALE
1403 uint32_t enc_rx_scale_max_exclusive_contexts;
1405 * Mask of supported hash algorithms.
1406 * Hash algorithm types are used as the bit indices.
1408 uint32_t enc_rx_scale_hash_alg_mask;
1410 * Indicates whether port numbers can be included to the
1411 * input data for hash computation.
1413 boolean_t enc_rx_scale_l4_hash_supported;
1414 boolean_t enc_rx_scale_additional_modes_supported;
1415 #endif /* EFSYS_OPT_RX_SCALE */
1416 #if EFSYS_OPT_LOOPBACK
1417 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1418 #endif /* EFSYS_OPT_LOOPBACK */
1419 #if EFSYS_OPT_PHY_FLAGS
1420 uint32_t enc_phy_flags_mask;
1421 #endif /* EFSYS_OPT_PHY_FLAGS */
1422 #if EFSYS_OPT_PHY_LED_CONTROL
1423 uint32_t enc_led_mask;
1424 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1425 #if EFSYS_OPT_PHY_STATS
1426 uint64_t enc_phy_stat_mask;
1427 #endif /* EFSYS_OPT_PHY_STATS */
1429 uint8_t enc_mcdi_mdio_channel;
1430 #if EFSYS_OPT_PHY_STATS
1431 uint32_t enc_mcdi_phy_stat_mask;
1432 #endif /* EFSYS_OPT_PHY_STATS */
1433 #if EFSYS_OPT_MON_STATS
1434 uint32_t *enc_mcdi_sensor_maskp;
1435 uint32_t enc_mcdi_sensor_mask_size;
1436 #endif /* EFSYS_OPT_MON_STATS */
1437 #endif /* EFSYS_OPT_MCDI */
1439 uint32_t enc_bist_mask;
1440 #endif /* EFSYS_OPT_BIST */
1444 uint32_t enc_privilege_mask;
1445 #endif /* EFX_OPTS_EF10() */
1446 boolean_t enc_bug26807_workaround;
1447 boolean_t enc_bug35388_workaround;
1448 boolean_t enc_bug41750_workaround;
1449 boolean_t enc_bug61265_workaround;
1450 boolean_t enc_bug61297_workaround;
1451 boolean_t enc_rx_batching_enabled;
1452 /* Maximum number of descriptors completed in an rx event. */
1453 uint32_t enc_rx_batch_max;
1454 /* Number of rx descriptors the hardware requires for a push. */
1455 uint32_t enc_rx_push_align;
1456 /* Maximum amount of data in DMA descriptor */
1457 uint32_t enc_tx_dma_desc_size_max;
1459 * Boundary which DMA descriptor data must not cross or 0 if no
1462 uint32_t enc_tx_dma_desc_boundary;
1464 * Maximum number of bytes into the packet the TCP header can start for
1465 * the hardware to apply TSO packet edits.
1467 uint32_t enc_tx_tso_tcp_header_offset_limit;
1468 boolean_t enc_fw_assisted_tso_enabled;
1469 boolean_t enc_fw_assisted_tso_v2_enabled;
1470 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1471 /* Number of TSO contexts on the NIC (FATSOv2) */
1472 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1473 boolean_t enc_hw_tx_insert_vlan_enabled;
1474 /* Number of PFs on the NIC */
1475 uint32_t enc_hw_pf_count;
1476 /* Datapath firmware vadapter/vport/vswitch support */
1477 boolean_t enc_datapath_cap_evb;
1478 /* Datapath firmware vport reconfigure support */
1479 boolean_t enc_vport_reconfigure_supported;
1480 boolean_t enc_rx_disable_scatter_supported;
1481 boolean_t enc_allow_set_mac_with_installed_filters;
1482 boolean_t enc_enhanced_set_mac_supported;
1483 boolean_t enc_init_evq_v2_supported;
1484 boolean_t enc_no_cont_ev_mode_supported;
1485 boolean_t enc_init_rxq_with_buffer_size;
1486 boolean_t enc_rx_packed_stream_supported;
1487 boolean_t enc_rx_var_packed_stream_supported;
1488 boolean_t enc_rx_es_super_buffer_supported;
1489 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1490 boolean_t enc_pm_and_rxdp_counters;
1491 boolean_t enc_mac_stats_40g_tx_size_bins;
1492 uint32_t enc_tunnel_encapsulations_supported;
1494 * NIC global maximum for unique UDP tunnel ports shared by all
1497 uint32_t enc_tunnel_config_udp_entries_max;
1498 /* External port identifier */
1499 uint8_t enc_external_port;
1500 uint32_t enc_mcdi_max_payload_length;
1501 /* VPD may be per-PF or global */
1502 boolean_t enc_vpd_is_global;
1503 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1504 uint32_t enc_required_pcie_bandwidth_mbps;
1505 uint32_t enc_max_pcie_link_gen;
1506 /* Firmware verifies integrity of NVRAM updates */
1507 boolean_t enc_nvram_update_verify_result_supported;
1508 /* Firmware supports polled NVRAM updates on select partitions */
1509 boolean_t enc_nvram_update_poll_verify_result_supported;
1510 /* Firmware accepts updates via the BUNDLE partition */
1511 boolean_t enc_nvram_bundle_update_supported;
1512 /* Firmware support for extended MAC_STATS buffer */
1513 uint32_t enc_mac_stats_nstats;
1514 boolean_t enc_fec_counters;
1515 boolean_t enc_hlb_counters;
1516 /* Firmware support for "FLAG" and "MARK" filter actions */
1517 boolean_t enc_filter_action_flag_supported;
1518 boolean_t enc_filter_action_mark_supported;
1519 uint32_t enc_filter_action_mark_max;
1520 /* Port assigned to this PCI function */
1521 uint32_t enc_assigned_port;
1524 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1525 ((configp)->evc_function == 0xffff)
1527 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1528 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1530 #define EFX_PCI_FUNCTION(_encp) \
1531 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1533 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1536 extern const efx_nic_cfg_t *
1538 __in const efx_nic_t *enp);
1540 /* RxDPCPU firmware id values by which FW variant can be identified */
1541 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1542 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1543 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1544 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1545 #define EFX_RXDP_DPDK_FW_ID 0x6
1547 typedef struct efx_nic_fw_info_s {
1548 /* Basic FW version information */
1549 uint16_t enfi_mc_fw_version[4];
1551 * If datapath capabilities can be detected,
1552 * additional FW information is to be shown
1554 boolean_t enfi_dpcpu_fw_ids_valid;
1555 /* Rx and Tx datapath CPU FW IDs */
1556 uint16_t enfi_rx_dpcpu_fw_id;
1557 uint16_t enfi_tx_dpcpu_fw_id;
1558 } efx_nic_fw_info_t;
1561 extern __checkReturn efx_rc_t
1562 efx_nic_get_fw_version(
1563 __in efx_nic_t *enp,
1564 __out efx_nic_fw_info_t *enfip);
1566 /* Driver resource limits (minimum required/maximum usable). */
1567 typedef struct efx_drv_limits_s {
1568 uint32_t edl_min_evq_count;
1569 uint32_t edl_max_evq_count;
1571 uint32_t edl_min_rxq_count;
1572 uint32_t edl_max_rxq_count;
1574 uint32_t edl_min_txq_count;
1575 uint32_t edl_max_txq_count;
1577 /* PIO blocks (sub-allocated from piobuf) */
1578 uint32_t edl_min_pio_alloc_size;
1579 uint32_t edl_max_pio_alloc_count;
1583 extern __checkReturn efx_rc_t
1584 efx_nic_set_drv_limits(
1585 __inout efx_nic_t *enp,
1586 __in efx_drv_limits_t *edlp);
1589 * Register the OS driver version string for management agents
1590 * (e.g. via NC-SI). The content length is provided (i.e. no
1591 * NUL terminator). Use length 0 to indicate no version string
1592 * should be advertised. It is valid to set the version string
1593 * only before efx_nic_probe() is called.
1596 extern __checkReturn efx_rc_t
1597 efx_nic_set_drv_version(
1598 __inout efx_nic_t *enp,
1599 __in_ecount(length) char const *verp,
1600 __in size_t length);
1602 typedef enum efx_nic_region_e {
1603 EFX_REGION_VI, /* Memory BAR UC mapping */
1604 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1608 extern __checkReturn efx_rc_t
1609 efx_nic_get_bar_region(
1610 __in efx_nic_t *enp,
1611 __in efx_nic_region_t region,
1612 __out uint32_t *offsetp,
1613 __out size_t *sizep);
1616 extern __checkReturn efx_rc_t
1617 efx_nic_get_vi_pool(
1618 __in efx_nic_t *enp,
1619 __out uint32_t *evq_countp,
1620 __out uint32_t *rxq_countp,
1621 __out uint32_t *txq_countp);
1626 typedef enum efx_vpd_tag_e {
1633 typedef uint16_t efx_vpd_keyword_t;
1635 typedef struct efx_vpd_value_s {
1636 efx_vpd_tag_t evv_tag;
1637 efx_vpd_keyword_t evv_keyword;
1639 uint8_t evv_value[0x100];
1643 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1646 extern __checkReturn efx_rc_t
1648 __in efx_nic_t *enp);
1651 extern __checkReturn efx_rc_t
1653 __in efx_nic_t *enp,
1654 __out size_t *sizep);
1657 extern __checkReturn efx_rc_t
1659 __in efx_nic_t *enp,
1660 __out_bcount(size) caddr_t data,
1664 extern __checkReturn efx_rc_t
1666 __in efx_nic_t *enp,
1667 __in_bcount(size) caddr_t data,
1671 extern __checkReturn efx_rc_t
1673 __in efx_nic_t *enp,
1674 __in_bcount(size) caddr_t data,
1678 extern __checkReturn efx_rc_t
1680 __in efx_nic_t *enp,
1681 __in_bcount(size) caddr_t data,
1683 __inout efx_vpd_value_t *evvp);
1686 extern __checkReturn efx_rc_t
1688 __in efx_nic_t *enp,
1689 __inout_bcount(size) caddr_t data,
1691 __in efx_vpd_value_t *evvp);
1694 extern __checkReturn efx_rc_t
1696 __in efx_nic_t *enp,
1697 __inout_bcount(size) caddr_t data,
1699 __out efx_vpd_value_t *evvp,
1700 __inout unsigned int *contp);
1703 extern __checkReturn efx_rc_t
1705 __in efx_nic_t *enp,
1706 __in_bcount(size) caddr_t data,
1712 __in efx_nic_t *enp);
1714 #endif /* EFSYS_OPT_VPD */
1720 typedef enum efx_nvram_type_e {
1721 EFX_NVRAM_INVALID = 0,
1723 EFX_NVRAM_BOOTROM_CFG,
1724 EFX_NVRAM_MC_FIRMWARE,
1725 EFX_NVRAM_MC_GOLDEN,
1731 EFX_NVRAM_FPGA_BACKUP,
1732 EFX_NVRAM_DYNAMIC_CFG,
1735 EFX_NVRAM_MUM_FIRMWARE,
1736 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1737 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1739 EFX_NVRAM_BUNDLE_METADATA,
1743 typedef struct efx_nvram_info_s {
1745 uint32_t eni_partn_size;
1746 uint32_t eni_address;
1747 uint32_t eni_erase_size;
1748 uint32_t eni_write_size;
1751 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1754 extern __checkReturn efx_rc_t
1756 __in efx_nic_t *enp);
1761 extern __checkReturn efx_rc_t
1763 __in efx_nic_t *enp);
1765 #endif /* EFSYS_OPT_DIAG */
1768 extern __checkReturn efx_rc_t
1770 __in efx_nic_t *enp,
1771 __in efx_nvram_type_t type,
1772 __out size_t *sizep);
1775 extern __checkReturn efx_rc_t
1777 __in efx_nic_t *enp,
1778 __in efx_nvram_type_t type,
1779 __out efx_nvram_info_t *enip);
1782 extern __checkReturn efx_rc_t
1784 __in efx_nic_t *enp,
1785 __in efx_nvram_type_t type,
1786 __out_opt size_t *pref_chunkp);
1789 extern __checkReturn efx_rc_t
1790 efx_nvram_rw_finish(
1791 __in efx_nic_t *enp,
1792 __in efx_nvram_type_t type,
1793 __out_opt uint32_t *verify_resultp);
1796 extern __checkReturn efx_rc_t
1797 efx_nvram_get_version(
1798 __in efx_nic_t *enp,
1799 __in efx_nvram_type_t type,
1800 __out uint32_t *subtypep,
1801 __out_ecount(4) uint16_t version[4]);
1804 extern __checkReturn efx_rc_t
1805 efx_nvram_read_chunk(
1806 __in efx_nic_t *enp,
1807 __in efx_nvram_type_t type,
1808 __in unsigned int offset,
1809 __out_bcount(size) caddr_t data,
1813 extern __checkReturn efx_rc_t
1814 efx_nvram_read_backup(
1815 __in efx_nic_t *enp,
1816 __in efx_nvram_type_t type,
1817 __in unsigned int offset,
1818 __out_bcount(size) caddr_t data,
1822 extern __checkReturn efx_rc_t
1823 efx_nvram_set_version(
1824 __in efx_nic_t *enp,
1825 __in efx_nvram_type_t type,
1826 __in_ecount(4) uint16_t version[4]);
1829 extern __checkReturn efx_rc_t
1831 __in efx_nic_t *enp,
1832 __in efx_nvram_type_t type,
1833 __in_bcount(partn_size) caddr_t partn_data,
1834 __in size_t partn_size);
1837 extern __checkReturn efx_rc_t
1839 __in efx_nic_t *enp,
1840 __in efx_nvram_type_t type);
1843 extern __checkReturn efx_rc_t
1844 efx_nvram_write_chunk(
1845 __in efx_nic_t *enp,
1846 __in efx_nvram_type_t type,
1847 __in unsigned int offset,
1848 __in_bcount(size) caddr_t data,
1854 __in efx_nic_t *enp);
1856 #endif /* EFSYS_OPT_NVRAM */
1858 #if EFSYS_OPT_BOOTCFG
1860 /* Report size and offset of bootcfg sector in NVRAM partition. */
1862 extern __checkReturn efx_rc_t
1863 efx_bootcfg_sector_info(
1864 __in efx_nic_t *enp,
1866 __out_opt uint32_t *sector_countp,
1867 __out size_t *offsetp,
1868 __out size_t *max_sizep);
1871 * Copy bootcfg sector data to a target buffer which may differ in size.
1872 * Optionally corrects format errors in source buffer.
1876 efx_bootcfg_copy_sector(
1877 __in efx_nic_t *enp,
1878 __inout_bcount(sector_length)
1880 __in size_t sector_length,
1881 __out_bcount(data_size) uint8_t *data,
1882 __in size_t data_size,
1883 __in boolean_t handle_format_errors);
1888 __in efx_nic_t *enp,
1889 __out_bcount(size) uint8_t *data,
1895 __in efx_nic_t *enp,
1896 __in_bcount(size) uint8_t *data,
1901 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1902 * (see https://tools.ietf.org/html/rfc1533)
1904 * Summarising the format: the buffer is a sequence of options. All options
1905 * begin with a tag octet, which uniquely identifies the option. Fixed-
1906 * length options without data consist of only a tag octet. Only options PAD
1907 * (0) and END (255) are fixed length. All other options are variable-length
1908 * with a length octet following the tag octet. The value of the length
1909 * octet does not include the two octets specifying the tag and length. The
1910 * length octet is followed by "length" octets of data.
1912 * Option data may be a sequence of sub-options in the same format. The data
1913 * content of the encapsulating option is one or more encapsulated sub-options,
1914 * with no terminating END tag is required.
1916 * To be valid, the top-level sequence of options should be terminated by an
1917 * END tag. The buffer should be padded with the PAD byte.
1919 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1920 * checksum octet. The full buffer (including after the END tag) contributes
1921 * to the checksum, hence the need to fill the buffer to the end with PAD.
1924 #define EFX_DHCP_END ((uint8_t)0xff)
1925 #define EFX_DHCP_PAD ((uint8_t)0)
1927 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1928 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1931 extern __checkReturn uint8_t
1933 __in_bcount(size) uint8_t const *data,
1937 extern __checkReturn efx_rc_t
1939 __in_bcount(size) uint8_t const *data,
1941 __out_opt size_t *usedp);
1944 extern __checkReturn efx_rc_t
1946 __in_bcount(buffer_length) uint8_t *bufferp,
1947 __in size_t buffer_length,
1949 __deref_out uint8_t **valuepp,
1950 __out size_t *value_lengthp);
1953 extern __checkReturn efx_rc_t
1955 __in_bcount(buffer_length) uint8_t *bufferp,
1956 __in size_t buffer_length,
1957 __deref_out uint8_t **endpp);
1961 extern __checkReturn efx_rc_t
1962 efx_dhcp_delete_tag(
1963 __inout_bcount(buffer_length) uint8_t *bufferp,
1964 __in size_t buffer_length,
1968 extern __checkReturn efx_rc_t
1970 __inout_bcount(buffer_length) uint8_t *bufferp,
1971 __in size_t buffer_length,
1973 __in_bcount_opt(value_length) uint8_t *valuep,
1974 __in size_t value_length);
1977 extern __checkReturn efx_rc_t
1978 efx_dhcp_update_tag(
1979 __inout_bcount(buffer_length) uint8_t *bufferp,
1980 __in size_t buffer_length,
1982 __in uint8_t *value_locationp,
1983 __in_bcount_opt(value_length) uint8_t *valuep,
1984 __in size_t value_length);
1987 #endif /* EFSYS_OPT_BOOTCFG */
1989 #if EFSYS_OPT_IMAGE_LAYOUT
1991 #include "ef10_signed_image_layout.h"
1994 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1997 * The image header format is extensible. However, older drivers require an
1998 * exact match of image header version and header length when validating and
1999 * writing firmware images.
2001 * To avoid breaking backward compatibility, we use the upper bits of the
2002 * controller version fields to contain an extra version number used for
2003 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2004 * version). See bug39254 and SF-102785-PS for details.
2006 typedef struct efx_image_header_s {
2008 uint32_t eih_version;
2010 uint32_t eih_subtype;
2011 uint32_t eih_code_size;
2014 uint32_t eih_controller_version_min;
2016 uint16_t eih_controller_version_min_short;
2017 uint8_t eih_extra_version_a;
2018 uint8_t eih_extra_version_b;
2022 uint32_t eih_controller_version_max;
2024 uint16_t eih_controller_version_max_short;
2025 uint8_t eih_extra_version_c;
2026 uint8_t eih_extra_version_d;
2029 uint16_t eih_code_version_a;
2030 uint16_t eih_code_version_b;
2031 uint16_t eih_code_version_c;
2032 uint16_t eih_code_version_d;
2033 } efx_image_header_t;
2035 #define EFX_IMAGE_HEADER_SIZE (40)
2036 #define EFX_IMAGE_HEADER_VERSION (4)
2037 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2040 typedef struct efx_image_trailer_s {
2042 } efx_image_trailer_t;
2044 #define EFX_IMAGE_TRAILER_SIZE (4)
2046 typedef enum efx_image_format_e {
2047 EFX_IMAGE_FORMAT_NO_IMAGE,
2048 EFX_IMAGE_FORMAT_INVALID,
2049 EFX_IMAGE_FORMAT_UNSIGNED,
2050 EFX_IMAGE_FORMAT_SIGNED,
2051 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2052 } efx_image_format_t;
2054 typedef struct efx_image_info_s {
2055 efx_image_format_t eii_format;
2056 uint8_t * eii_imagep;
2057 size_t eii_image_size;
2058 efx_image_header_t * eii_headerp;
2062 extern __checkReturn efx_rc_t
2063 efx_check_reflash_image(
2065 __in uint32_t buffer_size,
2066 __out efx_image_info_t *infop);
2069 extern __checkReturn efx_rc_t
2070 efx_build_signed_image_write_buffer(
2071 __out_bcount(buffer_size)
2073 __in uint32_t buffer_size,
2074 __in efx_image_info_t *infop,
2075 __out efx_image_header_t **headerpp);
2077 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2081 typedef enum efx_pattern_type_t {
2082 EFX_PATTERN_BYTE_INCREMENT = 0,
2083 EFX_PATTERN_ALL_THE_SAME,
2084 EFX_PATTERN_BIT_ALTERNATE,
2085 EFX_PATTERN_BYTE_ALTERNATE,
2086 EFX_PATTERN_BYTE_CHANGING,
2087 EFX_PATTERN_BIT_SWEEP,
2089 } efx_pattern_type_t;
2092 (*efx_sram_pattern_fn_t)(
2094 __in boolean_t negate,
2095 __out efx_qword_t *eqp);
2098 extern __checkReturn efx_rc_t
2100 __in efx_nic_t *enp,
2101 __in efx_pattern_type_t type);
2103 #endif /* EFSYS_OPT_DIAG */
2106 extern __checkReturn efx_rc_t
2107 efx_sram_buf_tbl_set(
2108 __in efx_nic_t *enp,
2110 __in efsys_mem_t *esmp,
2115 efx_sram_buf_tbl_clear(
2116 __in efx_nic_t *enp,
2120 #define EFX_BUF_TBL_SIZE 0x20000
2122 #define EFX_BUF_SIZE 4096
2126 typedef struct efx_evq_s efx_evq_t;
2128 #if EFSYS_OPT_QSTATS
2130 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2131 typedef enum efx_ev_qstat_e {
2137 EV_RX_PAUSE_FRM_ERR,
2138 EV_RX_BUF_OWNER_ID_ERR,
2139 EV_RX_IPV4_HDR_CHKSUM_ERR,
2140 EV_RX_TCP_UDP_CHKSUM_ERR,
2144 EV_RX_MCAST_HASH_MATCH,
2161 EV_DRIVER_SRM_UPD_DONE,
2162 EV_DRIVER_TX_DESCQ_FLS_DONE,
2163 EV_DRIVER_RX_DESCQ_FLS_DONE,
2164 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2165 EV_DRIVER_RX_DSC_ERROR,
2166 EV_DRIVER_TX_DSC_ERROR,
2169 EV_RX_PARSE_INCOMPLETE,
2173 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2175 #endif /* EFSYS_OPT_QSTATS */
2178 extern __checkReturn efx_rc_t
2180 __in efx_nic_t *enp);
2185 __in efx_nic_t *enp);
2188 extern __checkReturn size_t
2190 __in const efx_nic_t *enp,
2191 __in unsigned int ndescs);
2194 extern __checkReturn unsigned int
2196 __in const efx_nic_t *enp,
2197 __in unsigned int ndescs);
2199 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2200 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2201 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2202 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2204 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2205 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2206 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2209 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2210 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2213 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2214 * which is the case when an event queue is set to THROUGHPUT mode.
2216 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2219 extern __checkReturn efx_rc_t
2221 __in efx_nic_t *enp,
2222 __in unsigned int index,
2223 __in efsys_mem_t *esmp,
2227 __in uint32_t flags,
2228 __deref_out efx_evq_t **eepp);
2233 __in efx_evq_t *eep,
2234 __in uint16_t data);
2236 typedef __checkReturn boolean_t
2237 (*efx_initialized_ev_t)(
2238 __in_opt void *arg);
2240 #define EFX_PKT_UNICAST 0x0004
2241 #define EFX_PKT_START 0x0008
2243 #define EFX_PKT_VLAN_TAGGED 0x0010
2244 #define EFX_CKSUM_TCPUDP 0x0020
2245 #define EFX_CKSUM_IPV4 0x0040
2246 #define EFX_PKT_CONT 0x0080
2248 #define EFX_CHECK_VLAN 0x0100
2249 #define EFX_PKT_TCP 0x0200
2250 #define EFX_PKT_UDP 0x0400
2251 #define EFX_PKT_IPV4 0x0800
2253 #define EFX_PKT_IPV6 0x1000
2254 #define EFX_PKT_PREFIX_LEN 0x2000
2255 #define EFX_ADDR_MISMATCH 0x4000
2256 #define EFX_DISCARD 0x8000
2259 * The following flags are used only for packed stream
2260 * mode. The values for the flags are reused to fit into 16 bit,
2261 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2262 * packed stream mode
2264 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2265 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2268 #define EFX_EV_RX_NLABELS 32
2269 #define EFX_EV_TX_NLABELS 32
2271 typedef __checkReturn boolean_t
2274 __in uint32_t label,
2277 __in uint16_t flags);
2279 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2282 * Packed stream mode is documented in SF-112241-TC.
2283 * The general idea is that, instead of putting each incoming
2284 * packet into a separate buffer which is specified in a RX
2285 * descriptor, a large buffer is provided to the hardware and
2286 * packets are put there in a continuous stream.
2287 * The main advantage of such an approach is that RX queue refilling
2288 * happens much less frequently.
2290 * Equal stride packed stream mode is documented in SF-119419-TC.
2291 * The general idea is to utilize advantages of the packed stream,
2292 * but avoid indirection in packets representation.
2293 * The main advantage of such an approach is that RX queue refilling
2294 * happens much less frequently and packets buffers are independent
2295 * from upper layers point of view.
2298 typedef __checkReturn boolean_t
2301 __in uint32_t label,
2303 __in uint32_t pkt_count,
2304 __in uint16_t flags);
2308 typedef __checkReturn boolean_t
2311 __in uint32_t label,
2314 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2315 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2316 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2317 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2318 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2319 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2320 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2321 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2322 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2324 typedef __checkReturn boolean_t
2325 (*efx_exception_ev_t)(
2327 __in uint32_t label,
2328 __in uint32_t data);
2330 typedef __checkReturn boolean_t
2331 (*efx_rxq_flush_done_ev_t)(
2333 __in uint32_t rxq_index);
2335 typedef __checkReturn boolean_t
2336 (*efx_rxq_flush_failed_ev_t)(
2338 __in uint32_t rxq_index);
2340 typedef __checkReturn boolean_t
2341 (*efx_txq_flush_done_ev_t)(
2343 __in uint32_t txq_index);
2345 typedef __checkReturn boolean_t
2346 (*efx_software_ev_t)(
2348 __in uint16_t magic);
2350 typedef __checkReturn boolean_t
2353 __in uint32_t code);
2355 #define EFX_SRAM_CLEAR 0
2356 #define EFX_SRAM_UPDATE 1
2357 #define EFX_SRAM_ILLEGAL_CLEAR 2
2359 typedef __checkReturn boolean_t
2360 (*efx_wake_up_ev_t)(
2362 __in uint32_t label);
2364 typedef __checkReturn boolean_t
2367 __in uint32_t label);
2369 typedef __checkReturn boolean_t
2370 (*efx_link_change_ev_t)(
2372 __in efx_link_mode_t link_mode);
2374 #if EFSYS_OPT_MON_STATS
2376 typedef __checkReturn boolean_t
2377 (*efx_monitor_ev_t)(
2379 __in efx_mon_stat_t id,
2380 __in efx_mon_stat_value_t value);
2382 #endif /* EFSYS_OPT_MON_STATS */
2384 #if EFSYS_OPT_MAC_STATS
2386 typedef __checkReturn boolean_t
2387 (*efx_mac_stats_ev_t)(
2389 __in uint32_t generation);
2391 #endif /* EFSYS_OPT_MAC_STATS */
2393 typedef struct efx_ev_callbacks_s {
2394 efx_initialized_ev_t eec_initialized;
2396 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2397 efx_rx_ps_ev_t eec_rx_ps;
2400 efx_exception_ev_t eec_exception;
2401 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2402 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2403 efx_txq_flush_done_ev_t eec_txq_flush_done;
2404 efx_software_ev_t eec_software;
2405 efx_sram_ev_t eec_sram;
2406 efx_wake_up_ev_t eec_wake_up;
2407 efx_timer_ev_t eec_timer;
2408 efx_link_change_ev_t eec_link_change;
2409 #if EFSYS_OPT_MON_STATS
2410 efx_monitor_ev_t eec_monitor;
2411 #endif /* EFSYS_OPT_MON_STATS */
2412 #if EFSYS_OPT_MAC_STATS
2413 efx_mac_stats_ev_t eec_mac_stats;
2414 #endif /* EFSYS_OPT_MAC_STATS */
2415 } efx_ev_callbacks_t;
2418 extern __checkReturn boolean_t
2420 __in efx_evq_t *eep,
2421 __in unsigned int count);
2423 #if EFSYS_OPT_EV_PREFETCH
2428 __in efx_evq_t *eep,
2429 __in unsigned int count);
2431 #endif /* EFSYS_OPT_EV_PREFETCH */
2436 __in efx_evq_t *eep,
2437 __inout unsigned int *countp,
2438 __in const efx_ev_callbacks_t *eecp,
2439 __in_opt void *arg);
2442 extern __checkReturn efx_rc_t
2443 efx_ev_usecs_to_ticks(
2444 __in efx_nic_t *enp,
2445 __in unsigned int usecs,
2446 __out unsigned int *ticksp);
2449 extern __checkReturn efx_rc_t
2451 __in efx_evq_t *eep,
2452 __in unsigned int us);
2455 extern __checkReturn efx_rc_t
2457 __in efx_evq_t *eep,
2458 __in unsigned int count);
2460 #if EFSYS_OPT_QSTATS
2467 __in efx_nic_t *enp,
2468 __in unsigned int id);
2470 #endif /* EFSYS_OPT_NAMES */
2474 efx_ev_qstats_update(
2475 __in efx_evq_t *eep,
2476 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2478 #endif /* EFSYS_OPT_QSTATS */
2483 __in efx_evq_t *eep);
2488 extern __checkReturn efx_rc_t
2490 __inout efx_nic_t *enp);
2495 __in efx_nic_t *enp);
2497 #if EFSYS_OPT_RX_SCATTER
2499 extern __checkReturn efx_rc_t
2500 efx_rx_scatter_enable(
2501 __in efx_nic_t *enp,
2502 __in unsigned int buf_size);
2503 #endif /* EFSYS_OPT_RX_SCATTER */
2505 /* Handle to represent use of the default RSS context. */
2506 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2508 #if EFSYS_OPT_RX_SCALE
2510 typedef enum efx_rx_hash_alg_e {
2511 EFX_RX_HASHALG_LFSR = 0,
2512 EFX_RX_HASHALG_TOEPLITZ,
2513 EFX_RX_HASHALG_PACKED_STREAM,
2515 } efx_rx_hash_alg_t;
2518 * Legacy hash type flags.
2520 * They represent standard tuples for distinct traffic classes.
2522 #define EFX_RX_HASH_IPV4 (1U << 0)
2523 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2524 #define EFX_RX_HASH_IPV6 (1U << 2)
2525 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2527 #define EFX_RX_HASH_LEGACY_MASK \
2528 (EFX_RX_HASH_IPV4 | \
2529 EFX_RX_HASH_TCPIPV4 | \
2530 EFX_RX_HASH_IPV6 | \
2531 EFX_RX_HASH_TCPIPV6)
2534 * The type of the argument used by efx_rx_scale_mode_set() to
2535 * provide a means for the client drivers to configure hashing.
2537 * A properly constructed value can either be:
2538 * - a combination of legacy flags
2539 * - a combination of EFX_RX_HASH() flags
2541 typedef uint32_t efx_rx_hash_type_t;
2543 typedef enum efx_rx_hash_support_e {
2544 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2545 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2546 } efx_rx_hash_support_t;
2548 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2549 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2550 #define EFX_MAXRSS 64 /* RX indirection entry range */
2551 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2553 typedef enum efx_rx_scale_context_type_e {
2554 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2555 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2556 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2557 } efx_rx_scale_context_type_t;
2560 * Traffic classes eligible for hash computation.
2562 * Select packet headers used in computing the receive hash.
2563 * This uses the same encoding as the RSS_MODES field of
2564 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2566 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2567 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2568 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2569 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2570 #define EFX_RX_CLASS_IPV4_LBN 16
2571 #define EFX_RX_CLASS_IPV4_WIDTH 4
2572 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2573 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2574 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2575 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2576 #define EFX_RX_CLASS_IPV6_LBN 28
2577 #define EFX_RX_CLASS_IPV6_WIDTH 4
2579 #define EFX_RX_NCLASSES 6
2582 * Ancillary flags used to construct generic hash tuples.
2583 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2585 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2586 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2587 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2588 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2591 * Generic hash tuples.
2593 * They express combinations of packet fields
2594 * which can contribute to the hash value for
2595 * a particular traffic class.
2597 #define EFX_RX_CLASS_HASH_DISABLE 0
2599 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2600 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2602 #define EFX_RX_CLASS_HASH_2TUPLE \
2603 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2604 EFX_RX_CLASS_HASH_DST_ADDR)
2606 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2607 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2608 EFX_RX_CLASS_HASH_SRC_PORT)
2610 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2611 (EFX_RX_CLASS_HASH_DST_ADDR | \
2612 EFX_RX_CLASS_HASH_DST_PORT)
2614 #define EFX_RX_CLASS_HASH_4TUPLE \
2615 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2616 EFX_RX_CLASS_HASH_DST_ADDR | \
2617 EFX_RX_CLASS_HASH_SRC_PORT | \
2618 EFX_RX_CLASS_HASH_DST_PORT)
2620 #define EFX_RX_CLASS_HASH_NTUPLES 7
2623 * Hash flag constructor.
2625 * Resulting flags encode hash tuples for specific traffic classes.
2626 * The client drivers are encouraged to use these flags to form
2627 * a hash type value.
2629 #define EFX_RX_HASH(_class, _tuple) \
2630 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2631 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2634 * The maximum number of EFX_RX_HASH() flags.
2636 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2639 extern __checkReturn efx_rc_t
2640 efx_rx_scale_hash_flags_get(
2641 __in efx_nic_t *enp,
2642 __in efx_rx_hash_alg_t hash_alg,
2643 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2644 __in unsigned int max_nflags,
2645 __out unsigned int *nflagsp);
2648 extern __checkReturn efx_rc_t
2649 efx_rx_hash_default_support_get(
2650 __in efx_nic_t *enp,
2651 __out efx_rx_hash_support_t *supportp);
2655 extern __checkReturn efx_rc_t
2656 efx_rx_scale_default_support_get(
2657 __in efx_nic_t *enp,
2658 __out efx_rx_scale_context_type_t *typep);
2661 extern __checkReturn efx_rc_t
2662 efx_rx_scale_context_alloc(
2663 __in efx_nic_t *enp,
2664 __in efx_rx_scale_context_type_t type,
2665 __in uint32_t num_queues,
2666 __out uint32_t *rss_contextp);
2669 extern __checkReturn efx_rc_t
2670 efx_rx_scale_context_free(
2671 __in efx_nic_t *enp,
2672 __in uint32_t rss_context);
2675 extern __checkReturn efx_rc_t
2676 efx_rx_scale_mode_set(
2677 __in efx_nic_t *enp,
2678 __in uint32_t rss_context,
2679 __in efx_rx_hash_alg_t alg,
2680 __in efx_rx_hash_type_t type,
2681 __in boolean_t insert);
2684 extern __checkReturn efx_rc_t
2685 efx_rx_scale_tbl_set(
2686 __in efx_nic_t *enp,
2687 __in uint32_t rss_context,
2688 __in_ecount(n) unsigned int *table,
2692 extern __checkReturn efx_rc_t
2693 efx_rx_scale_key_set(
2694 __in efx_nic_t *enp,
2695 __in uint32_t rss_context,
2696 __in_ecount(n) uint8_t *key,
2700 extern __checkReturn uint32_t
2701 efx_pseudo_hdr_hash_get(
2702 __in efx_rxq_t *erp,
2703 __in efx_rx_hash_alg_t func,
2704 __in uint8_t *buffer);
2706 #endif /* EFSYS_OPT_RX_SCALE */
2709 extern __checkReturn efx_rc_t
2710 efx_pseudo_hdr_pkt_length_get(
2711 __in efx_rxq_t *erp,
2712 __in uint8_t *buffer,
2713 __out uint16_t *pkt_lengthp);
2716 extern __checkReturn size_t
2718 __in const efx_nic_t *enp,
2719 __in unsigned int ndescs);
2722 extern __checkReturn unsigned int
2724 __in const efx_nic_t *enp,
2725 __in unsigned int ndescs);
2727 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2729 typedef enum efx_rxq_type_e {
2730 EFX_RXQ_TYPE_DEFAULT,
2731 EFX_RXQ_TYPE_PACKED_STREAM,
2732 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2737 * Dummy flag to be used instead of 0 to make it clear that the argument
2738 * is receive queue flags.
2740 #define EFX_RXQ_FLAG_NONE 0x0
2741 #define EFX_RXQ_FLAG_SCATTER 0x1
2743 * If tunnels are supported and Rx event can provide information about
2744 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2745 * full-feature firmware variant running), outer classes are requested by
2746 * default. However, if the driver supports tunnels, the flag allows to
2747 * request inner classes which are required to be able to interpret inner
2748 * Rx checksum offload results.
2750 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2753 extern __checkReturn efx_rc_t
2755 __in efx_nic_t *enp,
2756 __in unsigned int index,
2757 __in unsigned int label,
2758 __in efx_rxq_type_t type,
2759 __in size_t buf_size,
2760 __in efsys_mem_t *esmp,
2763 __in unsigned int flags,
2764 __in efx_evq_t *eep,
2765 __deref_out efx_rxq_t **erpp);
2767 #if EFSYS_OPT_RX_PACKED_STREAM
2769 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2770 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2771 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2772 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2773 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2776 extern __checkReturn efx_rc_t
2777 efx_rx_qcreate_packed_stream(
2778 __in efx_nic_t *enp,
2779 __in unsigned int index,
2780 __in unsigned int label,
2781 __in uint32_t ps_buf_size,
2782 __in efsys_mem_t *esmp,
2784 __in efx_evq_t *eep,
2785 __deref_out efx_rxq_t **erpp);
2789 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2791 /* Maximum head-of-line block timeout in nanoseconds */
2792 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2795 extern __checkReturn efx_rc_t
2796 efx_rx_qcreate_es_super_buffer(
2797 __in efx_nic_t *enp,
2798 __in unsigned int index,
2799 __in unsigned int label,
2800 __in uint32_t n_bufs_per_desc,
2801 __in uint32_t max_dma_len,
2802 __in uint32_t buf_stride,
2803 __in uint32_t hol_block_timeout,
2804 __in efsys_mem_t *esmp,
2806 __in unsigned int flags,
2807 __in efx_evq_t *eep,
2808 __deref_out efx_rxq_t **erpp);
2812 typedef struct efx_buffer_s {
2813 efsys_dma_addr_t eb_addr;
2818 typedef struct efx_desc_s {
2825 __in efx_rxq_t *erp,
2826 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2828 __in unsigned int ndescs,
2829 __in unsigned int completed,
2830 __in unsigned int added);
2835 __in efx_rxq_t *erp,
2836 __in unsigned int added,
2837 __inout unsigned int *pushedp);
2839 #if EFSYS_OPT_RX_PACKED_STREAM
2843 efx_rx_qpush_ps_credits(
2844 __in efx_rxq_t *erp);
2847 extern __checkReturn uint8_t *
2848 efx_rx_qps_packet_info(
2849 __in efx_rxq_t *erp,
2850 __in uint8_t *buffer,
2851 __in uint32_t buffer_length,
2852 __in uint32_t current_offset,
2853 __out uint16_t *lengthp,
2854 __out uint32_t *next_offsetp,
2855 __out uint32_t *timestamp);
2859 extern __checkReturn efx_rc_t
2861 __in efx_rxq_t *erp);
2866 __in efx_rxq_t *erp);
2871 __in efx_rxq_t *erp);
2875 typedef struct efx_txq_s efx_txq_t;
2877 #if EFSYS_OPT_QSTATS
2879 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2880 typedef enum efx_tx_qstat_e {
2886 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2888 #endif /* EFSYS_OPT_QSTATS */
2891 extern __checkReturn efx_rc_t
2893 __in efx_nic_t *enp);
2898 __in efx_nic_t *enp);
2901 extern __checkReturn size_t
2903 __in const efx_nic_t *enp,
2904 __in unsigned int ndescs);
2907 extern __checkReturn unsigned int
2909 __in const efx_nic_t *enp,
2910 __in unsigned int ndescs);
2912 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2914 #define EFX_TXQ_CKSUM_IPV4 0x0001
2915 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2916 #define EFX_TXQ_FATSOV2 0x0004
2917 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2918 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2921 extern __checkReturn efx_rc_t
2923 __in efx_nic_t *enp,
2924 __in unsigned int index,
2925 __in unsigned int label,
2926 __in efsys_mem_t *esmp,
2929 __in uint16_t flags,
2930 __in efx_evq_t *eep,
2931 __deref_out efx_txq_t **etpp,
2932 __out unsigned int *addedp);
2935 extern __checkReturn efx_rc_t
2937 __in efx_txq_t *etp,
2938 __in_ecount(ndescs) efx_buffer_t *eb,
2939 __in unsigned int ndescs,
2940 __in unsigned int completed,
2941 __inout unsigned int *addedp);
2944 extern __checkReturn efx_rc_t
2946 __in efx_txq_t *etp,
2947 __in unsigned int ns);
2952 __in efx_txq_t *etp,
2953 __in unsigned int added,
2954 __in unsigned int pushed);
2957 extern __checkReturn efx_rc_t
2959 __in efx_txq_t *etp);
2964 __in efx_txq_t *etp);
2967 extern __checkReturn efx_rc_t
2969 __in efx_txq_t *etp);
2973 efx_tx_qpio_disable(
2974 __in efx_txq_t *etp);
2977 extern __checkReturn efx_rc_t
2979 __in efx_txq_t *etp,
2980 __in_ecount(buf_length) uint8_t *buffer,
2981 __in size_t buf_length,
2982 __in size_t pio_buf_offset);
2985 extern __checkReturn efx_rc_t
2987 __in efx_txq_t *etp,
2988 __in size_t pkt_length,
2989 __in unsigned int completed,
2990 __inout unsigned int *addedp);
2993 extern __checkReturn efx_rc_t
2995 __in efx_txq_t *etp,
2996 __in_ecount(n) efx_desc_t *ed,
2997 __in unsigned int n,
2998 __in unsigned int completed,
2999 __inout unsigned int *addedp);
3003 efx_tx_qdesc_dma_create(
3004 __in efx_txq_t *etp,
3005 __in efsys_dma_addr_t addr,
3008 __out efx_desc_t *edp);
3012 efx_tx_qdesc_tso_create(
3013 __in efx_txq_t *etp,
3014 __in uint16_t ipv4_id,
3015 __in uint32_t tcp_seq,
3016 __in uint8_t tcp_flags,
3017 __out efx_desc_t *edp);
3019 /* Number of FATSOv2 option descriptors */
3020 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3022 /* Maximum number of DMA segments per TSO packet (not superframe) */
3023 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3027 efx_tx_qdesc_tso2_create(
3028 __in efx_txq_t *etp,
3029 __in uint16_t ipv4_id,
3030 __in uint16_t outer_ipv4_id,
3031 __in uint32_t tcp_seq,
3032 __in uint16_t tcp_mss,
3033 __out_ecount(count) efx_desc_t *edp,
3038 efx_tx_qdesc_vlantci_create(
3039 __in efx_txq_t *etp,
3041 __out efx_desc_t *edp);
3045 efx_tx_qdesc_checksum_create(
3046 __in efx_txq_t *etp,
3047 __in uint16_t flags,
3048 __out efx_desc_t *edp);
3050 #if EFSYS_OPT_QSTATS
3057 __in efx_nic_t *etp,
3058 __in unsigned int id);
3060 #endif /* EFSYS_OPT_NAMES */
3064 efx_tx_qstats_update(
3065 __in efx_txq_t *etp,
3066 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3068 #endif /* EFSYS_OPT_QSTATS */
3073 __in efx_txq_t *etp);
3078 #if EFSYS_OPT_FILTER
3080 #define EFX_ETHER_TYPE_IPV4 0x0800
3081 #define EFX_ETHER_TYPE_IPV6 0x86DD
3083 #define EFX_IPPROTO_TCP 6
3084 #define EFX_IPPROTO_UDP 17
3085 #define EFX_IPPROTO_GRE 47
3087 /* Use RSS to spread across multiple queues */
3088 #define EFX_FILTER_FLAG_RX_RSS 0x01
3089 /* Enable RX scatter */
3090 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3092 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3093 * May only be set by the filter implementation for each type.
3094 * A removal request will restore the automatic filter in its place.
3096 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3097 /* Filter is for RX */
3098 #define EFX_FILTER_FLAG_RX 0x08
3099 /* Filter is for TX */
3100 #define EFX_FILTER_FLAG_TX 0x10
3101 /* Set match flag on the received packet */
3102 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3103 /* Set match mark on the received packet */
3104 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3106 typedef uint8_t efx_filter_flags_t;
3109 * Flags which specify the fields to match on. The values are the same as in the
3110 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3113 /* Match by remote IP host address */
3114 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3115 /* Match by local IP host address */
3116 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3117 /* Match by remote MAC address */
3118 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3119 /* Match by remote TCP/UDP port */
3120 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3121 /* Match by remote TCP/UDP port */
3122 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3123 /* Match by local TCP/UDP port */
3124 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3125 /* Match by Ether-type */
3126 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3127 /* Match by inner VLAN ID */
3128 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3129 /* Match by outer VLAN ID */
3130 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3131 /* Match by IP transport protocol */
3132 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3133 /* Match by VNI or VSID */
3134 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3135 /* For encapsulated packets, match by inner frame local MAC address */
3136 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3137 /* For encapsulated packets, match all multicast inner frames */
3138 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3139 /* For encapsulated packets, match all unicast inner frames */
3140 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3142 * Match by encap type, this flag does not correspond to
3143 * the MCDI match flags and any unoccupied value may be used
3145 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3146 /* Match otherwise-unmatched multicast and broadcast packets */
3147 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3148 /* Match otherwise-unmatched unicast packets */
3149 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3151 typedef uint32_t efx_filter_match_flags_t;
3153 /* Filter priority from lowest to highest */
3154 typedef enum efx_filter_priority_s {
3155 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3156 * address list or hardware
3157 * requirements. This may only be used
3158 * by the filter implementation for
3160 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3162 } efx_filter_priority_t;
3165 * FIXME: All these fields are assumed to be in little-endian byte order.
3166 * It may be better for some to be big-endian. See bug42804.
3169 typedef struct efx_filter_spec_s {
3170 efx_filter_match_flags_t efs_match_flags;
3171 uint8_t efs_priority;
3172 efx_filter_flags_t efs_flags;
3173 uint16_t efs_dmaq_id;
3174 uint32_t efs_rss_context;
3177 * Saved lower-priority filter. If it is set, it is restored on
3178 * filter delete operation.
3180 struct efx_filter_spec_s *efs_overridden_spec;
3181 /* Fields below here are hashed for software filter lookup */
3182 uint16_t efs_outer_vid;
3183 uint16_t efs_inner_vid;
3184 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3185 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3186 uint16_t efs_ether_type;
3187 uint8_t efs_ip_proto;
3188 efx_tunnel_protocol_t efs_encap_type;
3189 uint16_t efs_loc_port;
3190 uint16_t efs_rem_port;
3191 efx_oword_t efs_rem_host;
3192 efx_oword_t efs_loc_host;
3193 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3194 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3195 } efx_filter_spec_t;
3198 /* Default values for use in filter specifications */
3199 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3200 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3203 extern __checkReturn efx_rc_t
3205 __in efx_nic_t *enp);
3210 __in efx_nic_t *enp);
3213 extern __checkReturn efx_rc_t
3215 __in efx_nic_t *enp,
3216 __inout efx_filter_spec_t *spec);
3219 extern __checkReturn efx_rc_t
3221 __in efx_nic_t *enp,
3222 __inout efx_filter_spec_t *spec);
3225 extern __checkReturn efx_rc_t
3227 __in efx_nic_t *enp);
3230 extern __checkReturn efx_rc_t
3231 efx_filter_supported_filters(
3232 __in efx_nic_t *enp,
3233 __out_ecount(buffer_length) uint32_t *buffer,
3234 __in size_t buffer_length,
3235 __out size_t *list_lengthp);
3239 efx_filter_spec_init_rx(
3240 __out efx_filter_spec_t *spec,
3241 __in efx_filter_priority_t priority,
3242 __in efx_filter_flags_t flags,
3243 __in efx_rxq_t *erp);
3247 efx_filter_spec_init_tx(
3248 __out efx_filter_spec_t *spec,
3249 __in efx_txq_t *etp);
3252 extern __checkReturn efx_rc_t
3253 efx_filter_spec_set_ipv4_local(
3254 __inout efx_filter_spec_t *spec,
3257 __in uint16_t port);
3260 extern __checkReturn efx_rc_t
3261 efx_filter_spec_set_ipv4_full(
3262 __inout efx_filter_spec_t *spec,
3264 __in uint32_t lhost,
3265 __in uint16_t lport,
3266 __in uint32_t rhost,
3267 __in uint16_t rport);
3270 extern __checkReturn efx_rc_t
3271 efx_filter_spec_set_eth_local(
3272 __inout efx_filter_spec_t *spec,
3274 __in const uint8_t *addr);
3278 efx_filter_spec_set_ether_type(
3279 __inout efx_filter_spec_t *spec,
3280 __in uint16_t ether_type);
3283 extern __checkReturn efx_rc_t
3284 efx_filter_spec_set_uc_def(
3285 __inout efx_filter_spec_t *spec);
3288 extern __checkReturn efx_rc_t
3289 efx_filter_spec_set_mc_def(
3290 __inout efx_filter_spec_t *spec);
3292 typedef enum efx_filter_inner_frame_match_e {
3293 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3294 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3295 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3296 } efx_filter_inner_frame_match_t;
3299 extern __checkReturn efx_rc_t
3300 efx_filter_spec_set_encap_type(
3301 __inout efx_filter_spec_t *spec,
3302 __in efx_tunnel_protocol_t encap_type,
3303 __in efx_filter_inner_frame_match_t inner_frame_match);
3306 extern __checkReturn efx_rc_t
3307 efx_filter_spec_set_vxlan(
3308 __inout efx_filter_spec_t *spec,
3309 __in const uint8_t *vni,
3310 __in const uint8_t *inner_addr,
3311 __in const uint8_t *outer_addr);
3314 extern __checkReturn efx_rc_t
3315 efx_filter_spec_set_geneve(
3316 __inout efx_filter_spec_t *spec,
3317 __in const uint8_t *vni,
3318 __in const uint8_t *inner_addr,
3319 __in const uint8_t *outer_addr);
3322 extern __checkReturn efx_rc_t
3323 efx_filter_spec_set_nvgre(
3324 __inout efx_filter_spec_t *spec,
3325 __in const uint8_t *vsid,
3326 __in const uint8_t *inner_addr,
3327 __in const uint8_t *outer_addr);
3329 #if EFSYS_OPT_RX_SCALE
3331 extern __checkReturn efx_rc_t
3332 efx_filter_spec_set_rss_context(
3333 __inout efx_filter_spec_t *spec,
3334 __in uint32_t rss_context);
3336 #endif /* EFSYS_OPT_FILTER */
3341 extern __checkReturn uint32_t
3343 __in_ecount(count) uint32_t const *input,
3345 __in uint32_t init);
3348 extern __checkReturn uint32_t
3350 __in_ecount(length) uint8_t const *input,
3352 __in uint32_t init);
3354 #if EFSYS_OPT_LICENSING
3358 typedef struct efx_key_stats_s {
3360 uint32_t eks_invalid;
3361 uint32_t eks_blacklisted;
3362 uint32_t eks_unverifiable;
3363 uint32_t eks_wrong_node;
3364 uint32_t eks_licensed_apps_lo;
3365 uint32_t eks_licensed_apps_hi;
3366 uint32_t eks_licensed_features_lo;
3367 uint32_t eks_licensed_features_hi;
3371 extern __checkReturn efx_rc_t
3373 __in efx_nic_t *enp);
3378 __in efx_nic_t *enp);
3381 extern __checkReturn boolean_t
3382 efx_lic_check_support(
3383 __in efx_nic_t *enp);
3386 extern __checkReturn efx_rc_t
3387 efx_lic_update_licenses(
3388 __in efx_nic_t *enp);
3391 extern __checkReturn efx_rc_t
3392 efx_lic_get_key_stats(
3393 __in efx_nic_t *enp,
3394 __out efx_key_stats_t *ksp);
3397 extern __checkReturn efx_rc_t
3399 __in efx_nic_t *enp,
3400 __in uint64_t app_id,
3401 __out boolean_t *licensedp);
3404 extern __checkReturn efx_rc_t
3406 __in efx_nic_t *enp,
3407 __in size_t buffer_size,
3408 __out uint32_t *typep,
3409 __out size_t *lengthp,
3410 __out_opt uint8_t *bufferp);
3414 extern __checkReturn efx_rc_t
3416 __in efx_nic_t *enp,
3417 __in_bcount(buffer_size)
3419 __in size_t buffer_size,
3420 __out uint32_t *startp);
3423 extern __checkReturn efx_rc_t
3425 __in efx_nic_t *enp,
3426 __in_bcount(buffer_size)
3428 __in size_t buffer_size,
3429 __in uint32_t offset,
3430 __out uint32_t *endp);
3433 extern __checkReturn __success(return != B_FALSE) boolean_t
3435 __in efx_nic_t *enp,
3436 __in_bcount(buffer_size)
3438 __in size_t buffer_size,
3439 __in uint32_t offset,
3440 __out uint32_t *startp,
3441 __out uint32_t *lengthp);
3444 extern __checkReturn __success(return != B_FALSE) boolean_t
3445 efx_lic_validate_key(
3446 __in efx_nic_t *enp,
3447 __in_bcount(length) caddr_t keyp,
3448 __in uint32_t length);
3451 extern __checkReturn efx_rc_t
3453 __in efx_nic_t *enp,
3454 __in_bcount(buffer_size)
3456 __in size_t buffer_size,
3457 __in uint32_t offset,
3458 __in uint32_t length,
3459 __out_bcount_part(key_max_size, *lengthp)
3461 __in size_t key_max_size,
3462 __out uint32_t *lengthp);
3465 extern __checkReturn efx_rc_t
3467 __in efx_nic_t *enp,
3468 __in_bcount(buffer_size)
3470 __in size_t buffer_size,
3471 __in uint32_t offset,
3472 __in_bcount(length) caddr_t keyp,
3473 __in uint32_t length,
3474 __out uint32_t *lengthp);
3477 extern __checkReturn efx_rc_t
3479 __in efx_nic_t *enp,
3480 __in_bcount(buffer_size)
3482 __in size_t buffer_size,
3483 __in uint32_t offset,
3484 __in uint32_t length,
3486 __out uint32_t *deltap);
3489 extern __checkReturn efx_rc_t
3490 efx_lic_create_partition(
3491 __in efx_nic_t *enp,
3492 __in_bcount(buffer_size)
3494 __in size_t buffer_size);
3496 extern __checkReturn efx_rc_t
3497 efx_lic_finish_partition(
3498 __in efx_nic_t *enp,
3499 __in_bcount(buffer_size)
3501 __in size_t buffer_size);
3503 #endif /* EFSYS_OPT_LICENSING */
3507 #if EFSYS_OPT_TUNNEL
3510 extern __checkReturn efx_rc_t
3512 __in efx_nic_t *enp);
3517 __in efx_nic_t *enp);
3520 * For overlay network encapsulation using UDP, the firmware needs to know
3521 * the configured UDP port for the overlay so it can decode encapsulated
3523 * The UDP port/protocol list is global.
3527 extern __checkReturn efx_rc_t
3528 efx_tunnel_config_udp_add(
3529 __in efx_nic_t *enp,
3530 __in uint16_t port /* host/cpu-endian */,
3531 __in efx_tunnel_protocol_t protocol);
3534 extern __checkReturn efx_rc_t
3535 efx_tunnel_config_udp_remove(
3536 __in efx_nic_t *enp,
3537 __in uint16_t port /* host/cpu-endian */,
3538 __in efx_tunnel_protocol_t protocol);
3542 efx_tunnel_config_clear(
3543 __in efx_nic_t *enp);
3546 * Apply tunnel UDP ports configuration to hardware.
3548 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3552 extern __checkReturn efx_rc_t
3553 efx_tunnel_reconfigure(
3554 __in efx_nic_t *enp);
3556 #endif /* EFSYS_OPT_TUNNEL */
3558 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3561 * Firmware subvariant choice options.
3563 * It may be switched to no Tx checksum if attached drivers are either
3564 * preboot or firmware subvariant aware and no VIS are allocated.
3565 * If may be always switched to default explicitly using set request or
3566 * implicitly if unaware driver is attaching. If switching is done when
3567 * a driver is attached, it gets MC_REBOOT event and should recreate its
3570 * See SF-119419-TC DPDK Firmware Driver Interface and
3571 * SF-109306-TC EF10 for Driver Writers for details.
3573 typedef enum efx_nic_fw_subvariant_e {
3574 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3575 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3576 EFX_NIC_FW_SUBVARIANT_NTYPES
3577 } efx_nic_fw_subvariant_t;
3580 extern __checkReturn efx_rc_t
3581 efx_nic_get_fw_subvariant(
3582 __in efx_nic_t *enp,
3583 __out efx_nic_fw_subvariant_t *subvariantp);
3586 extern __checkReturn efx_rc_t
3587 efx_nic_set_fw_subvariant(
3588 __in efx_nic_t *enp,
3589 __in efx_nic_fw_subvariant_t subvariant);
3591 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3593 typedef enum efx_phy_fec_type_e {
3594 EFX_PHY_FEC_NONE = 0,
3597 } efx_phy_fec_type_t;
3600 extern __checkReturn efx_rc_t
3601 efx_phy_fec_type_get(
3602 __in efx_nic_t *enp,
3603 __out efx_phy_fec_type_t *typep);
3605 typedef struct efx_phy_link_state_s {
3606 uint32_t epls_adv_cap_mask;
3607 uint32_t epls_lp_cap_mask;
3608 uint32_t epls_ld_cap_mask;
3609 unsigned int epls_fcntl;
3610 efx_phy_fec_type_t epls_fec;
3611 efx_link_mode_t epls_link_mode;
3612 } efx_phy_link_state_t;
3615 extern __checkReturn efx_rc_t
3616 efx_phy_link_state_get(
3617 __in efx_nic_t *enp,
3618 __out efx_phy_link_state_t *eplsp);
3623 typedef uint32_t efx_vswitch_id_t;
3624 typedef uint32_t efx_vport_id_t;
3626 typedef enum efx_vswitch_type_e {
3627 EFX_VSWITCH_TYPE_VLAN = 1,
3628 EFX_VSWITCH_TYPE_VEB,
3629 /* VSWITCH_TYPE_VEPA: obsolete */
3630 EFX_VSWITCH_TYPE_MUX = 4,
3631 } efx_vswitch_type_t;
3633 typedef enum efx_vport_type_e {
3634 EFX_VPORT_TYPE_NORMAL = 4,
3635 EFX_VPORT_TYPE_EXPANSION,
3636 EFX_VPORT_TYPE_TEST,
3639 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3640 #define EFX_FILTER_VID_UNSPEC 0xffff
3641 #define EFX_DEFAULT_VSWITCH_ID 1
3643 /* Default VF VLAN ID on creation */
3644 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3645 #define EFX_VPORT_ID_INVALID 0
3647 typedef struct efx_vport_config_s {
3648 /* Either VF index or 0xffff for PF */
3649 uint16_t evc_function;
3650 /* VLAN ID of the associated function */
3652 /* vport id shared with client driver */
3653 efx_vport_id_t evc_vport_id;
3654 /* MAC address of the associated function */
3655 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3657 * vports created with this flag set may only transfer traffic on the
3658 * VLANs permitted by the vport. Also, an attempt to install filter with
3659 * VLAN will be refused unless requesting function has VLAN privilege.
3661 boolean_t evc_vlan_restrict;
3662 /* Whether this function is assigned or not */
3663 boolean_t evc_vport_assigned;
3664 } efx_vport_config_t;
3666 typedef struct efx_vswitch_s efx_vswitch_t;
3669 extern __checkReturn efx_rc_t
3671 __in efx_nic_t *enp);
3676 __in efx_nic_t *enp);
3679 extern __checkReturn efx_rc_t
3680 efx_evb_vswitch_create(
3681 __in efx_nic_t *enp,
3682 __in uint32_t num_vports,
3683 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3684 __deref_out efx_vswitch_t **evpp);
3687 extern __checkReturn efx_rc_t
3688 efx_evb_vswitch_destroy(
3689 __in efx_nic_t *enp,
3690 __in efx_vswitch_t *evp);
3693 extern __checkReturn efx_rc_t
3694 efx_evb_vport_mac_set(
3695 __in efx_nic_t *enp,
3696 __in efx_vswitch_t *evp,
3697 __in efx_vport_id_t vport_id,
3698 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3701 extern __checkReturn efx_rc_t
3702 efx_evb_vport_vlan_set(
3703 __in efx_nic_t *enp,
3704 __in efx_vswitch_t *evp,
3705 __in efx_vport_id_t vport_id,
3709 extern __checkReturn efx_rc_t
3710 efx_evb_vport_reset(
3711 __in efx_nic_t *enp,
3712 __in efx_vswitch_t *evp,
3713 __in efx_vport_id_t vport_id,
3714 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3716 __out boolean_t *is_fn_resetp);
3719 extern __checkReturn efx_rc_t
3720 efx_evb_vport_stats(
3721 __in efx_nic_t *enp,
3722 __in efx_vswitch_t *evp,
3723 __in efx_vport_id_t vport_id,
3724 __out efsys_mem_t *stats_bufferp);
3726 #endif /* EFSYS_OPT_EVB */
3728 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3730 typedef struct efx_proxy_auth_config_s {
3731 efsys_mem_t *request_bufferp;
3732 efsys_mem_t *response_bufferp;
3733 efsys_mem_t *status_bufferp;
3737 uint32_t handled_privileges;
3738 } efx_proxy_auth_config_t;
3740 typedef struct efx_proxy_cmd_params_s {
3743 uint8_t *request_bufferp;
3744 size_t request_size;
3745 uint8_t *response_bufferp;
3746 size_t response_size;
3747 size_t *response_size_actualp;
3748 } efx_proxy_cmd_params_t;
3751 extern __checkReturn efx_rc_t
3752 efx_proxy_auth_init(
3753 __in efx_nic_t *enp);
3757 efx_proxy_auth_fini(
3758 __in efx_nic_t *enp);
3761 extern __checkReturn efx_rc_t
3762 efx_proxy_auth_configure(
3763 __in efx_nic_t *enp,
3764 __in efx_proxy_auth_config_t *configp);
3767 extern __checkReturn efx_rc_t
3768 efx_proxy_auth_destroy(
3769 __in efx_nic_t *enp,
3770 __in uint32_t handled_privileges);
3773 extern __checkReturn efx_rc_t
3774 efx_proxy_auth_complete_request(
3775 __in efx_nic_t *enp,
3776 __in uint32_t fn_index,
3777 __in uint32_t proxy_result,
3778 __in uint32_t handle);
3781 extern __checkReturn efx_rc_t
3782 efx_proxy_auth_exec_cmd(
3783 __in efx_nic_t *enp,
3784 __inout efx_proxy_cmd_params_t *paramsp);
3787 extern __checkReturn efx_rc_t
3788 efx_proxy_auth_set_privilege_mask(
3789 __in efx_nic_t *enp,
3790 __in uint32_t vf_index,
3792 __in uint32_t value);
3795 extern __checkReturn efx_rc_t
3796 efx_proxy_auth_privilege_mask_get(
3797 __in efx_nic_t *enp,
3798 __in uint32_t pf_index,
3799 __in uint32_t vf_index,
3800 __out uint32_t *maskp);
3803 extern __checkReturn efx_rc_t
3804 efx_proxy_auth_privilege_modify(
3805 __in efx_nic_t *enp,
3806 __in uint32_t pf_index,
3807 __in uint32_t vf_index,
3808 __in uint32_t add_privileges_mask,
3809 __in uint32_t remove_privileges_mask);
3811 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3817 #endif /* _SYS_EFX_H */