1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
62 typedef enum efx_bar_type_e {
67 typedef struct efx_bar_region_s {
68 efx_bar_type_t ebr_type;
70 efsys_dma_addr_t ebr_offset;
71 efsys_dma_addr_t ebr_length;
74 /* The function is deprecated. It is used only if Riverhead is not supported. */
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
85 typedef struct efx_pci_ops_s {
87 * Function for reading PCIe configuration space.
89 * espcp System-specific PCIe device handle;
90 * offset Offset inside PCIe configuration space to start reading
92 * edp EFX DWORD structure that should be populated by function
93 * in little-endian order;
95 * Returns status code, 0 on success, any other value on error.
97 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp,
98 uint32_t offset, efx_dword_t *edp);
100 * Function for finding PCIe memory bar handle by its index from a PCIe
101 * device handle. The found memory bar is available in read-only mode.
103 * configp System-specific PCIe device handle;
104 * index Memory bar index;
105 * memp Pointer to the found memory bar handle;
107 * Returns status code, 0 on success, any other value on error.
109 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp,
110 int index, efsys_bar_t *memp);
113 /* Determine EFX family and perform lookup of the function control window
115 * The function requires PCI config handle from which all memory bars can
117 * A user of the API must be aware of memory bars indexes (not available
121 extern __checkReturn efx_rc_t
122 efx_family_probe_bar(
125 __in efsys_pci_config_t *espcp,
126 __in const efx_pci_ops_t *epop,
127 __out efx_family_t *efp,
128 __out efx_bar_region_t *ebrp);
130 #endif /* EFSYS_OPT_PCI */
133 #define EFX_PCI_VENID_SFC 0x1924
134 #define EFX_PCI_VENID_XILINX 0x10EE
136 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
138 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
139 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
140 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
142 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
143 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
144 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
146 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
147 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
149 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
150 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
151 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
153 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
154 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
155 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
157 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
158 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
160 #define EFX_MEM_BAR_SIENA 2
162 #define EFX_MEM_BAR_HUNTINGTON_PF 2
163 #define EFX_MEM_BAR_HUNTINGTON_VF 0
165 #define EFX_MEM_BAR_MEDFORD_PF 2
166 #define EFX_MEM_BAR_MEDFORD_VF 0
168 #define EFX_MEM_BAR_MEDFORD2 0
170 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
171 #define EFX_MEM_BAR_RIVERHEAD 2
179 EFX_ERR_BUFID_DC_OOB,
192 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
194 extern __checkReturn uint32_t
196 __in uint32_t crc_init,
197 __in_ecount(length) uint8_t const *input,
201 /* Type prototypes */
203 typedef struct efx_rxq_s efx_rxq_t;
207 typedef struct efx_nic_s efx_nic_t;
210 extern __checkReturn efx_rc_t
212 __in efx_family_t family,
213 __in efsys_identifier_t *esip,
214 __in efsys_bar_t *esbp,
215 __in uint32_t fcw_offset,
216 __in efsys_lock_t *eslp,
217 __deref_out efx_nic_t **enpp);
219 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
220 typedef enum efx_fw_variant_e {
221 EFX_FW_VARIANT_FULL_FEATURED,
222 EFX_FW_VARIANT_LOW_LATENCY,
223 EFX_FW_VARIANT_PACKED_STREAM,
224 EFX_FW_VARIANT_HIGH_TX_RATE,
225 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
226 EFX_FW_VARIANT_RULES_ENGINE,
228 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
232 extern __checkReturn efx_rc_t
235 __in efx_fw_variant_t efv);
238 extern __checkReturn efx_rc_t
240 __in efx_nic_t *enp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
248 extern __checkReturn boolean_t
249 efx_nic_hw_unavailable(
250 __in efx_nic_t *enp);
254 efx_nic_set_hw_unavailable(
255 __in efx_nic_t *enp);
260 extern __checkReturn efx_rc_t
261 efx_nic_register_test(
262 __in efx_nic_t *enp);
264 #endif /* EFSYS_OPT_DIAG */
269 __in efx_nic_t *enp);
274 __in efx_nic_t *enp);
279 __in efx_nic_t *enp);
281 #define EFX_PCIE_LINK_SPEED_GEN1 1
282 #define EFX_PCIE_LINK_SPEED_GEN2 2
283 #define EFX_PCIE_LINK_SPEED_GEN3 3
285 typedef enum efx_pcie_link_performance_e {
286 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
287 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
288 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
289 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
290 } efx_pcie_link_performance_t;
293 extern __checkReturn efx_rc_t
294 efx_nic_calculate_pcie_link_bandwidth(
295 __in uint32_t pcie_link_width,
296 __in uint32_t pcie_link_gen,
297 __out uint32_t *bandwidth_mbpsp);
300 extern __checkReturn efx_rc_t
301 efx_nic_check_pcie_link_speed(
303 __in uint32_t pcie_link_width,
304 __in uint32_t pcie_link_gen,
305 __out efx_pcie_link_performance_t *resultp);
309 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
310 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
311 #define WITH_MCDI_V2 1
314 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
316 typedef enum efx_mcdi_exception_e {
317 EFX_MCDI_EXCEPTION_MC_REBOOT,
318 EFX_MCDI_EXCEPTION_MC_BADASSERT,
319 } efx_mcdi_exception_t;
321 #if EFSYS_OPT_MCDI_LOGGING
322 typedef enum efx_log_msg_e {
324 EFX_LOG_MCDI_REQUEST,
325 EFX_LOG_MCDI_RESPONSE,
327 #endif /* EFSYS_OPT_MCDI_LOGGING */
329 typedef struct efx_mcdi_transport_s {
331 efsys_mem_t *emt_dma_mem;
332 void (*emt_execute)(void *, efx_mcdi_req_t *);
333 void (*emt_ev_cpl)(void *);
334 void (*emt_exception)(void *, efx_mcdi_exception_t);
335 #if EFSYS_OPT_MCDI_LOGGING
336 void (*emt_logger)(void *, efx_log_msg_t,
337 void *, size_t, void *, size_t);
338 #endif /* EFSYS_OPT_MCDI_LOGGING */
339 #if EFSYS_OPT_MCDI_PROXY_AUTH
340 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
341 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
342 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
343 void (*emt_ev_proxy_request)(void *, uint32_t);
344 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
345 } efx_mcdi_transport_t;
348 extern __checkReturn efx_rc_t
351 __in const efx_mcdi_transport_t *mtp);
354 extern __checkReturn efx_rc_t
356 __in efx_nic_t *enp);
361 __in efx_nic_t *enp);
365 efx_mcdi_get_timeout(
367 __in efx_mcdi_req_t *emrp,
368 __out uint32_t *usec_timeoutp);
372 efx_mcdi_request_start(
374 __in efx_mcdi_req_t *emrp,
375 __in boolean_t ev_cpl);
378 extern __checkReturn boolean_t
379 efx_mcdi_request_poll(
380 __in efx_nic_t *enp);
383 extern __checkReturn boolean_t
384 efx_mcdi_request_abort(
385 __in efx_nic_t *enp);
390 __in efx_nic_t *enp);
392 #endif /* EFSYS_OPT_MCDI */
396 #define EFX_NINTR_SIENA 1024
398 typedef enum efx_intr_type_e {
399 EFX_INTR_INVALID = 0,
405 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
408 extern __checkReturn efx_rc_t
411 __in efx_intr_type_t type,
412 __in_opt efsys_mem_t *esmp);
417 __in efx_nic_t *enp);
422 __in efx_nic_t *enp);
426 efx_intr_disable_unlocked(
427 __in efx_nic_t *enp);
429 #define EFX_INTR_NEVQS 32
432 extern __checkReturn efx_rc_t
435 __in unsigned int level);
439 efx_intr_status_line(
441 __out boolean_t *fatalp,
442 __out uint32_t *maskp);
446 efx_intr_status_message(
448 __in unsigned int message,
449 __out boolean_t *fatalp);
454 __in efx_nic_t *enp);
459 __in efx_nic_t *enp);
463 #if EFSYS_OPT_MAC_STATS
465 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
466 typedef enum efx_mac_stat_e {
469 EFX_MAC_RX_UNICST_PKTS,
470 EFX_MAC_RX_MULTICST_PKTS,
471 EFX_MAC_RX_BRDCST_PKTS,
472 EFX_MAC_RX_PAUSE_PKTS,
473 EFX_MAC_RX_LE_64_PKTS,
474 EFX_MAC_RX_65_TO_127_PKTS,
475 EFX_MAC_RX_128_TO_255_PKTS,
476 EFX_MAC_RX_256_TO_511_PKTS,
477 EFX_MAC_RX_512_TO_1023_PKTS,
478 EFX_MAC_RX_1024_TO_15XX_PKTS,
479 EFX_MAC_RX_GE_15XX_PKTS,
481 EFX_MAC_RX_FCS_ERRORS,
482 EFX_MAC_RX_DROP_EVENTS,
483 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
484 EFX_MAC_RX_SYMBOL_ERRORS,
485 EFX_MAC_RX_ALIGN_ERRORS,
486 EFX_MAC_RX_INTERNAL_ERRORS,
487 EFX_MAC_RX_JABBER_PKTS,
488 EFX_MAC_RX_LANE0_CHAR_ERR,
489 EFX_MAC_RX_LANE1_CHAR_ERR,
490 EFX_MAC_RX_LANE2_CHAR_ERR,
491 EFX_MAC_RX_LANE3_CHAR_ERR,
492 EFX_MAC_RX_LANE0_DISP_ERR,
493 EFX_MAC_RX_LANE1_DISP_ERR,
494 EFX_MAC_RX_LANE2_DISP_ERR,
495 EFX_MAC_RX_LANE3_DISP_ERR,
496 EFX_MAC_RX_MATCH_FAULT,
497 EFX_MAC_RX_NODESC_DROP_CNT,
500 EFX_MAC_TX_UNICST_PKTS,
501 EFX_MAC_TX_MULTICST_PKTS,
502 EFX_MAC_TX_BRDCST_PKTS,
503 EFX_MAC_TX_PAUSE_PKTS,
504 EFX_MAC_TX_LE_64_PKTS,
505 EFX_MAC_TX_65_TO_127_PKTS,
506 EFX_MAC_TX_128_TO_255_PKTS,
507 EFX_MAC_TX_256_TO_511_PKTS,
508 EFX_MAC_TX_512_TO_1023_PKTS,
509 EFX_MAC_TX_1024_TO_15XX_PKTS,
510 EFX_MAC_TX_GE_15XX_PKTS,
512 EFX_MAC_TX_SGL_COL_PKTS,
513 EFX_MAC_TX_MULT_COL_PKTS,
514 EFX_MAC_TX_EX_COL_PKTS,
515 EFX_MAC_TX_LATE_COL_PKTS,
517 EFX_MAC_TX_EX_DEF_PKTS,
518 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
519 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
520 EFX_MAC_PM_TRUNC_VFIFO_FULL,
521 EFX_MAC_PM_DISCARD_VFIFO_FULL,
522 EFX_MAC_PM_TRUNC_QBB,
523 EFX_MAC_PM_DISCARD_QBB,
524 EFX_MAC_PM_DISCARD_MAPPING,
525 EFX_MAC_RXDP_Q_DISABLED_PKTS,
526 EFX_MAC_RXDP_DI_DROPPED_PKTS,
527 EFX_MAC_RXDP_STREAMING_PKTS,
528 EFX_MAC_RXDP_HLB_FETCH,
529 EFX_MAC_RXDP_HLB_WAIT,
530 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
531 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
532 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
533 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
534 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
535 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
536 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
537 EFX_MAC_VADAPTER_RX_BAD_BYTES,
538 EFX_MAC_VADAPTER_RX_OVERFLOW,
539 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
540 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
541 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
542 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
543 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
544 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
545 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
546 EFX_MAC_VADAPTER_TX_BAD_BYTES,
547 EFX_MAC_VADAPTER_TX_OVERFLOW,
548 EFX_MAC_FEC_UNCORRECTED_ERRORS,
549 EFX_MAC_FEC_CORRECTED_ERRORS,
550 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
551 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
552 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
553 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
554 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
555 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
556 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
557 EFX_MAC_CTPIO_OVERFLOW_FAIL,
558 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
559 EFX_MAC_CTPIO_TIMEOUT_FAIL,
560 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
561 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
562 EFX_MAC_CTPIO_INVALID_WR_FAIL,
563 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
564 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
565 EFX_MAC_CTPIO_RUNT_FALLBACK,
566 EFX_MAC_CTPIO_SUCCESS,
567 EFX_MAC_CTPIO_FALLBACK,
568 EFX_MAC_CTPIO_POISON,
570 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
571 EFX_MAC_RXDP_HLB_IDLE,
572 EFX_MAC_RXDP_HLB_TIMEOUT,
576 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
578 #endif /* EFSYS_OPT_MAC_STATS */
580 typedef enum efx_link_mode_e {
581 EFX_LINK_UNKNOWN = 0,
597 #define EFX_MAC_ADDR_LEN 6
599 #define EFX_VNI_OR_VSID_LEN 3
601 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
603 #define EFX_MAC_MULTICAST_LIST_MAX 256
605 #define EFX_MAC_SDU_MAX 9202
607 #define EFX_MAC_PDU_ADJUSTMENT \
611 + /* bug16011 */ 16) \
613 #define EFX_MAC_PDU(_sdu) \
614 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
617 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
618 * the SDU rounded up slightly.
620 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
622 #define EFX_MAC_PDU_MIN 60
623 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
626 extern __checkReturn efx_rc_t
632 extern __checkReturn efx_rc_t
638 extern __checkReturn efx_rc_t
644 extern __checkReturn efx_rc_t
647 __in boolean_t all_unicst,
648 __in boolean_t mulcst,
649 __in boolean_t all_mulcst,
650 __in boolean_t brdcst);
654 efx_mac_filter_get_all_ucast_mcast(
656 __out boolean_t *all_unicst,
657 __out boolean_t *all_mulcst);
660 extern __checkReturn efx_rc_t
661 efx_mac_multicast_list_set(
663 __in_ecount(6*count) uint8_t const *addrs,
667 extern __checkReturn efx_rc_t
668 efx_mac_filter_default_rxq_set(
671 __in boolean_t using_rss);
675 efx_mac_filter_default_rxq_clear(
676 __in efx_nic_t *enp);
679 extern __checkReturn efx_rc_t
682 __in boolean_t enabled);
685 extern __checkReturn efx_rc_t
688 __out boolean_t *mac_upp);
690 #define EFX_FCNTL_RESPOND 0x00000001
691 #define EFX_FCNTL_GENERATE 0x00000002
694 extern __checkReturn efx_rc_t
697 __in unsigned int fcntl,
698 __in boolean_t autoneg);
704 __out unsigned int *fcntl_wantedp,
705 __out unsigned int *fcntl_linkp);
708 #if EFSYS_OPT_MAC_STATS
713 extern __checkReturn const char *
716 __in unsigned int id);
718 #endif /* EFSYS_OPT_NAMES */
720 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
722 #define EFX_MAC_STATS_MASK_NPAGES \
723 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
724 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
725 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
728 * Get mask of MAC statistics supported by the hardware.
730 * If mask_size is insufficient to return the mask, EINVAL error is
731 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
732 * (which is sizeof (uint32_t)) is sufficient.
735 extern __checkReturn efx_rc_t
736 efx_mac_stats_get_mask(
738 __out_bcount(mask_size) uint32_t *maskp,
739 __in size_t mask_size);
741 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
742 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
743 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
747 extern __checkReturn efx_rc_t
749 __in efx_nic_t *enp);
752 * Upload mac statistics supported by the hardware into the given buffer.
754 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
755 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
757 * The hardware will only DMA statistics that it understands (of course).
758 * Drivers should not make any assumptions about which statistics are
759 * supported, especially when the statistics are generated by firmware.
761 * Thus, drivers should zero this buffer before use, so that not-understood
762 * statistics read back as zero.
765 extern __checkReturn efx_rc_t
766 efx_mac_stats_upload(
768 __in efsys_mem_t *esmp);
771 extern __checkReturn efx_rc_t
772 efx_mac_stats_periodic(
774 __in efsys_mem_t *esmp,
775 __in uint16_t period_ms,
776 __in boolean_t events);
779 extern __checkReturn efx_rc_t
780 efx_mac_stats_update(
782 __in efsys_mem_t *esmp,
783 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
784 __inout_opt uint32_t *generationp);
786 #endif /* EFSYS_OPT_MAC_STATS */
790 typedef enum efx_mon_type_e {
803 __in efx_nic_t *enp);
805 #endif /* EFSYS_OPT_NAMES */
808 extern __checkReturn efx_rc_t
810 __in efx_nic_t *enp);
812 #if EFSYS_OPT_MON_STATS
814 #define EFX_MON_STATS_PAGE_SIZE 0x100
815 #define EFX_MON_MASK_ELEMENT_SIZE 32
817 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
818 typedef enum efx_mon_stat_e {
819 EFX_MON_STAT_CONTROLLER_TEMP,
820 EFX_MON_STAT_PHY_COMMON_TEMP,
821 EFX_MON_STAT_CONTROLLER_COOLING,
822 EFX_MON_STAT_PHY0_TEMP,
823 EFX_MON_STAT_PHY0_COOLING,
824 EFX_MON_STAT_PHY1_TEMP,
825 EFX_MON_STAT_PHY1_COOLING,
831 EFX_MON_STAT_IN_12V0,
832 EFX_MON_STAT_IN_1V2A,
833 EFX_MON_STAT_IN_VREF,
834 EFX_MON_STAT_OUT_VAOE,
835 EFX_MON_STAT_AOE_TEMP,
836 EFX_MON_STAT_PSU_AOE_TEMP,
837 EFX_MON_STAT_PSU_TEMP,
843 EFX_MON_STAT_IN_VAOE,
844 EFX_MON_STAT_OUT_IAOE,
845 EFX_MON_STAT_IN_IAOE,
846 EFX_MON_STAT_NIC_POWER,
848 EFX_MON_STAT_IN_I0V9,
849 EFX_MON_STAT_IN_I1V2,
850 EFX_MON_STAT_IN_0V9_ADC,
851 EFX_MON_STAT_CONTROLLER_2_TEMP,
852 EFX_MON_STAT_VREG_INTERNAL_TEMP,
853 EFX_MON_STAT_VREG_0V9_TEMP,
854 EFX_MON_STAT_VREG_1V2_TEMP,
855 EFX_MON_STAT_CONTROLLER_VPTAT,
856 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
857 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
858 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
859 EFX_MON_STAT_AMBIENT_TEMP,
860 EFX_MON_STAT_AIRFLOW,
861 EFX_MON_STAT_VDD08D_VSS08D_CSR,
862 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
863 EFX_MON_STAT_HOTPOINT_TEMP,
864 EFX_MON_STAT_PHY_POWER_PORT0,
865 EFX_MON_STAT_PHY_POWER_PORT1,
866 EFX_MON_STAT_MUM_VCC,
867 EFX_MON_STAT_IN_0V9_A,
868 EFX_MON_STAT_IN_I0V9_A,
869 EFX_MON_STAT_VREG_0V9_A_TEMP,
870 EFX_MON_STAT_IN_0V9_B,
871 EFX_MON_STAT_IN_I0V9_B,
872 EFX_MON_STAT_VREG_0V9_B_TEMP,
873 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
874 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
875 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
876 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
877 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
878 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
879 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
880 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
881 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
882 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
883 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
884 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
885 EFX_MON_STAT_SODIMM_VOUT,
886 EFX_MON_STAT_SODIMM_0_TEMP,
887 EFX_MON_STAT_SODIMM_1_TEMP,
888 EFX_MON_STAT_PHY0_VCC,
889 EFX_MON_STAT_PHY1_VCC,
890 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
891 EFX_MON_STAT_BOARD_FRONT_TEMP,
892 EFX_MON_STAT_BOARD_BACK_TEMP,
893 EFX_MON_STAT_IN_I1V8,
894 EFX_MON_STAT_IN_I2V5,
895 EFX_MON_STAT_IN_I3V3,
896 EFX_MON_STAT_IN_I12V0,
898 EFX_MON_STAT_IN_I1V3,
902 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
904 typedef enum efx_mon_stat_state_e {
905 EFX_MON_STAT_STATE_OK = 0,
906 EFX_MON_STAT_STATE_WARNING = 1,
907 EFX_MON_STAT_STATE_FATAL = 2,
908 EFX_MON_STAT_STATE_BROKEN = 3,
909 EFX_MON_STAT_STATE_NO_READING = 4,
910 } efx_mon_stat_state_t;
912 typedef enum efx_mon_stat_unit_e {
913 EFX_MON_STAT_UNIT_UNKNOWN = 0,
914 EFX_MON_STAT_UNIT_BOOL,
915 EFX_MON_STAT_UNIT_TEMP_C,
916 EFX_MON_STAT_UNIT_VOLTAGE_MV,
917 EFX_MON_STAT_UNIT_CURRENT_MA,
918 EFX_MON_STAT_UNIT_POWER_W,
919 EFX_MON_STAT_UNIT_RPM,
921 } efx_mon_stat_unit_t;
923 typedef struct efx_mon_stat_value_s {
925 efx_mon_stat_state_t emsv_state;
926 efx_mon_stat_unit_t emsv_unit;
927 } efx_mon_stat_value_t;
929 typedef struct efx_mon_limit_value_s {
930 uint16_t emlv_warning_min;
931 uint16_t emlv_warning_max;
932 uint16_t emlv_fatal_min;
933 uint16_t emlv_fatal_max;
934 } efx_mon_stat_limits_t;
936 typedef enum efx_mon_stat_portmask_e {
937 EFX_MON_STAT_PORTMAP_NONE = 0,
938 EFX_MON_STAT_PORTMAP_PORT0 = 1,
939 EFX_MON_STAT_PORTMAP_PORT1 = 2,
940 EFX_MON_STAT_PORTMAP_PORT2 = 3,
941 EFX_MON_STAT_PORTMAP_PORT3 = 4,
942 EFX_MON_STAT_PORTMAP_ALL = (-1),
943 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
944 } efx_mon_stat_portmask_t;
952 __in efx_mon_stat_t id);
956 efx_mon_stat_description(
958 __in efx_mon_stat_t id);
960 #endif /* EFSYS_OPT_NAMES */
963 extern __checkReturn boolean_t
964 efx_mon_mcdi_to_efx_stat(
966 __out efx_mon_stat_t *statp);
969 extern __checkReturn boolean_t
970 efx_mon_get_stat_unit(
971 __in efx_mon_stat_t stat,
972 __out efx_mon_stat_unit_t *unitp);
975 extern __checkReturn boolean_t
976 efx_mon_get_stat_portmap(
977 __in efx_mon_stat_t stat,
978 __out efx_mon_stat_portmask_t *maskp);
981 extern __checkReturn efx_rc_t
982 efx_mon_stats_update(
984 __in efsys_mem_t *esmp,
985 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
988 extern __checkReturn efx_rc_t
989 efx_mon_limits_update(
991 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
993 #endif /* EFSYS_OPT_MON_STATS */
998 __in efx_nic_t *enp);
1003 extern __checkReturn efx_rc_t
1005 __in efx_nic_t *enp);
1007 typedef enum efx_phy_led_mode_e {
1008 EFX_PHY_LED_DEFAULT = 0,
1013 } efx_phy_led_mode_t;
1015 #if EFSYS_OPT_PHY_LED_CONTROL
1018 extern __checkReturn efx_rc_t
1020 __in efx_nic_t *enp,
1021 __in efx_phy_led_mode_t mode);
1023 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1026 extern __checkReturn efx_rc_t
1028 __in efx_nic_t *enp);
1030 #if EFSYS_OPT_LOOPBACK
1032 typedef enum efx_loopback_type_e {
1033 EFX_LOOPBACK_OFF = 0,
1034 EFX_LOOPBACK_DATA = 1,
1035 EFX_LOOPBACK_GMAC = 2,
1036 EFX_LOOPBACK_XGMII = 3,
1037 EFX_LOOPBACK_XGXS = 4,
1038 EFX_LOOPBACK_XAUI = 5,
1039 EFX_LOOPBACK_GMII = 6,
1040 EFX_LOOPBACK_SGMII = 7,
1041 EFX_LOOPBACK_XGBR = 8,
1042 EFX_LOOPBACK_XFI = 9,
1043 EFX_LOOPBACK_XAUI_FAR = 10,
1044 EFX_LOOPBACK_GMII_FAR = 11,
1045 EFX_LOOPBACK_SGMII_FAR = 12,
1046 EFX_LOOPBACK_XFI_FAR = 13,
1047 EFX_LOOPBACK_GPHY = 14,
1048 EFX_LOOPBACK_PHY_XS = 15,
1049 EFX_LOOPBACK_PCS = 16,
1050 EFX_LOOPBACK_PMA_PMD = 17,
1051 EFX_LOOPBACK_XPORT = 18,
1052 EFX_LOOPBACK_XGMII_WS = 19,
1053 EFX_LOOPBACK_XAUI_WS = 20,
1054 EFX_LOOPBACK_XAUI_WS_FAR = 21,
1055 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
1056 EFX_LOOPBACK_GMII_WS = 23,
1057 EFX_LOOPBACK_XFI_WS = 24,
1058 EFX_LOOPBACK_XFI_WS_FAR = 25,
1059 EFX_LOOPBACK_PHYXS_WS = 26,
1060 EFX_LOOPBACK_PMA_INT = 27,
1061 EFX_LOOPBACK_SD_NEAR = 28,
1062 EFX_LOOPBACK_SD_FAR = 29,
1063 EFX_LOOPBACK_PMA_INT_WS = 30,
1064 EFX_LOOPBACK_SD_FEP2_WS = 31,
1065 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1066 EFX_LOOPBACK_SD_FEP_WS = 33,
1067 EFX_LOOPBACK_SD_FES_WS = 34,
1068 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1069 EFX_LOOPBACK_DATA_WS = 36,
1070 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1072 } efx_loopback_type_t;
1074 typedef enum efx_loopback_kind_e {
1075 EFX_LOOPBACK_KIND_OFF = 0,
1076 EFX_LOOPBACK_KIND_ALL,
1077 EFX_LOOPBACK_KIND_MAC,
1078 EFX_LOOPBACK_KIND_PHY,
1080 } efx_loopback_kind_t;
1085 __in efx_loopback_kind_t loopback_kind,
1086 __out efx_qword_t *maskp);
1089 extern __checkReturn efx_rc_t
1090 efx_port_loopback_set(
1091 __in efx_nic_t *enp,
1092 __in efx_link_mode_t link_mode,
1093 __in efx_loopback_type_t type);
1098 extern __checkReturn const char *
1099 efx_loopback_type_name(
1100 __in efx_nic_t *enp,
1101 __in efx_loopback_type_t type);
1103 #endif /* EFSYS_OPT_NAMES */
1105 #endif /* EFSYS_OPT_LOOPBACK */
1108 extern __checkReturn efx_rc_t
1110 __in efx_nic_t *enp,
1111 __out_opt efx_link_mode_t *link_modep);
1116 __in efx_nic_t *enp);
1118 typedef enum efx_phy_cap_type_e {
1119 EFX_PHY_CAP_INVALID = 0,
1124 EFX_PHY_CAP_1000HDX,
1125 EFX_PHY_CAP_1000FDX,
1126 EFX_PHY_CAP_10000FDX,
1130 EFX_PHY_CAP_40000FDX,
1132 EFX_PHY_CAP_100000FDX,
1133 EFX_PHY_CAP_25000FDX,
1134 EFX_PHY_CAP_50000FDX,
1135 EFX_PHY_CAP_BASER_FEC,
1136 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1138 EFX_PHY_CAP_RS_FEC_REQUESTED,
1139 EFX_PHY_CAP_25G_BASER_FEC,
1140 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1142 } efx_phy_cap_type_t;
1145 #define EFX_PHY_CAP_CURRENT 0x00000000
1146 #define EFX_PHY_CAP_DEFAULT 0x00000001
1147 #define EFX_PHY_CAP_PERM 0x00000002
1151 efx_phy_adv_cap_get(
1152 __in efx_nic_t *enp,
1154 __out uint32_t *maskp);
1157 extern __checkReturn efx_rc_t
1158 efx_phy_adv_cap_set(
1159 __in efx_nic_t *enp,
1160 __in uint32_t mask);
1165 __in efx_nic_t *enp,
1166 __out uint32_t *maskp);
1169 extern __checkReturn efx_rc_t
1171 __in efx_nic_t *enp,
1172 __out uint32_t *ouip);
1174 typedef enum efx_phy_media_type_e {
1175 EFX_PHY_MEDIA_INVALID = 0,
1180 EFX_PHY_MEDIA_SFP_PLUS,
1181 EFX_PHY_MEDIA_BASE_T,
1182 EFX_PHY_MEDIA_QSFP_PLUS,
1183 EFX_PHY_MEDIA_NTYPES
1184 } efx_phy_media_type_t;
1187 * Get the type of medium currently used. If the board has ports for
1188 * modules, a module is present, and we recognise the media type of
1189 * the module, then this will be the media type of the module.
1190 * Otherwise it will be the media type of the port.
1194 efx_phy_media_type_get(
1195 __in efx_nic_t *enp,
1196 __out efx_phy_media_type_t *typep);
1199 * 2-wire device address of the base information in accordance with SFF-8472
1200 * Diagnostic Monitoring Interface for Optical Transceivers section
1201 * 4 Memory Organization.
1203 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1206 * 2-wire device address of the digital diagnostics monitoring interface
1207 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1208 * Transceivers section 4 Memory Organization.
1210 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1213 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1214 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1217 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1220 * Maximum accessible data offset for PHY module information.
1222 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1226 extern __checkReturn efx_rc_t
1227 efx_phy_module_get_info(
1228 __in efx_nic_t *enp,
1229 __in uint8_t dev_addr,
1232 __out_bcount(len) uint8_t *data);
1234 #if EFSYS_OPT_PHY_STATS
1236 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1237 typedef enum efx_phy_stat_e {
1239 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1240 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1241 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1242 EFX_PHY_STAT_PMA_PMD_REV_A,
1243 EFX_PHY_STAT_PMA_PMD_REV_B,
1244 EFX_PHY_STAT_PMA_PMD_REV_C,
1245 EFX_PHY_STAT_PMA_PMD_REV_D,
1246 EFX_PHY_STAT_PCS_LINK_UP,
1247 EFX_PHY_STAT_PCS_RX_FAULT,
1248 EFX_PHY_STAT_PCS_TX_FAULT,
1249 EFX_PHY_STAT_PCS_BER,
1250 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1251 EFX_PHY_STAT_PHY_XS_LINK_UP,
1252 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1253 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1254 EFX_PHY_STAT_PHY_XS_ALIGN,
1255 EFX_PHY_STAT_PHY_XS_SYNC_A,
1256 EFX_PHY_STAT_PHY_XS_SYNC_B,
1257 EFX_PHY_STAT_PHY_XS_SYNC_C,
1258 EFX_PHY_STAT_PHY_XS_SYNC_D,
1259 EFX_PHY_STAT_AN_LINK_UP,
1260 EFX_PHY_STAT_AN_MASTER,
1261 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1262 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1263 EFX_PHY_STAT_CL22EXT_LINK_UP,
1268 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1269 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1270 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1271 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1272 EFX_PHY_STAT_AN_COMPLETE,
1273 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1274 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1275 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1276 EFX_PHY_STAT_PCS_FW_VERSION_0,
1277 EFX_PHY_STAT_PCS_FW_VERSION_1,
1278 EFX_PHY_STAT_PCS_FW_VERSION_2,
1279 EFX_PHY_STAT_PCS_FW_VERSION_3,
1280 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1281 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1282 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1283 EFX_PHY_STAT_PCS_OP_MODE,
1287 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1294 __in efx_nic_t *enp,
1295 __in efx_phy_stat_t stat);
1297 #endif /* EFSYS_OPT_NAMES */
1299 #define EFX_PHY_STATS_SIZE 0x100
1302 extern __checkReturn efx_rc_t
1303 efx_phy_stats_update(
1304 __in efx_nic_t *enp,
1305 __in efsys_mem_t *esmp,
1306 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1308 #endif /* EFSYS_OPT_PHY_STATS */
1313 typedef enum efx_bist_type_e {
1314 EFX_BIST_TYPE_UNKNOWN,
1315 EFX_BIST_TYPE_PHY_NORMAL,
1316 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1317 EFX_BIST_TYPE_PHY_CABLE_LONG,
1318 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1319 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1320 EFX_BIST_TYPE_REG, /* Test the register memories */
1321 EFX_BIST_TYPE_NTYPES,
1324 typedef enum efx_bist_result_e {
1325 EFX_BIST_RESULT_UNKNOWN,
1326 EFX_BIST_RESULT_RUNNING,
1327 EFX_BIST_RESULT_PASSED,
1328 EFX_BIST_RESULT_FAILED,
1329 } efx_bist_result_t;
1331 typedef enum efx_phy_cable_status_e {
1332 EFX_PHY_CABLE_STATUS_OK,
1333 EFX_PHY_CABLE_STATUS_INVALID,
1334 EFX_PHY_CABLE_STATUS_OPEN,
1335 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1336 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1337 EFX_PHY_CABLE_STATUS_BUSY,
1338 } efx_phy_cable_status_t;
1340 typedef enum efx_bist_value_e {
1341 EFX_BIST_PHY_CABLE_LENGTH_A,
1342 EFX_BIST_PHY_CABLE_LENGTH_B,
1343 EFX_BIST_PHY_CABLE_LENGTH_C,
1344 EFX_BIST_PHY_CABLE_LENGTH_D,
1345 EFX_BIST_PHY_CABLE_STATUS_A,
1346 EFX_BIST_PHY_CABLE_STATUS_B,
1347 EFX_BIST_PHY_CABLE_STATUS_C,
1348 EFX_BIST_PHY_CABLE_STATUS_D,
1349 EFX_BIST_FAULT_CODE,
1351 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1357 EFX_BIST_MEM_EXPECT,
1358 EFX_BIST_MEM_ACTUAL,
1360 EFX_BIST_MEM_ECC_PARITY,
1361 EFX_BIST_MEM_ECC_FATAL,
1366 extern __checkReturn efx_rc_t
1367 efx_bist_enable_offline(
1368 __in efx_nic_t *enp);
1371 extern __checkReturn efx_rc_t
1373 __in efx_nic_t *enp,
1374 __in efx_bist_type_t type);
1377 extern __checkReturn efx_rc_t
1379 __in efx_nic_t *enp,
1380 __in efx_bist_type_t type,
1381 __out efx_bist_result_t *resultp,
1382 __out_opt uint32_t *value_maskp,
1383 __out_ecount_opt(count) unsigned long *valuesp,
1389 __in efx_nic_t *enp,
1390 __in efx_bist_type_t type);
1392 #endif /* EFSYS_OPT_BIST */
1394 #define EFX_FEATURE_IPV6 0x00000001
1395 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1396 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1397 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1398 #define EFX_FEATURE_MCDI 0x00000020
1399 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1400 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1401 #define EFX_FEATURE_TURBO 0x00000100
1402 #define EFX_FEATURE_MCDI_DMA 0x00000200
1403 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1404 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1405 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1406 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1407 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1408 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1410 typedef enum efx_tunnel_protocol_e {
1411 EFX_TUNNEL_PROTOCOL_NONE = 0,
1412 EFX_TUNNEL_PROTOCOL_VXLAN,
1413 EFX_TUNNEL_PROTOCOL_GENEVE,
1414 EFX_TUNNEL_PROTOCOL_NVGRE,
1416 } efx_tunnel_protocol_t;
1418 typedef enum efx_vi_window_shift_e {
1419 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1420 EFX_VI_WINDOW_SHIFT_8K = 13,
1421 EFX_VI_WINDOW_SHIFT_16K = 14,
1422 EFX_VI_WINDOW_SHIFT_64K = 16,
1423 } efx_vi_window_shift_t;
1425 typedef struct efx_nic_cfg_s {
1426 uint32_t enc_board_type;
1427 uint32_t enc_phy_type;
1429 char enc_phy_name[21];
1431 char enc_phy_revision[21];
1432 efx_mon_type_t enc_mon_type;
1433 #if EFSYS_OPT_MON_STATS
1434 uint32_t enc_mon_stat_dma_buf_size;
1435 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1437 unsigned int enc_features;
1438 efx_vi_window_shift_t enc_vi_window_shift;
1439 uint8_t enc_mac_addr[6];
1440 uint8_t enc_port; /* PHY port number */
1441 uint32_t enc_intr_vec_base;
1442 uint32_t enc_intr_limit;
1443 uint32_t enc_evq_limit;
1444 uint32_t enc_txq_limit;
1445 uint32_t enc_rxq_limit;
1446 uint32_t enc_evq_max_nevs;
1447 uint32_t enc_evq_min_nevs;
1448 uint32_t enc_rxq_max_ndescs;
1449 uint32_t enc_rxq_min_ndescs;
1450 uint32_t enc_txq_max_ndescs;
1451 uint32_t enc_txq_min_ndescs;
1452 uint32_t enc_buftbl_limit;
1453 uint32_t enc_piobuf_limit;
1454 uint32_t enc_piobuf_size;
1455 uint32_t enc_piobuf_min_alloc_size;
1456 uint32_t enc_evq_timer_quantum_ns;
1457 uint32_t enc_evq_timer_max_us;
1458 uint32_t enc_clk_mult;
1459 uint32_t enc_ev_ew_desc_size;
1460 uint32_t enc_ev_desc_size;
1461 uint32_t enc_rx_desc_size;
1462 uint32_t enc_tx_desc_size;
1463 /* Maximum Rx prefix size if many Rx prefixes are supported */
1464 uint32_t enc_rx_prefix_size;
1465 uint32_t enc_rx_buf_align_start;
1466 uint32_t enc_rx_buf_align_end;
1467 #if EFSYS_OPT_RX_SCALE
1468 uint32_t enc_rx_scale_max_exclusive_contexts;
1470 * Mask of supported hash algorithms.
1471 * Hash algorithm types are used as the bit indices.
1473 uint32_t enc_rx_scale_hash_alg_mask;
1475 * Indicates whether port numbers can be included to the
1476 * input data for hash computation.
1478 boolean_t enc_rx_scale_l4_hash_supported;
1479 boolean_t enc_rx_scale_additional_modes_supported;
1480 #endif /* EFSYS_OPT_RX_SCALE */
1481 #if EFSYS_OPT_LOOPBACK
1482 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1483 #endif /* EFSYS_OPT_LOOPBACK */
1484 #if EFSYS_OPT_PHY_FLAGS
1485 uint32_t enc_phy_flags_mask;
1486 #endif /* EFSYS_OPT_PHY_FLAGS */
1487 #if EFSYS_OPT_PHY_LED_CONTROL
1488 uint32_t enc_led_mask;
1489 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1490 #if EFSYS_OPT_PHY_STATS
1491 uint64_t enc_phy_stat_mask;
1492 #endif /* EFSYS_OPT_PHY_STATS */
1494 uint8_t enc_mcdi_mdio_channel;
1495 #if EFSYS_OPT_PHY_STATS
1496 uint32_t enc_mcdi_phy_stat_mask;
1497 #endif /* EFSYS_OPT_PHY_STATS */
1498 #if EFSYS_OPT_MON_STATS
1499 uint32_t *enc_mcdi_sensor_maskp;
1500 uint32_t enc_mcdi_sensor_mask_size;
1501 #endif /* EFSYS_OPT_MON_STATS */
1502 #endif /* EFSYS_OPT_MCDI */
1504 uint32_t enc_bist_mask;
1505 #endif /* EFSYS_OPT_BIST */
1506 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1509 uint32_t enc_privilege_mask;
1510 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1511 boolean_t enc_evq_init_done_ev_supported;
1512 boolean_t enc_bug26807_workaround;
1513 boolean_t enc_bug35388_workaround;
1514 boolean_t enc_bug41750_workaround;
1515 boolean_t enc_bug61265_workaround;
1516 boolean_t enc_bug61297_workaround;
1517 boolean_t enc_rx_batching_enabled;
1518 /* Maximum number of descriptors completed in an rx event. */
1519 uint32_t enc_rx_batch_max;
1520 /* Number of rx descriptors the hardware requires for a push. */
1521 uint32_t enc_rx_push_align;
1522 /* Maximum amount of data in DMA descriptor */
1523 uint32_t enc_tx_dma_desc_size_max;
1525 * Boundary which DMA descriptor data must not cross or 0 if no
1528 uint32_t enc_tx_dma_desc_boundary;
1530 * Maximum number of bytes into the packet the TCP header can start for
1531 * the hardware to apply TSO packet edits.
1533 uint32_t enc_tx_tso_tcp_header_offset_limit;
1534 /* Maximum number of header DMA descriptors per TSO transaction. */
1535 uint32_t enc_tx_tso_max_header_ndescs;
1536 /* Maximum header length acceptable by TSO transaction. */
1537 uint32_t enc_tx_tso_max_header_length;
1538 /* Maximum number of payload DMA descriptors per TSO transaction. */
1539 uint32_t enc_tx_tso_max_payload_ndescs;
1540 /* Maximum payload length per TSO transaction. */
1541 uint32_t enc_tx_tso_max_payload_length;
1542 /* Maximum number of frames to be generated per TSO transaction. */
1543 uint32_t enc_tx_tso_max_nframes;
1544 boolean_t enc_fw_assisted_tso_enabled;
1545 boolean_t enc_fw_assisted_tso_v2_enabled;
1546 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1547 boolean_t enc_tso_v3_enabled;
1548 /* Number of TSO contexts on the NIC (FATSOv2) */
1549 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1550 boolean_t enc_hw_tx_insert_vlan_enabled;
1551 /* Number of PFs on the NIC */
1552 uint32_t enc_hw_pf_count;
1553 /* Datapath firmware vadapter/vport/vswitch support */
1554 boolean_t enc_datapath_cap_evb;
1555 /* Datapath firmware vport reconfigure support */
1556 boolean_t enc_vport_reconfigure_supported;
1557 boolean_t enc_rx_disable_scatter_supported;
1558 /* Maximum number of Rx scatter segments supported by HW */
1559 uint32_t enc_rx_scatter_max;
1560 boolean_t enc_allow_set_mac_with_installed_filters;
1561 boolean_t enc_enhanced_set_mac_supported;
1562 boolean_t enc_init_evq_v2_supported;
1563 boolean_t enc_init_evq_extended_width_supported;
1564 boolean_t enc_no_cont_ev_mode_supported;
1565 boolean_t enc_init_rxq_with_buffer_size;
1566 boolean_t enc_rx_packed_stream_supported;
1567 boolean_t enc_rx_var_packed_stream_supported;
1568 boolean_t enc_rx_es_super_buffer_supported;
1569 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1570 boolean_t enc_pm_and_rxdp_counters;
1571 boolean_t enc_mac_stats_40g_tx_size_bins;
1572 uint32_t enc_tunnel_encapsulations_supported;
1574 * NIC global maximum for unique UDP tunnel ports shared by all
1577 uint32_t enc_tunnel_config_udp_entries_max;
1578 /* External port identifier */
1579 uint8_t enc_external_port;
1580 uint32_t enc_mcdi_max_payload_length;
1581 /* VPD may be per-PF or global */
1582 boolean_t enc_vpd_is_global;
1583 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1584 uint32_t enc_required_pcie_bandwidth_mbps;
1585 uint32_t enc_max_pcie_link_gen;
1586 /* Firmware verifies integrity of NVRAM updates */
1587 boolean_t enc_nvram_update_verify_result_supported;
1588 /* Firmware supports polled NVRAM updates on select partitions */
1589 boolean_t enc_nvram_update_poll_verify_result_supported;
1590 /* Firmware accepts updates via the BUNDLE partition */
1591 boolean_t enc_nvram_bundle_update_supported;
1592 /* Firmware support for extended MAC_STATS buffer */
1593 uint32_t enc_mac_stats_nstats;
1594 boolean_t enc_fec_counters;
1595 boolean_t enc_hlb_counters;
1596 /* NIC support for Match-Action Engine (MAE). */
1597 boolean_t enc_mae_supported;
1598 /* Firmware support for "FLAG" and "MARK" filter actions */
1599 boolean_t enc_filter_action_flag_supported;
1600 boolean_t enc_filter_action_mark_supported;
1601 uint32_t enc_filter_action_mark_max;
1602 /* Port assigned to this PCI function */
1603 uint32_t enc_assigned_port;
1606 #define EFX_PCI_VF_INVALID 0xffff
1608 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1609 ((configp)->evc_function == EFX_PCI_VF_INVALID)
1611 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID)
1612 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID)
1614 #define EFX_PCI_FUNCTION(_encp) \
1615 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1617 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1620 extern const efx_nic_cfg_t *
1622 __in const efx_nic_t *enp);
1624 /* RxDPCPU firmware id values by which FW variant can be identified */
1625 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1626 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1627 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1628 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1629 #define EFX_RXDP_DPDK_FW_ID 0x6
1631 typedef struct efx_nic_fw_info_s {
1632 /* Basic FW version information */
1633 uint16_t enfi_mc_fw_version[4];
1635 * If datapath capabilities can be detected,
1636 * additional FW information is to be shown
1638 boolean_t enfi_dpcpu_fw_ids_valid;
1639 /* Rx and Tx datapath CPU FW IDs */
1640 uint16_t enfi_rx_dpcpu_fw_id;
1641 uint16_t enfi_tx_dpcpu_fw_id;
1642 } efx_nic_fw_info_t;
1645 extern __checkReturn efx_rc_t
1646 efx_nic_get_fw_version(
1647 __in efx_nic_t *enp,
1648 __out efx_nic_fw_info_t *enfip);
1650 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64)
1651 #define EFX_NIC_BOARD_INFO_NAME_LEN (16)
1653 typedef struct efx_nic_board_info_s {
1654 /* The following two fields are NUL-terminated ASCII strings. */
1655 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN];
1656 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN];
1657 uint32_t enbi_revision;
1658 } efx_nic_board_info_t;
1661 extern __checkReturn efx_rc_t
1662 efx_nic_get_board_info(
1663 __in efx_nic_t *enp,
1664 __out efx_nic_board_info_t *board_infop);
1666 /* Driver resource limits (minimum required/maximum usable). */
1667 typedef struct efx_drv_limits_s {
1668 uint32_t edl_min_evq_count;
1669 uint32_t edl_max_evq_count;
1671 uint32_t edl_min_rxq_count;
1672 uint32_t edl_max_rxq_count;
1674 uint32_t edl_min_txq_count;
1675 uint32_t edl_max_txq_count;
1677 /* PIO blocks (sub-allocated from piobuf) */
1678 uint32_t edl_min_pio_alloc_size;
1679 uint32_t edl_max_pio_alloc_count;
1683 extern __checkReturn efx_rc_t
1684 efx_nic_set_drv_limits(
1685 __inout efx_nic_t *enp,
1686 __in efx_drv_limits_t *edlp);
1689 * Register the OS driver version string for management agents
1690 * (e.g. via NC-SI). The content length is provided (i.e. no
1691 * NUL terminator). Use length 0 to indicate no version string
1692 * should be advertised. It is valid to set the version string
1693 * only before efx_nic_probe() is called.
1696 extern __checkReturn efx_rc_t
1697 efx_nic_set_drv_version(
1698 __inout efx_nic_t *enp,
1699 __in_ecount(length) char const *verp,
1700 __in size_t length);
1702 typedef enum efx_nic_region_e {
1703 EFX_REGION_VI, /* Memory BAR UC mapping */
1704 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1708 extern __checkReturn efx_rc_t
1709 efx_nic_get_bar_region(
1710 __in efx_nic_t *enp,
1711 __in efx_nic_region_t region,
1712 __out uint32_t *offsetp,
1713 __out size_t *sizep);
1716 extern __checkReturn efx_rc_t
1717 efx_nic_get_vi_pool(
1718 __in efx_nic_t *enp,
1719 __out uint32_t *evq_countp,
1720 __out uint32_t *rxq_countp,
1721 __out uint32_t *txq_countp);
1726 typedef enum efx_vpd_tag_e {
1733 typedef uint16_t efx_vpd_keyword_t;
1735 typedef struct efx_vpd_value_s {
1736 efx_vpd_tag_t evv_tag;
1737 efx_vpd_keyword_t evv_keyword;
1739 uint8_t evv_value[0x100];
1743 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1746 extern __checkReturn efx_rc_t
1748 __in efx_nic_t *enp);
1751 extern __checkReturn efx_rc_t
1753 __in efx_nic_t *enp,
1754 __out size_t *sizep);
1757 extern __checkReturn efx_rc_t
1759 __in efx_nic_t *enp,
1760 __out_bcount(size) caddr_t data,
1764 extern __checkReturn efx_rc_t
1766 __in efx_nic_t *enp,
1767 __in_bcount(size) caddr_t data,
1771 extern __checkReturn efx_rc_t
1773 __in efx_nic_t *enp,
1774 __in_bcount(size) caddr_t data,
1778 extern __checkReturn efx_rc_t
1780 __in efx_nic_t *enp,
1781 __in_bcount(size) caddr_t data,
1783 __inout efx_vpd_value_t *evvp);
1786 extern __checkReturn efx_rc_t
1788 __in efx_nic_t *enp,
1789 __inout_bcount(size) caddr_t data,
1791 __in efx_vpd_value_t *evvp);
1794 extern __checkReturn efx_rc_t
1796 __in efx_nic_t *enp,
1797 __inout_bcount(size) caddr_t data,
1799 __out efx_vpd_value_t *evvp,
1800 __inout unsigned int *contp);
1803 extern __checkReturn efx_rc_t
1805 __in efx_nic_t *enp,
1806 __in_bcount(size) caddr_t data,
1812 __in efx_nic_t *enp);
1814 #endif /* EFSYS_OPT_VPD */
1820 typedef enum efx_nvram_type_e {
1821 EFX_NVRAM_INVALID = 0,
1823 EFX_NVRAM_BOOTROM_CFG,
1824 EFX_NVRAM_MC_FIRMWARE,
1825 EFX_NVRAM_MC_GOLDEN,
1831 EFX_NVRAM_FPGA_BACKUP,
1832 EFX_NVRAM_DYNAMIC_CFG,
1835 EFX_NVRAM_MUM_FIRMWARE,
1836 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1837 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1839 EFX_NVRAM_BUNDLE_METADATA,
1843 typedef struct efx_nvram_info_s {
1845 uint32_t eni_partn_size;
1846 uint32_t eni_address;
1847 uint32_t eni_erase_size;
1848 uint32_t eni_write_size;
1851 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1854 extern __checkReturn efx_rc_t
1856 __in efx_nic_t *enp);
1861 extern __checkReturn efx_rc_t
1863 __in efx_nic_t *enp);
1865 #endif /* EFSYS_OPT_DIAG */
1868 extern __checkReturn efx_rc_t
1870 __in efx_nic_t *enp,
1871 __in efx_nvram_type_t type,
1872 __out size_t *sizep);
1875 extern __checkReturn efx_rc_t
1877 __in efx_nic_t *enp,
1878 __in efx_nvram_type_t type,
1879 __out efx_nvram_info_t *enip);
1882 extern __checkReturn efx_rc_t
1884 __in efx_nic_t *enp,
1885 __in efx_nvram_type_t type,
1886 __out_opt size_t *pref_chunkp);
1889 extern __checkReturn efx_rc_t
1890 efx_nvram_rw_finish(
1891 __in efx_nic_t *enp,
1892 __in efx_nvram_type_t type,
1893 __out_opt uint32_t *verify_resultp);
1896 extern __checkReturn efx_rc_t
1897 efx_nvram_get_version(
1898 __in efx_nic_t *enp,
1899 __in efx_nvram_type_t type,
1900 __out uint32_t *subtypep,
1901 __out_ecount(4) uint16_t version[4]);
1904 extern __checkReturn efx_rc_t
1905 efx_nvram_read_chunk(
1906 __in efx_nic_t *enp,
1907 __in efx_nvram_type_t type,
1908 __in unsigned int offset,
1909 __out_bcount(size) caddr_t data,
1913 extern __checkReturn efx_rc_t
1914 efx_nvram_read_backup(
1915 __in efx_nic_t *enp,
1916 __in efx_nvram_type_t type,
1917 __in unsigned int offset,
1918 __out_bcount(size) caddr_t data,
1922 extern __checkReturn efx_rc_t
1923 efx_nvram_set_version(
1924 __in efx_nic_t *enp,
1925 __in efx_nvram_type_t type,
1926 __in_ecount(4) uint16_t version[4]);
1929 extern __checkReturn efx_rc_t
1931 __in efx_nic_t *enp,
1932 __in efx_nvram_type_t type,
1933 __in_bcount(partn_size) caddr_t partn_data,
1934 __in size_t partn_size);
1937 extern __checkReturn efx_rc_t
1939 __in efx_nic_t *enp,
1940 __in efx_nvram_type_t type);
1943 extern __checkReturn efx_rc_t
1944 efx_nvram_write_chunk(
1945 __in efx_nic_t *enp,
1946 __in efx_nvram_type_t type,
1947 __in unsigned int offset,
1948 __in_bcount(size) caddr_t data,
1954 __in efx_nic_t *enp);
1956 #endif /* EFSYS_OPT_NVRAM */
1958 #if EFSYS_OPT_BOOTCFG
1960 /* Report size and offset of bootcfg sector in NVRAM partition. */
1962 extern __checkReturn efx_rc_t
1963 efx_bootcfg_sector_info(
1964 __in efx_nic_t *enp,
1966 __out_opt uint32_t *sector_countp,
1967 __out size_t *offsetp,
1968 __out size_t *max_sizep);
1971 * Copy bootcfg sector data to a target buffer which may differ in size.
1972 * Optionally corrects format errors in source buffer.
1976 efx_bootcfg_copy_sector(
1977 __in efx_nic_t *enp,
1978 __inout_bcount(sector_length)
1980 __in size_t sector_length,
1981 __out_bcount(data_size) uint8_t *data,
1982 __in size_t data_size,
1983 __in boolean_t handle_format_errors);
1988 __in efx_nic_t *enp,
1989 __out_bcount(size) uint8_t *data,
1995 __in efx_nic_t *enp,
1996 __in_bcount(size) uint8_t *data,
2001 * Processing routines for buffers arranged in the DHCP/BOOTP option format
2002 * (see https://tools.ietf.org/html/rfc1533)
2004 * Summarising the format: the buffer is a sequence of options. All options
2005 * begin with a tag octet, which uniquely identifies the option. Fixed-
2006 * length options without data consist of only a tag octet. Only options PAD
2007 * (0) and END (255) are fixed length. All other options are variable-length
2008 * with a length octet following the tag octet. The value of the length
2009 * octet does not include the two octets specifying the tag and length. The
2010 * length octet is followed by "length" octets of data.
2012 * Option data may be a sequence of sub-options in the same format. The data
2013 * content of the encapsulating option is one or more encapsulated sub-options,
2014 * with no terminating END tag is required.
2016 * To be valid, the top-level sequence of options should be terminated by an
2017 * END tag. The buffer should be padded with the PAD byte.
2019 * When stored to NVRAM, the DHCP option format buffer is preceded by a
2020 * checksum octet. The full buffer (including after the END tag) contributes
2021 * to the checksum, hence the need to fill the buffer to the end with PAD.
2024 #define EFX_DHCP_END ((uint8_t)0xff)
2025 #define EFX_DHCP_PAD ((uint8_t)0)
2027 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
2028 (uint16_t)(((encapsulator) << 8) | (encapsulated))
2031 extern __checkReturn uint8_t
2033 __in_bcount(size) uint8_t const *data,
2037 extern __checkReturn efx_rc_t
2039 __in_bcount(size) uint8_t const *data,
2041 __out_opt size_t *usedp);
2044 extern __checkReturn efx_rc_t
2046 __in_bcount(buffer_length) uint8_t *bufferp,
2047 __in size_t buffer_length,
2049 __deref_out uint8_t **valuepp,
2050 __out size_t *value_lengthp);
2053 extern __checkReturn efx_rc_t
2055 __in_bcount(buffer_length) uint8_t *bufferp,
2056 __in size_t buffer_length,
2057 __deref_out uint8_t **endpp);
2061 extern __checkReturn efx_rc_t
2062 efx_dhcp_delete_tag(
2063 __inout_bcount(buffer_length) uint8_t *bufferp,
2064 __in size_t buffer_length,
2068 extern __checkReturn efx_rc_t
2070 __inout_bcount(buffer_length) uint8_t *bufferp,
2071 __in size_t buffer_length,
2073 __in_bcount_opt(value_length) uint8_t *valuep,
2074 __in size_t value_length);
2077 extern __checkReturn efx_rc_t
2078 efx_dhcp_update_tag(
2079 __inout_bcount(buffer_length) uint8_t *bufferp,
2080 __in size_t buffer_length,
2082 __in uint8_t *value_locationp,
2083 __in_bcount_opt(value_length) uint8_t *valuep,
2084 __in size_t value_length);
2087 #endif /* EFSYS_OPT_BOOTCFG */
2089 #if EFSYS_OPT_IMAGE_LAYOUT
2091 #include "ef10_signed_image_layout.h"
2094 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2097 * The image header format is extensible. However, older drivers require an
2098 * exact match of image header version and header length when validating and
2099 * writing firmware images.
2101 * To avoid breaking backward compatibility, we use the upper bits of the
2102 * controller version fields to contain an extra version number used for
2103 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2104 * version). See bug39254 and SF-102785-PS for details.
2106 typedef struct efx_image_header_s {
2108 uint32_t eih_version;
2110 uint32_t eih_subtype;
2111 uint32_t eih_code_size;
2114 uint32_t eih_controller_version_min;
2116 uint16_t eih_controller_version_min_short;
2117 uint8_t eih_extra_version_a;
2118 uint8_t eih_extra_version_b;
2122 uint32_t eih_controller_version_max;
2124 uint16_t eih_controller_version_max_short;
2125 uint8_t eih_extra_version_c;
2126 uint8_t eih_extra_version_d;
2129 uint16_t eih_code_version_a;
2130 uint16_t eih_code_version_b;
2131 uint16_t eih_code_version_c;
2132 uint16_t eih_code_version_d;
2133 } efx_image_header_t;
2135 #define EFX_IMAGE_HEADER_SIZE (40)
2136 #define EFX_IMAGE_HEADER_VERSION (4)
2137 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2140 typedef struct efx_image_trailer_s {
2142 } efx_image_trailer_t;
2144 #define EFX_IMAGE_TRAILER_SIZE (4)
2146 typedef enum efx_image_format_e {
2147 EFX_IMAGE_FORMAT_NO_IMAGE,
2148 EFX_IMAGE_FORMAT_INVALID,
2149 EFX_IMAGE_FORMAT_UNSIGNED,
2150 EFX_IMAGE_FORMAT_SIGNED,
2151 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2152 } efx_image_format_t;
2154 typedef struct efx_image_info_s {
2155 efx_image_format_t eii_format;
2156 uint8_t * eii_imagep;
2157 size_t eii_image_size;
2158 efx_image_header_t * eii_headerp;
2162 extern __checkReturn efx_rc_t
2163 efx_check_reflash_image(
2165 __in uint32_t buffer_size,
2166 __out efx_image_info_t *infop);
2169 extern __checkReturn efx_rc_t
2170 efx_build_signed_image_write_buffer(
2171 __out_bcount(buffer_size)
2173 __in uint32_t buffer_size,
2174 __in efx_image_info_t *infop,
2175 __out efx_image_header_t **headerpp);
2177 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2181 typedef enum efx_pattern_type_t {
2182 EFX_PATTERN_BYTE_INCREMENT = 0,
2183 EFX_PATTERN_ALL_THE_SAME,
2184 EFX_PATTERN_BIT_ALTERNATE,
2185 EFX_PATTERN_BYTE_ALTERNATE,
2186 EFX_PATTERN_BYTE_CHANGING,
2187 EFX_PATTERN_BIT_SWEEP,
2189 } efx_pattern_type_t;
2192 (*efx_sram_pattern_fn_t)(
2194 __in boolean_t negate,
2195 __out efx_qword_t *eqp);
2198 extern __checkReturn efx_rc_t
2200 __in efx_nic_t *enp,
2201 __in efx_pattern_type_t type);
2203 #endif /* EFSYS_OPT_DIAG */
2206 extern __checkReturn efx_rc_t
2207 efx_sram_buf_tbl_set(
2208 __in efx_nic_t *enp,
2210 __in efsys_mem_t *esmp,
2215 efx_sram_buf_tbl_clear(
2216 __in efx_nic_t *enp,
2220 #define EFX_BUF_TBL_SIZE 0x20000
2222 #define EFX_BUF_SIZE 4096
2226 typedef struct efx_evq_s efx_evq_t;
2228 #if EFSYS_OPT_QSTATS
2230 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2231 typedef enum efx_ev_qstat_e {
2237 EV_RX_PAUSE_FRM_ERR,
2238 EV_RX_BUF_OWNER_ID_ERR,
2239 EV_RX_IPV4_HDR_CHKSUM_ERR,
2240 EV_RX_TCP_UDP_CHKSUM_ERR,
2244 EV_RX_MCAST_HASH_MATCH,
2261 EV_DRIVER_SRM_UPD_DONE,
2262 EV_DRIVER_TX_DESCQ_FLS_DONE,
2263 EV_DRIVER_RX_DESCQ_FLS_DONE,
2264 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2265 EV_DRIVER_RX_DSC_ERROR,
2266 EV_DRIVER_TX_DSC_ERROR,
2269 EV_RX_PARSE_INCOMPLETE,
2273 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2275 #endif /* EFSYS_OPT_QSTATS */
2278 extern __checkReturn efx_rc_t
2280 __in efx_nic_t *enp);
2285 __in efx_nic_t *enp);
2288 extern __checkReturn size_t
2290 __in const efx_nic_t *enp,
2291 __in unsigned int ndescs,
2292 __in uint32_t flags);
2295 extern __checkReturn unsigned int
2297 __in const efx_nic_t *enp,
2298 __in unsigned int ndescs,
2299 __in uint32_t flags);
2301 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2302 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2303 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2304 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2306 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2307 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2308 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2311 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2312 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2315 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2316 * which is the case when an event queue is set to THROUGHPUT mode.
2318 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2320 /* Configure EVQ for extended width events (EF100 only) */
2321 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20)
2325 extern __checkReturn efx_rc_t
2327 __in efx_nic_t *enp,
2328 __in unsigned int index,
2329 __in efsys_mem_t *esmp,
2333 __in uint32_t flags,
2334 __deref_out efx_evq_t **eepp);
2337 extern __checkReturn efx_rc_t
2339 __in efx_nic_t *enp,
2340 __in unsigned int index,
2341 __in efsys_mem_t *esmp,
2345 __in uint32_t flags,
2347 __deref_out efx_evq_t **eepp);
2352 __in efx_evq_t *eep,
2353 __in uint16_t data);
2355 typedef __checkReturn boolean_t
2356 (*efx_initialized_ev_t)(
2357 __in_opt void *arg);
2359 #define EFX_PKT_UNICAST 0x0004
2360 #define EFX_PKT_START 0x0008
2362 #define EFX_PKT_VLAN_TAGGED 0x0010
2363 #define EFX_CKSUM_TCPUDP 0x0020
2364 #define EFX_CKSUM_IPV4 0x0040
2365 #define EFX_PKT_CONT 0x0080
2367 #define EFX_CHECK_VLAN 0x0100
2368 #define EFX_PKT_TCP 0x0200
2369 #define EFX_PKT_UDP 0x0400
2370 #define EFX_PKT_IPV4 0x0800
2372 #define EFX_PKT_IPV6 0x1000
2373 #define EFX_PKT_PREFIX_LEN 0x2000
2374 #define EFX_ADDR_MISMATCH 0x4000
2375 #define EFX_DISCARD 0x8000
2378 * The following flags are used only for packed stream
2379 * mode. The values for the flags are reused to fit into 16 bit,
2380 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2381 * packed stream mode
2383 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2384 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2387 #define EFX_EV_RX_NLABELS 32
2388 #define EFX_EV_TX_NLABELS 32
2390 typedef __checkReturn boolean_t
2393 __in uint32_t label,
2396 __in uint16_t flags);
2398 typedef __checkReturn boolean_t
2399 (*efx_rx_packets_ev_t)(
2401 __in uint32_t label,
2402 __in unsigned int num_packets,
2403 __in uint32_t flags);
2405 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2408 * Packed stream mode is documented in SF-112241-TC.
2409 * The general idea is that, instead of putting each incoming
2410 * packet into a separate buffer which is specified in a RX
2411 * descriptor, a large buffer is provided to the hardware and
2412 * packets are put there in a continuous stream.
2413 * The main advantage of such an approach is that RX queue refilling
2414 * happens much less frequently.
2416 * Equal stride packed stream mode is documented in SF-119419-TC.
2417 * The general idea is to utilize advantages of the packed stream,
2418 * but avoid indirection in packets representation.
2419 * The main advantage of such an approach is that RX queue refilling
2420 * happens much less frequently and packets buffers are independent
2421 * from upper layers point of view.
2424 typedef __checkReturn boolean_t
2427 __in uint32_t label,
2429 __in uint32_t pkt_count,
2430 __in uint16_t flags);
2434 typedef __checkReturn boolean_t
2437 __in uint32_t label,
2440 typedef __checkReturn boolean_t
2441 (*efx_tx_ndescs_ev_t)(
2443 __in uint32_t label,
2444 __in unsigned int ndescs);
2446 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2447 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2448 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2449 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2450 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2451 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2452 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2453 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2454 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2456 typedef __checkReturn boolean_t
2457 (*efx_exception_ev_t)(
2459 __in uint32_t label,
2460 __in uint32_t data);
2462 typedef __checkReturn boolean_t
2463 (*efx_rxq_flush_done_ev_t)(
2465 __in uint32_t rxq_index);
2467 typedef __checkReturn boolean_t
2468 (*efx_rxq_flush_failed_ev_t)(
2470 __in uint32_t rxq_index);
2472 typedef __checkReturn boolean_t
2473 (*efx_txq_flush_done_ev_t)(
2475 __in uint32_t txq_index);
2477 typedef __checkReturn boolean_t
2478 (*efx_software_ev_t)(
2480 __in uint16_t magic);
2482 typedef __checkReturn boolean_t
2485 __in uint32_t code);
2487 #define EFX_SRAM_CLEAR 0
2488 #define EFX_SRAM_UPDATE 1
2489 #define EFX_SRAM_ILLEGAL_CLEAR 2
2491 typedef __checkReturn boolean_t
2492 (*efx_wake_up_ev_t)(
2494 __in uint32_t label);
2496 typedef __checkReturn boolean_t
2499 __in uint32_t label);
2501 typedef __checkReturn boolean_t
2502 (*efx_link_change_ev_t)(
2504 __in efx_link_mode_t link_mode);
2506 #if EFSYS_OPT_MON_STATS
2508 typedef __checkReturn boolean_t
2509 (*efx_monitor_ev_t)(
2511 __in efx_mon_stat_t id,
2512 __in efx_mon_stat_value_t value);
2514 #endif /* EFSYS_OPT_MON_STATS */
2516 #if EFSYS_OPT_MAC_STATS
2518 typedef __checkReturn boolean_t
2519 (*efx_mac_stats_ev_t)(
2521 __in uint32_t generation);
2523 #endif /* EFSYS_OPT_MAC_STATS */
2525 #if EFSYS_OPT_DESC_PROXY
2528 * NOTE: This callback returns the raw descriptor data, which has not been
2529 * converted to host endian. The callback must use the EFX_OWORD macros
2530 * to extract the descriptor fields as host endian values.
2532 typedef __checkReturn boolean_t
2533 (*efx_desc_proxy_txq_desc_ev_t)(
2535 __in uint16_t vi_id,
2536 __in efx_oword_t txq_desc);
2539 * NOTE: This callback returns the raw descriptor data, which has not been
2540 * converted to host endian. The callback must use the EFX_OWORD macros
2541 * to extract the descriptor fields as host endian values.
2543 typedef __checkReturn boolean_t
2544 (*efx_desc_proxy_virtq_desc_ev_t)(
2546 __in uint16_t vi_id,
2547 __in uint16_t avail,
2548 __in efx_oword_t virtq_desc);
2550 #endif /* EFSYS_OPT_DESC_PROXY */
2552 typedef struct efx_ev_callbacks_s {
2553 efx_initialized_ev_t eec_initialized;
2555 efx_rx_packets_ev_t eec_rx_packets;
2556 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2557 efx_rx_ps_ev_t eec_rx_ps;
2560 efx_tx_ndescs_ev_t eec_tx_ndescs;
2561 efx_exception_ev_t eec_exception;
2562 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2563 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2564 efx_txq_flush_done_ev_t eec_txq_flush_done;
2565 efx_software_ev_t eec_software;
2566 efx_sram_ev_t eec_sram;
2567 efx_wake_up_ev_t eec_wake_up;
2568 efx_timer_ev_t eec_timer;
2569 efx_link_change_ev_t eec_link_change;
2570 #if EFSYS_OPT_MON_STATS
2571 efx_monitor_ev_t eec_monitor;
2572 #endif /* EFSYS_OPT_MON_STATS */
2573 #if EFSYS_OPT_MAC_STATS
2574 efx_mac_stats_ev_t eec_mac_stats;
2575 #endif /* EFSYS_OPT_MAC_STATS */
2576 #if EFSYS_OPT_DESC_PROXY
2577 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc;
2578 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc;
2579 #endif /* EFSYS_OPT_DESC_PROXY */
2581 } efx_ev_callbacks_t;
2584 extern __checkReturn boolean_t
2586 __in efx_evq_t *eep,
2587 __in unsigned int count);
2589 #if EFSYS_OPT_EV_PREFETCH
2594 __in efx_evq_t *eep,
2595 __in unsigned int count);
2597 #endif /* EFSYS_OPT_EV_PREFETCH */
2601 efx_ev_qcreate_check_init_done(
2602 __in efx_evq_t *eep,
2603 __in const efx_ev_callbacks_t *eecp,
2604 __in_opt void *arg);
2609 __in efx_evq_t *eep,
2610 __inout unsigned int *countp,
2611 __in const efx_ev_callbacks_t *eecp,
2612 __in_opt void *arg);
2615 extern __checkReturn efx_rc_t
2616 efx_ev_usecs_to_ticks(
2617 __in efx_nic_t *enp,
2618 __in unsigned int usecs,
2619 __out unsigned int *ticksp);
2622 extern __checkReturn efx_rc_t
2624 __in efx_evq_t *eep,
2625 __in unsigned int us);
2628 extern __checkReturn efx_rc_t
2630 __in efx_evq_t *eep,
2631 __in unsigned int count);
2633 #if EFSYS_OPT_QSTATS
2640 __in efx_nic_t *enp,
2641 __in unsigned int id);
2643 #endif /* EFSYS_OPT_NAMES */
2647 efx_ev_qstats_update(
2648 __in efx_evq_t *eep,
2649 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2651 #endif /* EFSYS_OPT_QSTATS */
2656 __in efx_evq_t *eep);
2661 extern __checkReturn efx_rc_t
2663 __inout efx_nic_t *enp);
2668 __in efx_nic_t *enp);
2670 #if EFSYS_OPT_RX_SCATTER
2672 extern __checkReturn efx_rc_t
2673 efx_rx_scatter_enable(
2674 __in efx_nic_t *enp,
2675 __in unsigned int buf_size);
2676 #endif /* EFSYS_OPT_RX_SCATTER */
2678 /* Handle to represent use of the default RSS context. */
2679 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2681 #if EFSYS_OPT_RX_SCALE
2683 typedef enum efx_rx_hash_alg_e {
2684 EFX_RX_HASHALG_LFSR = 0,
2685 EFX_RX_HASHALG_TOEPLITZ,
2686 EFX_RX_HASHALG_PACKED_STREAM,
2688 } efx_rx_hash_alg_t;
2691 * Legacy hash type flags.
2693 * They represent standard tuples for distinct traffic classes.
2695 #define EFX_RX_HASH_IPV4 (1U << 0)
2696 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2697 #define EFX_RX_HASH_IPV6 (1U << 2)
2698 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2700 #define EFX_RX_HASH_LEGACY_MASK \
2701 (EFX_RX_HASH_IPV4 | \
2702 EFX_RX_HASH_TCPIPV4 | \
2703 EFX_RX_HASH_IPV6 | \
2704 EFX_RX_HASH_TCPIPV6)
2707 * The type of the argument used by efx_rx_scale_mode_set() to
2708 * provide a means for the client drivers to configure hashing.
2710 * A properly constructed value can either be:
2711 * - a combination of legacy flags
2712 * - a combination of EFX_RX_HASH() flags
2714 typedef uint32_t efx_rx_hash_type_t;
2716 typedef enum efx_rx_hash_support_e {
2717 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2718 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2719 } efx_rx_hash_support_t;
2721 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2722 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2723 #define EFX_MAXRSS 64 /* RX indirection entry range */
2724 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2726 typedef enum efx_rx_scale_context_type_e {
2727 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2728 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2729 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2730 } efx_rx_scale_context_type_t;
2733 * Traffic classes eligible for hash computation.
2735 * Select packet headers used in computing the receive hash.
2736 * This uses the same encoding as the RSS_MODES field of
2737 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2739 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2740 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2741 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2742 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2743 #define EFX_RX_CLASS_IPV4_LBN 16
2744 #define EFX_RX_CLASS_IPV4_WIDTH 4
2745 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2746 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2747 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2748 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2749 #define EFX_RX_CLASS_IPV6_LBN 28
2750 #define EFX_RX_CLASS_IPV6_WIDTH 4
2752 #define EFX_RX_NCLASSES 6
2755 * Ancillary flags used to construct generic hash tuples.
2756 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2758 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2759 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2760 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2761 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2764 * Generic hash tuples.
2766 * They express combinations of packet fields
2767 * which can contribute to the hash value for
2768 * a particular traffic class.
2770 #define EFX_RX_CLASS_HASH_DISABLE 0
2772 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2773 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2775 #define EFX_RX_CLASS_HASH_2TUPLE \
2776 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2777 EFX_RX_CLASS_HASH_DST_ADDR)
2779 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2780 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2781 EFX_RX_CLASS_HASH_SRC_PORT)
2783 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2784 (EFX_RX_CLASS_HASH_DST_ADDR | \
2785 EFX_RX_CLASS_HASH_DST_PORT)
2787 #define EFX_RX_CLASS_HASH_4TUPLE \
2788 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2789 EFX_RX_CLASS_HASH_DST_ADDR | \
2790 EFX_RX_CLASS_HASH_SRC_PORT | \
2791 EFX_RX_CLASS_HASH_DST_PORT)
2793 #define EFX_RX_CLASS_HASH_NTUPLES 7
2796 * Hash flag constructor.
2798 * Resulting flags encode hash tuples for specific traffic classes.
2799 * The client drivers are encouraged to use these flags to form
2800 * a hash type value.
2802 #define EFX_RX_HASH(_class, _tuple) \
2803 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2804 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2807 * The maximum number of EFX_RX_HASH() flags.
2809 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2812 extern __checkReturn efx_rc_t
2813 efx_rx_scale_hash_flags_get(
2814 __in efx_nic_t *enp,
2815 __in efx_rx_hash_alg_t hash_alg,
2816 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2817 __in unsigned int max_nflags,
2818 __out unsigned int *nflagsp);
2821 extern __checkReturn efx_rc_t
2822 efx_rx_hash_default_support_get(
2823 __in efx_nic_t *enp,
2824 __out efx_rx_hash_support_t *supportp);
2828 extern __checkReturn efx_rc_t
2829 efx_rx_scale_default_support_get(
2830 __in efx_nic_t *enp,
2831 __out efx_rx_scale_context_type_t *typep);
2834 extern __checkReturn efx_rc_t
2835 efx_rx_scale_context_alloc(
2836 __in efx_nic_t *enp,
2837 __in efx_rx_scale_context_type_t type,
2838 __in uint32_t num_queues,
2839 __out uint32_t *rss_contextp);
2842 extern __checkReturn efx_rc_t
2843 efx_rx_scale_context_free(
2844 __in efx_nic_t *enp,
2845 __in uint32_t rss_context);
2848 extern __checkReturn efx_rc_t
2849 efx_rx_scale_mode_set(
2850 __in efx_nic_t *enp,
2851 __in uint32_t rss_context,
2852 __in efx_rx_hash_alg_t alg,
2853 __in efx_rx_hash_type_t type,
2854 __in boolean_t insert);
2857 extern __checkReturn efx_rc_t
2858 efx_rx_scale_tbl_set(
2859 __in efx_nic_t *enp,
2860 __in uint32_t rss_context,
2861 __in_ecount(n) unsigned int *table,
2865 extern __checkReturn efx_rc_t
2866 efx_rx_scale_key_set(
2867 __in efx_nic_t *enp,
2868 __in uint32_t rss_context,
2869 __in_ecount(n) uint8_t *key,
2873 extern __checkReturn uint32_t
2874 efx_pseudo_hdr_hash_get(
2875 __in efx_rxq_t *erp,
2876 __in efx_rx_hash_alg_t func,
2877 __in uint8_t *buffer);
2879 #endif /* EFSYS_OPT_RX_SCALE */
2882 extern __checkReturn efx_rc_t
2883 efx_pseudo_hdr_pkt_length_get(
2884 __in efx_rxq_t *erp,
2885 __in uint8_t *buffer,
2886 __out uint16_t *pkt_lengthp);
2889 extern __checkReturn size_t
2891 __in const efx_nic_t *enp,
2892 __in unsigned int ndescs);
2895 extern __checkReturn unsigned int
2897 __in const efx_nic_t *enp,
2898 __in unsigned int ndescs);
2900 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2903 * libefx representation of the Rx prefix layout information.
2905 * The information may be used inside libefx to implement Rx prefix fields
2906 * accessors and by drivers which process Rx prefix itself.
2910 * All known Rx prefix fields.
2912 * An Rx prefix may have a subset of these fields.
2914 typedef enum efx_rx_prefix_field_e {
2915 EFX_RX_PREFIX_FIELD_LENGTH = 0,
2916 EFX_RX_PREFIX_FIELD_ORIG_LENGTH,
2917 EFX_RX_PREFIX_FIELD_CLASS,
2918 EFX_RX_PREFIX_FIELD_RSS_HASH,
2919 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID,
2920 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP,
2921 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI,
2922 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI,
2923 EFX_RX_PREFIX_FIELD_USER_FLAG,
2924 EFX_RX_PREFIX_FIELD_USER_MARK,
2925 EFX_RX_PREFIX_FIELD_USER_MARK_VALID,
2926 EFX_RX_PREFIX_FIELD_CSUM_FRAME,
2927 EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2928 EFX_RX_PREFIX_FIELD_INGRESS_MPORT = EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2929 EFX_RX_PREFIX_NFIELDS
2930 } efx_rx_prefix_field_t;
2933 * Location and endianness of a field in Rx prefix.
2935 * If width is zero, the field is not present.
2937 typedef struct efx_rx_prefix_field_info_s {
2938 uint16_t erpfi_offset_bits;
2939 uint8_t erpfi_width_bits;
2940 boolean_t erpfi_big_endian;
2941 } efx_rx_prefix_field_info_t;
2943 /* Helper macro to define Rx prefix fields */
2944 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \
2945 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \
2946 .erpfi_offset_bits = EFX_LOW_BIT(_field), \
2947 .erpfi_width_bits = EFX_WIDTH(_field), \
2948 .erpfi_big_endian = (_big_endian), \
2951 typedef struct efx_rx_prefix_layout_s {
2953 uint8_t erpl_length;
2954 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS];
2955 } efx_rx_prefix_layout_t;
2958 * Helper function to find out a bit mask of wanted but not available
2961 * A field is considered as not available if any parameter mismatch.
2964 extern __checkReturn uint32_t
2965 efx_rx_prefix_layout_check(
2966 __in const efx_rx_prefix_layout_t *available,
2967 __in const efx_rx_prefix_layout_t *wanted);
2970 extern __checkReturn efx_rc_t
2971 efx_rx_prefix_get_layout(
2972 __in const efx_rxq_t *erp,
2973 __out efx_rx_prefix_layout_t *erplp);
2975 typedef enum efx_rxq_type_e {
2976 EFX_RXQ_TYPE_DEFAULT,
2977 EFX_RXQ_TYPE_PACKED_STREAM,
2978 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2983 * Dummy flag to be used instead of 0 to make it clear that the argument
2984 * is receive queue flags.
2986 #define EFX_RXQ_FLAG_NONE 0x0
2987 #define EFX_RXQ_FLAG_SCATTER 0x1
2989 * If tunnels are supported and Rx event can provide information about
2990 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2991 * full-feature firmware variant running), outer classes are requested by
2992 * default. However, if the driver supports tunnels, the flag allows to
2993 * request inner classes which are required to be able to interpret inner
2994 * Rx checksum offload results.
2996 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2998 * Request delivery of the RSS hash calculated by HW to be used by
3001 #define EFX_RXQ_FLAG_RSS_HASH 0x4
3003 * Request ingress mport field in the Rx prefix of a queue.
3005 #define EFX_RXQ_FLAG_INGRESS_MPORT 0x8
3007 * Request user mark field in the Rx prefix of a queue.
3009 #define EFX_RXQ_FLAG_USER_MARK 0x10
3012 extern __checkReturn efx_rc_t
3014 __in efx_nic_t *enp,
3015 __in unsigned int index,
3016 __in unsigned int label,
3017 __in efx_rxq_type_t type,
3018 __in size_t buf_size,
3019 __in efsys_mem_t *esmp,
3022 __in unsigned int flags,
3023 __in efx_evq_t *eep,
3024 __deref_out efx_rxq_t **erpp);
3026 #if EFSYS_OPT_RX_PACKED_STREAM
3028 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
3029 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
3030 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
3031 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
3032 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
3035 extern __checkReturn efx_rc_t
3036 efx_rx_qcreate_packed_stream(
3037 __in efx_nic_t *enp,
3038 __in unsigned int index,
3039 __in unsigned int label,
3040 __in uint32_t ps_buf_size,
3041 __in efsys_mem_t *esmp,
3043 __in efx_evq_t *eep,
3044 __deref_out efx_rxq_t **erpp);
3048 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
3050 /* Maximum head-of-line block timeout in nanoseconds */
3051 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
3054 extern __checkReturn efx_rc_t
3055 efx_rx_qcreate_es_super_buffer(
3056 __in efx_nic_t *enp,
3057 __in unsigned int index,
3058 __in unsigned int label,
3059 __in uint32_t n_bufs_per_desc,
3060 __in uint32_t max_dma_len,
3061 __in uint32_t buf_stride,
3062 __in uint32_t hol_block_timeout,
3063 __in efsys_mem_t *esmp,
3065 __in unsigned int flags,
3066 __in efx_evq_t *eep,
3067 __deref_out efx_rxq_t **erpp);
3071 typedef struct efx_buffer_s {
3072 efsys_dma_addr_t eb_addr;
3077 typedef struct efx_desc_s {
3084 __in efx_rxq_t *erp,
3085 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
3087 __in unsigned int ndescs,
3088 __in unsigned int completed,
3089 __in unsigned int added);
3094 __in efx_rxq_t *erp,
3095 __in unsigned int added,
3096 __inout unsigned int *pushedp);
3098 #if EFSYS_OPT_RX_PACKED_STREAM
3102 efx_rx_qpush_ps_credits(
3103 __in efx_rxq_t *erp);
3106 extern __checkReturn uint8_t *
3107 efx_rx_qps_packet_info(
3108 __in efx_rxq_t *erp,
3109 __in uint8_t *buffer,
3110 __in uint32_t buffer_length,
3111 __in uint32_t current_offset,
3112 __out uint16_t *lengthp,
3113 __out uint32_t *next_offsetp,
3114 __out uint32_t *timestamp);
3118 extern __checkReturn efx_rc_t
3120 __in efx_rxq_t *erp);
3125 __in efx_rxq_t *erp);
3130 __in efx_rxq_t *erp);
3134 typedef struct efx_txq_s efx_txq_t;
3136 #if EFSYS_OPT_QSTATS
3138 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
3139 typedef enum efx_tx_qstat_e {
3145 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
3147 #endif /* EFSYS_OPT_QSTATS */
3150 extern __checkReturn efx_rc_t
3152 __in efx_nic_t *enp);
3157 __in efx_nic_t *enp);
3160 extern __checkReturn size_t
3162 __in const efx_nic_t *enp,
3163 __in unsigned int ndescs);
3166 extern __checkReturn unsigned int
3168 __in const efx_nic_t *enp,
3169 __in unsigned int ndescs);
3171 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
3173 #define EFX_TXQ_CKSUM_IPV4 0x0001
3174 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
3175 #define EFX_TXQ_FATSOV2 0x0004
3176 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
3177 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
3180 extern __checkReturn efx_rc_t
3182 __in efx_nic_t *enp,
3183 __in unsigned int index,
3184 __in unsigned int label,
3185 __in efsys_mem_t *esmp,
3188 __in uint16_t flags,
3189 __in efx_evq_t *eep,
3190 __deref_out efx_txq_t **etpp,
3191 __out unsigned int *addedp);
3194 extern __checkReturn efx_rc_t
3196 __in efx_txq_t *etp,
3197 __in_ecount(ndescs) efx_buffer_t *eb,
3198 __in unsigned int ndescs,
3199 __in unsigned int completed,
3200 __inout unsigned int *addedp);
3203 extern __checkReturn efx_rc_t
3205 __in efx_txq_t *etp,
3206 __in unsigned int ns);
3211 __in efx_txq_t *etp,
3212 __in unsigned int added,
3213 __in unsigned int pushed);
3216 extern __checkReturn efx_rc_t
3218 __in efx_txq_t *etp);
3223 __in efx_txq_t *etp);
3226 extern __checkReturn efx_rc_t
3228 __in efx_txq_t *etp);
3232 efx_tx_qpio_disable(
3233 __in efx_txq_t *etp);
3236 extern __checkReturn efx_rc_t
3238 __in efx_txq_t *etp,
3239 __in_ecount(buf_length) uint8_t *buffer,
3240 __in size_t buf_length,
3241 __in size_t pio_buf_offset);
3244 extern __checkReturn efx_rc_t
3246 __in efx_txq_t *etp,
3247 __in size_t pkt_length,
3248 __in unsigned int completed,
3249 __inout unsigned int *addedp);
3252 extern __checkReturn efx_rc_t
3254 __in efx_txq_t *etp,
3255 __in_ecount(n) efx_desc_t *ed,
3256 __in unsigned int n,
3257 __in unsigned int completed,
3258 __inout unsigned int *addedp);
3262 efx_tx_qdesc_dma_create(
3263 __in efx_txq_t *etp,
3264 __in efsys_dma_addr_t addr,
3267 __out efx_desc_t *edp);
3271 efx_tx_qdesc_tso_create(
3272 __in efx_txq_t *etp,
3273 __in uint16_t ipv4_id,
3274 __in uint32_t tcp_seq,
3275 __in uint8_t tcp_flags,
3276 __out efx_desc_t *edp);
3278 /* Number of FATSOv2 option descriptors */
3279 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3281 /* Maximum number of DMA segments per TSO packet (not superframe) */
3282 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3286 efx_tx_qdesc_tso2_create(
3287 __in efx_txq_t *etp,
3288 __in uint16_t ipv4_id,
3289 __in uint16_t outer_ipv4_id,
3290 __in uint32_t tcp_seq,
3291 __in uint16_t tcp_mss,
3292 __out_ecount(count) efx_desc_t *edp,
3297 efx_tx_qdesc_vlantci_create(
3298 __in efx_txq_t *etp,
3300 __out efx_desc_t *edp);
3304 efx_tx_qdesc_checksum_create(
3305 __in efx_txq_t *etp,
3306 __in uint16_t flags,
3307 __out efx_desc_t *edp);
3309 #if EFSYS_OPT_QSTATS
3316 __in efx_nic_t *etp,
3317 __in unsigned int id);
3319 #endif /* EFSYS_OPT_NAMES */
3323 efx_tx_qstats_update(
3324 __in efx_txq_t *etp,
3325 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3327 #endif /* EFSYS_OPT_QSTATS */
3332 __in efx_txq_t *etp);
3337 #if EFSYS_OPT_FILTER
3339 #define EFX_ETHER_TYPE_IPV4 0x0800
3340 #define EFX_ETHER_TYPE_IPV6 0x86DD
3342 #define EFX_IPPROTO_TCP 6
3343 #define EFX_IPPROTO_UDP 17
3344 #define EFX_IPPROTO_GRE 47
3346 /* Use RSS to spread across multiple queues */
3347 #define EFX_FILTER_FLAG_RX_RSS 0x01
3348 /* Enable RX scatter */
3349 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3351 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3352 * May only be set by the filter implementation for each type.
3353 * A removal request will restore the automatic filter in its place.
3355 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3356 /* Filter is for RX */
3357 #define EFX_FILTER_FLAG_RX 0x08
3358 /* Filter is for TX */
3359 #define EFX_FILTER_FLAG_TX 0x10
3360 /* Set match flag on the received packet */
3361 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3362 /* Set match mark on the received packet */
3363 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3365 typedef uint8_t efx_filter_flags_t;
3368 * Flags which specify the fields to match on. The values are the same as in the
3369 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3372 /* Match by remote IP host address */
3373 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3374 /* Match by local IP host address */
3375 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3376 /* Match by remote MAC address */
3377 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3378 /* Match by remote TCP/UDP port */
3379 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3380 /* Match by remote TCP/UDP port */
3381 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3382 /* Match by local TCP/UDP port */
3383 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3384 /* Match by Ether-type */
3385 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3386 /* Match by inner VLAN ID */
3387 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3388 /* Match by outer VLAN ID */
3389 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3390 /* Match by IP transport protocol */
3391 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3392 /* Match by VNI or VSID */
3393 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3394 /* For encapsulated packets, match by inner frame local MAC address */
3395 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3396 /* For encapsulated packets, match all multicast inner frames */
3397 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3398 /* For encapsulated packets, match all unicast inner frames */
3399 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3401 * Match by encap type, this flag does not correspond to
3402 * the MCDI match flags and any unoccupied value may be used
3404 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3405 /* Match otherwise-unmatched multicast and broadcast packets */
3406 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3407 /* Match otherwise-unmatched unicast packets */
3408 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3410 typedef uint32_t efx_filter_match_flags_t;
3412 /* Filter priority from lowest to highest */
3413 typedef enum efx_filter_priority_s {
3414 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3415 * address list or hardware
3416 * requirements. This may only be used
3417 * by the filter implementation for
3419 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3421 } efx_filter_priority_t;
3424 * FIXME: All these fields are assumed to be in little-endian byte order.
3425 * It may be better for some to be big-endian. See bug42804.
3428 typedef struct efx_filter_spec_s {
3429 efx_filter_match_flags_t efs_match_flags;
3430 uint8_t efs_priority;
3431 efx_filter_flags_t efs_flags;
3432 uint16_t efs_dmaq_id;
3433 uint32_t efs_rss_context;
3436 * Saved lower-priority filter. If it is set, it is restored on
3437 * filter delete operation.
3439 struct efx_filter_spec_s *efs_overridden_spec;
3440 /* Fields below here are hashed for software filter lookup */
3441 uint16_t efs_outer_vid;
3442 uint16_t efs_inner_vid;
3443 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3444 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3445 uint16_t efs_ether_type;
3446 uint8_t efs_ip_proto;
3447 efx_tunnel_protocol_t efs_encap_type;
3448 uint16_t efs_loc_port;
3449 uint16_t efs_rem_port;
3450 efx_oword_t efs_rem_host;
3451 efx_oword_t efs_loc_host;
3452 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3453 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3454 } efx_filter_spec_t;
3457 /* Default values for use in filter specifications */
3458 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3459 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3462 extern __checkReturn efx_rc_t
3464 __in efx_nic_t *enp);
3469 __in efx_nic_t *enp);
3472 extern __checkReturn efx_rc_t
3474 __in efx_nic_t *enp,
3475 __inout efx_filter_spec_t *spec);
3478 extern __checkReturn efx_rc_t
3480 __in efx_nic_t *enp,
3481 __inout efx_filter_spec_t *spec);
3484 extern __checkReturn efx_rc_t
3486 __in efx_nic_t *enp);
3489 extern __checkReturn efx_rc_t
3490 efx_filter_supported_filters(
3491 __in efx_nic_t *enp,
3492 __out_ecount(buffer_length) uint32_t *buffer,
3493 __in size_t buffer_length,
3494 __out size_t *list_lengthp);
3498 efx_filter_spec_init_rx(
3499 __out efx_filter_spec_t *spec,
3500 __in efx_filter_priority_t priority,
3501 __in efx_filter_flags_t flags,
3502 __in efx_rxq_t *erp);
3506 efx_filter_spec_init_tx(
3507 __out efx_filter_spec_t *spec,
3508 __in efx_txq_t *etp);
3511 extern __checkReturn efx_rc_t
3512 efx_filter_spec_set_ipv4_local(
3513 __inout efx_filter_spec_t *spec,
3516 __in uint16_t port);
3519 extern __checkReturn efx_rc_t
3520 efx_filter_spec_set_ipv4_full(
3521 __inout efx_filter_spec_t *spec,
3523 __in uint32_t lhost,
3524 __in uint16_t lport,
3525 __in uint32_t rhost,
3526 __in uint16_t rport);
3529 extern __checkReturn efx_rc_t
3530 efx_filter_spec_set_eth_local(
3531 __inout efx_filter_spec_t *spec,
3533 __in const uint8_t *addr);
3537 efx_filter_spec_set_ether_type(
3538 __inout efx_filter_spec_t *spec,
3539 __in uint16_t ether_type);
3542 extern __checkReturn efx_rc_t
3543 efx_filter_spec_set_uc_def(
3544 __inout efx_filter_spec_t *spec);
3547 extern __checkReturn efx_rc_t
3548 efx_filter_spec_set_mc_def(
3549 __inout efx_filter_spec_t *spec);
3551 typedef enum efx_filter_inner_frame_match_e {
3552 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3553 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3554 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3555 } efx_filter_inner_frame_match_t;
3558 extern __checkReturn efx_rc_t
3559 efx_filter_spec_set_encap_type(
3560 __inout efx_filter_spec_t *spec,
3561 __in efx_tunnel_protocol_t encap_type,
3562 __in efx_filter_inner_frame_match_t inner_frame_match);
3565 extern __checkReturn efx_rc_t
3566 efx_filter_spec_set_vxlan(
3567 __inout efx_filter_spec_t *spec,
3568 __in const uint8_t *vni,
3569 __in const uint8_t *inner_addr,
3570 __in const uint8_t *outer_addr);
3573 extern __checkReturn efx_rc_t
3574 efx_filter_spec_set_geneve(
3575 __inout efx_filter_spec_t *spec,
3576 __in const uint8_t *vni,
3577 __in const uint8_t *inner_addr,
3578 __in const uint8_t *outer_addr);
3581 extern __checkReturn efx_rc_t
3582 efx_filter_spec_set_nvgre(
3583 __inout efx_filter_spec_t *spec,
3584 __in const uint8_t *vsid,
3585 __in const uint8_t *inner_addr,
3586 __in const uint8_t *outer_addr);
3588 #if EFSYS_OPT_RX_SCALE
3590 extern __checkReturn efx_rc_t
3591 efx_filter_spec_set_rss_context(
3592 __inout efx_filter_spec_t *spec,
3593 __in uint32_t rss_context);
3595 #endif /* EFSYS_OPT_FILTER */
3600 extern __checkReturn uint32_t
3602 __in_ecount(count) uint32_t const *input,
3604 __in uint32_t init);
3607 extern __checkReturn uint32_t
3609 __in_ecount(length) uint8_t const *input,
3611 __in uint32_t init);
3613 #if EFSYS_OPT_LICENSING
3617 typedef struct efx_key_stats_s {
3619 uint32_t eks_invalid;
3620 uint32_t eks_blacklisted;
3621 uint32_t eks_unverifiable;
3622 uint32_t eks_wrong_node;
3623 uint32_t eks_licensed_apps_lo;
3624 uint32_t eks_licensed_apps_hi;
3625 uint32_t eks_licensed_features_lo;
3626 uint32_t eks_licensed_features_hi;
3630 extern __checkReturn efx_rc_t
3632 __in efx_nic_t *enp);
3637 __in efx_nic_t *enp);
3640 extern __checkReturn boolean_t
3641 efx_lic_check_support(
3642 __in efx_nic_t *enp);
3645 extern __checkReturn efx_rc_t
3646 efx_lic_update_licenses(
3647 __in efx_nic_t *enp);
3650 extern __checkReturn efx_rc_t
3651 efx_lic_get_key_stats(
3652 __in efx_nic_t *enp,
3653 __out efx_key_stats_t *ksp);
3656 extern __checkReturn efx_rc_t
3658 __in efx_nic_t *enp,
3659 __in uint64_t app_id,
3660 __out boolean_t *licensedp);
3663 extern __checkReturn efx_rc_t
3665 __in efx_nic_t *enp,
3666 __in size_t buffer_size,
3667 __out uint32_t *typep,
3668 __out size_t *lengthp,
3669 __out_opt uint8_t *bufferp);
3673 extern __checkReturn efx_rc_t
3675 __in efx_nic_t *enp,
3676 __in_bcount(buffer_size)
3678 __in size_t buffer_size,
3679 __out uint32_t *startp);
3682 extern __checkReturn efx_rc_t
3684 __in efx_nic_t *enp,
3685 __in_bcount(buffer_size)
3687 __in size_t buffer_size,
3688 __in uint32_t offset,
3689 __out uint32_t *endp);
3692 extern __checkReturn __success(return != B_FALSE) boolean_t
3694 __in efx_nic_t *enp,
3695 __in_bcount(buffer_size)
3697 __in size_t buffer_size,
3698 __in uint32_t offset,
3699 __out uint32_t *startp,
3700 __out uint32_t *lengthp);
3703 extern __checkReturn __success(return != B_FALSE) boolean_t
3704 efx_lic_validate_key(
3705 __in efx_nic_t *enp,
3706 __in_bcount(length) caddr_t keyp,
3707 __in uint32_t length);
3710 extern __checkReturn efx_rc_t
3712 __in efx_nic_t *enp,
3713 __in_bcount(buffer_size)
3715 __in size_t buffer_size,
3716 __in uint32_t offset,
3717 __in uint32_t length,
3718 __out_bcount_part(key_max_size, *lengthp)
3720 __in size_t key_max_size,
3721 __out uint32_t *lengthp);
3724 extern __checkReturn efx_rc_t
3726 __in efx_nic_t *enp,
3727 __in_bcount(buffer_size)
3729 __in size_t buffer_size,
3730 __in uint32_t offset,
3731 __in_bcount(length) caddr_t keyp,
3732 __in uint32_t length,
3733 __out uint32_t *lengthp);
3736 extern __checkReturn efx_rc_t
3738 __in efx_nic_t *enp,
3739 __in_bcount(buffer_size)
3741 __in size_t buffer_size,
3742 __in uint32_t offset,
3743 __in uint32_t length,
3745 __out uint32_t *deltap);
3748 extern __checkReturn efx_rc_t
3749 efx_lic_create_partition(
3750 __in efx_nic_t *enp,
3751 __in_bcount(buffer_size)
3753 __in size_t buffer_size);
3755 extern __checkReturn efx_rc_t
3756 efx_lic_finish_partition(
3757 __in efx_nic_t *enp,
3758 __in_bcount(buffer_size)
3760 __in size_t buffer_size);
3762 #endif /* EFSYS_OPT_LICENSING */
3766 #if EFSYS_OPT_TUNNEL
3769 extern __checkReturn efx_rc_t
3771 __in efx_nic_t *enp);
3776 __in efx_nic_t *enp);
3779 * For overlay network encapsulation using UDP, the firmware needs to know
3780 * the configured UDP port for the overlay so it can decode encapsulated
3782 * The UDP port/protocol list is global.
3786 extern __checkReturn efx_rc_t
3787 efx_tunnel_config_udp_add(
3788 __in efx_nic_t *enp,
3789 __in uint16_t port /* host/cpu-endian */,
3790 __in efx_tunnel_protocol_t protocol);
3793 * Returns EBUSY if reconfiguration of the port is in progress in other thread.
3796 extern __checkReturn efx_rc_t
3797 efx_tunnel_config_udp_remove(
3798 __in efx_nic_t *enp,
3799 __in uint16_t port /* host/cpu-endian */,
3800 __in efx_tunnel_protocol_t protocol);
3803 * Returns EBUSY if reconfiguration of any of the tunnel entries
3804 * is in progress in other thread.
3807 extern __checkReturn efx_rc_t
3808 efx_tunnel_config_clear(
3809 __in efx_nic_t *enp);
3812 * Apply tunnel UDP ports configuration to hardware.
3814 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3818 extern __checkReturn efx_rc_t
3819 efx_tunnel_reconfigure(
3820 __in efx_nic_t *enp);
3822 #endif /* EFSYS_OPT_TUNNEL */
3824 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3827 * Firmware subvariant choice options.
3829 * It may be switched to no Tx checksum if attached drivers are either
3830 * preboot or firmware subvariant aware and no VIS are allocated.
3831 * If may be always switched to default explicitly using set request or
3832 * implicitly if unaware driver is attaching. If switching is done when
3833 * a driver is attached, it gets MC_REBOOT event and should recreate its
3836 * See SF-119419-TC DPDK Firmware Driver Interface and
3837 * SF-109306-TC EF10 for Driver Writers for details.
3839 typedef enum efx_nic_fw_subvariant_e {
3840 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3841 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3842 EFX_NIC_FW_SUBVARIANT_NTYPES
3843 } efx_nic_fw_subvariant_t;
3846 extern __checkReturn efx_rc_t
3847 efx_nic_get_fw_subvariant(
3848 __in efx_nic_t *enp,
3849 __out efx_nic_fw_subvariant_t *subvariantp);
3852 extern __checkReturn efx_rc_t
3853 efx_nic_set_fw_subvariant(
3854 __in efx_nic_t *enp,
3855 __in efx_nic_fw_subvariant_t subvariant);
3857 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3859 typedef enum efx_phy_fec_type_e {
3860 EFX_PHY_FEC_NONE = 0,
3863 } efx_phy_fec_type_t;
3866 extern __checkReturn efx_rc_t
3867 efx_phy_fec_type_get(
3868 __in efx_nic_t *enp,
3869 __out efx_phy_fec_type_t *typep);
3871 typedef struct efx_phy_link_state_s {
3872 uint32_t epls_adv_cap_mask;
3873 uint32_t epls_lp_cap_mask;
3874 uint32_t epls_ld_cap_mask;
3875 unsigned int epls_fcntl;
3876 efx_phy_fec_type_t epls_fec;
3877 efx_link_mode_t epls_link_mode;
3878 } efx_phy_link_state_t;
3881 extern __checkReturn efx_rc_t
3882 efx_phy_link_state_get(
3883 __in efx_nic_t *enp,
3884 __out efx_phy_link_state_t *eplsp);
3889 typedef uint32_t efx_vswitch_id_t;
3890 typedef uint32_t efx_vport_id_t;
3892 typedef enum efx_vswitch_type_e {
3893 EFX_VSWITCH_TYPE_VLAN = 1,
3894 EFX_VSWITCH_TYPE_VEB,
3895 /* VSWITCH_TYPE_VEPA: obsolete */
3896 EFX_VSWITCH_TYPE_MUX = 4,
3897 } efx_vswitch_type_t;
3899 typedef enum efx_vport_type_e {
3900 EFX_VPORT_TYPE_NORMAL = 4,
3901 EFX_VPORT_TYPE_EXPANSION,
3902 EFX_VPORT_TYPE_TEST,
3905 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3906 #define EFX_FILTER_VID_UNSPEC 0xffff
3907 #define EFX_DEFAULT_VSWITCH_ID 1
3909 /* Default VF VLAN ID on creation */
3910 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3911 #define EFX_VPORT_ID_INVALID 0
3913 typedef struct efx_vport_config_s {
3914 /* Either VF index or EFX_PCI_VF_INVALID for PF */
3915 uint16_t evc_function;
3916 /* VLAN ID of the associated function */
3918 /* vport id shared with client driver */
3919 efx_vport_id_t evc_vport_id;
3920 /* MAC address of the associated function */
3921 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3923 * vports created with this flag set may only transfer traffic on the
3924 * VLANs permitted by the vport. Also, an attempt to install filter with
3925 * VLAN will be refused unless requesting function has VLAN privilege.
3927 boolean_t evc_vlan_restrict;
3928 /* Whether this function is assigned or not */
3929 boolean_t evc_vport_assigned;
3930 } efx_vport_config_t;
3932 typedef struct efx_vswitch_s efx_vswitch_t;
3935 extern __checkReturn efx_rc_t
3937 __in efx_nic_t *enp);
3942 __in efx_nic_t *enp);
3945 extern __checkReturn efx_rc_t
3946 efx_evb_vswitch_create(
3947 __in efx_nic_t *enp,
3948 __in uint32_t num_vports,
3949 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3950 __deref_out efx_vswitch_t **evpp);
3953 extern __checkReturn efx_rc_t
3954 efx_evb_vswitch_destroy(
3955 __in efx_nic_t *enp,
3956 __in efx_vswitch_t *evp);
3959 extern __checkReturn efx_rc_t
3960 efx_evb_vport_mac_set(
3961 __in efx_nic_t *enp,
3962 __in efx_vswitch_t *evp,
3963 __in efx_vport_id_t vport_id,
3964 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3967 extern __checkReturn efx_rc_t
3968 efx_evb_vport_vlan_set(
3969 __in efx_nic_t *enp,
3970 __in efx_vswitch_t *evp,
3971 __in efx_vport_id_t vport_id,
3975 extern __checkReturn efx_rc_t
3976 efx_evb_vport_reset(
3977 __in efx_nic_t *enp,
3978 __in efx_vswitch_t *evp,
3979 __in efx_vport_id_t vport_id,
3980 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3982 __out boolean_t *is_fn_resetp);
3985 extern __checkReturn efx_rc_t
3986 efx_evb_vport_stats(
3987 __in efx_nic_t *enp,
3988 __in efx_vswitch_t *evp,
3989 __in efx_vport_id_t vport_id,
3990 __out efsys_mem_t *stats_bufferp);
3992 #endif /* EFSYS_OPT_EVB */
3994 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3996 typedef struct efx_proxy_auth_config_s {
3997 efsys_mem_t *request_bufferp;
3998 efsys_mem_t *response_bufferp;
3999 efsys_mem_t *status_bufferp;
4003 uint32_t handled_privileges;
4004 } efx_proxy_auth_config_t;
4006 typedef struct efx_proxy_cmd_params_s {
4009 uint8_t *request_bufferp;
4010 size_t request_size;
4011 uint8_t *response_bufferp;
4012 size_t response_size;
4013 size_t *response_size_actualp;
4014 } efx_proxy_cmd_params_t;
4017 extern __checkReturn efx_rc_t
4018 efx_proxy_auth_init(
4019 __in efx_nic_t *enp);
4023 efx_proxy_auth_fini(
4024 __in efx_nic_t *enp);
4027 extern __checkReturn efx_rc_t
4028 efx_proxy_auth_configure(
4029 __in efx_nic_t *enp,
4030 __in efx_proxy_auth_config_t *configp);
4033 extern __checkReturn efx_rc_t
4034 efx_proxy_auth_destroy(
4035 __in efx_nic_t *enp,
4036 __in uint32_t handled_privileges);
4039 extern __checkReturn efx_rc_t
4040 efx_proxy_auth_complete_request(
4041 __in efx_nic_t *enp,
4042 __in uint32_t fn_index,
4043 __in uint32_t proxy_result,
4044 __in uint32_t handle);
4047 extern __checkReturn efx_rc_t
4048 efx_proxy_auth_exec_cmd(
4049 __in efx_nic_t *enp,
4050 __inout efx_proxy_cmd_params_t *paramsp);
4053 extern __checkReturn efx_rc_t
4054 efx_proxy_auth_set_privilege_mask(
4055 __in efx_nic_t *enp,
4056 __in uint32_t vf_index,
4058 __in uint32_t value);
4061 extern __checkReturn efx_rc_t
4062 efx_proxy_auth_privilege_mask_get(
4063 __in efx_nic_t *enp,
4064 __in uint32_t pf_index,
4065 __in uint32_t vf_index,
4066 __out uint32_t *maskp);
4069 extern __checkReturn efx_rc_t
4070 efx_proxy_auth_privilege_modify(
4071 __in efx_nic_t *enp,
4072 __in uint32_t pf_index,
4073 __in uint32_t vf_index,
4074 __in uint32_t add_privileges_mask,
4075 __in uint32_t remove_privileges_mask);
4077 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
4082 extern __checkReturn efx_rc_t
4084 __in efx_nic_t *enp);
4089 __in efx_nic_t *enp);
4091 typedef struct efx_mae_limits_s {
4092 uint32_t eml_max_n_action_prios;
4093 uint32_t eml_max_n_outer_prios;
4094 uint32_t eml_encap_types_supported;
4095 uint32_t eml_encap_header_size_limit;
4096 uint32_t eml_max_n_counters;
4100 extern __checkReturn efx_rc_t
4102 __in efx_nic_t *enp,
4103 __out efx_mae_limits_t *emlp);
4105 typedef enum efx_mae_rule_type_e {
4106 EFX_MAE_RULE_ACTION = 0,
4110 } efx_mae_rule_type_t;
4112 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t;
4115 extern __checkReturn efx_rc_t
4116 efx_mae_match_spec_init(
4117 __in efx_nic_t *enp,
4118 __in efx_mae_rule_type_t type,
4120 __out efx_mae_match_spec_t **specp);
4124 efx_mae_match_spec_fini(
4125 __in efx_nic_t *enp,
4126 __in efx_mae_match_spec_t *spec);
4128 typedef enum efx_mae_field_id_e {
4130 * Fields which can be set by efx_mae_match_spec_field_set()
4131 * or by using dedicated field-specific helper APIs.
4133 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
4134 EFX_MAE_FIELD_ETHER_TYPE_BE,
4135 EFX_MAE_FIELD_ETH_SADDR_BE,
4136 EFX_MAE_FIELD_ETH_DADDR_BE,
4137 EFX_MAE_FIELD_VLAN0_TCI_BE,
4138 EFX_MAE_FIELD_VLAN0_PROTO_BE,
4139 EFX_MAE_FIELD_VLAN1_TCI_BE,
4140 EFX_MAE_FIELD_VLAN1_PROTO_BE,
4141 EFX_MAE_FIELD_SRC_IP4_BE,
4142 EFX_MAE_FIELD_DST_IP4_BE,
4143 EFX_MAE_FIELD_IP_PROTO,
4144 EFX_MAE_FIELD_IP_TOS,
4145 EFX_MAE_FIELD_IP_TTL,
4146 EFX_MAE_FIELD_SRC_IP6_BE,
4147 EFX_MAE_FIELD_DST_IP6_BE,
4148 EFX_MAE_FIELD_L4_SPORT_BE,
4149 EFX_MAE_FIELD_L4_DPORT_BE,
4150 EFX_MAE_FIELD_TCP_FLAGS_BE,
4151 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE,
4152 EFX_MAE_FIELD_ENC_ETH_SADDR_BE,
4153 EFX_MAE_FIELD_ENC_ETH_DADDR_BE,
4154 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE,
4155 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE,
4156 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE,
4157 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE,
4158 EFX_MAE_FIELD_ENC_SRC_IP4_BE,
4159 EFX_MAE_FIELD_ENC_DST_IP4_BE,
4160 EFX_MAE_FIELD_ENC_IP_PROTO,
4161 EFX_MAE_FIELD_ENC_IP_TOS,
4162 EFX_MAE_FIELD_ENC_IP_TTL,
4163 EFX_MAE_FIELD_ENC_SRC_IP6_BE,
4164 EFX_MAE_FIELD_ENC_DST_IP6_BE,
4165 EFX_MAE_FIELD_ENC_L4_SPORT_BE,
4166 EFX_MAE_FIELD_ENC_L4_DPORT_BE,
4167 EFX_MAE_FIELD_ENC_VNET_ID_BE,
4168 EFX_MAE_FIELD_OUTER_RULE_ID,
4170 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
4171 EFX_MAE_FIELD_HAS_OVLAN,
4172 EFX_MAE_FIELD_HAS_IVLAN,
4173 EFX_MAE_FIELD_ENC_HAS_OVLAN,
4174 EFX_MAE_FIELD_ENC_HAS_IVLAN,
4177 } efx_mae_field_id_t;
4179 /* MPORT selector. Used to refer to MPORTs in match/action rules. */
4180 typedef struct efx_mport_sel_s {
4184 #define EFX_MPORT_NULL (0U)
4187 * Get MPORT selector of a physical port.
4189 * The resulting MPORT selector is opaque to the caller and can be
4190 * passed as an argument to efx_mae_match_spec_mport_set()
4191 * and efx_mae_action_set_populate_deliver().
4194 extern __checkReturn efx_rc_t
4195 efx_mae_mport_by_phy_port(
4196 __in uint32_t phy_port,
4197 __out efx_mport_sel_t *mportp);
4200 * Get MPORT selector of a PCIe function.
4202 * The resulting MPORT selector is opaque to the caller and can be
4203 * passed as an argument to efx_mae_match_spec_mport_set()
4204 * and efx_mae_action_set_populate_deliver().
4207 extern __checkReturn efx_rc_t
4208 efx_mae_mport_by_pcie_function(
4211 __out efx_mport_sel_t *mportp);
4214 * Fields which have BE postfix in their named constants are expected
4215 * to be passed by callers in big-endian byte order. They will appear
4216 * in the MCDI buffer, which is a part of the match specification, in
4217 * the very same byte order, that is, no conversion will be performed.
4219 * Fields which don't have BE postfix in their named constants are in
4220 * host byte order. MCDI expects them to be little-endian, so the API
4221 * will take care to carry out conversion to little-endian byte order.
4222 * At the moment, the only field in host byte order is MPORT selector.
4225 extern __checkReturn efx_rc_t
4226 efx_mae_match_spec_field_set(
4227 __in efx_mae_match_spec_t *spec,
4228 __in efx_mae_field_id_t field_id,
4229 __in size_t value_size,
4230 __in_bcount(value_size) const uint8_t *value,
4231 __in size_t mask_size,
4232 __in_bcount(mask_size) const uint8_t *mask);
4234 /* The corresponding mask will be set to B_TRUE. */
4236 extern __checkReturn efx_rc_t
4237 efx_mae_match_spec_bit_set(
4238 __in efx_mae_match_spec_t *spec,
4239 __in efx_mae_field_id_t field_id,
4240 __in boolean_t value);
4242 /* If the mask argument is NULL, the API will use full mask by default. */
4244 extern __checkReturn efx_rc_t
4245 efx_mae_match_spec_mport_set(
4246 __in efx_mae_match_spec_t *spec,
4247 __in const efx_mport_sel_t *valuep,
4248 __in_opt const efx_mport_sel_t *maskp);
4251 extern __checkReturn boolean_t
4252 efx_mae_match_specs_equal(
4253 __in const efx_mae_match_spec_t *left,
4254 __in const efx_mae_match_spec_t *right);
4257 * Make sure that match fields known by EFX have proper masks set
4258 * in the match specification as per requirements of SF-122526-TC.
4260 * In the case efx_mae_field_id_t lacks named identifiers for any
4261 * fields which the FW maintains with support status MATCH_ALWAYS,
4262 * the validation result may not be accurate.
4265 extern __checkReturn boolean_t
4266 efx_mae_match_spec_is_valid(
4267 __in efx_nic_t *enp,
4268 __in const efx_mae_match_spec_t *spec);
4270 typedef struct efx_mae_actions_s efx_mae_actions_t;
4273 extern __checkReturn efx_rc_t
4274 efx_mae_action_set_spec_init(
4275 __in efx_nic_t *enp,
4276 __out efx_mae_actions_t **specp);
4280 efx_mae_action_set_spec_fini(
4281 __in efx_nic_t *enp,
4282 __in efx_mae_actions_t *spec);
4285 extern __checkReturn efx_rc_t
4286 efx_mae_action_set_populate_decap(
4287 __in efx_mae_actions_t *spec);
4290 extern __checkReturn efx_rc_t
4291 efx_mae_action_set_populate_vlan_pop(
4292 __in efx_mae_actions_t *spec);
4295 extern __checkReturn efx_rc_t
4296 efx_mae_action_set_populate_vlan_push(
4297 __in efx_mae_actions_t *spec,
4298 __in uint16_t tpid_be,
4299 __in uint16_t tci_be);
4302 * Use efx_mae_action_set_fill_in_eh_id() to set ID of the allocated
4303 * encap. header in the specification prior to action set allocation.
4306 extern __checkReturn efx_rc_t
4307 efx_mae_action_set_populate_encap(
4308 __in efx_mae_actions_t *spec);
4311 * Use efx_mae_action_set_fill_in_counter_id() to set ID of a counter
4312 * in the specification prior to action set allocation.
4314 * NOTICE: the HW will conduct action COUNT after actions DECAP,
4315 * VLAN_POP, VLAN_PUSH (if any) have been applied to the packet,
4316 * but, as a workaround, this order is not validated by the API.
4318 * The workaround helps to unblock DPDK + Open vSwitch use case.
4319 * In Open vSwitch, this action is always the first to be added,
4320 * in particular, it's known to be inserted before action DECAP,
4321 * so enforcing the right order here would cause runtime errors.
4322 * The existing behaviour in Open vSwitch is unlikely to change
4323 * any time soon, and the workaround is a good solution because
4324 * in fact the real COUNT order is a don't care to Open vSwitch.
4327 extern __checkReturn efx_rc_t
4328 efx_mae_action_set_populate_count(
4329 __in efx_mae_actions_t *spec);
4332 extern __checkReturn efx_rc_t
4333 efx_mae_action_set_populate_flag(
4334 __in efx_mae_actions_t *spec);
4337 extern __checkReturn efx_rc_t
4338 efx_mae_action_set_populate_mark(
4339 __in efx_mae_actions_t *spec,
4340 __in uint32_t mark_value);
4343 extern __checkReturn efx_rc_t
4344 efx_mae_action_set_populate_deliver(
4345 __in efx_mae_actions_t *spec,
4346 __in const efx_mport_sel_t *mportp);
4349 extern __checkReturn efx_rc_t
4350 efx_mae_action_set_populate_drop(
4351 __in efx_mae_actions_t *spec);
4354 extern __checkReturn boolean_t
4355 efx_mae_action_set_specs_equal(
4356 __in const efx_mae_actions_t *left,
4357 __in const efx_mae_actions_t *right);
4360 * Conduct a comparison to check whether two match specifications
4361 * of equal rule type (action / outer) and priority would map to
4362 * the very same rule class from the firmware's standpoint.
4364 * For match specification fields that are not supported by firmware,
4365 * the rule class only matches if the mask/value pairs for that field
4366 * are equal. Clients should use efx_mae_match_spec_is_valid() before
4367 * calling this API to detect usage of unsupported fields.
4370 extern __checkReturn efx_rc_t
4371 efx_mae_match_specs_class_cmp(
4372 __in efx_nic_t *enp,
4373 __in const efx_mae_match_spec_t *left,
4374 __in const efx_mae_match_spec_t *right,
4375 __out boolean_t *have_same_classp);
4377 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX
4380 typedef struct efx_mae_rule_id_s {
4382 } efx_mae_rule_id_t;
4385 extern __checkReturn efx_rc_t
4386 efx_mae_outer_rule_insert(
4387 __in efx_nic_t *enp,
4388 __in const efx_mae_match_spec_t *spec,
4389 __in efx_tunnel_protocol_t encap_type,
4390 __out efx_mae_rule_id_t *or_idp);
4393 extern __checkReturn efx_rc_t
4394 efx_mae_outer_rule_remove(
4395 __in efx_nic_t *enp,
4396 __in const efx_mae_rule_id_t *or_idp);
4399 extern __checkReturn efx_rc_t
4400 efx_mae_match_spec_outer_rule_id_set(
4401 __in efx_mae_match_spec_t *spec,
4402 __in const efx_mae_rule_id_t *or_idp);
4404 /* Encap. header ID */
4405 typedef struct efx_mae_eh_id_s {
4410 extern __checkReturn efx_rc_t
4411 efx_mae_encap_header_alloc(
4412 __in efx_nic_t *enp,
4413 __in efx_tunnel_protocol_t encap_type,
4414 __in_bcount(header_size) uint8_t *header_data,
4415 __in size_t header_size,
4416 __out efx_mae_eh_id_t *eh_idp);
4419 extern __checkReturn efx_rc_t
4420 efx_mae_encap_header_free(
4421 __in efx_nic_t *enp,
4422 __in const efx_mae_eh_id_t *eh_idp);
4424 /* See description before efx_mae_action_set_populate_encap(). */
4426 extern __checkReturn efx_rc_t
4427 efx_mae_action_set_fill_in_eh_id(
4428 __in efx_mae_actions_t *spec,
4429 __in const efx_mae_eh_id_t *eh_idp);
4431 typedef struct efx_counter_s {
4436 extern __checkReturn unsigned int
4437 efx_mae_action_set_get_nb_count(
4438 __in const efx_mae_actions_t *spec);
4440 /* See description before efx_mae_action_set_populate_count(). */
4442 extern __checkReturn efx_rc_t
4443 efx_mae_action_set_fill_in_counter_id(
4444 __in efx_mae_actions_t *spec,
4445 __in const efx_counter_t *counter_idp);
4448 typedef struct efx_mae_aset_id_s {
4450 } efx_mae_aset_id_t;
4453 extern __checkReturn efx_rc_t
4454 efx_mae_action_set_alloc(
4455 __in efx_nic_t *enp,
4456 __in const efx_mae_actions_t *spec,
4457 __out efx_mae_aset_id_t *aset_idp);
4460 * Generation count has two purposes:
4462 * 1) Distinguish between counter packets that belong to freed counter
4463 * and the packets that belong to reallocated counter (with the same ID);
4464 * 2) Make sure that all packets are received for a counter that was freed;
4466 * API users should provide generation count out parameter in allocation
4467 * function if counters can be reallocated and consistent counter values are
4470 * API users that need consistent final counter values after counter
4471 * deallocation or counter stream stop should provide the parameter in
4472 * functions that free the counters and stop the counter stream.
4475 extern __checkReturn efx_rc_t
4476 efx_mae_counters_alloc(
4477 __in efx_nic_t *enp,
4478 __in uint32_t n_counters,
4479 __out uint32_t *n_allocatedp,
4480 __out_ecount(n_counters) efx_counter_t *countersp,
4481 __out_opt uint32_t *gen_countp);
4484 extern __checkReturn efx_rc_t
4485 efx_mae_counters_free(
4486 __in efx_nic_t *enp,
4487 __in uint32_t n_counters,
4488 __out uint32_t *n_freedp,
4489 __in_ecount(n_counters) const efx_counter_t *countersp,
4490 __out_opt uint32_t *gen_countp);
4492 /* When set, include counters with a value of zero */
4493 #define EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE (1U << 0)
4496 * Set if credit-based flow control is used. In this case the driver
4497 * must call efx_mae_counters_stream_give_credits() to notify the
4498 * packetiser of descriptors written.
4500 #define EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS (1U << 0)
4503 extern __checkReturn efx_rc_t
4504 efx_mae_counters_stream_start(
4505 __in efx_nic_t *enp,
4506 __in uint16_t rxq_id,
4507 __in uint16_t packet_size,
4508 __in uint32_t flags_in,
4509 __out uint32_t *flags_out);
4512 extern __checkReturn efx_rc_t
4513 efx_mae_counters_stream_stop(
4514 __in efx_nic_t *enp,
4515 __in uint16_t rxq_id,
4516 __out_opt uint32_t *gen_countp);
4519 extern __checkReturn efx_rc_t
4520 efx_mae_counters_stream_give_credits(
4521 __in efx_nic_t *enp,
4522 __in uint32_t n_credits);
4525 extern __checkReturn efx_rc_t
4526 efx_mae_action_set_free(
4527 __in efx_nic_t *enp,
4528 __in const efx_mae_aset_id_t *aset_idp);
4530 /* Action set list ID */
4531 typedef struct efx_mae_aset_list_id_s {
4533 } efx_mae_aset_list_id_t;
4536 * Either action set list ID or action set ID must be passed to this API,
4540 extern __checkReturn efx_rc_t
4541 efx_mae_action_rule_insert(
4542 __in efx_nic_t *enp,
4543 __in const efx_mae_match_spec_t *spec,
4544 __in const efx_mae_aset_list_id_t *asl_idp,
4545 __in const efx_mae_aset_id_t *as_idp,
4546 __out efx_mae_rule_id_t *ar_idp);
4549 extern __checkReturn efx_rc_t
4550 efx_mae_action_rule_remove(
4551 __in efx_nic_t *enp,
4552 __in const efx_mae_rule_id_t *ar_idp);
4554 #endif /* EFSYS_OPT_MAE */
4556 #if EFSYS_OPT_VIRTIO
4558 /* A Virtio net device can have one or more pairs of Rx/Tx virtqueues
4559 * while virtio block device has a single virtqueue,
4560 * for further details refer section of 4.2.3 of SF-120734
4562 typedef enum efx_virtio_vq_type_e {
4563 EFX_VIRTIO_VQ_TYPE_NET_RXQ,
4564 EFX_VIRTIO_VQ_TYPE_NET_TXQ,
4565 EFX_VIRTIO_VQ_TYPE_BLOCK,
4566 EFX_VIRTIO_VQ_NTYPES
4567 } efx_virtio_vq_type_t;
4569 typedef struct efx_virtio_vq_dyncfg_s {
4571 * If queue is being created to be migrated then this
4572 * should be the FINAL_PIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE
4573 * of the queue being migrated from. Otherwise, it should be zero.
4575 uint32_t evvd_vq_pidx;
4577 * If this queue is being created to be migrated then this
4578 * should be the FINAL_CIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE
4579 * of the queue being migrated from. Otherwise, it should be zero.
4581 uint32_t evvd_vq_cidx;
4582 } efx_virtio_vq_dyncfg_t;
4585 * Virtqueue size must be a power of 2, maximum size is 32768
4586 * (see VIRTIO v1.1 section 2.6)
4588 #define EFX_VIRTIO_MAX_VQ_SIZE 0x8000
4590 typedef struct efx_virtio_vq_cfg_s {
4591 unsigned int evvc_vq_num;
4592 efx_virtio_vq_type_t evvc_type;
4594 * vDPA as VF : It is target VF number if queue is being created on VF.
4595 * vDPA as PF : If queue to be created on PF then it should be
4596 * EFX_PCI_VF_INVALID.
4598 uint16_t evvc_target_vf;
4600 * Maximum virtqueue size is EFX_VIRTIO_MAX_VQ_SIZE and
4601 * virtqueue size 0 means the queue is unavailable.
4603 uint32_t evvc_vq_size;
4604 efsys_dma_addr_t evvc_desc_tbl_addr;
4605 efsys_dma_addr_t evvc_avail_ring_addr;
4606 efsys_dma_addr_t evvc_used_ring_addr;
4607 /* MSIX vector number for the virtqueue or 0xFFFF if MSIX is not used */
4608 uint16_t evvc_msix_vector;
4610 * evvc_pas_id contains a PCIe address space identifier if the queue
4613 boolean_t evvc_use_pasid;
4614 uint32_t evvc_pas_id;
4615 /* Negotiated virtio features to be applied to this virtqueue */
4616 uint64_t evcc_features;
4617 } efx_virtio_vq_cfg_t;
4619 typedef struct efx_virtio_vq_s efx_virtio_vq_t;
4621 typedef enum efx_virtio_device_type_e {
4622 EFX_VIRTIO_DEVICE_TYPE_RESERVED,
4623 EFX_VIRTIO_DEVICE_TYPE_NET,
4624 EFX_VIRTIO_DEVICE_TYPE_BLOCK,
4625 EFX_VIRTIO_DEVICE_NTYPES
4626 } efx_virtio_device_type_t;
4629 extern __checkReturn efx_rc_t
4631 __in efx_nic_t *enp);
4636 __in efx_nic_t *enp);
4639 * When virtio net driver in the guest sets VIRTIO_CONFIG_STATUS_DRIVER_OK bit,
4640 * hypervisor starts configuring all the virtqueues in the device. When the
4641 * vhost_user has received VHOST_USER_SET_VRING_ENABLE for all the virtqueues,
4642 * then it invokes VDPA driver callback dev_conf. APIs qstart and qcreate would
4643 * be invoked from dev_conf callback to create the virtqueues, For further
4644 * details refer SF-122427.
4647 extern __checkReturn efx_rc_t
4649 __in efx_nic_t *enp,
4650 __deref_out efx_virtio_vq_t **evvpp);
4653 extern __checkReturn efx_rc_t
4655 __in efx_virtio_vq_t *evvp,
4656 __in efx_virtio_vq_cfg_t *evvcp,
4657 __in_opt efx_virtio_vq_dyncfg_t *evvdp);
4660 extern __checkReturn efx_rc_t
4662 __in efx_virtio_vq_t *evvp,
4663 __out_opt efx_virtio_vq_dyncfg_t *evvdp);
4667 efx_virtio_qdestroy(
4668 __in efx_virtio_vq_t *evvp);
4671 * Get the offset in the BAR of the doorbells for a VI.
4672 * net device : doorbell offset of RX & TX queues
4673 * block device : request doorbell offset in the BAR.
4674 * For further details refer section of 4 of SF-119689
4677 extern __checkReturn efx_rc_t
4678 efx_virtio_get_doorbell_offset(
4679 __in efx_virtio_vq_t *evvp,
4680 __out uint32_t *offsetp);
4683 extern __checkReturn efx_rc_t
4684 efx_virtio_get_features(
4685 __in efx_nic_t *enp,
4686 __in efx_virtio_device_type_t type,
4687 __out uint64_t *featuresp);
4690 extern __checkReturn efx_rc_t
4691 efx_virtio_verify_features(
4692 __in efx_nic_t *enp,
4693 __in efx_virtio_device_type_t type,
4694 __in uint64_t features);
4696 #endif /* EFSYS_OPT_VIRTIO */
4702 #endif /* _SYS_EFX_H */