1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
63 extern __checkReturn efx_rc_t
67 __out efx_family_t *efp,
68 __out unsigned int *membarp);
71 #define EFX_PCI_VENID_SFC 0x1924
72 #define EFX_PCI_VENID_XILINX 0x10EE
74 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
76 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
77 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
78 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
80 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
81 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
82 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
84 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
85 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
87 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
88 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
89 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
91 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
92 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
93 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
95 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
96 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
98 #define EFX_MEM_BAR_SIENA 2
100 #define EFX_MEM_BAR_HUNTINGTON_PF 2
101 #define EFX_MEM_BAR_HUNTINGTON_VF 0
103 #define EFX_MEM_BAR_MEDFORD_PF 2
104 #define EFX_MEM_BAR_MEDFORD_VF 0
106 #define EFX_MEM_BAR_MEDFORD2 0
108 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
109 #define EFX_MEM_BAR_RIVERHEAD 2
117 EFX_ERR_BUFID_DC_OOB,
130 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
132 extern __checkReturn uint32_t
134 __in uint32_t crc_init,
135 __in_ecount(length) uint8_t const *input,
139 /* Type prototypes */
141 typedef struct efx_rxq_s efx_rxq_t;
145 typedef struct efx_nic_s efx_nic_t;
148 extern __checkReturn efx_rc_t
150 __in efx_family_t family,
151 __in efsys_identifier_t *esip,
152 __in efsys_bar_t *esbp,
153 __in efsys_lock_t *eslp,
154 __deref_out efx_nic_t **enpp);
156 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
157 typedef enum efx_fw_variant_e {
158 EFX_FW_VARIANT_FULL_FEATURED,
159 EFX_FW_VARIANT_LOW_LATENCY,
160 EFX_FW_VARIANT_PACKED_STREAM,
161 EFX_FW_VARIANT_HIGH_TX_RATE,
162 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
163 EFX_FW_VARIANT_RULES_ENGINE,
165 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
169 extern __checkReturn efx_rc_t
172 __in efx_fw_variant_t efv);
175 extern __checkReturn efx_rc_t
177 __in efx_nic_t *enp);
180 extern __checkReturn efx_rc_t
182 __in efx_nic_t *enp);
185 extern __checkReturn boolean_t
186 efx_nic_hw_unavailable(
187 __in efx_nic_t *enp);
191 efx_nic_set_hw_unavailable(
192 __in efx_nic_t *enp);
197 extern __checkReturn efx_rc_t
198 efx_nic_register_test(
199 __in efx_nic_t *enp);
201 #endif /* EFSYS_OPT_DIAG */
206 __in efx_nic_t *enp);
211 __in efx_nic_t *enp);
216 __in efx_nic_t *enp);
218 #define EFX_PCIE_LINK_SPEED_GEN1 1
219 #define EFX_PCIE_LINK_SPEED_GEN2 2
220 #define EFX_PCIE_LINK_SPEED_GEN3 3
222 typedef enum efx_pcie_link_performance_e {
223 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
224 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
225 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
226 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
227 } efx_pcie_link_performance_t;
230 extern __checkReturn efx_rc_t
231 efx_nic_calculate_pcie_link_bandwidth(
232 __in uint32_t pcie_link_width,
233 __in uint32_t pcie_link_gen,
234 __out uint32_t *bandwidth_mbpsp);
237 extern __checkReturn efx_rc_t
238 efx_nic_check_pcie_link_speed(
240 __in uint32_t pcie_link_width,
241 __in uint32_t pcie_link_gen,
242 __out efx_pcie_link_performance_t *resultp);
246 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
247 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
248 #define WITH_MCDI_V2 1
251 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
253 typedef enum efx_mcdi_exception_e {
254 EFX_MCDI_EXCEPTION_MC_REBOOT,
255 EFX_MCDI_EXCEPTION_MC_BADASSERT,
256 } efx_mcdi_exception_t;
258 #if EFSYS_OPT_MCDI_LOGGING
259 typedef enum efx_log_msg_e {
261 EFX_LOG_MCDI_REQUEST,
262 EFX_LOG_MCDI_RESPONSE,
264 #endif /* EFSYS_OPT_MCDI_LOGGING */
266 typedef struct efx_mcdi_transport_s {
268 efsys_mem_t *emt_dma_mem;
269 void (*emt_execute)(void *, efx_mcdi_req_t *);
270 void (*emt_ev_cpl)(void *);
271 void (*emt_exception)(void *, efx_mcdi_exception_t);
272 #if EFSYS_OPT_MCDI_LOGGING
273 void (*emt_logger)(void *, efx_log_msg_t,
274 void *, size_t, void *, size_t);
275 #endif /* EFSYS_OPT_MCDI_LOGGING */
276 #if EFSYS_OPT_MCDI_PROXY_AUTH
277 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
278 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
279 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
280 void (*emt_ev_proxy_request)(void *, uint32_t);
281 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
282 } efx_mcdi_transport_t;
285 extern __checkReturn efx_rc_t
288 __in const efx_mcdi_transport_t *mtp);
291 extern __checkReturn efx_rc_t
293 __in efx_nic_t *enp);
298 __in efx_nic_t *enp);
302 efx_mcdi_get_timeout(
304 __in efx_mcdi_req_t *emrp,
305 __out uint32_t *usec_timeoutp);
309 efx_mcdi_request_start(
311 __in efx_mcdi_req_t *emrp,
312 __in boolean_t ev_cpl);
315 extern __checkReturn boolean_t
316 efx_mcdi_request_poll(
317 __in efx_nic_t *enp);
320 extern __checkReturn boolean_t
321 efx_mcdi_request_abort(
322 __in efx_nic_t *enp);
327 __in efx_nic_t *enp);
329 #endif /* EFSYS_OPT_MCDI */
333 #define EFX_NINTR_SIENA 1024
335 typedef enum efx_intr_type_e {
336 EFX_INTR_INVALID = 0,
342 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
345 extern __checkReturn efx_rc_t
348 __in efx_intr_type_t type,
349 __in_opt efsys_mem_t *esmp);
354 __in efx_nic_t *enp);
359 __in efx_nic_t *enp);
363 efx_intr_disable_unlocked(
364 __in efx_nic_t *enp);
366 #define EFX_INTR_NEVQS 32
369 extern __checkReturn efx_rc_t
372 __in unsigned int level);
376 efx_intr_status_line(
378 __out boolean_t *fatalp,
379 __out uint32_t *maskp);
383 efx_intr_status_message(
385 __in unsigned int message,
386 __out boolean_t *fatalp);
391 __in efx_nic_t *enp);
396 __in efx_nic_t *enp);
400 #if EFSYS_OPT_MAC_STATS
402 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
403 typedef enum efx_mac_stat_e {
406 EFX_MAC_RX_UNICST_PKTS,
407 EFX_MAC_RX_MULTICST_PKTS,
408 EFX_MAC_RX_BRDCST_PKTS,
409 EFX_MAC_RX_PAUSE_PKTS,
410 EFX_MAC_RX_LE_64_PKTS,
411 EFX_MAC_RX_65_TO_127_PKTS,
412 EFX_MAC_RX_128_TO_255_PKTS,
413 EFX_MAC_RX_256_TO_511_PKTS,
414 EFX_MAC_RX_512_TO_1023_PKTS,
415 EFX_MAC_RX_1024_TO_15XX_PKTS,
416 EFX_MAC_RX_GE_15XX_PKTS,
418 EFX_MAC_RX_FCS_ERRORS,
419 EFX_MAC_RX_DROP_EVENTS,
420 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
421 EFX_MAC_RX_SYMBOL_ERRORS,
422 EFX_MAC_RX_ALIGN_ERRORS,
423 EFX_MAC_RX_INTERNAL_ERRORS,
424 EFX_MAC_RX_JABBER_PKTS,
425 EFX_MAC_RX_LANE0_CHAR_ERR,
426 EFX_MAC_RX_LANE1_CHAR_ERR,
427 EFX_MAC_RX_LANE2_CHAR_ERR,
428 EFX_MAC_RX_LANE3_CHAR_ERR,
429 EFX_MAC_RX_LANE0_DISP_ERR,
430 EFX_MAC_RX_LANE1_DISP_ERR,
431 EFX_MAC_RX_LANE2_DISP_ERR,
432 EFX_MAC_RX_LANE3_DISP_ERR,
433 EFX_MAC_RX_MATCH_FAULT,
434 EFX_MAC_RX_NODESC_DROP_CNT,
437 EFX_MAC_TX_UNICST_PKTS,
438 EFX_MAC_TX_MULTICST_PKTS,
439 EFX_MAC_TX_BRDCST_PKTS,
440 EFX_MAC_TX_PAUSE_PKTS,
441 EFX_MAC_TX_LE_64_PKTS,
442 EFX_MAC_TX_65_TO_127_PKTS,
443 EFX_MAC_TX_128_TO_255_PKTS,
444 EFX_MAC_TX_256_TO_511_PKTS,
445 EFX_MAC_TX_512_TO_1023_PKTS,
446 EFX_MAC_TX_1024_TO_15XX_PKTS,
447 EFX_MAC_TX_GE_15XX_PKTS,
449 EFX_MAC_TX_SGL_COL_PKTS,
450 EFX_MAC_TX_MULT_COL_PKTS,
451 EFX_MAC_TX_EX_COL_PKTS,
452 EFX_MAC_TX_LATE_COL_PKTS,
454 EFX_MAC_TX_EX_DEF_PKTS,
455 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
456 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
457 EFX_MAC_PM_TRUNC_VFIFO_FULL,
458 EFX_MAC_PM_DISCARD_VFIFO_FULL,
459 EFX_MAC_PM_TRUNC_QBB,
460 EFX_MAC_PM_DISCARD_QBB,
461 EFX_MAC_PM_DISCARD_MAPPING,
462 EFX_MAC_RXDP_Q_DISABLED_PKTS,
463 EFX_MAC_RXDP_DI_DROPPED_PKTS,
464 EFX_MAC_RXDP_STREAMING_PKTS,
465 EFX_MAC_RXDP_HLB_FETCH,
466 EFX_MAC_RXDP_HLB_WAIT,
467 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
468 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
469 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
470 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
471 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
472 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
473 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
474 EFX_MAC_VADAPTER_RX_BAD_BYTES,
475 EFX_MAC_VADAPTER_RX_OVERFLOW,
476 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
477 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
478 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
479 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
480 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
481 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
482 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
483 EFX_MAC_VADAPTER_TX_BAD_BYTES,
484 EFX_MAC_VADAPTER_TX_OVERFLOW,
485 EFX_MAC_FEC_UNCORRECTED_ERRORS,
486 EFX_MAC_FEC_CORRECTED_ERRORS,
487 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
488 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
489 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
490 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
491 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
492 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
493 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
494 EFX_MAC_CTPIO_OVERFLOW_FAIL,
495 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
496 EFX_MAC_CTPIO_TIMEOUT_FAIL,
497 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
498 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
499 EFX_MAC_CTPIO_INVALID_WR_FAIL,
500 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
501 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
502 EFX_MAC_CTPIO_RUNT_FALLBACK,
503 EFX_MAC_CTPIO_SUCCESS,
504 EFX_MAC_CTPIO_FALLBACK,
505 EFX_MAC_CTPIO_POISON,
507 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
508 EFX_MAC_RXDP_HLB_IDLE,
509 EFX_MAC_RXDP_HLB_TIMEOUT,
513 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
515 #endif /* EFSYS_OPT_MAC_STATS */
517 typedef enum efx_link_mode_e {
518 EFX_LINK_UNKNOWN = 0,
534 #define EFX_MAC_ADDR_LEN 6
536 #define EFX_VNI_OR_VSID_LEN 3
538 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
540 #define EFX_MAC_MULTICAST_LIST_MAX 256
542 #define EFX_MAC_SDU_MAX 9202
544 #define EFX_MAC_PDU_ADJUSTMENT \
548 + /* bug16011 */ 16) \
550 #define EFX_MAC_PDU(_sdu) \
551 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
554 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
555 * the SDU rounded up slightly.
557 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
559 #define EFX_MAC_PDU_MIN 60
560 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
563 extern __checkReturn efx_rc_t
569 extern __checkReturn efx_rc_t
575 extern __checkReturn efx_rc_t
581 extern __checkReturn efx_rc_t
584 __in boolean_t all_unicst,
585 __in boolean_t mulcst,
586 __in boolean_t all_mulcst,
587 __in boolean_t brdcst);
591 efx_mac_filter_get_all_ucast_mcast(
593 __out boolean_t *all_unicst,
594 __out boolean_t *all_mulcst);
597 extern __checkReturn efx_rc_t
598 efx_mac_multicast_list_set(
600 __in_ecount(6*count) uint8_t const *addrs,
604 extern __checkReturn efx_rc_t
605 efx_mac_filter_default_rxq_set(
608 __in boolean_t using_rss);
612 efx_mac_filter_default_rxq_clear(
613 __in efx_nic_t *enp);
616 extern __checkReturn efx_rc_t
619 __in boolean_t enabled);
622 extern __checkReturn efx_rc_t
625 __out boolean_t *mac_upp);
627 #define EFX_FCNTL_RESPOND 0x00000001
628 #define EFX_FCNTL_GENERATE 0x00000002
631 extern __checkReturn efx_rc_t
634 __in unsigned int fcntl,
635 __in boolean_t autoneg);
641 __out unsigned int *fcntl_wantedp,
642 __out unsigned int *fcntl_linkp);
645 #if EFSYS_OPT_MAC_STATS
650 extern __checkReturn const char *
653 __in unsigned int id);
655 #endif /* EFSYS_OPT_NAMES */
657 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
659 #define EFX_MAC_STATS_MASK_NPAGES \
660 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
661 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
662 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
665 * Get mask of MAC statistics supported by the hardware.
667 * If mask_size is insufficient to return the mask, EINVAL error is
668 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
669 * (which is sizeof (uint32_t)) is sufficient.
672 extern __checkReturn efx_rc_t
673 efx_mac_stats_get_mask(
675 __out_bcount(mask_size) uint32_t *maskp,
676 __in size_t mask_size);
678 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
679 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
680 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
684 extern __checkReturn efx_rc_t
686 __in efx_nic_t *enp);
689 * Upload mac statistics supported by the hardware into the given buffer.
691 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
692 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
694 * The hardware will only DMA statistics that it understands (of course).
695 * Drivers should not make any assumptions about which statistics are
696 * supported, especially when the statistics are generated by firmware.
698 * Thus, drivers should zero this buffer before use, so that not-understood
699 * statistics read back as zero.
702 extern __checkReturn efx_rc_t
703 efx_mac_stats_upload(
705 __in efsys_mem_t *esmp);
708 extern __checkReturn efx_rc_t
709 efx_mac_stats_periodic(
711 __in efsys_mem_t *esmp,
712 __in uint16_t period_ms,
713 __in boolean_t events);
716 extern __checkReturn efx_rc_t
717 efx_mac_stats_update(
719 __in efsys_mem_t *esmp,
720 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
721 __inout_opt uint32_t *generationp);
723 #endif /* EFSYS_OPT_MAC_STATS */
727 typedef enum efx_mon_type_e {
740 __in efx_nic_t *enp);
742 #endif /* EFSYS_OPT_NAMES */
745 extern __checkReturn efx_rc_t
747 __in efx_nic_t *enp);
749 #if EFSYS_OPT_MON_STATS
751 #define EFX_MON_STATS_PAGE_SIZE 0x100
752 #define EFX_MON_MASK_ELEMENT_SIZE 32
754 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
755 typedef enum efx_mon_stat_e {
756 EFX_MON_STAT_CONTROLLER_TEMP,
757 EFX_MON_STAT_PHY_COMMON_TEMP,
758 EFX_MON_STAT_CONTROLLER_COOLING,
759 EFX_MON_STAT_PHY0_TEMP,
760 EFX_MON_STAT_PHY0_COOLING,
761 EFX_MON_STAT_PHY1_TEMP,
762 EFX_MON_STAT_PHY1_COOLING,
768 EFX_MON_STAT_IN_12V0,
769 EFX_MON_STAT_IN_1V2A,
770 EFX_MON_STAT_IN_VREF,
771 EFX_MON_STAT_OUT_VAOE,
772 EFX_MON_STAT_AOE_TEMP,
773 EFX_MON_STAT_PSU_AOE_TEMP,
774 EFX_MON_STAT_PSU_TEMP,
780 EFX_MON_STAT_IN_VAOE,
781 EFX_MON_STAT_OUT_IAOE,
782 EFX_MON_STAT_IN_IAOE,
783 EFX_MON_STAT_NIC_POWER,
785 EFX_MON_STAT_IN_I0V9,
786 EFX_MON_STAT_IN_I1V2,
787 EFX_MON_STAT_IN_0V9_ADC,
788 EFX_MON_STAT_CONTROLLER_2_TEMP,
789 EFX_MON_STAT_VREG_INTERNAL_TEMP,
790 EFX_MON_STAT_VREG_0V9_TEMP,
791 EFX_MON_STAT_VREG_1V2_TEMP,
792 EFX_MON_STAT_CONTROLLER_VPTAT,
793 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
794 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
795 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
796 EFX_MON_STAT_AMBIENT_TEMP,
797 EFX_MON_STAT_AIRFLOW,
798 EFX_MON_STAT_VDD08D_VSS08D_CSR,
799 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
800 EFX_MON_STAT_HOTPOINT_TEMP,
801 EFX_MON_STAT_PHY_POWER_PORT0,
802 EFX_MON_STAT_PHY_POWER_PORT1,
803 EFX_MON_STAT_MUM_VCC,
804 EFX_MON_STAT_IN_0V9_A,
805 EFX_MON_STAT_IN_I0V9_A,
806 EFX_MON_STAT_VREG_0V9_A_TEMP,
807 EFX_MON_STAT_IN_0V9_B,
808 EFX_MON_STAT_IN_I0V9_B,
809 EFX_MON_STAT_VREG_0V9_B_TEMP,
810 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
811 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
812 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
813 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
814 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
815 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
816 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
817 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
818 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
819 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
820 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
821 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
822 EFX_MON_STAT_SODIMM_VOUT,
823 EFX_MON_STAT_SODIMM_0_TEMP,
824 EFX_MON_STAT_SODIMM_1_TEMP,
825 EFX_MON_STAT_PHY0_VCC,
826 EFX_MON_STAT_PHY1_VCC,
827 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
828 EFX_MON_STAT_BOARD_FRONT_TEMP,
829 EFX_MON_STAT_BOARD_BACK_TEMP,
830 EFX_MON_STAT_IN_I1V8,
831 EFX_MON_STAT_IN_I2V5,
832 EFX_MON_STAT_IN_I3V3,
833 EFX_MON_STAT_IN_I12V0,
835 EFX_MON_STAT_IN_I1V3,
839 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
841 typedef enum efx_mon_stat_state_e {
842 EFX_MON_STAT_STATE_OK = 0,
843 EFX_MON_STAT_STATE_WARNING = 1,
844 EFX_MON_STAT_STATE_FATAL = 2,
845 EFX_MON_STAT_STATE_BROKEN = 3,
846 EFX_MON_STAT_STATE_NO_READING = 4,
847 } efx_mon_stat_state_t;
849 typedef enum efx_mon_stat_unit_e {
850 EFX_MON_STAT_UNIT_UNKNOWN = 0,
851 EFX_MON_STAT_UNIT_BOOL,
852 EFX_MON_STAT_UNIT_TEMP_C,
853 EFX_MON_STAT_UNIT_VOLTAGE_MV,
854 EFX_MON_STAT_UNIT_CURRENT_MA,
855 EFX_MON_STAT_UNIT_POWER_W,
856 EFX_MON_STAT_UNIT_RPM,
858 } efx_mon_stat_unit_t;
860 typedef struct efx_mon_stat_value_s {
862 efx_mon_stat_state_t emsv_state;
863 efx_mon_stat_unit_t emsv_unit;
864 } efx_mon_stat_value_t;
866 typedef struct efx_mon_limit_value_s {
867 uint16_t emlv_warning_min;
868 uint16_t emlv_warning_max;
869 uint16_t emlv_fatal_min;
870 uint16_t emlv_fatal_max;
871 } efx_mon_stat_limits_t;
873 typedef enum efx_mon_stat_portmask_e {
874 EFX_MON_STAT_PORTMAP_NONE = 0,
875 EFX_MON_STAT_PORTMAP_PORT0 = 1,
876 EFX_MON_STAT_PORTMAP_PORT1 = 2,
877 EFX_MON_STAT_PORTMAP_PORT2 = 3,
878 EFX_MON_STAT_PORTMAP_PORT3 = 4,
879 EFX_MON_STAT_PORTMAP_ALL = (-1),
880 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
881 } efx_mon_stat_portmask_t;
889 __in efx_mon_stat_t id);
893 efx_mon_stat_description(
895 __in efx_mon_stat_t id);
897 #endif /* EFSYS_OPT_NAMES */
900 extern __checkReturn boolean_t
901 efx_mon_mcdi_to_efx_stat(
903 __out efx_mon_stat_t *statp);
906 extern __checkReturn boolean_t
907 efx_mon_get_stat_unit(
908 __in efx_mon_stat_t stat,
909 __out efx_mon_stat_unit_t *unitp);
912 extern __checkReturn boolean_t
913 efx_mon_get_stat_portmap(
914 __in efx_mon_stat_t stat,
915 __out efx_mon_stat_portmask_t *maskp);
918 extern __checkReturn efx_rc_t
919 efx_mon_stats_update(
921 __in efsys_mem_t *esmp,
922 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
925 extern __checkReturn efx_rc_t
926 efx_mon_limits_update(
928 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
930 #endif /* EFSYS_OPT_MON_STATS */
935 __in efx_nic_t *enp);
940 extern __checkReturn efx_rc_t
942 __in efx_nic_t *enp);
944 #if EFSYS_OPT_PHY_LED_CONTROL
946 typedef enum efx_phy_led_mode_e {
947 EFX_PHY_LED_DEFAULT = 0,
952 } efx_phy_led_mode_t;
955 extern __checkReturn efx_rc_t
958 __in efx_phy_led_mode_t mode);
960 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
963 extern __checkReturn efx_rc_t
965 __in efx_nic_t *enp);
967 #if EFSYS_OPT_LOOPBACK
969 typedef enum efx_loopback_type_e {
970 EFX_LOOPBACK_OFF = 0,
971 EFX_LOOPBACK_DATA = 1,
972 EFX_LOOPBACK_GMAC = 2,
973 EFX_LOOPBACK_XGMII = 3,
974 EFX_LOOPBACK_XGXS = 4,
975 EFX_LOOPBACK_XAUI = 5,
976 EFX_LOOPBACK_GMII = 6,
977 EFX_LOOPBACK_SGMII = 7,
978 EFX_LOOPBACK_XGBR = 8,
979 EFX_LOOPBACK_XFI = 9,
980 EFX_LOOPBACK_XAUI_FAR = 10,
981 EFX_LOOPBACK_GMII_FAR = 11,
982 EFX_LOOPBACK_SGMII_FAR = 12,
983 EFX_LOOPBACK_XFI_FAR = 13,
984 EFX_LOOPBACK_GPHY = 14,
985 EFX_LOOPBACK_PHY_XS = 15,
986 EFX_LOOPBACK_PCS = 16,
987 EFX_LOOPBACK_PMA_PMD = 17,
988 EFX_LOOPBACK_XPORT = 18,
989 EFX_LOOPBACK_XGMII_WS = 19,
990 EFX_LOOPBACK_XAUI_WS = 20,
991 EFX_LOOPBACK_XAUI_WS_FAR = 21,
992 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
993 EFX_LOOPBACK_GMII_WS = 23,
994 EFX_LOOPBACK_XFI_WS = 24,
995 EFX_LOOPBACK_XFI_WS_FAR = 25,
996 EFX_LOOPBACK_PHYXS_WS = 26,
997 EFX_LOOPBACK_PMA_INT = 27,
998 EFX_LOOPBACK_SD_NEAR = 28,
999 EFX_LOOPBACK_SD_FAR = 29,
1000 EFX_LOOPBACK_PMA_INT_WS = 30,
1001 EFX_LOOPBACK_SD_FEP2_WS = 31,
1002 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1003 EFX_LOOPBACK_SD_FEP_WS = 33,
1004 EFX_LOOPBACK_SD_FES_WS = 34,
1005 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1006 EFX_LOOPBACK_DATA_WS = 36,
1007 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1009 } efx_loopback_type_t;
1011 typedef enum efx_loopback_kind_e {
1012 EFX_LOOPBACK_KIND_OFF = 0,
1013 EFX_LOOPBACK_KIND_ALL,
1014 EFX_LOOPBACK_KIND_MAC,
1015 EFX_LOOPBACK_KIND_PHY,
1017 } efx_loopback_kind_t;
1022 __in efx_loopback_kind_t loopback_kind,
1023 __out efx_qword_t *maskp);
1026 extern __checkReturn efx_rc_t
1027 efx_port_loopback_set(
1028 __in efx_nic_t *enp,
1029 __in efx_link_mode_t link_mode,
1030 __in efx_loopback_type_t type);
1035 extern __checkReturn const char *
1036 efx_loopback_type_name(
1037 __in efx_nic_t *enp,
1038 __in efx_loopback_type_t type);
1040 #endif /* EFSYS_OPT_NAMES */
1042 #endif /* EFSYS_OPT_LOOPBACK */
1045 extern __checkReturn efx_rc_t
1047 __in efx_nic_t *enp,
1048 __out_opt efx_link_mode_t *link_modep);
1053 __in efx_nic_t *enp);
1055 typedef enum efx_phy_cap_type_e {
1056 EFX_PHY_CAP_INVALID = 0,
1061 EFX_PHY_CAP_1000HDX,
1062 EFX_PHY_CAP_1000FDX,
1063 EFX_PHY_CAP_10000FDX,
1067 EFX_PHY_CAP_40000FDX,
1069 EFX_PHY_CAP_100000FDX,
1070 EFX_PHY_CAP_25000FDX,
1071 EFX_PHY_CAP_50000FDX,
1072 EFX_PHY_CAP_BASER_FEC,
1073 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1075 EFX_PHY_CAP_RS_FEC_REQUESTED,
1076 EFX_PHY_CAP_25G_BASER_FEC,
1077 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1079 } efx_phy_cap_type_t;
1082 #define EFX_PHY_CAP_CURRENT 0x00000000
1083 #define EFX_PHY_CAP_DEFAULT 0x00000001
1084 #define EFX_PHY_CAP_PERM 0x00000002
1088 efx_phy_adv_cap_get(
1089 __in efx_nic_t *enp,
1091 __out uint32_t *maskp);
1094 extern __checkReturn efx_rc_t
1095 efx_phy_adv_cap_set(
1096 __in efx_nic_t *enp,
1097 __in uint32_t mask);
1102 __in efx_nic_t *enp,
1103 __out uint32_t *maskp);
1106 extern __checkReturn efx_rc_t
1108 __in efx_nic_t *enp,
1109 __out uint32_t *ouip);
1111 typedef enum efx_phy_media_type_e {
1112 EFX_PHY_MEDIA_INVALID = 0,
1117 EFX_PHY_MEDIA_SFP_PLUS,
1118 EFX_PHY_MEDIA_BASE_T,
1119 EFX_PHY_MEDIA_QSFP_PLUS,
1120 EFX_PHY_MEDIA_NTYPES
1121 } efx_phy_media_type_t;
1124 * Get the type of medium currently used. If the board has ports for
1125 * modules, a module is present, and we recognise the media type of
1126 * the module, then this will be the media type of the module.
1127 * Otherwise it will be the media type of the port.
1131 efx_phy_media_type_get(
1132 __in efx_nic_t *enp,
1133 __out efx_phy_media_type_t *typep);
1136 * 2-wire device address of the base information in accordance with SFF-8472
1137 * Diagnostic Monitoring Interface for Optical Transceivers section
1138 * 4 Memory Organization.
1140 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1143 * 2-wire device address of the digital diagnostics monitoring interface
1144 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1145 * Transceivers section 4 Memory Organization.
1147 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1150 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1151 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1154 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1157 * Maximum accessible data offset for PHY module information.
1159 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1163 extern __checkReturn efx_rc_t
1164 efx_phy_module_get_info(
1165 __in efx_nic_t *enp,
1166 __in uint8_t dev_addr,
1169 __out_bcount(len) uint8_t *data);
1171 #if EFSYS_OPT_PHY_STATS
1173 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1174 typedef enum efx_phy_stat_e {
1176 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1177 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1178 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1179 EFX_PHY_STAT_PMA_PMD_REV_A,
1180 EFX_PHY_STAT_PMA_PMD_REV_B,
1181 EFX_PHY_STAT_PMA_PMD_REV_C,
1182 EFX_PHY_STAT_PMA_PMD_REV_D,
1183 EFX_PHY_STAT_PCS_LINK_UP,
1184 EFX_PHY_STAT_PCS_RX_FAULT,
1185 EFX_PHY_STAT_PCS_TX_FAULT,
1186 EFX_PHY_STAT_PCS_BER,
1187 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1188 EFX_PHY_STAT_PHY_XS_LINK_UP,
1189 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1190 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1191 EFX_PHY_STAT_PHY_XS_ALIGN,
1192 EFX_PHY_STAT_PHY_XS_SYNC_A,
1193 EFX_PHY_STAT_PHY_XS_SYNC_B,
1194 EFX_PHY_STAT_PHY_XS_SYNC_C,
1195 EFX_PHY_STAT_PHY_XS_SYNC_D,
1196 EFX_PHY_STAT_AN_LINK_UP,
1197 EFX_PHY_STAT_AN_MASTER,
1198 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1199 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1200 EFX_PHY_STAT_CL22EXT_LINK_UP,
1205 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1206 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1207 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1208 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1209 EFX_PHY_STAT_AN_COMPLETE,
1210 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1211 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1212 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1213 EFX_PHY_STAT_PCS_FW_VERSION_0,
1214 EFX_PHY_STAT_PCS_FW_VERSION_1,
1215 EFX_PHY_STAT_PCS_FW_VERSION_2,
1216 EFX_PHY_STAT_PCS_FW_VERSION_3,
1217 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1218 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1219 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1220 EFX_PHY_STAT_PCS_OP_MODE,
1224 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1231 __in efx_nic_t *enp,
1232 __in efx_phy_stat_t stat);
1234 #endif /* EFSYS_OPT_NAMES */
1236 #define EFX_PHY_STATS_SIZE 0x100
1239 extern __checkReturn efx_rc_t
1240 efx_phy_stats_update(
1241 __in efx_nic_t *enp,
1242 __in efsys_mem_t *esmp,
1243 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1245 #endif /* EFSYS_OPT_PHY_STATS */
1250 typedef enum efx_bist_type_e {
1251 EFX_BIST_TYPE_UNKNOWN,
1252 EFX_BIST_TYPE_PHY_NORMAL,
1253 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1254 EFX_BIST_TYPE_PHY_CABLE_LONG,
1255 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1256 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1257 EFX_BIST_TYPE_REG, /* Test the register memories */
1258 EFX_BIST_TYPE_NTYPES,
1261 typedef enum efx_bist_result_e {
1262 EFX_BIST_RESULT_UNKNOWN,
1263 EFX_BIST_RESULT_RUNNING,
1264 EFX_BIST_RESULT_PASSED,
1265 EFX_BIST_RESULT_FAILED,
1266 } efx_bist_result_t;
1268 typedef enum efx_phy_cable_status_e {
1269 EFX_PHY_CABLE_STATUS_OK,
1270 EFX_PHY_CABLE_STATUS_INVALID,
1271 EFX_PHY_CABLE_STATUS_OPEN,
1272 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1273 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1274 EFX_PHY_CABLE_STATUS_BUSY,
1275 } efx_phy_cable_status_t;
1277 typedef enum efx_bist_value_e {
1278 EFX_BIST_PHY_CABLE_LENGTH_A,
1279 EFX_BIST_PHY_CABLE_LENGTH_B,
1280 EFX_BIST_PHY_CABLE_LENGTH_C,
1281 EFX_BIST_PHY_CABLE_LENGTH_D,
1282 EFX_BIST_PHY_CABLE_STATUS_A,
1283 EFX_BIST_PHY_CABLE_STATUS_B,
1284 EFX_BIST_PHY_CABLE_STATUS_C,
1285 EFX_BIST_PHY_CABLE_STATUS_D,
1286 EFX_BIST_FAULT_CODE,
1288 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1294 EFX_BIST_MEM_EXPECT,
1295 EFX_BIST_MEM_ACTUAL,
1297 EFX_BIST_MEM_ECC_PARITY,
1298 EFX_BIST_MEM_ECC_FATAL,
1303 extern __checkReturn efx_rc_t
1304 efx_bist_enable_offline(
1305 __in efx_nic_t *enp);
1308 extern __checkReturn efx_rc_t
1310 __in efx_nic_t *enp,
1311 __in efx_bist_type_t type);
1314 extern __checkReturn efx_rc_t
1316 __in efx_nic_t *enp,
1317 __in efx_bist_type_t type,
1318 __out efx_bist_result_t *resultp,
1319 __out_opt uint32_t *value_maskp,
1320 __out_ecount_opt(count) unsigned long *valuesp,
1326 __in efx_nic_t *enp,
1327 __in efx_bist_type_t type);
1329 #endif /* EFSYS_OPT_BIST */
1331 #define EFX_FEATURE_IPV6 0x00000001
1332 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1333 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1334 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1335 #define EFX_FEATURE_MCDI 0x00000020
1336 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1337 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1338 #define EFX_FEATURE_TURBO 0x00000100
1339 #define EFX_FEATURE_MCDI_DMA 0x00000200
1340 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1341 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1342 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1343 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1344 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1345 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1347 typedef enum efx_tunnel_protocol_e {
1348 EFX_TUNNEL_PROTOCOL_NONE = 0,
1349 EFX_TUNNEL_PROTOCOL_VXLAN,
1350 EFX_TUNNEL_PROTOCOL_GENEVE,
1351 EFX_TUNNEL_PROTOCOL_NVGRE,
1353 } efx_tunnel_protocol_t;
1355 typedef enum efx_vi_window_shift_e {
1356 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1357 EFX_VI_WINDOW_SHIFT_8K = 13,
1358 EFX_VI_WINDOW_SHIFT_16K = 14,
1359 EFX_VI_WINDOW_SHIFT_64K = 16,
1360 } efx_vi_window_shift_t;
1362 typedef struct efx_nic_cfg_s {
1363 uint32_t enc_board_type;
1364 uint32_t enc_phy_type;
1366 char enc_phy_name[21];
1368 char enc_phy_revision[21];
1369 efx_mon_type_t enc_mon_type;
1370 #if EFSYS_OPT_MON_STATS
1371 uint32_t enc_mon_stat_dma_buf_size;
1372 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1374 unsigned int enc_features;
1375 efx_vi_window_shift_t enc_vi_window_shift;
1376 uint8_t enc_mac_addr[6];
1377 uint8_t enc_port; /* PHY port number */
1378 uint32_t enc_intr_vec_base;
1379 uint32_t enc_intr_limit;
1380 uint32_t enc_evq_limit;
1381 uint32_t enc_txq_limit;
1382 uint32_t enc_rxq_limit;
1383 uint32_t enc_evq_max_nevs;
1384 uint32_t enc_evq_min_nevs;
1385 uint32_t enc_rxq_max_ndescs;
1386 uint32_t enc_rxq_min_ndescs;
1387 uint32_t enc_txq_max_ndescs;
1388 uint32_t enc_txq_min_ndescs;
1389 uint32_t enc_buftbl_limit;
1390 uint32_t enc_piobuf_limit;
1391 uint32_t enc_piobuf_size;
1392 uint32_t enc_piobuf_min_alloc_size;
1393 uint32_t enc_evq_timer_quantum_ns;
1394 uint32_t enc_evq_timer_max_us;
1395 uint32_t enc_clk_mult;
1396 uint32_t enc_ev_desc_size;
1397 uint32_t enc_rx_desc_size;
1398 uint32_t enc_tx_desc_size;
1399 /* Maximum Rx prefix size if many Rx prefixes are supported */
1400 uint32_t enc_rx_prefix_size;
1401 uint32_t enc_rx_buf_align_start;
1402 uint32_t enc_rx_buf_align_end;
1403 #if EFSYS_OPT_RX_SCALE
1404 uint32_t enc_rx_scale_max_exclusive_contexts;
1406 * Mask of supported hash algorithms.
1407 * Hash algorithm types are used as the bit indices.
1409 uint32_t enc_rx_scale_hash_alg_mask;
1411 * Indicates whether port numbers can be included to the
1412 * input data for hash computation.
1414 boolean_t enc_rx_scale_l4_hash_supported;
1415 boolean_t enc_rx_scale_additional_modes_supported;
1416 #endif /* EFSYS_OPT_RX_SCALE */
1417 #if EFSYS_OPT_LOOPBACK
1418 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1419 #endif /* EFSYS_OPT_LOOPBACK */
1420 #if EFSYS_OPT_PHY_FLAGS
1421 uint32_t enc_phy_flags_mask;
1422 #endif /* EFSYS_OPT_PHY_FLAGS */
1423 #if EFSYS_OPT_PHY_LED_CONTROL
1424 uint32_t enc_led_mask;
1425 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1426 #if EFSYS_OPT_PHY_STATS
1427 uint64_t enc_phy_stat_mask;
1428 #endif /* EFSYS_OPT_PHY_STATS */
1430 uint8_t enc_mcdi_mdio_channel;
1431 #if EFSYS_OPT_PHY_STATS
1432 uint32_t enc_mcdi_phy_stat_mask;
1433 #endif /* EFSYS_OPT_PHY_STATS */
1434 #if EFSYS_OPT_MON_STATS
1435 uint32_t *enc_mcdi_sensor_maskp;
1436 uint32_t enc_mcdi_sensor_mask_size;
1437 #endif /* EFSYS_OPT_MON_STATS */
1438 #endif /* EFSYS_OPT_MCDI */
1440 uint32_t enc_bist_mask;
1441 #endif /* EFSYS_OPT_BIST */
1442 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1445 uint32_t enc_privilege_mask;
1446 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1447 boolean_t enc_evq_init_done_ev_supported;
1448 boolean_t enc_bug26807_workaround;
1449 boolean_t enc_bug35388_workaround;
1450 boolean_t enc_bug41750_workaround;
1451 boolean_t enc_bug61265_workaround;
1452 boolean_t enc_bug61297_workaround;
1453 boolean_t enc_rx_batching_enabled;
1454 /* Maximum number of descriptors completed in an rx event. */
1455 uint32_t enc_rx_batch_max;
1456 /* Number of rx descriptors the hardware requires for a push. */
1457 uint32_t enc_rx_push_align;
1458 /* Maximum amount of data in DMA descriptor */
1459 uint32_t enc_tx_dma_desc_size_max;
1461 * Boundary which DMA descriptor data must not cross or 0 if no
1464 uint32_t enc_tx_dma_desc_boundary;
1466 * Maximum number of bytes into the packet the TCP header can start for
1467 * the hardware to apply TSO packet edits.
1469 uint32_t enc_tx_tso_tcp_header_offset_limit;
1470 /* Maximum number of header DMA descriptors per TSO transaction. */
1471 uint32_t enc_tx_tso_max_header_ndescs;
1472 /* Maximum header length acceptable by TSO transaction. */
1473 uint32_t enc_tx_tso_max_header_length;
1474 /* Maximum number of payload DMA descriptors per TSO transaction. */
1475 uint32_t enc_tx_tso_max_payload_ndescs;
1476 /* Maximum payload length per TSO transaction. */
1477 uint32_t enc_tx_tso_max_payload_length;
1478 /* Maximum number of frames to be generated per TSO transaction. */
1479 uint32_t enc_tx_tso_max_nframes;
1480 boolean_t enc_fw_assisted_tso_enabled;
1481 boolean_t enc_fw_assisted_tso_v2_enabled;
1482 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1483 boolean_t enc_tso_v3_enabled;
1484 /* Number of TSO contexts on the NIC (FATSOv2) */
1485 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1486 boolean_t enc_hw_tx_insert_vlan_enabled;
1487 /* Number of PFs on the NIC */
1488 uint32_t enc_hw_pf_count;
1489 /* Datapath firmware vadapter/vport/vswitch support */
1490 boolean_t enc_datapath_cap_evb;
1491 /* Datapath firmware vport reconfigure support */
1492 boolean_t enc_vport_reconfigure_supported;
1493 boolean_t enc_rx_disable_scatter_supported;
1494 boolean_t enc_allow_set_mac_with_installed_filters;
1495 boolean_t enc_enhanced_set_mac_supported;
1496 boolean_t enc_init_evq_v2_supported;
1497 boolean_t enc_no_cont_ev_mode_supported;
1498 boolean_t enc_init_rxq_with_buffer_size;
1499 boolean_t enc_rx_packed_stream_supported;
1500 boolean_t enc_rx_var_packed_stream_supported;
1501 boolean_t enc_rx_es_super_buffer_supported;
1502 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1503 boolean_t enc_pm_and_rxdp_counters;
1504 boolean_t enc_mac_stats_40g_tx_size_bins;
1505 uint32_t enc_tunnel_encapsulations_supported;
1507 * NIC global maximum for unique UDP tunnel ports shared by all
1510 uint32_t enc_tunnel_config_udp_entries_max;
1511 /* External port identifier */
1512 uint8_t enc_external_port;
1513 uint32_t enc_mcdi_max_payload_length;
1514 /* VPD may be per-PF or global */
1515 boolean_t enc_vpd_is_global;
1516 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1517 uint32_t enc_required_pcie_bandwidth_mbps;
1518 uint32_t enc_max_pcie_link_gen;
1519 /* Firmware verifies integrity of NVRAM updates */
1520 boolean_t enc_nvram_update_verify_result_supported;
1521 /* Firmware supports polled NVRAM updates on select partitions */
1522 boolean_t enc_nvram_update_poll_verify_result_supported;
1523 /* Firmware accepts updates via the BUNDLE partition */
1524 boolean_t enc_nvram_bundle_update_supported;
1525 /* Firmware support for extended MAC_STATS buffer */
1526 uint32_t enc_mac_stats_nstats;
1527 boolean_t enc_fec_counters;
1528 boolean_t enc_hlb_counters;
1529 /* Firmware support for "FLAG" and "MARK" filter actions */
1530 boolean_t enc_filter_action_flag_supported;
1531 boolean_t enc_filter_action_mark_supported;
1532 uint32_t enc_filter_action_mark_max;
1533 /* Port assigned to this PCI function */
1534 uint32_t enc_assigned_port;
1537 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1538 ((configp)->evc_function == 0xffff)
1540 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1541 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1543 #define EFX_PCI_FUNCTION(_encp) \
1544 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1546 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1549 extern const efx_nic_cfg_t *
1551 __in const efx_nic_t *enp);
1553 /* RxDPCPU firmware id values by which FW variant can be identified */
1554 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1555 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1556 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1557 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1558 #define EFX_RXDP_DPDK_FW_ID 0x6
1560 typedef struct efx_nic_fw_info_s {
1561 /* Basic FW version information */
1562 uint16_t enfi_mc_fw_version[4];
1564 * If datapath capabilities can be detected,
1565 * additional FW information is to be shown
1567 boolean_t enfi_dpcpu_fw_ids_valid;
1568 /* Rx and Tx datapath CPU FW IDs */
1569 uint16_t enfi_rx_dpcpu_fw_id;
1570 uint16_t enfi_tx_dpcpu_fw_id;
1571 } efx_nic_fw_info_t;
1574 extern __checkReturn efx_rc_t
1575 efx_nic_get_fw_version(
1576 __in efx_nic_t *enp,
1577 __out efx_nic_fw_info_t *enfip);
1579 /* Driver resource limits (minimum required/maximum usable). */
1580 typedef struct efx_drv_limits_s {
1581 uint32_t edl_min_evq_count;
1582 uint32_t edl_max_evq_count;
1584 uint32_t edl_min_rxq_count;
1585 uint32_t edl_max_rxq_count;
1587 uint32_t edl_min_txq_count;
1588 uint32_t edl_max_txq_count;
1590 /* PIO blocks (sub-allocated from piobuf) */
1591 uint32_t edl_min_pio_alloc_size;
1592 uint32_t edl_max_pio_alloc_count;
1596 extern __checkReturn efx_rc_t
1597 efx_nic_set_drv_limits(
1598 __inout efx_nic_t *enp,
1599 __in efx_drv_limits_t *edlp);
1602 * Register the OS driver version string for management agents
1603 * (e.g. via NC-SI). The content length is provided (i.e. no
1604 * NUL terminator). Use length 0 to indicate no version string
1605 * should be advertised. It is valid to set the version string
1606 * only before efx_nic_probe() is called.
1609 extern __checkReturn efx_rc_t
1610 efx_nic_set_drv_version(
1611 __inout efx_nic_t *enp,
1612 __in_ecount(length) char const *verp,
1613 __in size_t length);
1615 typedef enum efx_nic_region_e {
1616 EFX_REGION_VI, /* Memory BAR UC mapping */
1617 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1621 extern __checkReturn efx_rc_t
1622 efx_nic_get_bar_region(
1623 __in efx_nic_t *enp,
1624 __in efx_nic_region_t region,
1625 __out uint32_t *offsetp,
1626 __out size_t *sizep);
1629 extern __checkReturn efx_rc_t
1630 efx_nic_get_vi_pool(
1631 __in efx_nic_t *enp,
1632 __out uint32_t *evq_countp,
1633 __out uint32_t *rxq_countp,
1634 __out uint32_t *txq_countp);
1639 typedef enum efx_vpd_tag_e {
1646 typedef uint16_t efx_vpd_keyword_t;
1648 typedef struct efx_vpd_value_s {
1649 efx_vpd_tag_t evv_tag;
1650 efx_vpd_keyword_t evv_keyword;
1652 uint8_t evv_value[0x100];
1656 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1659 extern __checkReturn efx_rc_t
1661 __in efx_nic_t *enp);
1664 extern __checkReturn efx_rc_t
1666 __in efx_nic_t *enp,
1667 __out size_t *sizep);
1670 extern __checkReturn efx_rc_t
1672 __in efx_nic_t *enp,
1673 __out_bcount(size) caddr_t data,
1677 extern __checkReturn efx_rc_t
1679 __in efx_nic_t *enp,
1680 __in_bcount(size) caddr_t data,
1684 extern __checkReturn efx_rc_t
1686 __in efx_nic_t *enp,
1687 __in_bcount(size) caddr_t data,
1691 extern __checkReturn efx_rc_t
1693 __in efx_nic_t *enp,
1694 __in_bcount(size) caddr_t data,
1696 __inout efx_vpd_value_t *evvp);
1699 extern __checkReturn efx_rc_t
1701 __in efx_nic_t *enp,
1702 __inout_bcount(size) caddr_t data,
1704 __in efx_vpd_value_t *evvp);
1707 extern __checkReturn efx_rc_t
1709 __in efx_nic_t *enp,
1710 __inout_bcount(size) caddr_t data,
1712 __out efx_vpd_value_t *evvp,
1713 __inout unsigned int *contp);
1716 extern __checkReturn efx_rc_t
1718 __in efx_nic_t *enp,
1719 __in_bcount(size) caddr_t data,
1725 __in efx_nic_t *enp);
1727 #endif /* EFSYS_OPT_VPD */
1733 typedef enum efx_nvram_type_e {
1734 EFX_NVRAM_INVALID = 0,
1736 EFX_NVRAM_BOOTROM_CFG,
1737 EFX_NVRAM_MC_FIRMWARE,
1738 EFX_NVRAM_MC_GOLDEN,
1744 EFX_NVRAM_FPGA_BACKUP,
1745 EFX_NVRAM_DYNAMIC_CFG,
1748 EFX_NVRAM_MUM_FIRMWARE,
1749 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1750 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1752 EFX_NVRAM_BUNDLE_METADATA,
1756 typedef struct efx_nvram_info_s {
1758 uint32_t eni_partn_size;
1759 uint32_t eni_address;
1760 uint32_t eni_erase_size;
1761 uint32_t eni_write_size;
1764 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1767 extern __checkReturn efx_rc_t
1769 __in efx_nic_t *enp);
1774 extern __checkReturn efx_rc_t
1776 __in efx_nic_t *enp);
1778 #endif /* EFSYS_OPT_DIAG */
1781 extern __checkReturn efx_rc_t
1783 __in efx_nic_t *enp,
1784 __in efx_nvram_type_t type,
1785 __out size_t *sizep);
1788 extern __checkReturn efx_rc_t
1790 __in efx_nic_t *enp,
1791 __in efx_nvram_type_t type,
1792 __out efx_nvram_info_t *enip);
1795 extern __checkReturn efx_rc_t
1797 __in efx_nic_t *enp,
1798 __in efx_nvram_type_t type,
1799 __out_opt size_t *pref_chunkp);
1802 extern __checkReturn efx_rc_t
1803 efx_nvram_rw_finish(
1804 __in efx_nic_t *enp,
1805 __in efx_nvram_type_t type,
1806 __out_opt uint32_t *verify_resultp);
1809 extern __checkReturn efx_rc_t
1810 efx_nvram_get_version(
1811 __in efx_nic_t *enp,
1812 __in efx_nvram_type_t type,
1813 __out uint32_t *subtypep,
1814 __out_ecount(4) uint16_t version[4]);
1817 extern __checkReturn efx_rc_t
1818 efx_nvram_read_chunk(
1819 __in efx_nic_t *enp,
1820 __in efx_nvram_type_t type,
1821 __in unsigned int offset,
1822 __out_bcount(size) caddr_t data,
1826 extern __checkReturn efx_rc_t
1827 efx_nvram_read_backup(
1828 __in efx_nic_t *enp,
1829 __in efx_nvram_type_t type,
1830 __in unsigned int offset,
1831 __out_bcount(size) caddr_t data,
1835 extern __checkReturn efx_rc_t
1836 efx_nvram_set_version(
1837 __in efx_nic_t *enp,
1838 __in efx_nvram_type_t type,
1839 __in_ecount(4) uint16_t version[4]);
1842 extern __checkReturn efx_rc_t
1844 __in efx_nic_t *enp,
1845 __in efx_nvram_type_t type,
1846 __in_bcount(partn_size) caddr_t partn_data,
1847 __in size_t partn_size);
1850 extern __checkReturn efx_rc_t
1852 __in efx_nic_t *enp,
1853 __in efx_nvram_type_t type);
1856 extern __checkReturn efx_rc_t
1857 efx_nvram_write_chunk(
1858 __in efx_nic_t *enp,
1859 __in efx_nvram_type_t type,
1860 __in unsigned int offset,
1861 __in_bcount(size) caddr_t data,
1867 __in efx_nic_t *enp);
1869 #endif /* EFSYS_OPT_NVRAM */
1871 #if EFSYS_OPT_BOOTCFG
1873 /* Report size and offset of bootcfg sector in NVRAM partition. */
1875 extern __checkReturn efx_rc_t
1876 efx_bootcfg_sector_info(
1877 __in efx_nic_t *enp,
1879 __out_opt uint32_t *sector_countp,
1880 __out size_t *offsetp,
1881 __out size_t *max_sizep);
1884 * Copy bootcfg sector data to a target buffer which may differ in size.
1885 * Optionally corrects format errors in source buffer.
1889 efx_bootcfg_copy_sector(
1890 __in efx_nic_t *enp,
1891 __inout_bcount(sector_length)
1893 __in size_t sector_length,
1894 __out_bcount(data_size) uint8_t *data,
1895 __in size_t data_size,
1896 __in boolean_t handle_format_errors);
1901 __in efx_nic_t *enp,
1902 __out_bcount(size) uint8_t *data,
1908 __in efx_nic_t *enp,
1909 __in_bcount(size) uint8_t *data,
1914 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1915 * (see https://tools.ietf.org/html/rfc1533)
1917 * Summarising the format: the buffer is a sequence of options. All options
1918 * begin with a tag octet, which uniquely identifies the option. Fixed-
1919 * length options without data consist of only a tag octet. Only options PAD
1920 * (0) and END (255) are fixed length. All other options are variable-length
1921 * with a length octet following the tag octet. The value of the length
1922 * octet does not include the two octets specifying the tag and length. The
1923 * length octet is followed by "length" octets of data.
1925 * Option data may be a sequence of sub-options in the same format. The data
1926 * content of the encapsulating option is one or more encapsulated sub-options,
1927 * with no terminating END tag is required.
1929 * To be valid, the top-level sequence of options should be terminated by an
1930 * END tag. The buffer should be padded with the PAD byte.
1932 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1933 * checksum octet. The full buffer (including after the END tag) contributes
1934 * to the checksum, hence the need to fill the buffer to the end with PAD.
1937 #define EFX_DHCP_END ((uint8_t)0xff)
1938 #define EFX_DHCP_PAD ((uint8_t)0)
1940 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1941 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1944 extern __checkReturn uint8_t
1946 __in_bcount(size) uint8_t const *data,
1950 extern __checkReturn efx_rc_t
1952 __in_bcount(size) uint8_t const *data,
1954 __out_opt size_t *usedp);
1957 extern __checkReturn efx_rc_t
1959 __in_bcount(buffer_length) uint8_t *bufferp,
1960 __in size_t buffer_length,
1962 __deref_out uint8_t **valuepp,
1963 __out size_t *value_lengthp);
1966 extern __checkReturn efx_rc_t
1968 __in_bcount(buffer_length) uint8_t *bufferp,
1969 __in size_t buffer_length,
1970 __deref_out uint8_t **endpp);
1974 extern __checkReturn efx_rc_t
1975 efx_dhcp_delete_tag(
1976 __inout_bcount(buffer_length) uint8_t *bufferp,
1977 __in size_t buffer_length,
1981 extern __checkReturn efx_rc_t
1983 __inout_bcount(buffer_length) uint8_t *bufferp,
1984 __in size_t buffer_length,
1986 __in_bcount_opt(value_length) uint8_t *valuep,
1987 __in size_t value_length);
1990 extern __checkReturn efx_rc_t
1991 efx_dhcp_update_tag(
1992 __inout_bcount(buffer_length) uint8_t *bufferp,
1993 __in size_t buffer_length,
1995 __in uint8_t *value_locationp,
1996 __in_bcount_opt(value_length) uint8_t *valuep,
1997 __in size_t value_length);
2000 #endif /* EFSYS_OPT_BOOTCFG */
2002 #if EFSYS_OPT_IMAGE_LAYOUT
2004 #include "ef10_signed_image_layout.h"
2007 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2010 * The image header format is extensible. However, older drivers require an
2011 * exact match of image header version and header length when validating and
2012 * writing firmware images.
2014 * To avoid breaking backward compatibility, we use the upper bits of the
2015 * controller version fields to contain an extra version number used for
2016 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2017 * version). See bug39254 and SF-102785-PS for details.
2019 typedef struct efx_image_header_s {
2021 uint32_t eih_version;
2023 uint32_t eih_subtype;
2024 uint32_t eih_code_size;
2027 uint32_t eih_controller_version_min;
2029 uint16_t eih_controller_version_min_short;
2030 uint8_t eih_extra_version_a;
2031 uint8_t eih_extra_version_b;
2035 uint32_t eih_controller_version_max;
2037 uint16_t eih_controller_version_max_short;
2038 uint8_t eih_extra_version_c;
2039 uint8_t eih_extra_version_d;
2042 uint16_t eih_code_version_a;
2043 uint16_t eih_code_version_b;
2044 uint16_t eih_code_version_c;
2045 uint16_t eih_code_version_d;
2046 } efx_image_header_t;
2048 #define EFX_IMAGE_HEADER_SIZE (40)
2049 #define EFX_IMAGE_HEADER_VERSION (4)
2050 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2053 typedef struct efx_image_trailer_s {
2055 } efx_image_trailer_t;
2057 #define EFX_IMAGE_TRAILER_SIZE (4)
2059 typedef enum efx_image_format_e {
2060 EFX_IMAGE_FORMAT_NO_IMAGE,
2061 EFX_IMAGE_FORMAT_INVALID,
2062 EFX_IMAGE_FORMAT_UNSIGNED,
2063 EFX_IMAGE_FORMAT_SIGNED,
2064 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2065 } efx_image_format_t;
2067 typedef struct efx_image_info_s {
2068 efx_image_format_t eii_format;
2069 uint8_t * eii_imagep;
2070 size_t eii_image_size;
2071 efx_image_header_t * eii_headerp;
2075 extern __checkReturn efx_rc_t
2076 efx_check_reflash_image(
2078 __in uint32_t buffer_size,
2079 __out efx_image_info_t *infop);
2082 extern __checkReturn efx_rc_t
2083 efx_build_signed_image_write_buffer(
2084 __out_bcount(buffer_size)
2086 __in uint32_t buffer_size,
2087 __in efx_image_info_t *infop,
2088 __out efx_image_header_t **headerpp);
2090 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2094 typedef enum efx_pattern_type_t {
2095 EFX_PATTERN_BYTE_INCREMENT = 0,
2096 EFX_PATTERN_ALL_THE_SAME,
2097 EFX_PATTERN_BIT_ALTERNATE,
2098 EFX_PATTERN_BYTE_ALTERNATE,
2099 EFX_PATTERN_BYTE_CHANGING,
2100 EFX_PATTERN_BIT_SWEEP,
2102 } efx_pattern_type_t;
2105 (*efx_sram_pattern_fn_t)(
2107 __in boolean_t negate,
2108 __out efx_qword_t *eqp);
2111 extern __checkReturn efx_rc_t
2113 __in efx_nic_t *enp,
2114 __in efx_pattern_type_t type);
2116 #endif /* EFSYS_OPT_DIAG */
2119 extern __checkReturn efx_rc_t
2120 efx_sram_buf_tbl_set(
2121 __in efx_nic_t *enp,
2123 __in efsys_mem_t *esmp,
2128 efx_sram_buf_tbl_clear(
2129 __in efx_nic_t *enp,
2133 #define EFX_BUF_TBL_SIZE 0x20000
2135 #define EFX_BUF_SIZE 4096
2139 typedef struct efx_evq_s efx_evq_t;
2141 #if EFSYS_OPT_QSTATS
2143 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2144 typedef enum efx_ev_qstat_e {
2150 EV_RX_PAUSE_FRM_ERR,
2151 EV_RX_BUF_OWNER_ID_ERR,
2152 EV_RX_IPV4_HDR_CHKSUM_ERR,
2153 EV_RX_TCP_UDP_CHKSUM_ERR,
2157 EV_RX_MCAST_HASH_MATCH,
2174 EV_DRIVER_SRM_UPD_DONE,
2175 EV_DRIVER_TX_DESCQ_FLS_DONE,
2176 EV_DRIVER_RX_DESCQ_FLS_DONE,
2177 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2178 EV_DRIVER_RX_DSC_ERROR,
2179 EV_DRIVER_TX_DSC_ERROR,
2182 EV_RX_PARSE_INCOMPLETE,
2186 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2188 #endif /* EFSYS_OPT_QSTATS */
2191 extern __checkReturn efx_rc_t
2193 __in efx_nic_t *enp);
2198 __in efx_nic_t *enp);
2201 extern __checkReturn size_t
2203 __in const efx_nic_t *enp,
2204 __in unsigned int ndescs);
2207 extern __checkReturn unsigned int
2209 __in const efx_nic_t *enp,
2210 __in unsigned int ndescs);
2212 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2213 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2214 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2215 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2217 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2218 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2219 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2222 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2223 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2226 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2227 * which is the case when an event queue is set to THROUGHPUT mode.
2229 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2232 extern __checkReturn efx_rc_t
2234 __in efx_nic_t *enp,
2235 __in unsigned int index,
2236 __in efsys_mem_t *esmp,
2240 __in uint32_t flags,
2241 __deref_out efx_evq_t **eepp);
2246 __in efx_evq_t *eep,
2247 __in uint16_t data);
2249 typedef __checkReturn boolean_t
2250 (*efx_initialized_ev_t)(
2251 __in_opt void *arg);
2253 #define EFX_PKT_UNICAST 0x0004
2254 #define EFX_PKT_START 0x0008
2256 #define EFX_PKT_VLAN_TAGGED 0x0010
2257 #define EFX_CKSUM_TCPUDP 0x0020
2258 #define EFX_CKSUM_IPV4 0x0040
2259 #define EFX_PKT_CONT 0x0080
2261 #define EFX_CHECK_VLAN 0x0100
2262 #define EFX_PKT_TCP 0x0200
2263 #define EFX_PKT_UDP 0x0400
2264 #define EFX_PKT_IPV4 0x0800
2266 #define EFX_PKT_IPV6 0x1000
2267 #define EFX_PKT_PREFIX_LEN 0x2000
2268 #define EFX_ADDR_MISMATCH 0x4000
2269 #define EFX_DISCARD 0x8000
2272 * The following flags are used only for packed stream
2273 * mode. The values for the flags are reused to fit into 16 bit,
2274 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2275 * packed stream mode
2277 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2278 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2281 #define EFX_EV_RX_NLABELS 32
2282 #define EFX_EV_TX_NLABELS 32
2284 typedef __checkReturn boolean_t
2287 __in uint32_t label,
2290 __in uint16_t flags);
2292 typedef __checkReturn boolean_t
2293 (*efx_rx_packets_ev_t)(
2295 __in uint32_t label,
2296 __in unsigned int num_packets,
2297 __in uint32_t flags);
2299 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2302 * Packed stream mode is documented in SF-112241-TC.
2303 * The general idea is that, instead of putting each incoming
2304 * packet into a separate buffer which is specified in a RX
2305 * descriptor, a large buffer is provided to the hardware and
2306 * packets are put there in a continuous stream.
2307 * The main advantage of such an approach is that RX queue refilling
2308 * happens much less frequently.
2310 * Equal stride packed stream mode is documented in SF-119419-TC.
2311 * The general idea is to utilize advantages of the packed stream,
2312 * but avoid indirection in packets representation.
2313 * The main advantage of such an approach is that RX queue refilling
2314 * happens much less frequently and packets buffers are independent
2315 * from upper layers point of view.
2318 typedef __checkReturn boolean_t
2321 __in uint32_t label,
2323 __in uint32_t pkt_count,
2324 __in uint16_t flags);
2328 typedef __checkReturn boolean_t
2331 __in uint32_t label,
2334 typedef __checkReturn boolean_t
2335 (*efx_tx_ndescs_ev_t)(
2337 __in uint32_t label,
2338 __in unsigned int ndescs);
2340 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2341 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2342 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2343 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2344 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2345 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2346 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2347 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2348 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2350 typedef __checkReturn boolean_t
2351 (*efx_exception_ev_t)(
2353 __in uint32_t label,
2354 __in uint32_t data);
2356 typedef __checkReturn boolean_t
2357 (*efx_rxq_flush_done_ev_t)(
2359 __in uint32_t rxq_index);
2361 typedef __checkReturn boolean_t
2362 (*efx_rxq_flush_failed_ev_t)(
2364 __in uint32_t rxq_index);
2366 typedef __checkReturn boolean_t
2367 (*efx_txq_flush_done_ev_t)(
2369 __in uint32_t txq_index);
2371 typedef __checkReturn boolean_t
2372 (*efx_software_ev_t)(
2374 __in uint16_t magic);
2376 typedef __checkReturn boolean_t
2379 __in uint32_t code);
2381 #define EFX_SRAM_CLEAR 0
2382 #define EFX_SRAM_UPDATE 1
2383 #define EFX_SRAM_ILLEGAL_CLEAR 2
2385 typedef __checkReturn boolean_t
2386 (*efx_wake_up_ev_t)(
2388 __in uint32_t label);
2390 typedef __checkReturn boolean_t
2393 __in uint32_t label);
2395 typedef __checkReturn boolean_t
2396 (*efx_link_change_ev_t)(
2398 __in efx_link_mode_t link_mode);
2400 #if EFSYS_OPT_MON_STATS
2402 typedef __checkReturn boolean_t
2403 (*efx_monitor_ev_t)(
2405 __in efx_mon_stat_t id,
2406 __in efx_mon_stat_value_t value);
2408 #endif /* EFSYS_OPT_MON_STATS */
2410 #if EFSYS_OPT_MAC_STATS
2412 typedef __checkReturn boolean_t
2413 (*efx_mac_stats_ev_t)(
2415 __in uint32_t generation);
2417 #endif /* EFSYS_OPT_MAC_STATS */
2419 typedef struct efx_ev_callbacks_s {
2420 efx_initialized_ev_t eec_initialized;
2422 efx_rx_packets_ev_t eec_rx_packets;
2423 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2424 efx_rx_ps_ev_t eec_rx_ps;
2427 efx_tx_ndescs_ev_t eec_tx_ndescs;
2428 efx_exception_ev_t eec_exception;
2429 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2430 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2431 efx_txq_flush_done_ev_t eec_txq_flush_done;
2432 efx_software_ev_t eec_software;
2433 efx_sram_ev_t eec_sram;
2434 efx_wake_up_ev_t eec_wake_up;
2435 efx_timer_ev_t eec_timer;
2436 efx_link_change_ev_t eec_link_change;
2437 #if EFSYS_OPT_MON_STATS
2438 efx_monitor_ev_t eec_monitor;
2439 #endif /* EFSYS_OPT_MON_STATS */
2440 #if EFSYS_OPT_MAC_STATS
2441 efx_mac_stats_ev_t eec_mac_stats;
2442 #endif /* EFSYS_OPT_MAC_STATS */
2443 } efx_ev_callbacks_t;
2446 extern __checkReturn boolean_t
2448 __in efx_evq_t *eep,
2449 __in unsigned int count);
2451 #if EFSYS_OPT_EV_PREFETCH
2456 __in efx_evq_t *eep,
2457 __in unsigned int count);
2459 #endif /* EFSYS_OPT_EV_PREFETCH */
2463 efx_ev_qcreate_check_init_done(
2464 __in efx_evq_t *eep,
2465 __in const efx_ev_callbacks_t *eecp,
2466 __in_opt void *arg);
2471 __in efx_evq_t *eep,
2472 __inout unsigned int *countp,
2473 __in const efx_ev_callbacks_t *eecp,
2474 __in_opt void *arg);
2477 extern __checkReturn efx_rc_t
2478 efx_ev_usecs_to_ticks(
2479 __in efx_nic_t *enp,
2480 __in unsigned int usecs,
2481 __out unsigned int *ticksp);
2484 extern __checkReturn efx_rc_t
2486 __in efx_evq_t *eep,
2487 __in unsigned int us);
2490 extern __checkReturn efx_rc_t
2492 __in efx_evq_t *eep,
2493 __in unsigned int count);
2495 #if EFSYS_OPT_QSTATS
2502 __in efx_nic_t *enp,
2503 __in unsigned int id);
2505 #endif /* EFSYS_OPT_NAMES */
2509 efx_ev_qstats_update(
2510 __in efx_evq_t *eep,
2511 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2513 #endif /* EFSYS_OPT_QSTATS */
2518 __in efx_evq_t *eep);
2523 extern __checkReturn efx_rc_t
2525 __inout efx_nic_t *enp);
2530 __in efx_nic_t *enp);
2532 #if EFSYS_OPT_RX_SCATTER
2534 extern __checkReturn efx_rc_t
2535 efx_rx_scatter_enable(
2536 __in efx_nic_t *enp,
2537 __in unsigned int buf_size);
2538 #endif /* EFSYS_OPT_RX_SCATTER */
2540 /* Handle to represent use of the default RSS context. */
2541 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2543 #if EFSYS_OPT_RX_SCALE
2545 typedef enum efx_rx_hash_alg_e {
2546 EFX_RX_HASHALG_LFSR = 0,
2547 EFX_RX_HASHALG_TOEPLITZ,
2548 EFX_RX_HASHALG_PACKED_STREAM,
2550 } efx_rx_hash_alg_t;
2553 * Legacy hash type flags.
2555 * They represent standard tuples for distinct traffic classes.
2557 #define EFX_RX_HASH_IPV4 (1U << 0)
2558 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2559 #define EFX_RX_HASH_IPV6 (1U << 2)
2560 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2562 #define EFX_RX_HASH_LEGACY_MASK \
2563 (EFX_RX_HASH_IPV4 | \
2564 EFX_RX_HASH_TCPIPV4 | \
2565 EFX_RX_HASH_IPV6 | \
2566 EFX_RX_HASH_TCPIPV6)
2569 * The type of the argument used by efx_rx_scale_mode_set() to
2570 * provide a means for the client drivers to configure hashing.
2572 * A properly constructed value can either be:
2573 * - a combination of legacy flags
2574 * - a combination of EFX_RX_HASH() flags
2576 typedef uint32_t efx_rx_hash_type_t;
2578 typedef enum efx_rx_hash_support_e {
2579 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2580 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2581 } efx_rx_hash_support_t;
2583 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2584 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2585 #define EFX_MAXRSS 64 /* RX indirection entry range */
2586 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2588 typedef enum efx_rx_scale_context_type_e {
2589 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2590 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2591 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2592 } efx_rx_scale_context_type_t;
2595 * Traffic classes eligible for hash computation.
2597 * Select packet headers used in computing the receive hash.
2598 * This uses the same encoding as the RSS_MODES field of
2599 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2601 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2602 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2603 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2604 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2605 #define EFX_RX_CLASS_IPV4_LBN 16
2606 #define EFX_RX_CLASS_IPV4_WIDTH 4
2607 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2608 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2609 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2610 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2611 #define EFX_RX_CLASS_IPV6_LBN 28
2612 #define EFX_RX_CLASS_IPV6_WIDTH 4
2614 #define EFX_RX_NCLASSES 6
2617 * Ancillary flags used to construct generic hash tuples.
2618 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2620 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2621 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2622 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2623 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2626 * Generic hash tuples.
2628 * They express combinations of packet fields
2629 * which can contribute to the hash value for
2630 * a particular traffic class.
2632 #define EFX_RX_CLASS_HASH_DISABLE 0
2634 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2635 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2637 #define EFX_RX_CLASS_HASH_2TUPLE \
2638 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2639 EFX_RX_CLASS_HASH_DST_ADDR)
2641 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2642 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2643 EFX_RX_CLASS_HASH_SRC_PORT)
2645 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2646 (EFX_RX_CLASS_HASH_DST_ADDR | \
2647 EFX_RX_CLASS_HASH_DST_PORT)
2649 #define EFX_RX_CLASS_HASH_4TUPLE \
2650 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2651 EFX_RX_CLASS_HASH_DST_ADDR | \
2652 EFX_RX_CLASS_HASH_SRC_PORT | \
2653 EFX_RX_CLASS_HASH_DST_PORT)
2655 #define EFX_RX_CLASS_HASH_NTUPLES 7
2658 * Hash flag constructor.
2660 * Resulting flags encode hash tuples for specific traffic classes.
2661 * The client drivers are encouraged to use these flags to form
2662 * a hash type value.
2664 #define EFX_RX_HASH(_class, _tuple) \
2665 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2666 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2669 * The maximum number of EFX_RX_HASH() flags.
2671 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2674 extern __checkReturn efx_rc_t
2675 efx_rx_scale_hash_flags_get(
2676 __in efx_nic_t *enp,
2677 __in efx_rx_hash_alg_t hash_alg,
2678 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2679 __in unsigned int max_nflags,
2680 __out unsigned int *nflagsp);
2683 extern __checkReturn efx_rc_t
2684 efx_rx_hash_default_support_get(
2685 __in efx_nic_t *enp,
2686 __out efx_rx_hash_support_t *supportp);
2690 extern __checkReturn efx_rc_t
2691 efx_rx_scale_default_support_get(
2692 __in efx_nic_t *enp,
2693 __out efx_rx_scale_context_type_t *typep);
2696 extern __checkReturn efx_rc_t
2697 efx_rx_scale_context_alloc(
2698 __in efx_nic_t *enp,
2699 __in efx_rx_scale_context_type_t type,
2700 __in uint32_t num_queues,
2701 __out uint32_t *rss_contextp);
2704 extern __checkReturn efx_rc_t
2705 efx_rx_scale_context_free(
2706 __in efx_nic_t *enp,
2707 __in uint32_t rss_context);
2710 extern __checkReturn efx_rc_t
2711 efx_rx_scale_mode_set(
2712 __in efx_nic_t *enp,
2713 __in uint32_t rss_context,
2714 __in efx_rx_hash_alg_t alg,
2715 __in efx_rx_hash_type_t type,
2716 __in boolean_t insert);
2719 extern __checkReturn efx_rc_t
2720 efx_rx_scale_tbl_set(
2721 __in efx_nic_t *enp,
2722 __in uint32_t rss_context,
2723 __in_ecount(n) unsigned int *table,
2727 extern __checkReturn efx_rc_t
2728 efx_rx_scale_key_set(
2729 __in efx_nic_t *enp,
2730 __in uint32_t rss_context,
2731 __in_ecount(n) uint8_t *key,
2735 extern __checkReturn uint32_t
2736 efx_pseudo_hdr_hash_get(
2737 __in efx_rxq_t *erp,
2738 __in efx_rx_hash_alg_t func,
2739 __in uint8_t *buffer);
2741 #endif /* EFSYS_OPT_RX_SCALE */
2744 extern __checkReturn efx_rc_t
2745 efx_pseudo_hdr_pkt_length_get(
2746 __in efx_rxq_t *erp,
2747 __in uint8_t *buffer,
2748 __out uint16_t *pkt_lengthp);
2751 extern __checkReturn size_t
2753 __in const efx_nic_t *enp,
2754 __in unsigned int ndescs);
2757 extern __checkReturn unsigned int
2759 __in const efx_nic_t *enp,
2760 __in unsigned int ndescs);
2762 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2765 * libefx representation of the Rx prefix layout information.
2767 * The information may be used inside libefx to implement Rx prefix fields
2768 * accessors and by drivers which process Rx prefix itself.
2772 * All known Rx prefix fields.
2774 * An Rx prefix may have a subset of these fields.
2776 typedef enum efx_rx_prefix_field_e {
2777 EFX_RX_PREFIX_FIELD_LENGTH = 0,
2778 EFX_RX_PREFIX_FIELD_ORIG_LENGTH,
2779 EFX_RX_PREFIX_FIELD_CLASS,
2780 EFX_RX_PREFIX_FIELD_RSS_HASH,
2781 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID,
2782 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP,
2783 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI,
2784 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI,
2785 EFX_RX_PREFIX_FIELD_USER_FLAG,
2786 EFX_RX_PREFIX_FIELD_USER_MARK,
2787 EFX_RX_PREFIX_FIELD_USER_MARK_VALID,
2788 EFX_RX_PREFIX_FIELD_CSUM_FRAME,
2789 EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2790 EFX_RX_PREFIX_NFIELDS
2791 } efx_rx_prefix_field_t;
2794 * Location and endianness of a field in Rx prefix.
2796 * If width is zero, the field is not present.
2798 typedef struct efx_rx_prefix_field_info_s {
2799 uint16_t erpfi_offset_bits;
2800 uint8_t erpfi_width_bits;
2801 boolean_t erpfi_big_endian;
2802 } efx_rx_prefix_field_info_t;
2804 /* Helper macro to define Rx prefix fields */
2805 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \
2806 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \
2807 .erpfi_offset_bits = EFX_LOW_BIT(_field), \
2808 .erpfi_width_bits = EFX_WIDTH(_field), \
2809 .erpfi_big_endian = (_big_endian), \
2812 typedef struct efx_rx_prefix_layout_s {
2814 uint8_t erpl_length;
2815 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS];
2816 } efx_rx_prefix_layout_t;
2819 extern __checkReturn efx_rc_t
2820 efx_rx_prefix_get_layout(
2821 __in const efx_rxq_t *erp,
2822 __out efx_rx_prefix_layout_t *erplp);
2824 typedef enum efx_rxq_type_e {
2825 EFX_RXQ_TYPE_DEFAULT,
2826 EFX_RXQ_TYPE_PACKED_STREAM,
2827 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2832 * Dummy flag to be used instead of 0 to make it clear that the argument
2833 * is receive queue flags.
2835 #define EFX_RXQ_FLAG_NONE 0x0
2836 #define EFX_RXQ_FLAG_SCATTER 0x1
2838 * If tunnels are supported and Rx event can provide information about
2839 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2840 * full-feature firmware variant running), outer classes are requested by
2841 * default. However, if the driver supports tunnels, the flag allows to
2842 * request inner classes which are required to be able to interpret inner
2843 * Rx checksum offload results.
2845 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2848 extern __checkReturn efx_rc_t
2850 __in efx_nic_t *enp,
2851 __in unsigned int index,
2852 __in unsigned int label,
2853 __in efx_rxq_type_t type,
2854 __in size_t buf_size,
2855 __in efsys_mem_t *esmp,
2858 __in unsigned int flags,
2859 __in efx_evq_t *eep,
2860 __deref_out efx_rxq_t **erpp);
2862 #if EFSYS_OPT_RX_PACKED_STREAM
2864 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2865 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2866 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2867 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2868 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2871 extern __checkReturn efx_rc_t
2872 efx_rx_qcreate_packed_stream(
2873 __in efx_nic_t *enp,
2874 __in unsigned int index,
2875 __in unsigned int label,
2876 __in uint32_t ps_buf_size,
2877 __in efsys_mem_t *esmp,
2879 __in efx_evq_t *eep,
2880 __deref_out efx_rxq_t **erpp);
2884 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2886 /* Maximum head-of-line block timeout in nanoseconds */
2887 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2890 extern __checkReturn efx_rc_t
2891 efx_rx_qcreate_es_super_buffer(
2892 __in efx_nic_t *enp,
2893 __in unsigned int index,
2894 __in unsigned int label,
2895 __in uint32_t n_bufs_per_desc,
2896 __in uint32_t max_dma_len,
2897 __in uint32_t buf_stride,
2898 __in uint32_t hol_block_timeout,
2899 __in efsys_mem_t *esmp,
2901 __in unsigned int flags,
2902 __in efx_evq_t *eep,
2903 __deref_out efx_rxq_t **erpp);
2907 typedef struct efx_buffer_s {
2908 efsys_dma_addr_t eb_addr;
2913 typedef struct efx_desc_s {
2920 __in efx_rxq_t *erp,
2921 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2923 __in unsigned int ndescs,
2924 __in unsigned int completed,
2925 __in unsigned int added);
2930 __in efx_rxq_t *erp,
2931 __in unsigned int added,
2932 __inout unsigned int *pushedp);
2934 #if EFSYS_OPT_RX_PACKED_STREAM
2938 efx_rx_qpush_ps_credits(
2939 __in efx_rxq_t *erp);
2942 extern __checkReturn uint8_t *
2943 efx_rx_qps_packet_info(
2944 __in efx_rxq_t *erp,
2945 __in uint8_t *buffer,
2946 __in uint32_t buffer_length,
2947 __in uint32_t current_offset,
2948 __out uint16_t *lengthp,
2949 __out uint32_t *next_offsetp,
2950 __out uint32_t *timestamp);
2954 extern __checkReturn efx_rc_t
2956 __in efx_rxq_t *erp);
2961 __in efx_rxq_t *erp);
2966 __in efx_rxq_t *erp);
2970 typedef struct efx_txq_s efx_txq_t;
2972 #if EFSYS_OPT_QSTATS
2974 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2975 typedef enum efx_tx_qstat_e {
2981 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2983 #endif /* EFSYS_OPT_QSTATS */
2986 extern __checkReturn efx_rc_t
2988 __in efx_nic_t *enp);
2993 __in efx_nic_t *enp);
2996 extern __checkReturn size_t
2998 __in const efx_nic_t *enp,
2999 __in unsigned int ndescs);
3002 extern __checkReturn unsigned int
3004 __in const efx_nic_t *enp,
3005 __in unsigned int ndescs);
3007 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
3009 #define EFX_TXQ_CKSUM_IPV4 0x0001
3010 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
3011 #define EFX_TXQ_FATSOV2 0x0004
3012 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
3013 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
3016 extern __checkReturn efx_rc_t
3018 __in efx_nic_t *enp,
3019 __in unsigned int index,
3020 __in unsigned int label,
3021 __in efsys_mem_t *esmp,
3024 __in uint16_t flags,
3025 __in efx_evq_t *eep,
3026 __deref_out efx_txq_t **etpp,
3027 __out unsigned int *addedp);
3030 extern __checkReturn efx_rc_t
3032 __in efx_txq_t *etp,
3033 __in_ecount(ndescs) efx_buffer_t *eb,
3034 __in unsigned int ndescs,
3035 __in unsigned int completed,
3036 __inout unsigned int *addedp);
3039 extern __checkReturn efx_rc_t
3041 __in efx_txq_t *etp,
3042 __in unsigned int ns);
3047 __in efx_txq_t *etp,
3048 __in unsigned int added,
3049 __in unsigned int pushed);
3052 extern __checkReturn efx_rc_t
3054 __in efx_txq_t *etp);
3059 __in efx_txq_t *etp);
3062 extern __checkReturn efx_rc_t
3064 __in efx_txq_t *etp);
3068 efx_tx_qpio_disable(
3069 __in efx_txq_t *etp);
3072 extern __checkReturn efx_rc_t
3074 __in efx_txq_t *etp,
3075 __in_ecount(buf_length) uint8_t *buffer,
3076 __in size_t buf_length,
3077 __in size_t pio_buf_offset);
3080 extern __checkReturn efx_rc_t
3082 __in efx_txq_t *etp,
3083 __in size_t pkt_length,
3084 __in unsigned int completed,
3085 __inout unsigned int *addedp);
3088 extern __checkReturn efx_rc_t
3090 __in efx_txq_t *etp,
3091 __in_ecount(n) efx_desc_t *ed,
3092 __in unsigned int n,
3093 __in unsigned int completed,
3094 __inout unsigned int *addedp);
3098 efx_tx_qdesc_dma_create(
3099 __in efx_txq_t *etp,
3100 __in efsys_dma_addr_t addr,
3103 __out efx_desc_t *edp);
3107 efx_tx_qdesc_tso_create(
3108 __in efx_txq_t *etp,
3109 __in uint16_t ipv4_id,
3110 __in uint32_t tcp_seq,
3111 __in uint8_t tcp_flags,
3112 __out efx_desc_t *edp);
3114 /* Number of FATSOv2 option descriptors */
3115 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3117 /* Maximum number of DMA segments per TSO packet (not superframe) */
3118 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3122 efx_tx_qdesc_tso2_create(
3123 __in efx_txq_t *etp,
3124 __in uint16_t ipv4_id,
3125 __in uint16_t outer_ipv4_id,
3126 __in uint32_t tcp_seq,
3127 __in uint16_t tcp_mss,
3128 __out_ecount(count) efx_desc_t *edp,
3133 efx_tx_qdesc_vlantci_create(
3134 __in efx_txq_t *etp,
3136 __out efx_desc_t *edp);
3140 efx_tx_qdesc_checksum_create(
3141 __in efx_txq_t *etp,
3142 __in uint16_t flags,
3143 __out efx_desc_t *edp);
3145 #if EFSYS_OPT_QSTATS
3152 __in efx_nic_t *etp,
3153 __in unsigned int id);
3155 #endif /* EFSYS_OPT_NAMES */
3159 efx_tx_qstats_update(
3160 __in efx_txq_t *etp,
3161 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3163 #endif /* EFSYS_OPT_QSTATS */
3168 __in efx_txq_t *etp);
3173 #if EFSYS_OPT_FILTER
3175 #define EFX_ETHER_TYPE_IPV4 0x0800
3176 #define EFX_ETHER_TYPE_IPV6 0x86DD
3178 #define EFX_IPPROTO_TCP 6
3179 #define EFX_IPPROTO_UDP 17
3180 #define EFX_IPPROTO_GRE 47
3182 /* Use RSS to spread across multiple queues */
3183 #define EFX_FILTER_FLAG_RX_RSS 0x01
3184 /* Enable RX scatter */
3185 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3187 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3188 * May only be set by the filter implementation for each type.
3189 * A removal request will restore the automatic filter in its place.
3191 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3192 /* Filter is for RX */
3193 #define EFX_FILTER_FLAG_RX 0x08
3194 /* Filter is for TX */
3195 #define EFX_FILTER_FLAG_TX 0x10
3196 /* Set match flag on the received packet */
3197 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3198 /* Set match mark on the received packet */
3199 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3201 typedef uint8_t efx_filter_flags_t;
3204 * Flags which specify the fields to match on. The values are the same as in the
3205 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3208 /* Match by remote IP host address */
3209 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3210 /* Match by local IP host address */
3211 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3212 /* Match by remote MAC address */
3213 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3214 /* Match by remote TCP/UDP port */
3215 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3216 /* Match by remote TCP/UDP port */
3217 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3218 /* Match by local TCP/UDP port */
3219 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3220 /* Match by Ether-type */
3221 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3222 /* Match by inner VLAN ID */
3223 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3224 /* Match by outer VLAN ID */
3225 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3226 /* Match by IP transport protocol */
3227 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3228 /* Match by VNI or VSID */
3229 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3230 /* For encapsulated packets, match by inner frame local MAC address */
3231 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3232 /* For encapsulated packets, match all multicast inner frames */
3233 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3234 /* For encapsulated packets, match all unicast inner frames */
3235 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3237 * Match by encap type, this flag does not correspond to
3238 * the MCDI match flags and any unoccupied value may be used
3240 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3241 /* Match otherwise-unmatched multicast and broadcast packets */
3242 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3243 /* Match otherwise-unmatched unicast packets */
3244 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3246 typedef uint32_t efx_filter_match_flags_t;
3248 /* Filter priority from lowest to highest */
3249 typedef enum efx_filter_priority_s {
3250 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3251 * address list or hardware
3252 * requirements. This may only be used
3253 * by the filter implementation for
3255 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3257 } efx_filter_priority_t;
3260 * FIXME: All these fields are assumed to be in little-endian byte order.
3261 * It may be better for some to be big-endian. See bug42804.
3264 typedef struct efx_filter_spec_s {
3265 efx_filter_match_flags_t efs_match_flags;
3266 uint8_t efs_priority;
3267 efx_filter_flags_t efs_flags;
3268 uint16_t efs_dmaq_id;
3269 uint32_t efs_rss_context;
3272 * Saved lower-priority filter. If it is set, it is restored on
3273 * filter delete operation.
3275 struct efx_filter_spec_s *efs_overridden_spec;
3276 /* Fields below here are hashed for software filter lookup */
3277 uint16_t efs_outer_vid;
3278 uint16_t efs_inner_vid;
3279 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3280 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3281 uint16_t efs_ether_type;
3282 uint8_t efs_ip_proto;
3283 efx_tunnel_protocol_t efs_encap_type;
3284 uint16_t efs_loc_port;
3285 uint16_t efs_rem_port;
3286 efx_oword_t efs_rem_host;
3287 efx_oword_t efs_loc_host;
3288 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3289 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3290 } efx_filter_spec_t;
3293 /* Default values for use in filter specifications */
3294 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3295 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3298 extern __checkReturn efx_rc_t
3300 __in efx_nic_t *enp);
3305 __in efx_nic_t *enp);
3308 extern __checkReturn efx_rc_t
3310 __in efx_nic_t *enp,
3311 __inout efx_filter_spec_t *spec);
3314 extern __checkReturn efx_rc_t
3316 __in efx_nic_t *enp,
3317 __inout efx_filter_spec_t *spec);
3320 extern __checkReturn efx_rc_t
3322 __in efx_nic_t *enp);
3325 extern __checkReturn efx_rc_t
3326 efx_filter_supported_filters(
3327 __in efx_nic_t *enp,
3328 __out_ecount(buffer_length) uint32_t *buffer,
3329 __in size_t buffer_length,
3330 __out size_t *list_lengthp);
3334 efx_filter_spec_init_rx(
3335 __out efx_filter_spec_t *spec,
3336 __in efx_filter_priority_t priority,
3337 __in efx_filter_flags_t flags,
3338 __in efx_rxq_t *erp);
3342 efx_filter_spec_init_tx(
3343 __out efx_filter_spec_t *spec,
3344 __in efx_txq_t *etp);
3347 extern __checkReturn efx_rc_t
3348 efx_filter_spec_set_ipv4_local(
3349 __inout efx_filter_spec_t *spec,
3352 __in uint16_t port);
3355 extern __checkReturn efx_rc_t
3356 efx_filter_spec_set_ipv4_full(
3357 __inout efx_filter_spec_t *spec,
3359 __in uint32_t lhost,
3360 __in uint16_t lport,
3361 __in uint32_t rhost,
3362 __in uint16_t rport);
3365 extern __checkReturn efx_rc_t
3366 efx_filter_spec_set_eth_local(
3367 __inout efx_filter_spec_t *spec,
3369 __in const uint8_t *addr);
3373 efx_filter_spec_set_ether_type(
3374 __inout efx_filter_spec_t *spec,
3375 __in uint16_t ether_type);
3378 extern __checkReturn efx_rc_t
3379 efx_filter_spec_set_uc_def(
3380 __inout efx_filter_spec_t *spec);
3383 extern __checkReturn efx_rc_t
3384 efx_filter_spec_set_mc_def(
3385 __inout efx_filter_spec_t *spec);
3387 typedef enum efx_filter_inner_frame_match_e {
3388 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3389 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3390 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3391 } efx_filter_inner_frame_match_t;
3394 extern __checkReturn efx_rc_t
3395 efx_filter_spec_set_encap_type(
3396 __inout efx_filter_spec_t *spec,
3397 __in efx_tunnel_protocol_t encap_type,
3398 __in efx_filter_inner_frame_match_t inner_frame_match);
3401 extern __checkReturn efx_rc_t
3402 efx_filter_spec_set_vxlan(
3403 __inout efx_filter_spec_t *spec,
3404 __in const uint8_t *vni,
3405 __in const uint8_t *inner_addr,
3406 __in const uint8_t *outer_addr);
3409 extern __checkReturn efx_rc_t
3410 efx_filter_spec_set_geneve(
3411 __inout efx_filter_spec_t *spec,
3412 __in const uint8_t *vni,
3413 __in const uint8_t *inner_addr,
3414 __in const uint8_t *outer_addr);
3417 extern __checkReturn efx_rc_t
3418 efx_filter_spec_set_nvgre(
3419 __inout efx_filter_spec_t *spec,
3420 __in const uint8_t *vsid,
3421 __in const uint8_t *inner_addr,
3422 __in const uint8_t *outer_addr);
3424 #if EFSYS_OPT_RX_SCALE
3426 extern __checkReturn efx_rc_t
3427 efx_filter_spec_set_rss_context(
3428 __inout efx_filter_spec_t *spec,
3429 __in uint32_t rss_context);
3431 #endif /* EFSYS_OPT_FILTER */
3436 extern __checkReturn uint32_t
3438 __in_ecount(count) uint32_t const *input,
3440 __in uint32_t init);
3443 extern __checkReturn uint32_t
3445 __in_ecount(length) uint8_t const *input,
3447 __in uint32_t init);
3449 #if EFSYS_OPT_LICENSING
3453 typedef struct efx_key_stats_s {
3455 uint32_t eks_invalid;
3456 uint32_t eks_blacklisted;
3457 uint32_t eks_unverifiable;
3458 uint32_t eks_wrong_node;
3459 uint32_t eks_licensed_apps_lo;
3460 uint32_t eks_licensed_apps_hi;
3461 uint32_t eks_licensed_features_lo;
3462 uint32_t eks_licensed_features_hi;
3466 extern __checkReturn efx_rc_t
3468 __in efx_nic_t *enp);
3473 __in efx_nic_t *enp);
3476 extern __checkReturn boolean_t
3477 efx_lic_check_support(
3478 __in efx_nic_t *enp);
3481 extern __checkReturn efx_rc_t
3482 efx_lic_update_licenses(
3483 __in efx_nic_t *enp);
3486 extern __checkReturn efx_rc_t
3487 efx_lic_get_key_stats(
3488 __in efx_nic_t *enp,
3489 __out efx_key_stats_t *ksp);
3492 extern __checkReturn efx_rc_t
3494 __in efx_nic_t *enp,
3495 __in uint64_t app_id,
3496 __out boolean_t *licensedp);
3499 extern __checkReturn efx_rc_t
3501 __in efx_nic_t *enp,
3502 __in size_t buffer_size,
3503 __out uint32_t *typep,
3504 __out size_t *lengthp,
3505 __out_opt uint8_t *bufferp);
3509 extern __checkReturn efx_rc_t
3511 __in efx_nic_t *enp,
3512 __in_bcount(buffer_size)
3514 __in size_t buffer_size,
3515 __out uint32_t *startp);
3518 extern __checkReturn efx_rc_t
3520 __in efx_nic_t *enp,
3521 __in_bcount(buffer_size)
3523 __in size_t buffer_size,
3524 __in uint32_t offset,
3525 __out uint32_t *endp);
3528 extern __checkReturn __success(return != B_FALSE) boolean_t
3530 __in efx_nic_t *enp,
3531 __in_bcount(buffer_size)
3533 __in size_t buffer_size,
3534 __in uint32_t offset,
3535 __out uint32_t *startp,
3536 __out uint32_t *lengthp);
3539 extern __checkReturn __success(return != B_FALSE) boolean_t
3540 efx_lic_validate_key(
3541 __in efx_nic_t *enp,
3542 __in_bcount(length) caddr_t keyp,
3543 __in uint32_t length);
3546 extern __checkReturn efx_rc_t
3548 __in efx_nic_t *enp,
3549 __in_bcount(buffer_size)
3551 __in size_t buffer_size,
3552 __in uint32_t offset,
3553 __in uint32_t length,
3554 __out_bcount_part(key_max_size, *lengthp)
3556 __in size_t key_max_size,
3557 __out uint32_t *lengthp);
3560 extern __checkReturn efx_rc_t
3562 __in efx_nic_t *enp,
3563 __in_bcount(buffer_size)
3565 __in size_t buffer_size,
3566 __in uint32_t offset,
3567 __in_bcount(length) caddr_t keyp,
3568 __in uint32_t length,
3569 __out uint32_t *lengthp);
3572 extern __checkReturn efx_rc_t
3574 __in efx_nic_t *enp,
3575 __in_bcount(buffer_size)
3577 __in size_t buffer_size,
3578 __in uint32_t offset,
3579 __in uint32_t length,
3581 __out uint32_t *deltap);
3584 extern __checkReturn efx_rc_t
3585 efx_lic_create_partition(
3586 __in efx_nic_t *enp,
3587 __in_bcount(buffer_size)
3589 __in size_t buffer_size);
3591 extern __checkReturn efx_rc_t
3592 efx_lic_finish_partition(
3593 __in efx_nic_t *enp,
3594 __in_bcount(buffer_size)
3596 __in size_t buffer_size);
3598 #endif /* EFSYS_OPT_LICENSING */
3602 #if EFSYS_OPT_TUNNEL
3605 extern __checkReturn efx_rc_t
3607 __in efx_nic_t *enp);
3612 __in efx_nic_t *enp);
3615 * For overlay network encapsulation using UDP, the firmware needs to know
3616 * the configured UDP port for the overlay so it can decode encapsulated
3618 * The UDP port/protocol list is global.
3622 extern __checkReturn efx_rc_t
3623 efx_tunnel_config_udp_add(
3624 __in efx_nic_t *enp,
3625 __in uint16_t port /* host/cpu-endian */,
3626 __in efx_tunnel_protocol_t protocol);
3629 extern __checkReturn efx_rc_t
3630 efx_tunnel_config_udp_remove(
3631 __in efx_nic_t *enp,
3632 __in uint16_t port /* host/cpu-endian */,
3633 __in efx_tunnel_protocol_t protocol);
3637 efx_tunnel_config_clear(
3638 __in efx_nic_t *enp);
3641 * Apply tunnel UDP ports configuration to hardware.
3643 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3647 extern __checkReturn efx_rc_t
3648 efx_tunnel_reconfigure(
3649 __in efx_nic_t *enp);
3651 #endif /* EFSYS_OPT_TUNNEL */
3653 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3656 * Firmware subvariant choice options.
3658 * It may be switched to no Tx checksum if attached drivers are either
3659 * preboot or firmware subvariant aware and no VIS are allocated.
3660 * If may be always switched to default explicitly using set request or
3661 * implicitly if unaware driver is attaching. If switching is done when
3662 * a driver is attached, it gets MC_REBOOT event and should recreate its
3665 * See SF-119419-TC DPDK Firmware Driver Interface and
3666 * SF-109306-TC EF10 for Driver Writers for details.
3668 typedef enum efx_nic_fw_subvariant_e {
3669 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3670 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3671 EFX_NIC_FW_SUBVARIANT_NTYPES
3672 } efx_nic_fw_subvariant_t;
3675 extern __checkReturn efx_rc_t
3676 efx_nic_get_fw_subvariant(
3677 __in efx_nic_t *enp,
3678 __out efx_nic_fw_subvariant_t *subvariantp);
3681 extern __checkReturn efx_rc_t
3682 efx_nic_set_fw_subvariant(
3683 __in efx_nic_t *enp,
3684 __in efx_nic_fw_subvariant_t subvariant);
3686 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3688 typedef enum efx_phy_fec_type_e {
3689 EFX_PHY_FEC_NONE = 0,
3692 } efx_phy_fec_type_t;
3695 extern __checkReturn efx_rc_t
3696 efx_phy_fec_type_get(
3697 __in efx_nic_t *enp,
3698 __out efx_phy_fec_type_t *typep);
3700 typedef struct efx_phy_link_state_s {
3701 uint32_t epls_adv_cap_mask;
3702 uint32_t epls_lp_cap_mask;
3703 uint32_t epls_ld_cap_mask;
3704 unsigned int epls_fcntl;
3705 efx_phy_fec_type_t epls_fec;
3706 efx_link_mode_t epls_link_mode;
3707 } efx_phy_link_state_t;
3710 extern __checkReturn efx_rc_t
3711 efx_phy_link_state_get(
3712 __in efx_nic_t *enp,
3713 __out efx_phy_link_state_t *eplsp);
3718 typedef uint32_t efx_vswitch_id_t;
3719 typedef uint32_t efx_vport_id_t;
3721 typedef enum efx_vswitch_type_e {
3722 EFX_VSWITCH_TYPE_VLAN = 1,
3723 EFX_VSWITCH_TYPE_VEB,
3724 /* VSWITCH_TYPE_VEPA: obsolete */
3725 EFX_VSWITCH_TYPE_MUX = 4,
3726 } efx_vswitch_type_t;
3728 typedef enum efx_vport_type_e {
3729 EFX_VPORT_TYPE_NORMAL = 4,
3730 EFX_VPORT_TYPE_EXPANSION,
3731 EFX_VPORT_TYPE_TEST,
3734 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3735 #define EFX_FILTER_VID_UNSPEC 0xffff
3736 #define EFX_DEFAULT_VSWITCH_ID 1
3738 /* Default VF VLAN ID on creation */
3739 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3740 #define EFX_VPORT_ID_INVALID 0
3742 typedef struct efx_vport_config_s {
3743 /* Either VF index or 0xffff for PF */
3744 uint16_t evc_function;
3745 /* VLAN ID of the associated function */
3747 /* vport id shared with client driver */
3748 efx_vport_id_t evc_vport_id;
3749 /* MAC address of the associated function */
3750 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3752 * vports created with this flag set may only transfer traffic on the
3753 * VLANs permitted by the vport. Also, an attempt to install filter with
3754 * VLAN will be refused unless requesting function has VLAN privilege.
3756 boolean_t evc_vlan_restrict;
3757 /* Whether this function is assigned or not */
3758 boolean_t evc_vport_assigned;
3759 } efx_vport_config_t;
3761 typedef struct efx_vswitch_s efx_vswitch_t;
3764 extern __checkReturn efx_rc_t
3766 __in efx_nic_t *enp);
3771 __in efx_nic_t *enp);
3774 extern __checkReturn efx_rc_t
3775 efx_evb_vswitch_create(
3776 __in efx_nic_t *enp,
3777 __in uint32_t num_vports,
3778 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3779 __deref_out efx_vswitch_t **evpp);
3782 extern __checkReturn efx_rc_t
3783 efx_evb_vswitch_destroy(
3784 __in efx_nic_t *enp,
3785 __in efx_vswitch_t *evp);
3788 extern __checkReturn efx_rc_t
3789 efx_evb_vport_mac_set(
3790 __in efx_nic_t *enp,
3791 __in efx_vswitch_t *evp,
3792 __in efx_vport_id_t vport_id,
3793 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3796 extern __checkReturn efx_rc_t
3797 efx_evb_vport_vlan_set(
3798 __in efx_nic_t *enp,
3799 __in efx_vswitch_t *evp,
3800 __in efx_vport_id_t vport_id,
3804 extern __checkReturn efx_rc_t
3805 efx_evb_vport_reset(
3806 __in efx_nic_t *enp,
3807 __in efx_vswitch_t *evp,
3808 __in efx_vport_id_t vport_id,
3809 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3811 __out boolean_t *is_fn_resetp);
3814 extern __checkReturn efx_rc_t
3815 efx_evb_vport_stats(
3816 __in efx_nic_t *enp,
3817 __in efx_vswitch_t *evp,
3818 __in efx_vport_id_t vport_id,
3819 __out efsys_mem_t *stats_bufferp);
3821 #endif /* EFSYS_OPT_EVB */
3823 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3825 typedef struct efx_proxy_auth_config_s {
3826 efsys_mem_t *request_bufferp;
3827 efsys_mem_t *response_bufferp;
3828 efsys_mem_t *status_bufferp;
3832 uint32_t handled_privileges;
3833 } efx_proxy_auth_config_t;
3835 typedef struct efx_proxy_cmd_params_s {
3838 uint8_t *request_bufferp;
3839 size_t request_size;
3840 uint8_t *response_bufferp;
3841 size_t response_size;
3842 size_t *response_size_actualp;
3843 } efx_proxy_cmd_params_t;
3846 extern __checkReturn efx_rc_t
3847 efx_proxy_auth_init(
3848 __in efx_nic_t *enp);
3852 efx_proxy_auth_fini(
3853 __in efx_nic_t *enp);
3856 extern __checkReturn efx_rc_t
3857 efx_proxy_auth_configure(
3858 __in efx_nic_t *enp,
3859 __in efx_proxy_auth_config_t *configp);
3862 extern __checkReturn efx_rc_t
3863 efx_proxy_auth_destroy(
3864 __in efx_nic_t *enp,
3865 __in uint32_t handled_privileges);
3868 extern __checkReturn efx_rc_t
3869 efx_proxy_auth_complete_request(
3870 __in efx_nic_t *enp,
3871 __in uint32_t fn_index,
3872 __in uint32_t proxy_result,
3873 __in uint32_t handle);
3876 extern __checkReturn efx_rc_t
3877 efx_proxy_auth_exec_cmd(
3878 __in efx_nic_t *enp,
3879 __inout efx_proxy_cmd_params_t *paramsp);
3882 extern __checkReturn efx_rc_t
3883 efx_proxy_auth_set_privilege_mask(
3884 __in efx_nic_t *enp,
3885 __in uint32_t vf_index,
3887 __in uint32_t value);
3890 extern __checkReturn efx_rc_t
3891 efx_proxy_auth_privilege_mask_get(
3892 __in efx_nic_t *enp,
3893 __in uint32_t pf_index,
3894 __in uint32_t vf_index,
3895 __out uint32_t *maskp);
3898 extern __checkReturn efx_rc_t
3899 efx_proxy_auth_privilege_modify(
3900 __in efx_nic_t *enp,
3901 __in uint32_t pf_index,
3902 __in uint32_t vf_index,
3903 __in uint32_t add_privileges_mask,
3904 __in uint32_t remove_privileges_mask);
3906 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3912 #endif /* _SYS_EFX_H */