1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
62 typedef enum efx_bar_type_e {
67 typedef struct efx_bar_region_s {
68 efx_bar_type_t ebr_type;
70 efsys_dma_addr_t ebr_offset;
71 efsys_dma_addr_t ebr_length;
74 /* The function is deprecated. It is used only if Riverhead is not supported. */
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
85 /* PCIe interface numbers for multi-host configurations. */
86 typedef enum efx_pcie_interface_e {
87 EFX_PCIE_INTERFACE_CALLER = 1000,
88 EFX_PCIE_INTERFACE_HOST_PRIMARY,
89 EFX_PCIE_INTERFACE_NIC_EMBEDDED,
90 } efx_pcie_interface_t;
92 typedef struct efx_pci_ops_s {
94 * Function for reading PCIe configuration space.
96 * espcp System-specific PCIe device handle;
97 * offset Offset inside PCIe configuration space to start reading
99 * edp EFX DWORD structure that should be populated by function
100 * in little-endian order;
102 * Returns status code, 0 on success, any other value on error.
104 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp,
105 uint32_t offset, efx_dword_t *edp);
107 * Function for finding PCIe memory bar handle by its index from a PCIe
108 * device handle. The found memory bar is available in read-only mode.
110 * configp System-specific PCIe device handle;
111 * index Memory bar index;
112 * memp Pointer to the found memory bar handle;
114 * Returns status code, 0 on success, any other value on error.
116 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp,
117 int index, efsys_bar_t *memp);
120 /* Determine EFX family and perform lookup of the function control window
122 * The function requires PCI config handle from which all memory bars can
124 * A user of the API must be aware of memory bars indexes (not available
128 extern __checkReturn efx_rc_t
129 efx_family_probe_bar(
132 __in efsys_pci_config_t *espcp,
133 __in const efx_pci_ops_t *epop,
134 __out efx_family_t *efp,
135 __out efx_bar_region_t *ebrp);
137 #endif /* EFSYS_OPT_PCI */
140 #define EFX_PCI_VENID_SFC 0x1924
141 #define EFX_PCI_VENID_XILINX 0x10EE
143 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
145 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
146 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
147 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
149 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
150 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
151 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
153 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
154 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
156 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
157 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
158 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
160 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
161 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
162 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
164 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
165 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
167 #define EFX_MEM_BAR_SIENA 2
169 #define EFX_MEM_BAR_HUNTINGTON_PF 2
170 #define EFX_MEM_BAR_HUNTINGTON_VF 0
172 #define EFX_MEM_BAR_MEDFORD_PF 2
173 #define EFX_MEM_BAR_MEDFORD_VF 0
175 #define EFX_MEM_BAR_MEDFORD2 0
177 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
178 #define EFX_MEM_BAR_RIVERHEAD 2
186 EFX_ERR_BUFID_DC_OOB,
199 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
201 extern __checkReturn uint32_t
203 __in uint32_t crc_init,
204 __in_ecount(length) uint8_t const *input,
208 /* Type prototypes */
210 typedef struct efx_rxq_s efx_rxq_t;
214 typedef struct efx_nic_s efx_nic_t;
217 extern __checkReturn efx_rc_t
219 __in efx_family_t family,
220 __in efsys_identifier_t *esip,
221 __in efsys_bar_t *esbp,
222 __in uint32_t fcw_offset,
223 __in efsys_lock_t *eslp,
224 __deref_out efx_nic_t **enpp);
226 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
227 typedef enum efx_fw_variant_e {
228 EFX_FW_VARIANT_FULL_FEATURED,
229 EFX_FW_VARIANT_LOW_LATENCY,
230 EFX_FW_VARIANT_PACKED_STREAM,
231 EFX_FW_VARIANT_HIGH_TX_RATE,
232 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
233 EFX_FW_VARIANT_RULES_ENGINE,
235 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
239 extern __checkReturn efx_rc_t
242 __in efx_fw_variant_t efv);
245 extern __checkReturn efx_rc_t
247 __in efx_nic_t *enp);
250 extern __checkReturn efx_rc_t
252 __in efx_nic_t *enp);
255 extern __checkReturn boolean_t
256 efx_nic_hw_unavailable(
257 __in efx_nic_t *enp);
261 efx_nic_set_hw_unavailable(
262 __in efx_nic_t *enp);
267 extern __checkReturn efx_rc_t
268 efx_nic_register_test(
269 __in efx_nic_t *enp);
271 #endif /* EFSYS_OPT_DIAG */
276 __in efx_nic_t *enp);
281 __in efx_nic_t *enp);
286 __in efx_nic_t *enp);
288 #define EFX_PCIE_LINK_SPEED_GEN1 1
289 #define EFX_PCIE_LINK_SPEED_GEN2 2
290 #define EFX_PCIE_LINK_SPEED_GEN3 3
292 typedef enum efx_pcie_link_performance_e {
293 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
294 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
295 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
296 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
297 } efx_pcie_link_performance_t;
300 extern __checkReturn efx_rc_t
301 efx_nic_calculate_pcie_link_bandwidth(
302 __in uint32_t pcie_link_width,
303 __in uint32_t pcie_link_gen,
304 __out uint32_t *bandwidth_mbpsp);
307 extern __checkReturn efx_rc_t
308 efx_nic_check_pcie_link_speed(
310 __in uint32_t pcie_link_width,
311 __in uint32_t pcie_link_gen,
312 __out efx_pcie_link_performance_t *resultp);
316 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
317 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
318 #define WITH_MCDI_V2 1
321 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
323 typedef enum efx_mcdi_exception_e {
324 EFX_MCDI_EXCEPTION_MC_REBOOT,
325 EFX_MCDI_EXCEPTION_MC_BADASSERT,
326 } efx_mcdi_exception_t;
328 #if EFSYS_OPT_MCDI_LOGGING
329 typedef enum efx_log_msg_e {
331 EFX_LOG_MCDI_REQUEST,
332 EFX_LOG_MCDI_RESPONSE,
334 #endif /* EFSYS_OPT_MCDI_LOGGING */
336 typedef struct efx_mcdi_transport_s {
338 efsys_mem_t *emt_dma_mem;
339 void (*emt_execute)(void *, efx_mcdi_req_t *);
340 void (*emt_ev_cpl)(void *);
341 void (*emt_exception)(void *, efx_mcdi_exception_t);
342 #if EFSYS_OPT_MCDI_LOGGING
343 void (*emt_logger)(void *, efx_log_msg_t,
344 void *, size_t, void *, size_t);
345 #endif /* EFSYS_OPT_MCDI_LOGGING */
346 #if EFSYS_OPT_MCDI_PROXY_AUTH
347 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
348 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
349 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
350 void (*emt_ev_proxy_request)(void *, uint32_t);
351 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
352 } efx_mcdi_transport_t;
355 extern __checkReturn efx_rc_t
358 __in const efx_mcdi_transport_t *mtp);
361 extern __checkReturn efx_rc_t
363 __in efx_nic_t *enp);
368 __in efx_nic_t *enp);
372 efx_mcdi_get_timeout(
374 __in efx_mcdi_req_t *emrp,
375 __out uint32_t *usec_timeoutp);
379 efx_mcdi_request_start(
381 __in efx_mcdi_req_t *emrp,
382 __in boolean_t ev_cpl);
385 extern __checkReturn boolean_t
386 efx_mcdi_request_poll(
387 __in efx_nic_t *enp);
390 extern __checkReturn boolean_t
391 efx_mcdi_request_abort(
392 __in efx_nic_t *enp);
395 extern __checkReturn efx_rc_t
396 efx_mcdi_get_client_handle(
398 __in efx_pcie_interface_t intf,
401 __out uint32_t *handle);
404 extern __checkReturn efx_rc_t
405 efx_mcdi_get_own_client_handle(
407 __out uint32_t *handle);
412 __in efx_nic_t *enp);
414 #endif /* EFSYS_OPT_MCDI */
418 #define EFX_NINTR_SIENA 1024
420 typedef enum efx_intr_type_e {
421 EFX_INTR_INVALID = 0,
427 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
430 extern __checkReturn efx_rc_t
433 __in efx_intr_type_t type,
434 __in_opt efsys_mem_t *esmp);
439 __in efx_nic_t *enp);
444 __in efx_nic_t *enp);
448 efx_intr_disable_unlocked(
449 __in efx_nic_t *enp);
451 #define EFX_INTR_NEVQS 32
454 extern __checkReturn efx_rc_t
457 __in unsigned int level);
461 efx_intr_status_line(
463 __out boolean_t *fatalp,
464 __out uint32_t *maskp);
468 efx_intr_status_message(
470 __in unsigned int message,
471 __out boolean_t *fatalp);
476 __in efx_nic_t *enp);
481 __in efx_nic_t *enp);
485 #if EFSYS_OPT_MAC_STATS
487 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
488 typedef enum efx_mac_stat_e {
491 EFX_MAC_RX_UNICST_PKTS,
492 EFX_MAC_RX_MULTICST_PKTS,
493 EFX_MAC_RX_BRDCST_PKTS,
494 EFX_MAC_RX_PAUSE_PKTS,
495 EFX_MAC_RX_LE_64_PKTS,
496 EFX_MAC_RX_65_TO_127_PKTS,
497 EFX_MAC_RX_128_TO_255_PKTS,
498 EFX_MAC_RX_256_TO_511_PKTS,
499 EFX_MAC_RX_512_TO_1023_PKTS,
500 EFX_MAC_RX_1024_TO_15XX_PKTS,
501 EFX_MAC_RX_GE_15XX_PKTS,
503 EFX_MAC_RX_FCS_ERRORS,
504 EFX_MAC_RX_DROP_EVENTS,
505 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
506 EFX_MAC_RX_SYMBOL_ERRORS,
507 EFX_MAC_RX_ALIGN_ERRORS,
508 EFX_MAC_RX_INTERNAL_ERRORS,
509 EFX_MAC_RX_JABBER_PKTS,
510 EFX_MAC_RX_LANE0_CHAR_ERR,
511 EFX_MAC_RX_LANE1_CHAR_ERR,
512 EFX_MAC_RX_LANE2_CHAR_ERR,
513 EFX_MAC_RX_LANE3_CHAR_ERR,
514 EFX_MAC_RX_LANE0_DISP_ERR,
515 EFX_MAC_RX_LANE1_DISP_ERR,
516 EFX_MAC_RX_LANE2_DISP_ERR,
517 EFX_MAC_RX_LANE3_DISP_ERR,
518 EFX_MAC_RX_MATCH_FAULT,
519 EFX_MAC_RX_NODESC_DROP_CNT,
522 EFX_MAC_TX_UNICST_PKTS,
523 EFX_MAC_TX_MULTICST_PKTS,
524 EFX_MAC_TX_BRDCST_PKTS,
525 EFX_MAC_TX_PAUSE_PKTS,
526 EFX_MAC_TX_LE_64_PKTS,
527 EFX_MAC_TX_65_TO_127_PKTS,
528 EFX_MAC_TX_128_TO_255_PKTS,
529 EFX_MAC_TX_256_TO_511_PKTS,
530 EFX_MAC_TX_512_TO_1023_PKTS,
531 EFX_MAC_TX_1024_TO_15XX_PKTS,
532 EFX_MAC_TX_GE_15XX_PKTS,
534 EFX_MAC_TX_SGL_COL_PKTS,
535 EFX_MAC_TX_MULT_COL_PKTS,
536 EFX_MAC_TX_EX_COL_PKTS,
537 EFX_MAC_TX_LATE_COL_PKTS,
539 EFX_MAC_TX_EX_DEF_PKTS,
540 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
541 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
542 EFX_MAC_PM_TRUNC_VFIFO_FULL,
543 EFX_MAC_PM_DISCARD_VFIFO_FULL,
544 EFX_MAC_PM_TRUNC_QBB,
545 EFX_MAC_PM_DISCARD_QBB,
546 EFX_MAC_PM_DISCARD_MAPPING,
547 EFX_MAC_RXDP_Q_DISABLED_PKTS,
548 EFX_MAC_RXDP_DI_DROPPED_PKTS,
549 EFX_MAC_RXDP_STREAMING_PKTS,
550 EFX_MAC_RXDP_HLB_FETCH,
551 EFX_MAC_RXDP_HLB_WAIT,
552 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
553 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
554 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
555 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
556 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
557 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
558 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
559 EFX_MAC_VADAPTER_RX_BAD_BYTES,
560 EFX_MAC_VADAPTER_RX_OVERFLOW,
561 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
562 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
563 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
564 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
565 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
566 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
567 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
568 EFX_MAC_VADAPTER_TX_BAD_BYTES,
569 EFX_MAC_VADAPTER_TX_OVERFLOW,
570 EFX_MAC_FEC_UNCORRECTED_ERRORS,
571 EFX_MAC_FEC_CORRECTED_ERRORS,
572 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
573 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
574 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
575 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
576 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
577 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
578 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
579 EFX_MAC_CTPIO_OVERFLOW_FAIL,
580 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
581 EFX_MAC_CTPIO_TIMEOUT_FAIL,
582 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
583 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
584 EFX_MAC_CTPIO_INVALID_WR_FAIL,
585 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
586 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
587 EFX_MAC_CTPIO_RUNT_FALLBACK,
588 EFX_MAC_CTPIO_SUCCESS,
589 EFX_MAC_CTPIO_FALLBACK,
590 EFX_MAC_CTPIO_POISON,
592 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
593 EFX_MAC_RXDP_HLB_IDLE,
594 EFX_MAC_RXDP_HLB_TIMEOUT,
598 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
600 #endif /* EFSYS_OPT_MAC_STATS */
602 typedef enum efx_link_mode_e {
603 EFX_LINK_UNKNOWN = 0,
619 #define EFX_MAC_ADDR_LEN 6
621 #define EFX_VNI_OR_VSID_LEN 3
623 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
625 #define EFX_MAC_MULTICAST_LIST_MAX 256
627 #define EFX_MAC_SDU_MAX 9202
629 #define EFX_MAC_PDU_ADJUSTMENT \
633 + /* bug16011 */ 16) \
635 #define EFX_MAC_PDU(_sdu) \
636 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
639 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
640 * the SDU rounded up slightly.
642 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
644 #define EFX_MAC_PDU_MIN 60
645 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
648 extern __checkReturn efx_rc_t
654 extern __checkReturn efx_rc_t
660 extern __checkReturn efx_rc_t
666 extern __checkReturn efx_rc_t
669 __in boolean_t all_unicst,
670 __in boolean_t mulcst,
671 __in boolean_t all_mulcst,
672 __in boolean_t brdcst);
676 efx_mac_filter_get_all_ucast_mcast(
678 __out boolean_t *all_unicst,
679 __out boolean_t *all_mulcst);
682 extern __checkReturn efx_rc_t
683 efx_mac_multicast_list_set(
685 __in_ecount(6*count) uint8_t const *addrs,
689 extern __checkReturn efx_rc_t
690 efx_mac_filter_default_rxq_set(
693 __in boolean_t using_rss);
697 efx_mac_filter_default_rxq_clear(
698 __in efx_nic_t *enp);
701 extern __checkReturn efx_rc_t
704 __in boolean_t enabled);
707 extern __checkReturn efx_rc_t
710 __out boolean_t *mac_upp);
712 #define EFX_FCNTL_RESPOND 0x00000001
713 #define EFX_FCNTL_GENERATE 0x00000002
716 extern __checkReturn efx_rc_t
719 __in unsigned int fcntl,
720 __in boolean_t autoneg);
726 __out unsigned int *fcntl_wantedp,
727 __out unsigned int *fcntl_linkp);
730 #if EFSYS_OPT_MAC_STATS
735 extern __checkReturn const char *
738 __in unsigned int id);
740 #endif /* EFSYS_OPT_NAMES */
742 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
744 #define EFX_MAC_STATS_MASK_NPAGES \
745 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
746 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
747 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
750 * Get mask of MAC statistics supported by the hardware.
752 * If mask_size is insufficient to return the mask, EINVAL error is
753 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
754 * (which is sizeof (uint32_t)) is sufficient.
757 extern __checkReturn efx_rc_t
758 efx_mac_stats_get_mask(
760 __out_bcount(mask_size) uint32_t *maskp,
761 __in size_t mask_size);
763 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
764 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
765 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
769 extern __checkReturn efx_rc_t
771 __in efx_nic_t *enp);
774 * Upload mac statistics supported by the hardware into the given buffer.
776 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
777 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
779 * The hardware will only DMA statistics that it understands (of course).
780 * Drivers should not make any assumptions about which statistics are
781 * supported, especially when the statistics are generated by firmware.
783 * Thus, drivers should zero this buffer before use, so that not-understood
784 * statistics read back as zero.
787 extern __checkReturn efx_rc_t
788 efx_mac_stats_upload(
790 __in efsys_mem_t *esmp);
793 extern __checkReturn efx_rc_t
794 efx_mac_stats_periodic(
796 __in efsys_mem_t *esmp,
797 __in uint16_t period_ms,
798 __in boolean_t events);
801 extern __checkReturn efx_rc_t
802 efx_mac_stats_update(
804 __in efsys_mem_t *esmp,
805 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
806 __inout_opt uint32_t *generationp);
808 #endif /* EFSYS_OPT_MAC_STATS */
812 typedef enum efx_mon_type_e {
825 __in efx_nic_t *enp);
827 #endif /* EFSYS_OPT_NAMES */
830 extern __checkReturn efx_rc_t
832 __in efx_nic_t *enp);
834 #if EFSYS_OPT_MON_STATS
836 #define EFX_MON_STATS_PAGE_SIZE 0x100
837 #define EFX_MON_MASK_ELEMENT_SIZE 32
839 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
840 typedef enum efx_mon_stat_e {
841 EFX_MON_STAT_CONTROLLER_TEMP,
842 EFX_MON_STAT_PHY_COMMON_TEMP,
843 EFX_MON_STAT_CONTROLLER_COOLING,
844 EFX_MON_STAT_PHY0_TEMP,
845 EFX_MON_STAT_PHY0_COOLING,
846 EFX_MON_STAT_PHY1_TEMP,
847 EFX_MON_STAT_PHY1_COOLING,
853 EFX_MON_STAT_IN_12V0,
854 EFX_MON_STAT_IN_1V2A,
855 EFX_MON_STAT_IN_VREF,
856 EFX_MON_STAT_OUT_VAOE,
857 EFX_MON_STAT_AOE_TEMP,
858 EFX_MON_STAT_PSU_AOE_TEMP,
859 EFX_MON_STAT_PSU_TEMP,
865 EFX_MON_STAT_IN_VAOE,
866 EFX_MON_STAT_OUT_IAOE,
867 EFX_MON_STAT_IN_IAOE,
868 EFX_MON_STAT_NIC_POWER,
870 EFX_MON_STAT_IN_I0V9,
871 EFX_MON_STAT_IN_I1V2,
872 EFX_MON_STAT_IN_0V9_ADC,
873 EFX_MON_STAT_CONTROLLER_2_TEMP,
874 EFX_MON_STAT_VREG_INTERNAL_TEMP,
875 EFX_MON_STAT_VREG_0V9_TEMP,
876 EFX_MON_STAT_VREG_1V2_TEMP,
877 EFX_MON_STAT_CONTROLLER_VPTAT,
878 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
879 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
880 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
881 EFX_MON_STAT_AMBIENT_TEMP,
882 EFX_MON_STAT_AIRFLOW,
883 EFX_MON_STAT_VDD08D_VSS08D_CSR,
884 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
885 EFX_MON_STAT_HOTPOINT_TEMP,
886 EFX_MON_STAT_PHY_POWER_PORT0,
887 EFX_MON_STAT_PHY_POWER_PORT1,
888 EFX_MON_STAT_MUM_VCC,
889 EFX_MON_STAT_IN_0V9_A,
890 EFX_MON_STAT_IN_I0V9_A,
891 EFX_MON_STAT_VREG_0V9_A_TEMP,
892 EFX_MON_STAT_IN_0V9_B,
893 EFX_MON_STAT_IN_I0V9_B,
894 EFX_MON_STAT_VREG_0V9_B_TEMP,
895 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
896 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
897 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
898 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
899 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
900 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
901 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
902 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
903 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
904 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
905 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
906 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
907 EFX_MON_STAT_SODIMM_VOUT,
908 EFX_MON_STAT_SODIMM_0_TEMP,
909 EFX_MON_STAT_SODIMM_1_TEMP,
910 EFX_MON_STAT_PHY0_VCC,
911 EFX_MON_STAT_PHY1_VCC,
912 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
913 EFX_MON_STAT_BOARD_FRONT_TEMP,
914 EFX_MON_STAT_BOARD_BACK_TEMP,
915 EFX_MON_STAT_IN_I1V8,
916 EFX_MON_STAT_IN_I2V5,
917 EFX_MON_STAT_IN_I3V3,
918 EFX_MON_STAT_IN_I12V0,
920 EFX_MON_STAT_IN_I1V3,
924 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
926 typedef enum efx_mon_stat_state_e {
927 EFX_MON_STAT_STATE_OK = 0,
928 EFX_MON_STAT_STATE_WARNING = 1,
929 EFX_MON_STAT_STATE_FATAL = 2,
930 EFX_MON_STAT_STATE_BROKEN = 3,
931 EFX_MON_STAT_STATE_NO_READING = 4,
932 } efx_mon_stat_state_t;
934 typedef enum efx_mon_stat_unit_e {
935 EFX_MON_STAT_UNIT_UNKNOWN = 0,
936 EFX_MON_STAT_UNIT_BOOL,
937 EFX_MON_STAT_UNIT_TEMP_C,
938 EFX_MON_STAT_UNIT_VOLTAGE_MV,
939 EFX_MON_STAT_UNIT_CURRENT_MA,
940 EFX_MON_STAT_UNIT_POWER_W,
941 EFX_MON_STAT_UNIT_RPM,
943 } efx_mon_stat_unit_t;
945 typedef struct efx_mon_stat_value_s {
947 efx_mon_stat_state_t emsv_state;
948 efx_mon_stat_unit_t emsv_unit;
949 } efx_mon_stat_value_t;
951 typedef struct efx_mon_limit_value_s {
952 uint16_t emlv_warning_min;
953 uint16_t emlv_warning_max;
954 uint16_t emlv_fatal_min;
955 uint16_t emlv_fatal_max;
956 } efx_mon_stat_limits_t;
958 typedef enum efx_mon_stat_portmask_e {
959 EFX_MON_STAT_PORTMAP_NONE = 0,
960 EFX_MON_STAT_PORTMAP_PORT0 = 1,
961 EFX_MON_STAT_PORTMAP_PORT1 = 2,
962 EFX_MON_STAT_PORTMAP_PORT2 = 3,
963 EFX_MON_STAT_PORTMAP_PORT3 = 4,
964 EFX_MON_STAT_PORTMAP_ALL = (-1),
965 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
966 } efx_mon_stat_portmask_t;
974 __in efx_mon_stat_t id);
978 efx_mon_stat_description(
980 __in efx_mon_stat_t id);
982 #endif /* EFSYS_OPT_NAMES */
985 extern __checkReturn boolean_t
986 efx_mon_mcdi_to_efx_stat(
988 __out efx_mon_stat_t *statp);
991 extern __checkReturn boolean_t
992 efx_mon_get_stat_unit(
993 __in efx_mon_stat_t stat,
994 __out efx_mon_stat_unit_t *unitp);
997 extern __checkReturn boolean_t
998 efx_mon_get_stat_portmap(
999 __in efx_mon_stat_t stat,
1000 __out efx_mon_stat_portmask_t *maskp);
1003 extern __checkReturn efx_rc_t
1004 efx_mon_stats_update(
1005 __in efx_nic_t *enp,
1006 __in efsys_mem_t *esmp,
1007 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
1010 extern __checkReturn efx_rc_t
1011 efx_mon_limits_update(
1012 __in efx_nic_t *enp,
1013 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
1015 #endif /* EFSYS_OPT_MON_STATS */
1020 __in efx_nic_t *enp);
1025 extern __checkReturn efx_rc_t
1027 __in efx_nic_t *enp);
1029 typedef enum efx_phy_led_mode_e {
1030 EFX_PHY_LED_DEFAULT = 0,
1035 } efx_phy_led_mode_t;
1037 #if EFSYS_OPT_PHY_LED_CONTROL
1040 extern __checkReturn efx_rc_t
1042 __in efx_nic_t *enp,
1043 __in efx_phy_led_mode_t mode);
1045 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1048 extern __checkReturn efx_rc_t
1050 __in efx_nic_t *enp);
1052 #if EFSYS_OPT_LOOPBACK
1054 typedef enum efx_loopback_type_e {
1055 EFX_LOOPBACK_OFF = 0,
1056 EFX_LOOPBACK_DATA = 1,
1057 EFX_LOOPBACK_GMAC = 2,
1058 EFX_LOOPBACK_XGMII = 3,
1059 EFX_LOOPBACK_XGXS = 4,
1060 EFX_LOOPBACK_XAUI = 5,
1061 EFX_LOOPBACK_GMII = 6,
1062 EFX_LOOPBACK_SGMII = 7,
1063 EFX_LOOPBACK_XGBR = 8,
1064 EFX_LOOPBACK_XFI = 9,
1065 EFX_LOOPBACK_XAUI_FAR = 10,
1066 EFX_LOOPBACK_GMII_FAR = 11,
1067 EFX_LOOPBACK_SGMII_FAR = 12,
1068 EFX_LOOPBACK_XFI_FAR = 13,
1069 EFX_LOOPBACK_GPHY = 14,
1070 EFX_LOOPBACK_PHY_XS = 15,
1071 EFX_LOOPBACK_PCS = 16,
1072 EFX_LOOPBACK_PMA_PMD = 17,
1073 EFX_LOOPBACK_XPORT = 18,
1074 EFX_LOOPBACK_XGMII_WS = 19,
1075 EFX_LOOPBACK_XAUI_WS = 20,
1076 EFX_LOOPBACK_XAUI_WS_FAR = 21,
1077 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
1078 EFX_LOOPBACK_GMII_WS = 23,
1079 EFX_LOOPBACK_XFI_WS = 24,
1080 EFX_LOOPBACK_XFI_WS_FAR = 25,
1081 EFX_LOOPBACK_PHYXS_WS = 26,
1082 EFX_LOOPBACK_PMA_INT = 27,
1083 EFX_LOOPBACK_SD_NEAR = 28,
1084 EFX_LOOPBACK_SD_FAR = 29,
1085 EFX_LOOPBACK_PMA_INT_WS = 30,
1086 EFX_LOOPBACK_SD_FEP2_WS = 31,
1087 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1088 EFX_LOOPBACK_SD_FEP_WS = 33,
1089 EFX_LOOPBACK_SD_FES_WS = 34,
1090 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1091 EFX_LOOPBACK_DATA_WS = 36,
1092 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1094 } efx_loopback_type_t;
1096 typedef enum efx_loopback_kind_e {
1097 EFX_LOOPBACK_KIND_OFF = 0,
1098 EFX_LOOPBACK_KIND_ALL,
1099 EFX_LOOPBACK_KIND_MAC,
1100 EFX_LOOPBACK_KIND_PHY,
1102 } efx_loopback_kind_t;
1107 __in efx_loopback_kind_t loopback_kind,
1108 __out efx_qword_t *maskp);
1111 extern __checkReturn efx_rc_t
1112 efx_port_loopback_set(
1113 __in efx_nic_t *enp,
1114 __in efx_link_mode_t link_mode,
1115 __in efx_loopback_type_t type);
1120 extern __checkReturn const char *
1121 efx_loopback_type_name(
1122 __in efx_nic_t *enp,
1123 __in efx_loopback_type_t type);
1125 #endif /* EFSYS_OPT_NAMES */
1127 #endif /* EFSYS_OPT_LOOPBACK */
1130 extern __checkReturn efx_rc_t
1132 __in efx_nic_t *enp,
1133 __out_opt efx_link_mode_t *link_modep);
1138 __in efx_nic_t *enp);
1140 typedef enum efx_phy_cap_type_e {
1141 EFX_PHY_CAP_INVALID = 0,
1146 EFX_PHY_CAP_1000HDX,
1147 EFX_PHY_CAP_1000FDX,
1148 EFX_PHY_CAP_10000FDX,
1152 EFX_PHY_CAP_40000FDX,
1154 EFX_PHY_CAP_100000FDX,
1155 EFX_PHY_CAP_25000FDX,
1156 EFX_PHY_CAP_50000FDX,
1157 EFX_PHY_CAP_BASER_FEC,
1158 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1160 EFX_PHY_CAP_RS_FEC_REQUESTED,
1161 EFX_PHY_CAP_25G_BASER_FEC,
1162 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1164 } efx_phy_cap_type_t;
1167 #define EFX_PHY_CAP_CURRENT 0x00000000
1168 #define EFX_PHY_CAP_DEFAULT 0x00000001
1169 #define EFX_PHY_CAP_PERM 0x00000002
1173 efx_phy_adv_cap_get(
1174 __in efx_nic_t *enp,
1176 __out uint32_t *maskp);
1179 extern __checkReturn efx_rc_t
1180 efx_phy_adv_cap_set(
1181 __in efx_nic_t *enp,
1182 __in uint32_t mask);
1187 __in efx_nic_t *enp,
1188 __out uint32_t *maskp);
1191 extern __checkReturn efx_rc_t
1193 __in efx_nic_t *enp,
1194 __out uint32_t *ouip);
1196 typedef enum efx_phy_media_type_e {
1197 EFX_PHY_MEDIA_INVALID = 0,
1202 EFX_PHY_MEDIA_SFP_PLUS,
1203 EFX_PHY_MEDIA_BASE_T,
1204 EFX_PHY_MEDIA_QSFP_PLUS,
1205 EFX_PHY_MEDIA_NTYPES
1206 } efx_phy_media_type_t;
1209 * Get the type of medium currently used. If the board has ports for
1210 * modules, a module is present, and we recognise the media type of
1211 * the module, then this will be the media type of the module.
1212 * Otherwise it will be the media type of the port.
1216 efx_phy_media_type_get(
1217 __in efx_nic_t *enp,
1218 __out efx_phy_media_type_t *typep);
1221 * 2-wire device address of the base information in accordance with SFF-8472
1222 * Diagnostic Monitoring Interface for Optical Transceivers section
1223 * 4 Memory Organization.
1225 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1228 * 2-wire device address of the digital diagnostics monitoring interface
1229 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1230 * Transceivers section 4 Memory Organization.
1232 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1235 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1236 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1239 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1242 * Maximum accessible data offset for PHY module information.
1244 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1248 extern __checkReturn efx_rc_t
1249 efx_phy_module_get_info(
1250 __in efx_nic_t *enp,
1251 __in uint8_t dev_addr,
1254 __out_bcount(len) uint8_t *data);
1256 #if EFSYS_OPT_PHY_STATS
1258 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1259 typedef enum efx_phy_stat_e {
1261 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1262 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1263 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1264 EFX_PHY_STAT_PMA_PMD_REV_A,
1265 EFX_PHY_STAT_PMA_PMD_REV_B,
1266 EFX_PHY_STAT_PMA_PMD_REV_C,
1267 EFX_PHY_STAT_PMA_PMD_REV_D,
1268 EFX_PHY_STAT_PCS_LINK_UP,
1269 EFX_PHY_STAT_PCS_RX_FAULT,
1270 EFX_PHY_STAT_PCS_TX_FAULT,
1271 EFX_PHY_STAT_PCS_BER,
1272 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1273 EFX_PHY_STAT_PHY_XS_LINK_UP,
1274 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1275 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1276 EFX_PHY_STAT_PHY_XS_ALIGN,
1277 EFX_PHY_STAT_PHY_XS_SYNC_A,
1278 EFX_PHY_STAT_PHY_XS_SYNC_B,
1279 EFX_PHY_STAT_PHY_XS_SYNC_C,
1280 EFX_PHY_STAT_PHY_XS_SYNC_D,
1281 EFX_PHY_STAT_AN_LINK_UP,
1282 EFX_PHY_STAT_AN_MASTER,
1283 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1284 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1285 EFX_PHY_STAT_CL22EXT_LINK_UP,
1290 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1291 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1292 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1293 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1294 EFX_PHY_STAT_AN_COMPLETE,
1295 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1296 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1297 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1298 EFX_PHY_STAT_PCS_FW_VERSION_0,
1299 EFX_PHY_STAT_PCS_FW_VERSION_1,
1300 EFX_PHY_STAT_PCS_FW_VERSION_2,
1301 EFX_PHY_STAT_PCS_FW_VERSION_3,
1302 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1303 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1304 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1305 EFX_PHY_STAT_PCS_OP_MODE,
1309 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1316 __in efx_nic_t *enp,
1317 __in efx_phy_stat_t stat);
1319 #endif /* EFSYS_OPT_NAMES */
1321 #define EFX_PHY_STATS_SIZE 0x100
1324 extern __checkReturn efx_rc_t
1325 efx_phy_stats_update(
1326 __in efx_nic_t *enp,
1327 __in efsys_mem_t *esmp,
1328 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1330 #endif /* EFSYS_OPT_PHY_STATS */
1335 typedef enum efx_bist_type_e {
1336 EFX_BIST_TYPE_UNKNOWN,
1337 EFX_BIST_TYPE_PHY_NORMAL,
1338 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1339 EFX_BIST_TYPE_PHY_CABLE_LONG,
1340 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1341 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1342 EFX_BIST_TYPE_REG, /* Test the register memories */
1343 EFX_BIST_TYPE_NTYPES,
1346 typedef enum efx_bist_result_e {
1347 EFX_BIST_RESULT_UNKNOWN,
1348 EFX_BIST_RESULT_RUNNING,
1349 EFX_BIST_RESULT_PASSED,
1350 EFX_BIST_RESULT_FAILED,
1351 } efx_bist_result_t;
1353 typedef enum efx_phy_cable_status_e {
1354 EFX_PHY_CABLE_STATUS_OK,
1355 EFX_PHY_CABLE_STATUS_INVALID,
1356 EFX_PHY_CABLE_STATUS_OPEN,
1357 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1358 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1359 EFX_PHY_CABLE_STATUS_BUSY,
1360 } efx_phy_cable_status_t;
1362 typedef enum efx_bist_value_e {
1363 EFX_BIST_PHY_CABLE_LENGTH_A,
1364 EFX_BIST_PHY_CABLE_LENGTH_B,
1365 EFX_BIST_PHY_CABLE_LENGTH_C,
1366 EFX_BIST_PHY_CABLE_LENGTH_D,
1367 EFX_BIST_PHY_CABLE_STATUS_A,
1368 EFX_BIST_PHY_CABLE_STATUS_B,
1369 EFX_BIST_PHY_CABLE_STATUS_C,
1370 EFX_BIST_PHY_CABLE_STATUS_D,
1371 EFX_BIST_FAULT_CODE,
1373 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1379 EFX_BIST_MEM_EXPECT,
1380 EFX_BIST_MEM_ACTUAL,
1382 EFX_BIST_MEM_ECC_PARITY,
1383 EFX_BIST_MEM_ECC_FATAL,
1388 extern __checkReturn efx_rc_t
1389 efx_bist_enable_offline(
1390 __in efx_nic_t *enp);
1393 extern __checkReturn efx_rc_t
1395 __in efx_nic_t *enp,
1396 __in efx_bist_type_t type);
1399 extern __checkReturn efx_rc_t
1401 __in efx_nic_t *enp,
1402 __in efx_bist_type_t type,
1403 __out efx_bist_result_t *resultp,
1404 __out_opt uint32_t *value_maskp,
1405 __out_ecount_opt(count) unsigned long *valuesp,
1411 __in efx_nic_t *enp,
1412 __in efx_bist_type_t type);
1414 #endif /* EFSYS_OPT_BIST */
1416 #define EFX_FEATURE_IPV6 0x00000001
1417 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1418 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1419 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1420 #define EFX_FEATURE_MCDI 0x00000020
1421 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1422 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1423 #define EFX_FEATURE_TURBO 0x00000100
1424 #define EFX_FEATURE_MCDI_DMA 0x00000200
1425 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1426 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1427 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1428 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1429 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1430 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1432 typedef enum efx_tunnel_protocol_e {
1433 EFX_TUNNEL_PROTOCOL_NONE = 0,
1434 EFX_TUNNEL_PROTOCOL_VXLAN,
1435 EFX_TUNNEL_PROTOCOL_GENEVE,
1436 EFX_TUNNEL_PROTOCOL_NVGRE,
1438 } efx_tunnel_protocol_t;
1440 typedef enum efx_vi_window_shift_e {
1441 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1442 EFX_VI_WINDOW_SHIFT_8K = 13,
1443 EFX_VI_WINDOW_SHIFT_16K = 14,
1444 EFX_VI_WINDOW_SHIFT_64K = 16,
1445 } efx_vi_window_shift_t;
1447 typedef struct efx_nic_cfg_s {
1448 uint32_t enc_board_type;
1449 uint32_t enc_phy_type;
1451 char enc_phy_name[21];
1453 char enc_phy_revision[21];
1454 efx_mon_type_t enc_mon_type;
1455 #if EFSYS_OPT_MON_STATS
1456 uint32_t enc_mon_stat_dma_buf_size;
1457 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1459 unsigned int enc_features;
1460 efx_vi_window_shift_t enc_vi_window_shift;
1461 uint8_t enc_mac_addr[6];
1462 uint8_t enc_port; /* PHY port number */
1463 uint32_t enc_intr_vec_base;
1464 uint32_t enc_intr_limit;
1465 uint32_t enc_evq_limit;
1466 uint32_t enc_txq_limit;
1467 uint32_t enc_rxq_limit;
1468 uint32_t enc_evq_max_nevs;
1469 uint32_t enc_evq_min_nevs;
1470 uint32_t enc_rxq_max_ndescs;
1471 uint32_t enc_rxq_min_ndescs;
1472 uint32_t enc_txq_max_ndescs;
1473 uint32_t enc_txq_min_ndescs;
1474 uint32_t enc_buftbl_limit;
1475 uint32_t enc_piobuf_limit;
1476 uint32_t enc_piobuf_size;
1477 uint32_t enc_piobuf_min_alloc_size;
1478 uint32_t enc_evq_timer_quantum_ns;
1479 uint32_t enc_evq_timer_max_us;
1480 uint32_t enc_clk_mult;
1481 uint32_t enc_ev_ew_desc_size;
1482 uint32_t enc_ev_desc_size;
1483 uint32_t enc_rx_desc_size;
1484 uint32_t enc_tx_desc_size;
1485 /* Maximum Rx prefix size if many Rx prefixes are supported */
1486 uint32_t enc_rx_prefix_size;
1487 uint32_t enc_rx_buf_align_start;
1488 uint32_t enc_rx_buf_align_end;
1489 #if EFSYS_OPT_RX_SCALE
1490 uint32_t enc_rx_scale_max_exclusive_contexts;
1492 * Mask of supported hash algorithms.
1493 * Hash algorithm types are used as the bit indices.
1495 uint32_t enc_rx_scale_hash_alg_mask;
1497 * Indicates whether port numbers can be included to the
1498 * input data for hash computation.
1500 boolean_t enc_rx_scale_l4_hash_supported;
1501 boolean_t enc_rx_scale_additional_modes_supported;
1502 #endif /* EFSYS_OPT_RX_SCALE */
1503 #if EFSYS_OPT_LOOPBACK
1504 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1505 #endif /* EFSYS_OPT_LOOPBACK */
1506 #if EFSYS_OPT_PHY_FLAGS
1507 uint32_t enc_phy_flags_mask;
1508 #endif /* EFSYS_OPT_PHY_FLAGS */
1509 #if EFSYS_OPT_PHY_LED_CONTROL
1510 uint32_t enc_led_mask;
1511 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1512 #if EFSYS_OPT_PHY_STATS
1513 uint64_t enc_phy_stat_mask;
1514 #endif /* EFSYS_OPT_PHY_STATS */
1516 uint8_t enc_mcdi_mdio_channel;
1517 #if EFSYS_OPT_PHY_STATS
1518 uint32_t enc_mcdi_phy_stat_mask;
1519 #endif /* EFSYS_OPT_PHY_STATS */
1520 #if EFSYS_OPT_MON_STATS
1521 uint32_t *enc_mcdi_sensor_maskp;
1522 uint32_t enc_mcdi_sensor_mask_size;
1523 #endif /* EFSYS_OPT_MON_STATS */
1524 #endif /* EFSYS_OPT_MCDI */
1526 uint32_t enc_bist_mask;
1527 #endif /* EFSYS_OPT_BIST */
1528 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1529 efx_pcie_interface_t enc_intf;
1532 uint32_t enc_privilege_mask;
1533 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1534 boolean_t enc_evq_init_done_ev_supported;
1535 boolean_t enc_bug26807_workaround;
1536 boolean_t enc_bug35388_workaround;
1537 boolean_t enc_bug41750_workaround;
1538 boolean_t enc_bug61265_workaround;
1539 boolean_t enc_bug61297_workaround;
1540 boolean_t enc_rx_batching_enabled;
1541 /* Maximum number of descriptors completed in an rx event. */
1542 uint32_t enc_rx_batch_max;
1543 /* Number of rx descriptors the hardware requires for a push. */
1544 uint32_t enc_rx_push_align;
1545 /* Maximum amount of data in DMA descriptor */
1546 uint32_t enc_tx_dma_desc_size_max;
1548 * Boundary which DMA descriptor data must not cross or 0 if no
1551 uint32_t enc_tx_dma_desc_boundary;
1553 * Maximum number of bytes into the packet the TCP header can start for
1554 * the hardware to apply TSO packet edits.
1556 uint32_t enc_tx_tso_tcp_header_offset_limit;
1557 /* Maximum number of header DMA descriptors per TSO transaction. */
1558 uint32_t enc_tx_tso_max_header_ndescs;
1559 /* Maximum header length acceptable by TSO transaction. */
1560 uint32_t enc_tx_tso_max_header_length;
1561 /* Maximum number of payload DMA descriptors per TSO transaction. */
1562 uint32_t enc_tx_tso_max_payload_ndescs;
1563 /* Maximum payload length per TSO transaction. */
1564 uint32_t enc_tx_tso_max_payload_length;
1565 /* Maximum number of frames to be generated per TSO transaction. */
1566 uint32_t enc_tx_tso_max_nframes;
1567 boolean_t enc_fw_assisted_tso_enabled;
1568 boolean_t enc_fw_assisted_tso_v2_enabled;
1569 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1570 boolean_t enc_tso_v3_enabled;
1571 /* Number of TSO contexts on the NIC (FATSOv2) */
1572 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1573 boolean_t enc_hw_tx_insert_vlan_enabled;
1574 /* Number of PFs on the NIC */
1575 uint32_t enc_hw_pf_count;
1576 /* Datapath firmware vadapter/vport/vswitch support */
1577 boolean_t enc_datapath_cap_evb;
1578 /* Datapath firmware vport reconfigure support */
1579 boolean_t enc_vport_reconfigure_supported;
1580 boolean_t enc_rx_disable_scatter_supported;
1581 /* Maximum number of Rx scatter segments supported by HW */
1582 uint32_t enc_rx_scatter_max;
1583 boolean_t enc_allow_set_mac_with_installed_filters;
1584 boolean_t enc_enhanced_set_mac_supported;
1585 boolean_t enc_init_evq_v2_supported;
1586 boolean_t enc_init_evq_extended_width_supported;
1587 boolean_t enc_no_cont_ev_mode_supported;
1588 boolean_t enc_init_rxq_with_buffer_size;
1589 boolean_t enc_rx_packed_stream_supported;
1590 boolean_t enc_rx_var_packed_stream_supported;
1591 boolean_t enc_rx_es_super_buffer_supported;
1592 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1593 boolean_t enc_pm_and_rxdp_counters;
1594 boolean_t enc_mac_stats_40g_tx_size_bins;
1595 uint32_t enc_tunnel_encapsulations_supported;
1597 * NIC global maximum for unique UDP tunnel ports shared by all
1600 uint32_t enc_tunnel_config_udp_entries_max;
1601 /* External port identifier */
1602 uint8_t enc_external_port;
1603 uint32_t enc_mcdi_max_payload_length;
1604 /* VPD may be per-PF or global */
1605 boolean_t enc_vpd_is_global;
1606 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1607 uint32_t enc_required_pcie_bandwidth_mbps;
1608 uint32_t enc_max_pcie_link_gen;
1609 /* Firmware verifies integrity of NVRAM updates */
1610 boolean_t enc_nvram_update_verify_result_supported;
1611 /* Firmware supports polled NVRAM updates on select partitions */
1612 boolean_t enc_nvram_update_poll_verify_result_supported;
1613 /* Firmware accepts updates via the BUNDLE partition */
1614 boolean_t enc_nvram_bundle_update_supported;
1615 /* Firmware support for extended MAC_STATS buffer */
1616 uint32_t enc_mac_stats_nstats;
1617 boolean_t enc_fec_counters;
1618 boolean_t enc_hlb_counters;
1619 /* NIC support for Match-Action Engine (MAE). */
1620 boolean_t enc_mae_supported;
1621 /* Firmware support for "FLAG" and "MARK" filter actions */
1622 boolean_t enc_filter_action_flag_supported;
1623 boolean_t enc_filter_action_mark_supported;
1624 uint32_t enc_filter_action_mark_max;
1625 /* Port assigned to this PCI function */
1626 uint32_t enc_assigned_port;
1629 #define EFX_PCI_VF_INVALID 0xffff
1631 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1632 ((configp)->evc_function == EFX_PCI_VF_INVALID)
1634 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID)
1635 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID)
1637 #define EFX_PCI_FUNCTION(_encp) \
1638 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1640 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1643 extern const efx_nic_cfg_t *
1645 __in const efx_nic_t *enp);
1647 /* RxDPCPU firmware id values by which FW variant can be identified */
1648 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1649 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1650 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1651 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1652 #define EFX_RXDP_DPDK_FW_ID 0x6
1654 typedef struct efx_nic_fw_info_s {
1655 /* Basic FW version information */
1656 uint16_t enfi_mc_fw_version[4];
1658 * If datapath capabilities can be detected,
1659 * additional FW information is to be shown
1661 boolean_t enfi_dpcpu_fw_ids_valid;
1662 /* Rx and Tx datapath CPU FW IDs */
1663 uint16_t enfi_rx_dpcpu_fw_id;
1664 uint16_t enfi_tx_dpcpu_fw_id;
1665 } efx_nic_fw_info_t;
1668 extern __checkReturn efx_rc_t
1669 efx_nic_get_fw_version(
1670 __in efx_nic_t *enp,
1671 __out efx_nic_fw_info_t *enfip);
1673 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64)
1674 #define EFX_NIC_BOARD_INFO_NAME_LEN (16)
1676 typedef struct efx_nic_board_info_s {
1677 /* The following two fields are NUL-terminated ASCII strings. */
1678 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN];
1679 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN];
1680 uint32_t enbi_revision;
1681 } efx_nic_board_info_t;
1684 extern __checkReturn efx_rc_t
1685 efx_nic_get_board_info(
1686 __in efx_nic_t *enp,
1687 __out efx_nic_board_info_t *board_infop);
1689 /* Driver resource limits (minimum required/maximum usable). */
1690 typedef struct efx_drv_limits_s {
1691 uint32_t edl_min_evq_count;
1692 uint32_t edl_max_evq_count;
1694 uint32_t edl_min_rxq_count;
1695 uint32_t edl_max_rxq_count;
1697 uint32_t edl_min_txq_count;
1698 uint32_t edl_max_txq_count;
1700 /* PIO blocks (sub-allocated from piobuf) */
1701 uint32_t edl_min_pio_alloc_size;
1702 uint32_t edl_max_pio_alloc_count;
1706 extern __checkReturn efx_rc_t
1707 efx_nic_set_drv_limits(
1708 __inout efx_nic_t *enp,
1709 __in efx_drv_limits_t *edlp);
1712 * Register the OS driver version string for management agents
1713 * (e.g. via NC-SI). The content length is provided (i.e. no
1714 * NUL terminator). Use length 0 to indicate no version string
1715 * should be advertised. It is valid to set the version string
1716 * only before efx_nic_probe() is called.
1719 extern __checkReturn efx_rc_t
1720 efx_nic_set_drv_version(
1721 __inout efx_nic_t *enp,
1722 __in_ecount(length) char const *verp,
1723 __in size_t length);
1725 typedef enum efx_nic_region_e {
1726 EFX_REGION_VI, /* Memory BAR UC mapping */
1727 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1731 extern __checkReturn efx_rc_t
1732 efx_nic_get_bar_region(
1733 __in efx_nic_t *enp,
1734 __in efx_nic_region_t region,
1735 __out uint32_t *offsetp,
1736 __out size_t *sizep);
1739 extern __checkReturn efx_rc_t
1740 efx_nic_get_vi_pool(
1741 __in efx_nic_t *enp,
1742 __out uint32_t *evq_countp,
1743 __out uint32_t *rxq_countp,
1744 __out uint32_t *txq_countp);
1749 typedef enum efx_vpd_tag_e {
1756 typedef uint16_t efx_vpd_keyword_t;
1758 typedef struct efx_vpd_value_s {
1759 efx_vpd_tag_t evv_tag;
1760 efx_vpd_keyword_t evv_keyword;
1762 uint8_t evv_value[0x100];
1766 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1769 extern __checkReturn efx_rc_t
1771 __in efx_nic_t *enp);
1774 extern __checkReturn efx_rc_t
1776 __in efx_nic_t *enp,
1777 __out size_t *sizep);
1780 extern __checkReturn efx_rc_t
1782 __in efx_nic_t *enp,
1783 __out_bcount(size) caddr_t data,
1787 extern __checkReturn efx_rc_t
1789 __in efx_nic_t *enp,
1790 __in_bcount(size) caddr_t data,
1794 extern __checkReturn efx_rc_t
1796 __in efx_nic_t *enp,
1797 __in_bcount(size) caddr_t data,
1801 extern __checkReturn efx_rc_t
1803 __in efx_nic_t *enp,
1804 __in_bcount(size) caddr_t data,
1806 __inout efx_vpd_value_t *evvp);
1809 extern __checkReturn efx_rc_t
1811 __in efx_nic_t *enp,
1812 __inout_bcount(size) caddr_t data,
1814 __in efx_vpd_value_t *evvp);
1817 extern __checkReturn efx_rc_t
1819 __in efx_nic_t *enp,
1820 __inout_bcount(size) caddr_t data,
1822 __out efx_vpd_value_t *evvp,
1823 __inout unsigned int *contp);
1826 extern __checkReturn efx_rc_t
1828 __in efx_nic_t *enp,
1829 __in_bcount(size) caddr_t data,
1835 __in efx_nic_t *enp);
1837 #endif /* EFSYS_OPT_VPD */
1843 typedef enum efx_nvram_type_e {
1844 EFX_NVRAM_INVALID = 0,
1846 EFX_NVRAM_BOOTROM_CFG,
1847 EFX_NVRAM_MC_FIRMWARE,
1848 EFX_NVRAM_MC_GOLDEN,
1854 EFX_NVRAM_FPGA_BACKUP,
1855 EFX_NVRAM_DYNAMIC_CFG,
1858 EFX_NVRAM_MUM_FIRMWARE,
1859 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1860 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1862 EFX_NVRAM_BUNDLE_METADATA,
1866 typedef struct efx_nvram_info_s {
1868 uint32_t eni_partn_size;
1869 uint32_t eni_address;
1870 uint32_t eni_erase_size;
1871 uint32_t eni_write_size;
1874 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1877 extern __checkReturn efx_rc_t
1879 __in efx_nic_t *enp);
1884 extern __checkReturn efx_rc_t
1886 __in efx_nic_t *enp);
1888 #endif /* EFSYS_OPT_DIAG */
1891 extern __checkReturn efx_rc_t
1893 __in efx_nic_t *enp,
1894 __in efx_nvram_type_t type,
1895 __out size_t *sizep);
1898 extern __checkReturn efx_rc_t
1900 __in efx_nic_t *enp,
1901 __in efx_nvram_type_t type,
1902 __out efx_nvram_info_t *enip);
1905 extern __checkReturn efx_rc_t
1907 __in efx_nic_t *enp,
1908 __in efx_nvram_type_t type,
1909 __out_opt size_t *pref_chunkp);
1912 extern __checkReturn efx_rc_t
1913 efx_nvram_rw_finish(
1914 __in efx_nic_t *enp,
1915 __in efx_nvram_type_t type,
1916 __out_opt uint32_t *verify_resultp);
1919 extern __checkReturn efx_rc_t
1920 efx_nvram_get_version(
1921 __in efx_nic_t *enp,
1922 __in efx_nvram_type_t type,
1923 __out uint32_t *subtypep,
1924 __out_ecount(4) uint16_t version[4]);
1927 extern __checkReturn efx_rc_t
1928 efx_nvram_read_chunk(
1929 __in efx_nic_t *enp,
1930 __in efx_nvram_type_t type,
1931 __in unsigned int offset,
1932 __out_bcount(size) caddr_t data,
1936 extern __checkReturn efx_rc_t
1937 efx_nvram_read_backup(
1938 __in efx_nic_t *enp,
1939 __in efx_nvram_type_t type,
1940 __in unsigned int offset,
1941 __out_bcount(size) caddr_t data,
1945 extern __checkReturn efx_rc_t
1946 efx_nvram_set_version(
1947 __in efx_nic_t *enp,
1948 __in efx_nvram_type_t type,
1949 __in_ecount(4) uint16_t version[4]);
1952 extern __checkReturn efx_rc_t
1954 __in efx_nic_t *enp,
1955 __in efx_nvram_type_t type,
1956 __in_bcount(partn_size) caddr_t partn_data,
1957 __in size_t partn_size);
1960 extern __checkReturn efx_rc_t
1962 __in efx_nic_t *enp,
1963 __in efx_nvram_type_t type);
1966 extern __checkReturn efx_rc_t
1967 efx_nvram_write_chunk(
1968 __in efx_nic_t *enp,
1969 __in efx_nvram_type_t type,
1970 __in unsigned int offset,
1971 __in_bcount(size) caddr_t data,
1977 __in efx_nic_t *enp);
1979 #endif /* EFSYS_OPT_NVRAM */
1981 #if EFSYS_OPT_BOOTCFG
1983 /* Report size and offset of bootcfg sector in NVRAM partition. */
1985 extern __checkReturn efx_rc_t
1986 efx_bootcfg_sector_info(
1987 __in efx_nic_t *enp,
1989 __out_opt uint32_t *sector_countp,
1990 __out size_t *offsetp,
1991 __out size_t *max_sizep);
1994 * Copy bootcfg sector data to a target buffer which may differ in size.
1995 * Optionally corrects format errors in source buffer.
1999 efx_bootcfg_copy_sector(
2000 __in efx_nic_t *enp,
2001 __inout_bcount(sector_length)
2003 __in size_t sector_length,
2004 __out_bcount(data_size) uint8_t *data,
2005 __in size_t data_size,
2006 __in boolean_t handle_format_errors);
2011 __in efx_nic_t *enp,
2012 __out_bcount(size) uint8_t *data,
2018 __in efx_nic_t *enp,
2019 __in_bcount(size) uint8_t *data,
2024 * Processing routines for buffers arranged in the DHCP/BOOTP option format
2025 * (see https://tools.ietf.org/html/rfc1533)
2027 * Summarising the format: the buffer is a sequence of options. All options
2028 * begin with a tag octet, which uniquely identifies the option. Fixed-
2029 * length options without data consist of only a tag octet. Only options PAD
2030 * (0) and END (255) are fixed length. All other options are variable-length
2031 * with a length octet following the tag octet. The value of the length
2032 * octet does not include the two octets specifying the tag and length. The
2033 * length octet is followed by "length" octets of data.
2035 * Option data may be a sequence of sub-options in the same format. The data
2036 * content of the encapsulating option is one or more encapsulated sub-options,
2037 * with no terminating END tag is required.
2039 * To be valid, the top-level sequence of options should be terminated by an
2040 * END tag. The buffer should be padded with the PAD byte.
2042 * When stored to NVRAM, the DHCP option format buffer is preceded by a
2043 * checksum octet. The full buffer (including after the END tag) contributes
2044 * to the checksum, hence the need to fill the buffer to the end with PAD.
2047 #define EFX_DHCP_END ((uint8_t)0xff)
2048 #define EFX_DHCP_PAD ((uint8_t)0)
2050 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
2051 (uint16_t)(((encapsulator) << 8) | (encapsulated))
2054 extern __checkReturn uint8_t
2056 __in_bcount(size) uint8_t const *data,
2060 extern __checkReturn efx_rc_t
2062 __in_bcount(size) uint8_t const *data,
2064 __out_opt size_t *usedp);
2067 extern __checkReturn efx_rc_t
2069 __in_bcount(buffer_length) uint8_t *bufferp,
2070 __in size_t buffer_length,
2072 __deref_out uint8_t **valuepp,
2073 __out size_t *value_lengthp);
2076 extern __checkReturn efx_rc_t
2078 __in_bcount(buffer_length) uint8_t *bufferp,
2079 __in size_t buffer_length,
2080 __deref_out uint8_t **endpp);
2084 extern __checkReturn efx_rc_t
2085 efx_dhcp_delete_tag(
2086 __inout_bcount(buffer_length) uint8_t *bufferp,
2087 __in size_t buffer_length,
2091 extern __checkReturn efx_rc_t
2093 __inout_bcount(buffer_length) uint8_t *bufferp,
2094 __in size_t buffer_length,
2096 __in_bcount_opt(value_length) uint8_t *valuep,
2097 __in size_t value_length);
2100 extern __checkReturn efx_rc_t
2101 efx_dhcp_update_tag(
2102 __inout_bcount(buffer_length) uint8_t *bufferp,
2103 __in size_t buffer_length,
2105 __in uint8_t *value_locationp,
2106 __in_bcount_opt(value_length) uint8_t *valuep,
2107 __in size_t value_length);
2110 #endif /* EFSYS_OPT_BOOTCFG */
2112 #if EFSYS_OPT_IMAGE_LAYOUT
2114 #include "ef10_signed_image_layout.h"
2117 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2120 * The image header format is extensible. However, older drivers require an
2121 * exact match of image header version and header length when validating and
2122 * writing firmware images.
2124 * To avoid breaking backward compatibility, we use the upper bits of the
2125 * controller version fields to contain an extra version number used for
2126 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2127 * version). See bug39254 and SF-102785-PS for details.
2129 typedef struct efx_image_header_s {
2131 uint32_t eih_version;
2133 uint32_t eih_subtype;
2134 uint32_t eih_code_size;
2137 uint32_t eih_controller_version_min;
2139 uint16_t eih_controller_version_min_short;
2140 uint8_t eih_extra_version_a;
2141 uint8_t eih_extra_version_b;
2145 uint32_t eih_controller_version_max;
2147 uint16_t eih_controller_version_max_short;
2148 uint8_t eih_extra_version_c;
2149 uint8_t eih_extra_version_d;
2152 uint16_t eih_code_version_a;
2153 uint16_t eih_code_version_b;
2154 uint16_t eih_code_version_c;
2155 uint16_t eih_code_version_d;
2156 } efx_image_header_t;
2158 #define EFX_IMAGE_HEADER_SIZE (40)
2159 #define EFX_IMAGE_HEADER_VERSION (4)
2160 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2163 typedef struct efx_image_trailer_s {
2165 } efx_image_trailer_t;
2167 #define EFX_IMAGE_TRAILER_SIZE (4)
2169 typedef enum efx_image_format_e {
2170 EFX_IMAGE_FORMAT_NO_IMAGE,
2171 EFX_IMAGE_FORMAT_INVALID,
2172 EFX_IMAGE_FORMAT_UNSIGNED,
2173 EFX_IMAGE_FORMAT_SIGNED,
2174 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2175 } efx_image_format_t;
2177 typedef struct efx_image_info_s {
2178 efx_image_format_t eii_format;
2179 uint8_t * eii_imagep;
2180 size_t eii_image_size;
2181 efx_image_header_t * eii_headerp;
2185 extern __checkReturn efx_rc_t
2186 efx_check_reflash_image(
2188 __in uint32_t buffer_size,
2189 __out efx_image_info_t *infop);
2192 extern __checkReturn efx_rc_t
2193 efx_build_signed_image_write_buffer(
2194 __out_bcount(buffer_size)
2196 __in uint32_t buffer_size,
2197 __in efx_image_info_t *infop,
2198 __out efx_image_header_t **headerpp);
2200 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2204 typedef enum efx_pattern_type_t {
2205 EFX_PATTERN_BYTE_INCREMENT = 0,
2206 EFX_PATTERN_ALL_THE_SAME,
2207 EFX_PATTERN_BIT_ALTERNATE,
2208 EFX_PATTERN_BYTE_ALTERNATE,
2209 EFX_PATTERN_BYTE_CHANGING,
2210 EFX_PATTERN_BIT_SWEEP,
2212 } efx_pattern_type_t;
2215 (*efx_sram_pattern_fn_t)(
2217 __in boolean_t negate,
2218 __out efx_qword_t *eqp);
2221 extern __checkReturn efx_rc_t
2223 __in efx_nic_t *enp,
2224 __in efx_pattern_type_t type);
2226 #endif /* EFSYS_OPT_DIAG */
2229 extern __checkReturn efx_rc_t
2230 efx_sram_buf_tbl_set(
2231 __in efx_nic_t *enp,
2233 __in efsys_mem_t *esmp,
2238 efx_sram_buf_tbl_clear(
2239 __in efx_nic_t *enp,
2243 #define EFX_BUF_TBL_SIZE 0x20000
2245 #define EFX_BUF_SIZE 4096
2249 typedef struct efx_evq_s efx_evq_t;
2251 #if EFSYS_OPT_QSTATS
2253 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2254 typedef enum efx_ev_qstat_e {
2260 EV_RX_PAUSE_FRM_ERR,
2261 EV_RX_BUF_OWNER_ID_ERR,
2262 EV_RX_IPV4_HDR_CHKSUM_ERR,
2263 EV_RX_TCP_UDP_CHKSUM_ERR,
2267 EV_RX_MCAST_HASH_MATCH,
2284 EV_DRIVER_SRM_UPD_DONE,
2285 EV_DRIVER_TX_DESCQ_FLS_DONE,
2286 EV_DRIVER_RX_DESCQ_FLS_DONE,
2287 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2288 EV_DRIVER_RX_DSC_ERROR,
2289 EV_DRIVER_TX_DSC_ERROR,
2292 EV_RX_PARSE_INCOMPLETE,
2296 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2298 #endif /* EFSYS_OPT_QSTATS */
2301 extern __checkReturn efx_rc_t
2303 __in efx_nic_t *enp);
2308 __in efx_nic_t *enp);
2311 extern __checkReturn size_t
2313 __in const efx_nic_t *enp,
2314 __in unsigned int ndescs,
2315 __in uint32_t flags);
2318 extern __checkReturn unsigned int
2320 __in const efx_nic_t *enp,
2321 __in unsigned int ndescs,
2322 __in uint32_t flags);
2324 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2325 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2326 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2327 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2329 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2330 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2331 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2334 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2335 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2338 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2339 * which is the case when an event queue is set to THROUGHPUT mode.
2341 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2343 /* Configure EVQ for extended width events (EF100 only) */
2344 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20)
2348 extern __checkReturn efx_rc_t
2350 __in efx_nic_t *enp,
2351 __in unsigned int index,
2352 __in efsys_mem_t *esmp,
2356 __in uint32_t flags,
2357 __deref_out efx_evq_t **eepp);
2360 extern __checkReturn efx_rc_t
2362 __in efx_nic_t *enp,
2363 __in unsigned int index,
2364 __in efsys_mem_t *esmp,
2368 __in uint32_t flags,
2370 __deref_out efx_evq_t **eepp);
2375 __in efx_evq_t *eep,
2376 __in uint16_t data);
2378 typedef __checkReturn boolean_t
2379 (*efx_initialized_ev_t)(
2380 __in_opt void *arg);
2382 #define EFX_PKT_UNICAST 0x0004
2383 #define EFX_PKT_START 0x0008
2385 #define EFX_PKT_VLAN_TAGGED 0x0010
2386 #define EFX_CKSUM_TCPUDP 0x0020
2387 #define EFX_CKSUM_IPV4 0x0040
2388 #define EFX_PKT_CONT 0x0080
2390 #define EFX_CHECK_VLAN 0x0100
2391 #define EFX_PKT_TCP 0x0200
2392 #define EFX_PKT_UDP 0x0400
2393 #define EFX_PKT_IPV4 0x0800
2395 #define EFX_PKT_IPV6 0x1000
2396 #define EFX_PKT_PREFIX_LEN 0x2000
2397 #define EFX_ADDR_MISMATCH 0x4000
2398 #define EFX_DISCARD 0x8000
2401 * The following flags are used only for packed stream
2402 * mode. The values for the flags are reused to fit into 16 bit,
2403 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2404 * packed stream mode
2406 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2407 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2410 #define EFX_EV_RX_NLABELS 32
2411 #define EFX_EV_TX_NLABELS 32
2413 typedef __checkReturn boolean_t
2416 __in uint32_t label,
2419 __in uint16_t flags);
2421 typedef __checkReturn boolean_t
2422 (*efx_rx_packets_ev_t)(
2424 __in uint32_t label,
2425 __in unsigned int num_packets,
2426 __in uint32_t flags);
2428 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2431 * Packed stream mode is documented in SF-112241-TC.
2432 * The general idea is that, instead of putting each incoming
2433 * packet into a separate buffer which is specified in a RX
2434 * descriptor, a large buffer is provided to the hardware and
2435 * packets are put there in a continuous stream.
2436 * The main advantage of such an approach is that RX queue refilling
2437 * happens much less frequently.
2439 * Equal stride packed stream mode is documented in SF-119419-TC.
2440 * The general idea is to utilize advantages of the packed stream,
2441 * but avoid indirection in packets representation.
2442 * The main advantage of such an approach is that RX queue refilling
2443 * happens much less frequently and packets buffers are independent
2444 * from upper layers point of view.
2447 typedef __checkReturn boolean_t
2450 __in uint32_t label,
2452 __in uint32_t pkt_count,
2453 __in uint16_t flags);
2457 typedef __checkReturn boolean_t
2460 __in uint32_t label,
2463 typedef __checkReturn boolean_t
2464 (*efx_tx_ndescs_ev_t)(
2466 __in uint32_t label,
2467 __in unsigned int ndescs);
2469 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2470 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2471 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2472 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2473 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2474 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2475 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2476 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2477 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2479 typedef __checkReturn boolean_t
2480 (*efx_exception_ev_t)(
2482 __in uint32_t label,
2483 __in uint32_t data);
2485 typedef __checkReturn boolean_t
2486 (*efx_rxq_flush_done_ev_t)(
2488 __in uint32_t rxq_index);
2490 typedef __checkReturn boolean_t
2491 (*efx_rxq_flush_failed_ev_t)(
2493 __in uint32_t rxq_index);
2495 typedef __checkReturn boolean_t
2496 (*efx_txq_flush_done_ev_t)(
2498 __in uint32_t txq_index);
2500 typedef __checkReturn boolean_t
2501 (*efx_software_ev_t)(
2503 __in uint16_t magic);
2505 typedef __checkReturn boolean_t
2508 __in uint32_t code);
2510 #define EFX_SRAM_CLEAR 0
2511 #define EFX_SRAM_UPDATE 1
2512 #define EFX_SRAM_ILLEGAL_CLEAR 2
2514 typedef __checkReturn boolean_t
2515 (*efx_wake_up_ev_t)(
2517 __in uint32_t label);
2519 typedef __checkReturn boolean_t
2522 __in uint32_t label);
2524 typedef __checkReturn boolean_t
2525 (*efx_link_change_ev_t)(
2527 __in efx_link_mode_t link_mode);
2529 #if EFSYS_OPT_MON_STATS
2531 typedef __checkReturn boolean_t
2532 (*efx_monitor_ev_t)(
2534 __in efx_mon_stat_t id,
2535 __in efx_mon_stat_value_t value);
2537 #endif /* EFSYS_OPT_MON_STATS */
2539 #if EFSYS_OPT_MAC_STATS
2541 typedef __checkReturn boolean_t
2542 (*efx_mac_stats_ev_t)(
2544 __in uint32_t generation);
2546 #endif /* EFSYS_OPT_MAC_STATS */
2548 #if EFSYS_OPT_DESC_PROXY
2551 * NOTE: This callback returns the raw descriptor data, which has not been
2552 * converted to host endian. The callback must use the EFX_OWORD macros
2553 * to extract the descriptor fields as host endian values.
2555 typedef __checkReturn boolean_t
2556 (*efx_desc_proxy_txq_desc_ev_t)(
2558 __in uint16_t vi_id,
2559 __in efx_oword_t txq_desc);
2562 * NOTE: This callback returns the raw descriptor data, which has not been
2563 * converted to host endian. The callback must use the EFX_OWORD macros
2564 * to extract the descriptor fields as host endian values.
2566 typedef __checkReturn boolean_t
2567 (*efx_desc_proxy_virtq_desc_ev_t)(
2569 __in uint16_t vi_id,
2570 __in uint16_t avail,
2571 __in efx_oword_t virtq_desc);
2573 #endif /* EFSYS_OPT_DESC_PROXY */
2575 typedef struct efx_ev_callbacks_s {
2576 efx_initialized_ev_t eec_initialized;
2578 efx_rx_packets_ev_t eec_rx_packets;
2579 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2580 efx_rx_ps_ev_t eec_rx_ps;
2583 efx_tx_ndescs_ev_t eec_tx_ndescs;
2584 efx_exception_ev_t eec_exception;
2585 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2586 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2587 efx_txq_flush_done_ev_t eec_txq_flush_done;
2588 efx_software_ev_t eec_software;
2589 efx_sram_ev_t eec_sram;
2590 efx_wake_up_ev_t eec_wake_up;
2591 efx_timer_ev_t eec_timer;
2592 efx_link_change_ev_t eec_link_change;
2593 #if EFSYS_OPT_MON_STATS
2594 efx_monitor_ev_t eec_monitor;
2595 #endif /* EFSYS_OPT_MON_STATS */
2596 #if EFSYS_OPT_MAC_STATS
2597 efx_mac_stats_ev_t eec_mac_stats;
2598 #endif /* EFSYS_OPT_MAC_STATS */
2599 #if EFSYS_OPT_DESC_PROXY
2600 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc;
2601 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc;
2602 #endif /* EFSYS_OPT_DESC_PROXY */
2604 } efx_ev_callbacks_t;
2607 extern __checkReturn boolean_t
2609 __in efx_evq_t *eep,
2610 __in unsigned int count);
2612 #if EFSYS_OPT_EV_PREFETCH
2617 __in efx_evq_t *eep,
2618 __in unsigned int count);
2620 #endif /* EFSYS_OPT_EV_PREFETCH */
2624 efx_ev_qcreate_check_init_done(
2625 __in efx_evq_t *eep,
2626 __in const efx_ev_callbacks_t *eecp,
2627 __in_opt void *arg);
2632 __in efx_evq_t *eep,
2633 __inout unsigned int *countp,
2634 __in const efx_ev_callbacks_t *eecp,
2635 __in_opt void *arg);
2638 extern __checkReturn efx_rc_t
2639 efx_ev_usecs_to_ticks(
2640 __in efx_nic_t *enp,
2641 __in unsigned int usecs,
2642 __out unsigned int *ticksp);
2645 extern __checkReturn efx_rc_t
2647 __in efx_evq_t *eep,
2648 __in unsigned int us);
2651 extern __checkReturn efx_rc_t
2653 __in efx_evq_t *eep,
2654 __in unsigned int count);
2656 #if EFSYS_OPT_QSTATS
2663 __in efx_nic_t *enp,
2664 __in unsigned int id);
2666 #endif /* EFSYS_OPT_NAMES */
2670 efx_ev_qstats_update(
2671 __in efx_evq_t *eep,
2672 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2674 #endif /* EFSYS_OPT_QSTATS */
2679 __in efx_evq_t *eep);
2684 extern __checkReturn efx_rc_t
2686 __inout efx_nic_t *enp);
2691 __in efx_nic_t *enp);
2693 #if EFSYS_OPT_RX_SCATTER
2695 extern __checkReturn efx_rc_t
2696 efx_rx_scatter_enable(
2697 __in efx_nic_t *enp,
2698 __in unsigned int buf_size);
2699 #endif /* EFSYS_OPT_RX_SCATTER */
2701 /* Handle to represent use of the default RSS context. */
2702 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2704 #if EFSYS_OPT_RX_SCALE
2706 typedef enum efx_rx_hash_alg_e {
2707 EFX_RX_HASHALG_LFSR = 0,
2708 EFX_RX_HASHALG_TOEPLITZ,
2709 EFX_RX_HASHALG_PACKED_STREAM,
2711 } efx_rx_hash_alg_t;
2714 * Legacy hash type flags.
2716 * They represent standard tuples for distinct traffic classes.
2718 #define EFX_RX_HASH_IPV4 (1U << 0)
2719 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2720 #define EFX_RX_HASH_IPV6 (1U << 2)
2721 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2723 #define EFX_RX_HASH_LEGACY_MASK \
2724 (EFX_RX_HASH_IPV4 | \
2725 EFX_RX_HASH_TCPIPV4 | \
2726 EFX_RX_HASH_IPV6 | \
2727 EFX_RX_HASH_TCPIPV6)
2730 * The type of the argument used by efx_rx_scale_mode_set() to
2731 * provide a means for the client drivers to configure hashing.
2733 * A properly constructed value can either be:
2734 * - a combination of legacy flags
2735 * - a combination of EFX_RX_HASH() flags
2737 typedef uint32_t efx_rx_hash_type_t;
2739 typedef enum efx_rx_hash_support_e {
2740 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2741 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2742 } efx_rx_hash_support_t;
2744 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2745 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2746 #define EFX_MAXRSS 64 /* RX indirection entry range */
2747 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2749 typedef enum efx_rx_scale_context_type_e {
2750 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2751 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2752 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2753 } efx_rx_scale_context_type_t;
2756 * Traffic classes eligible for hash computation.
2758 * Select packet headers used in computing the receive hash.
2759 * This uses the same encoding as the RSS_MODES field of
2760 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2762 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2763 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2764 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2765 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2766 #define EFX_RX_CLASS_IPV4_LBN 16
2767 #define EFX_RX_CLASS_IPV4_WIDTH 4
2768 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2769 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2770 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2771 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2772 #define EFX_RX_CLASS_IPV6_LBN 28
2773 #define EFX_RX_CLASS_IPV6_WIDTH 4
2775 #define EFX_RX_NCLASSES 6
2778 * Ancillary flags used to construct generic hash tuples.
2779 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2781 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2782 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2783 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2784 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2787 * Generic hash tuples.
2789 * They express combinations of packet fields
2790 * which can contribute to the hash value for
2791 * a particular traffic class.
2793 #define EFX_RX_CLASS_HASH_DISABLE 0
2795 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2796 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2798 #define EFX_RX_CLASS_HASH_2TUPLE \
2799 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2800 EFX_RX_CLASS_HASH_DST_ADDR)
2802 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2803 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2804 EFX_RX_CLASS_HASH_SRC_PORT)
2806 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2807 (EFX_RX_CLASS_HASH_DST_ADDR | \
2808 EFX_RX_CLASS_HASH_DST_PORT)
2810 #define EFX_RX_CLASS_HASH_4TUPLE \
2811 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2812 EFX_RX_CLASS_HASH_DST_ADDR | \
2813 EFX_RX_CLASS_HASH_SRC_PORT | \
2814 EFX_RX_CLASS_HASH_DST_PORT)
2816 #define EFX_RX_CLASS_HASH_NTUPLES 7
2819 * Hash flag constructor.
2821 * Resulting flags encode hash tuples for specific traffic classes.
2822 * The client drivers are encouraged to use these flags to form
2823 * a hash type value.
2825 #define EFX_RX_HASH(_class, _tuple) \
2826 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2827 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2830 * The maximum number of EFX_RX_HASH() flags.
2832 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2835 extern __checkReturn efx_rc_t
2836 efx_rx_scale_hash_flags_get(
2837 __in efx_nic_t *enp,
2838 __in efx_rx_hash_alg_t hash_alg,
2839 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2840 __in unsigned int max_nflags,
2841 __out unsigned int *nflagsp);
2844 extern __checkReturn efx_rc_t
2845 efx_rx_hash_default_support_get(
2846 __in efx_nic_t *enp,
2847 __out efx_rx_hash_support_t *supportp);
2851 extern __checkReturn efx_rc_t
2852 efx_rx_scale_default_support_get(
2853 __in efx_nic_t *enp,
2854 __out efx_rx_scale_context_type_t *typep);
2857 extern __checkReturn efx_rc_t
2858 efx_rx_scale_context_alloc(
2859 __in efx_nic_t *enp,
2860 __in efx_rx_scale_context_type_t type,
2861 __in uint32_t num_queues,
2862 __out uint32_t *rss_contextp);
2865 extern __checkReturn efx_rc_t
2866 efx_rx_scale_context_free(
2867 __in efx_nic_t *enp,
2868 __in uint32_t rss_context);
2871 extern __checkReturn efx_rc_t
2872 efx_rx_scale_mode_set(
2873 __in efx_nic_t *enp,
2874 __in uint32_t rss_context,
2875 __in efx_rx_hash_alg_t alg,
2876 __in efx_rx_hash_type_t type,
2877 __in boolean_t insert);
2880 extern __checkReturn efx_rc_t
2881 efx_rx_scale_tbl_set(
2882 __in efx_nic_t *enp,
2883 __in uint32_t rss_context,
2884 __in_ecount(n) unsigned int *table,
2888 extern __checkReturn efx_rc_t
2889 efx_rx_scale_key_set(
2890 __in efx_nic_t *enp,
2891 __in uint32_t rss_context,
2892 __in_ecount(n) uint8_t *key,
2896 extern __checkReturn uint32_t
2897 efx_pseudo_hdr_hash_get(
2898 __in efx_rxq_t *erp,
2899 __in efx_rx_hash_alg_t func,
2900 __in uint8_t *buffer);
2902 #endif /* EFSYS_OPT_RX_SCALE */
2905 extern __checkReturn efx_rc_t
2906 efx_pseudo_hdr_pkt_length_get(
2907 __in efx_rxq_t *erp,
2908 __in uint8_t *buffer,
2909 __out uint16_t *pkt_lengthp);
2912 extern __checkReturn size_t
2914 __in const efx_nic_t *enp,
2915 __in unsigned int ndescs);
2918 extern __checkReturn unsigned int
2920 __in const efx_nic_t *enp,
2921 __in unsigned int ndescs);
2923 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2926 * libefx representation of the Rx prefix layout information.
2928 * The information may be used inside libefx to implement Rx prefix fields
2929 * accessors and by drivers which process Rx prefix itself.
2933 * All known Rx prefix fields.
2935 * An Rx prefix may have a subset of these fields.
2937 typedef enum efx_rx_prefix_field_e {
2938 EFX_RX_PREFIX_FIELD_LENGTH = 0,
2939 EFX_RX_PREFIX_FIELD_ORIG_LENGTH,
2940 EFX_RX_PREFIX_FIELD_CLASS,
2941 EFX_RX_PREFIX_FIELD_RSS_HASH,
2942 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID,
2943 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP,
2944 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI,
2945 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI,
2946 EFX_RX_PREFIX_FIELD_USER_FLAG,
2947 EFX_RX_PREFIX_FIELD_USER_MARK,
2948 EFX_RX_PREFIX_FIELD_USER_MARK_VALID,
2949 EFX_RX_PREFIX_FIELD_CSUM_FRAME,
2950 EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2951 EFX_RX_PREFIX_FIELD_INGRESS_MPORT = EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2952 EFX_RX_PREFIX_NFIELDS
2953 } efx_rx_prefix_field_t;
2956 * Location and endianness of a field in Rx prefix.
2958 * If width is zero, the field is not present.
2960 typedef struct efx_rx_prefix_field_info_s {
2961 uint16_t erpfi_offset_bits;
2962 uint8_t erpfi_width_bits;
2963 boolean_t erpfi_big_endian;
2964 } efx_rx_prefix_field_info_t;
2966 /* Helper macro to define Rx prefix fields */
2967 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \
2968 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \
2969 .erpfi_offset_bits = EFX_LOW_BIT(_field), \
2970 .erpfi_width_bits = EFX_WIDTH(_field), \
2971 .erpfi_big_endian = (_big_endian), \
2974 typedef struct efx_rx_prefix_layout_s {
2976 uint8_t erpl_length;
2977 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS];
2978 } efx_rx_prefix_layout_t;
2981 * Helper function to find out a bit mask of wanted but not available
2984 * A field is considered as not available if any parameter mismatch.
2987 extern __checkReturn uint32_t
2988 efx_rx_prefix_layout_check(
2989 __in const efx_rx_prefix_layout_t *available,
2990 __in const efx_rx_prefix_layout_t *wanted);
2993 extern __checkReturn efx_rc_t
2994 efx_rx_prefix_get_layout(
2995 __in const efx_rxq_t *erp,
2996 __out efx_rx_prefix_layout_t *erplp);
2998 typedef enum efx_rxq_type_e {
2999 EFX_RXQ_TYPE_DEFAULT,
3000 EFX_RXQ_TYPE_PACKED_STREAM,
3001 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
3006 * Dummy flag to be used instead of 0 to make it clear that the argument
3007 * is receive queue flags.
3009 #define EFX_RXQ_FLAG_NONE 0x0
3010 #define EFX_RXQ_FLAG_SCATTER 0x1
3012 * If tunnels are supported and Rx event can provide information about
3013 * either outer or inner packet classes (e.g. SFN8xxx adapters with
3014 * full-feature firmware variant running), outer classes are requested by
3015 * default. However, if the driver supports tunnels, the flag allows to
3016 * request inner classes which are required to be able to interpret inner
3017 * Rx checksum offload results.
3019 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
3021 * Request delivery of the RSS hash calculated by HW to be used by
3024 #define EFX_RXQ_FLAG_RSS_HASH 0x4
3026 * Request ingress mport field in the Rx prefix of a queue.
3028 #define EFX_RXQ_FLAG_INGRESS_MPORT 0x8
3030 * Request user mark field in the Rx prefix of a queue.
3032 #define EFX_RXQ_FLAG_USER_MARK 0x10
3034 * Request user flag field in the Rx prefix of a queue.
3036 #define EFX_RXQ_FLAG_USER_FLAG 0x20
3039 extern __checkReturn efx_rc_t
3041 __in efx_nic_t *enp,
3042 __in unsigned int index,
3043 __in unsigned int label,
3044 __in efx_rxq_type_t type,
3045 __in size_t buf_size,
3046 __in efsys_mem_t *esmp,
3049 __in unsigned int flags,
3050 __in efx_evq_t *eep,
3051 __deref_out efx_rxq_t **erpp);
3053 #if EFSYS_OPT_RX_PACKED_STREAM
3055 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
3056 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
3057 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
3058 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
3059 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
3062 extern __checkReturn efx_rc_t
3063 efx_rx_qcreate_packed_stream(
3064 __in efx_nic_t *enp,
3065 __in unsigned int index,
3066 __in unsigned int label,
3067 __in uint32_t ps_buf_size,
3068 __in efsys_mem_t *esmp,
3070 __in efx_evq_t *eep,
3071 __deref_out efx_rxq_t **erpp);
3075 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
3077 /* Maximum head-of-line block timeout in nanoseconds */
3078 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
3081 extern __checkReturn efx_rc_t
3082 efx_rx_qcreate_es_super_buffer(
3083 __in efx_nic_t *enp,
3084 __in unsigned int index,
3085 __in unsigned int label,
3086 __in uint32_t n_bufs_per_desc,
3087 __in uint32_t max_dma_len,
3088 __in uint32_t buf_stride,
3089 __in uint32_t hol_block_timeout,
3090 __in efsys_mem_t *esmp,
3092 __in unsigned int flags,
3093 __in efx_evq_t *eep,
3094 __deref_out efx_rxq_t **erpp);
3098 typedef struct efx_buffer_s {
3099 efsys_dma_addr_t eb_addr;
3104 typedef struct efx_desc_s {
3111 __in efx_rxq_t *erp,
3112 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
3114 __in unsigned int ndescs,
3115 __in unsigned int completed,
3116 __in unsigned int added);
3121 __in efx_rxq_t *erp,
3122 __in unsigned int added,
3123 __inout unsigned int *pushedp);
3125 #if EFSYS_OPT_RX_PACKED_STREAM
3129 efx_rx_qpush_ps_credits(
3130 __in efx_rxq_t *erp);
3133 extern __checkReturn uint8_t *
3134 efx_rx_qps_packet_info(
3135 __in efx_rxq_t *erp,
3136 __in uint8_t *buffer,
3137 __in uint32_t buffer_length,
3138 __in uint32_t current_offset,
3139 __out uint16_t *lengthp,
3140 __out uint32_t *next_offsetp,
3141 __out uint32_t *timestamp);
3145 extern __checkReturn efx_rc_t
3147 __in efx_rxq_t *erp);
3152 __in efx_rxq_t *erp);
3157 __in efx_rxq_t *erp);
3161 typedef struct efx_txq_s efx_txq_t;
3163 #if EFSYS_OPT_QSTATS
3165 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
3166 typedef enum efx_tx_qstat_e {
3172 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
3174 #endif /* EFSYS_OPT_QSTATS */
3177 extern __checkReturn efx_rc_t
3179 __in efx_nic_t *enp);
3184 __in efx_nic_t *enp);
3187 extern __checkReturn size_t
3189 __in const efx_nic_t *enp,
3190 __in unsigned int ndescs);
3193 extern __checkReturn unsigned int
3195 __in const efx_nic_t *enp,
3196 __in unsigned int ndescs);
3198 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
3200 #define EFX_TXQ_CKSUM_IPV4 0x0001
3201 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
3202 #define EFX_TXQ_FATSOV2 0x0004
3203 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
3204 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
3207 extern __checkReturn efx_rc_t
3209 __in efx_nic_t *enp,
3210 __in unsigned int index,
3211 __in unsigned int label,
3212 __in efsys_mem_t *esmp,
3215 __in uint16_t flags,
3216 __in efx_evq_t *eep,
3217 __deref_out efx_txq_t **etpp,
3218 __out unsigned int *addedp);
3221 extern __checkReturn efx_rc_t
3223 __in efx_txq_t *etp,
3224 __in_ecount(ndescs) efx_buffer_t *eb,
3225 __in unsigned int ndescs,
3226 __in unsigned int completed,
3227 __inout unsigned int *addedp);
3230 extern __checkReturn efx_rc_t
3232 __in efx_txq_t *etp,
3233 __in unsigned int ns);
3238 __in efx_txq_t *etp,
3239 __in unsigned int added,
3240 __in unsigned int pushed);
3243 extern __checkReturn efx_rc_t
3245 __in efx_txq_t *etp);
3250 __in efx_txq_t *etp);
3253 extern __checkReturn efx_rc_t
3255 __in efx_txq_t *etp);
3259 efx_tx_qpio_disable(
3260 __in efx_txq_t *etp);
3263 extern __checkReturn efx_rc_t
3265 __in efx_txq_t *etp,
3266 __in_ecount(buf_length) uint8_t *buffer,
3267 __in size_t buf_length,
3268 __in size_t pio_buf_offset);
3271 extern __checkReturn efx_rc_t
3273 __in efx_txq_t *etp,
3274 __in size_t pkt_length,
3275 __in unsigned int completed,
3276 __inout unsigned int *addedp);
3279 extern __checkReturn efx_rc_t
3281 __in efx_txq_t *etp,
3282 __in_ecount(n) efx_desc_t *ed,
3283 __in unsigned int n,
3284 __in unsigned int completed,
3285 __inout unsigned int *addedp);
3289 efx_tx_qdesc_dma_create(
3290 __in efx_txq_t *etp,
3291 __in efsys_dma_addr_t addr,
3294 __out efx_desc_t *edp);
3298 efx_tx_qdesc_tso_create(
3299 __in efx_txq_t *etp,
3300 __in uint16_t ipv4_id,
3301 __in uint32_t tcp_seq,
3302 __in uint8_t tcp_flags,
3303 __out efx_desc_t *edp);
3305 /* Number of FATSOv2 option descriptors */
3306 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3308 /* Maximum number of DMA segments per TSO packet (not superframe) */
3309 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3313 efx_tx_qdesc_tso2_create(
3314 __in efx_txq_t *etp,
3315 __in uint16_t ipv4_id,
3316 __in uint16_t outer_ipv4_id,
3317 __in uint32_t tcp_seq,
3318 __in uint16_t tcp_mss,
3319 __out_ecount(count) efx_desc_t *edp,
3324 efx_tx_qdesc_vlantci_create(
3325 __in efx_txq_t *etp,
3327 __out efx_desc_t *edp);
3331 efx_tx_qdesc_checksum_create(
3332 __in efx_txq_t *etp,
3333 __in uint16_t flags,
3334 __out efx_desc_t *edp);
3336 #if EFSYS_OPT_QSTATS
3343 __in efx_nic_t *etp,
3344 __in unsigned int id);
3346 #endif /* EFSYS_OPT_NAMES */
3350 efx_tx_qstats_update(
3351 __in efx_txq_t *etp,
3352 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3354 #endif /* EFSYS_OPT_QSTATS */
3359 __in efx_txq_t *etp);
3364 #if EFSYS_OPT_FILTER
3366 #define EFX_ETHER_TYPE_IPV4 0x0800
3367 #define EFX_ETHER_TYPE_IPV6 0x86DD
3369 #define EFX_IPPROTO_TCP 6
3370 #define EFX_IPPROTO_UDP 17
3371 #define EFX_IPPROTO_GRE 47
3373 /* Use RSS to spread across multiple queues */
3374 #define EFX_FILTER_FLAG_RX_RSS 0x01
3375 /* Enable RX scatter */
3376 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3378 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3379 * May only be set by the filter implementation for each type.
3380 * A removal request will restore the automatic filter in its place.
3382 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3383 /* Filter is for RX */
3384 #define EFX_FILTER_FLAG_RX 0x08
3385 /* Filter is for TX */
3386 #define EFX_FILTER_FLAG_TX 0x10
3387 /* Set match flag on the received packet */
3388 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3389 /* Set match mark on the received packet */
3390 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3392 typedef uint8_t efx_filter_flags_t;
3395 * Flags which specify the fields to match on. The values are the same as in the
3396 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3399 /* Match by remote IP host address */
3400 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3401 /* Match by local IP host address */
3402 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3403 /* Match by remote MAC address */
3404 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3405 /* Match by remote TCP/UDP port */
3406 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3407 /* Match by remote TCP/UDP port */
3408 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3409 /* Match by local TCP/UDP port */
3410 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3411 /* Match by Ether-type */
3412 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3413 /* Match by inner VLAN ID */
3414 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3415 /* Match by outer VLAN ID */
3416 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3417 /* Match by IP transport protocol */
3418 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3419 /* Match by ingress MPORT */
3420 #define EFX_FILTER_MATCH_MPORT 0x00000400
3421 /* Match by VNI or VSID */
3422 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3423 /* For encapsulated packets, match by inner frame local MAC address */
3424 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3425 /* For encapsulated packets, match all multicast inner frames */
3426 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3427 /* For encapsulated packets, match all unicast inner frames */
3428 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3430 * Match by encap type, this flag does not correspond to
3431 * the MCDI match flags and any unoccupied value may be used
3433 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3434 /* Match otherwise-unmatched multicast and broadcast packets */
3435 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3436 /* Match otherwise-unmatched unicast packets */
3437 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3439 typedef uint32_t efx_filter_match_flags_t;
3441 /* Filter priority from lowest to highest */
3442 typedef enum efx_filter_priority_s {
3443 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3444 * address list or hardware
3445 * requirements. This may only be used
3446 * by the filter implementation for
3448 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3450 } efx_filter_priority_t;
3453 * FIXME: All these fields are assumed to be in little-endian byte order.
3454 * It may be better for some to be big-endian. See bug42804.
3457 typedef struct efx_filter_spec_s {
3458 efx_filter_match_flags_t efs_match_flags;
3459 uint8_t efs_priority;
3460 efx_filter_flags_t efs_flags;
3461 uint16_t efs_dmaq_id;
3462 uint32_t efs_rss_context;
3465 * Saved lower-priority filter. If it is set, it is restored on
3466 * filter delete operation.
3468 struct efx_filter_spec_s *efs_overridden_spec;
3469 /* Fields below here are hashed for software filter lookup */
3470 uint16_t efs_outer_vid;
3471 uint16_t efs_inner_vid;
3472 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3473 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3474 uint16_t efs_ether_type;
3475 uint8_t efs_ip_proto;
3476 efx_tunnel_protocol_t efs_encap_type;
3477 uint16_t efs_loc_port;
3478 uint16_t efs_rem_port;
3479 efx_oword_t efs_rem_host;
3480 efx_oword_t efs_loc_host;
3481 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3482 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3483 uint32_t efs_ingress_mport;
3484 } efx_filter_spec_t;
3487 /* Default values for use in filter specifications */
3488 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3489 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3492 extern __checkReturn efx_rc_t
3494 __in efx_nic_t *enp);
3499 __in efx_nic_t *enp);
3502 extern __checkReturn efx_rc_t
3504 __in efx_nic_t *enp,
3505 __inout efx_filter_spec_t *spec);
3508 extern __checkReturn efx_rc_t
3510 __in efx_nic_t *enp,
3511 __inout efx_filter_spec_t *spec);
3514 extern __checkReturn efx_rc_t
3516 __in efx_nic_t *enp);
3519 extern __checkReturn efx_rc_t
3520 efx_filter_supported_filters(
3521 __in efx_nic_t *enp,
3522 __out_ecount(buffer_length) uint32_t *buffer,
3523 __in size_t buffer_length,
3524 __out size_t *list_lengthp);
3528 efx_filter_spec_init_rx(
3529 __out efx_filter_spec_t *spec,
3530 __in efx_filter_priority_t priority,
3531 __in efx_filter_flags_t flags,
3532 __in efx_rxq_t *erp);
3536 efx_filter_spec_init_tx(
3537 __out efx_filter_spec_t *spec,
3538 __in efx_txq_t *etp);
3541 extern __checkReturn efx_rc_t
3542 efx_filter_spec_set_ipv4_local(
3543 __inout efx_filter_spec_t *spec,
3546 __in uint16_t port);
3549 extern __checkReturn efx_rc_t
3550 efx_filter_spec_set_ipv4_full(
3551 __inout efx_filter_spec_t *spec,
3553 __in uint32_t lhost,
3554 __in uint16_t lport,
3555 __in uint32_t rhost,
3556 __in uint16_t rport);
3559 extern __checkReturn efx_rc_t
3560 efx_filter_spec_set_eth_local(
3561 __inout efx_filter_spec_t *spec,
3563 __in const uint8_t *addr);
3567 efx_filter_spec_set_ether_type(
3568 __inout efx_filter_spec_t *spec,
3569 __in uint16_t ether_type);
3572 extern __checkReturn efx_rc_t
3573 efx_filter_spec_set_uc_def(
3574 __inout efx_filter_spec_t *spec);
3577 extern __checkReturn efx_rc_t
3578 efx_filter_spec_set_mc_def(
3579 __inout efx_filter_spec_t *spec);
3581 typedef enum efx_filter_inner_frame_match_e {
3582 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3583 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3584 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3585 } efx_filter_inner_frame_match_t;
3588 extern __checkReturn efx_rc_t
3589 efx_filter_spec_set_encap_type(
3590 __inout efx_filter_spec_t *spec,
3591 __in efx_tunnel_protocol_t encap_type,
3592 __in efx_filter_inner_frame_match_t inner_frame_match);
3595 extern __checkReturn efx_rc_t
3596 efx_filter_spec_set_vxlan(
3597 __inout efx_filter_spec_t *spec,
3598 __in const uint8_t *vni,
3599 __in const uint8_t *inner_addr,
3600 __in const uint8_t *outer_addr);
3603 extern __checkReturn efx_rc_t
3604 efx_filter_spec_set_geneve(
3605 __inout efx_filter_spec_t *spec,
3606 __in const uint8_t *vni,
3607 __in const uint8_t *inner_addr,
3608 __in const uint8_t *outer_addr);
3611 extern __checkReturn efx_rc_t
3612 efx_filter_spec_set_nvgre(
3613 __inout efx_filter_spec_t *spec,
3614 __in const uint8_t *vsid,
3615 __in const uint8_t *inner_addr,
3616 __in const uint8_t *outer_addr);
3618 #if EFSYS_OPT_RX_SCALE
3620 extern __checkReturn efx_rc_t
3621 efx_filter_spec_set_rss_context(
3622 __inout efx_filter_spec_t *spec,
3623 __in uint32_t rss_context);
3625 #endif /* EFSYS_OPT_FILTER */
3630 extern __checkReturn uint32_t
3632 __in_ecount(count) uint32_t const *input,
3634 __in uint32_t init);
3637 extern __checkReturn uint32_t
3639 __in_ecount(length) uint8_t const *input,
3641 __in uint32_t init);
3643 #if EFSYS_OPT_LICENSING
3647 typedef struct efx_key_stats_s {
3649 uint32_t eks_invalid;
3650 uint32_t eks_blacklisted;
3651 uint32_t eks_unverifiable;
3652 uint32_t eks_wrong_node;
3653 uint32_t eks_licensed_apps_lo;
3654 uint32_t eks_licensed_apps_hi;
3655 uint32_t eks_licensed_features_lo;
3656 uint32_t eks_licensed_features_hi;
3660 extern __checkReturn efx_rc_t
3662 __in efx_nic_t *enp);
3667 __in efx_nic_t *enp);
3670 extern __checkReturn boolean_t
3671 efx_lic_check_support(
3672 __in efx_nic_t *enp);
3675 extern __checkReturn efx_rc_t
3676 efx_lic_update_licenses(
3677 __in efx_nic_t *enp);
3680 extern __checkReturn efx_rc_t
3681 efx_lic_get_key_stats(
3682 __in efx_nic_t *enp,
3683 __out efx_key_stats_t *ksp);
3686 extern __checkReturn efx_rc_t
3688 __in efx_nic_t *enp,
3689 __in uint64_t app_id,
3690 __out boolean_t *licensedp);
3693 extern __checkReturn efx_rc_t
3695 __in efx_nic_t *enp,
3696 __in size_t buffer_size,
3697 __out uint32_t *typep,
3698 __out size_t *lengthp,
3699 __out_opt uint8_t *bufferp);
3703 extern __checkReturn efx_rc_t
3705 __in efx_nic_t *enp,
3706 __in_bcount(buffer_size)
3708 __in size_t buffer_size,
3709 __out uint32_t *startp);
3712 extern __checkReturn efx_rc_t
3714 __in efx_nic_t *enp,
3715 __in_bcount(buffer_size)
3717 __in size_t buffer_size,
3718 __in uint32_t offset,
3719 __out uint32_t *endp);
3722 extern __checkReturn __success(return != B_FALSE) boolean_t
3724 __in efx_nic_t *enp,
3725 __in_bcount(buffer_size)
3727 __in size_t buffer_size,
3728 __in uint32_t offset,
3729 __out uint32_t *startp,
3730 __out uint32_t *lengthp);
3733 extern __checkReturn __success(return != B_FALSE) boolean_t
3734 efx_lic_validate_key(
3735 __in efx_nic_t *enp,
3736 __in_bcount(length) caddr_t keyp,
3737 __in uint32_t length);
3740 extern __checkReturn efx_rc_t
3742 __in efx_nic_t *enp,
3743 __in_bcount(buffer_size)
3745 __in size_t buffer_size,
3746 __in uint32_t offset,
3747 __in uint32_t length,
3748 __out_bcount_part(key_max_size, *lengthp)
3750 __in size_t key_max_size,
3751 __out uint32_t *lengthp);
3754 extern __checkReturn efx_rc_t
3756 __in efx_nic_t *enp,
3757 __in_bcount(buffer_size)
3759 __in size_t buffer_size,
3760 __in uint32_t offset,
3761 __in_bcount(length) caddr_t keyp,
3762 __in uint32_t length,
3763 __out uint32_t *lengthp);
3766 extern __checkReturn efx_rc_t
3768 __in efx_nic_t *enp,
3769 __in_bcount(buffer_size)
3771 __in size_t buffer_size,
3772 __in uint32_t offset,
3773 __in uint32_t length,
3775 __out uint32_t *deltap);
3778 extern __checkReturn efx_rc_t
3779 efx_lic_create_partition(
3780 __in efx_nic_t *enp,
3781 __in_bcount(buffer_size)
3783 __in size_t buffer_size);
3785 extern __checkReturn efx_rc_t
3786 efx_lic_finish_partition(
3787 __in efx_nic_t *enp,
3788 __in_bcount(buffer_size)
3790 __in size_t buffer_size);
3792 #endif /* EFSYS_OPT_LICENSING */
3796 #if EFSYS_OPT_TUNNEL
3799 extern __checkReturn efx_rc_t
3801 __in efx_nic_t *enp);
3806 __in efx_nic_t *enp);
3809 * For overlay network encapsulation using UDP, the firmware needs to know
3810 * the configured UDP port for the overlay so it can decode encapsulated
3812 * The UDP port/protocol list is global.
3816 extern __checkReturn efx_rc_t
3817 efx_tunnel_config_udp_add(
3818 __in efx_nic_t *enp,
3819 __in uint16_t port /* host/cpu-endian */,
3820 __in efx_tunnel_protocol_t protocol);
3823 * Returns EBUSY if reconfiguration of the port is in progress in other thread.
3826 extern __checkReturn efx_rc_t
3827 efx_tunnel_config_udp_remove(
3828 __in efx_nic_t *enp,
3829 __in uint16_t port /* host/cpu-endian */,
3830 __in efx_tunnel_protocol_t protocol);
3833 * Returns EBUSY if reconfiguration of any of the tunnel entries
3834 * is in progress in other thread.
3837 extern __checkReturn efx_rc_t
3838 efx_tunnel_config_clear(
3839 __in efx_nic_t *enp);
3842 * Apply tunnel UDP ports configuration to hardware.
3844 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3848 extern __checkReturn efx_rc_t
3849 efx_tunnel_reconfigure(
3850 __in efx_nic_t *enp);
3852 #endif /* EFSYS_OPT_TUNNEL */
3854 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3857 * Firmware subvariant choice options.
3859 * It may be switched to no Tx checksum if attached drivers are either
3860 * preboot or firmware subvariant aware and no VIS are allocated.
3861 * If may be always switched to default explicitly using set request or
3862 * implicitly if unaware driver is attaching. If switching is done when
3863 * a driver is attached, it gets MC_REBOOT event and should recreate its
3866 * See SF-119419-TC DPDK Firmware Driver Interface and
3867 * SF-109306-TC EF10 for Driver Writers for details.
3869 typedef enum efx_nic_fw_subvariant_e {
3870 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3871 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3872 EFX_NIC_FW_SUBVARIANT_NTYPES
3873 } efx_nic_fw_subvariant_t;
3876 extern __checkReturn efx_rc_t
3877 efx_nic_get_fw_subvariant(
3878 __in efx_nic_t *enp,
3879 __out efx_nic_fw_subvariant_t *subvariantp);
3882 extern __checkReturn efx_rc_t
3883 efx_nic_set_fw_subvariant(
3884 __in efx_nic_t *enp,
3885 __in efx_nic_fw_subvariant_t subvariant);
3887 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3889 typedef enum efx_phy_fec_type_e {
3890 EFX_PHY_FEC_NONE = 0,
3893 } efx_phy_fec_type_t;
3896 extern __checkReturn efx_rc_t
3897 efx_phy_fec_type_get(
3898 __in efx_nic_t *enp,
3899 __out efx_phy_fec_type_t *typep);
3901 typedef struct efx_phy_link_state_s {
3902 uint32_t epls_adv_cap_mask;
3903 uint32_t epls_lp_cap_mask;
3904 uint32_t epls_ld_cap_mask;
3905 unsigned int epls_fcntl;
3906 efx_phy_fec_type_t epls_fec;
3907 efx_link_mode_t epls_link_mode;
3908 } efx_phy_link_state_t;
3911 extern __checkReturn efx_rc_t
3912 efx_phy_link_state_get(
3913 __in efx_nic_t *enp,
3914 __out efx_phy_link_state_t *eplsp);
3919 typedef uint32_t efx_vswitch_id_t;
3920 typedef uint32_t efx_vport_id_t;
3922 typedef enum efx_vswitch_type_e {
3923 EFX_VSWITCH_TYPE_VLAN = 1,
3924 EFX_VSWITCH_TYPE_VEB,
3925 /* VSWITCH_TYPE_VEPA: obsolete */
3926 EFX_VSWITCH_TYPE_MUX = 4,
3927 } efx_vswitch_type_t;
3929 typedef enum efx_vport_type_e {
3930 EFX_VPORT_TYPE_NORMAL = 4,
3931 EFX_VPORT_TYPE_EXPANSION,
3932 EFX_VPORT_TYPE_TEST,
3935 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3936 #define EFX_FILTER_VID_UNSPEC 0xffff
3937 #define EFX_DEFAULT_VSWITCH_ID 1
3939 /* Default VF VLAN ID on creation */
3940 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3941 #define EFX_VPORT_ID_INVALID 0
3943 typedef struct efx_vport_config_s {
3944 /* Either VF index or EFX_PCI_VF_INVALID for PF */
3945 uint16_t evc_function;
3946 /* VLAN ID of the associated function */
3948 /* vport id shared with client driver */
3949 efx_vport_id_t evc_vport_id;
3950 /* MAC address of the associated function */
3951 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3953 * vports created with this flag set may only transfer traffic on the
3954 * VLANs permitted by the vport. Also, an attempt to install filter with
3955 * VLAN will be refused unless requesting function has VLAN privilege.
3957 boolean_t evc_vlan_restrict;
3958 /* Whether this function is assigned or not */
3959 boolean_t evc_vport_assigned;
3960 } efx_vport_config_t;
3962 typedef struct efx_vswitch_s efx_vswitch_t;
3965 extern __checkReturn efx_rc_t
3967 __in efx_nic_t *enp);
3972 __in efx_nic_t *enp);
3975 extern __checkReturn efx_rc_t
3976 efx_evb_vswitch_create(
3977 __in efx_nic_t *enp,
3978 __in uint32_t num_vports,
3979 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3980 __deref_out efx_vswitch_t **evpp);
3983 extern __checkReturn efx_rc_t
3984 efx_evb_vswitch_destroy(
3985 __in efx_nic_t *enp,
3986 __in efx_vswitch_t *evp);
3989 extern __checkReturn efx_rc_t
3990 efx_evb_vport_mac_set(
3991 __in efx_nic_t *enp,
3992 __in efx_vswitch_t *evp,
3993 __in efx_vport_id_t vport_id,
3994 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3997 extern __checkReturn efx_rc_t
3998 efx_evb_vport_vlan_set(
3999 __in efx_nic_t *enp,
4000 __in efx_vswitch_t *evp,
4001 __in efx_vport_id_t vport_id,
4005 extern __checkReturn efx_rc_t
4006 efx_evb_vport_reset(
4007 __in efx_nic_t *enp,
4008 __in efx_vswitch_t *evp,
4009 __in efx_vport_id_t vport_id,
4010 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
4012 __out boolean_t *is_fn_resetp);
4015 extern __checkReturn efx_rc_t
4016 efx_evb_vport_stats(
4017 __in efx_nic_t *enp,
4018 __in efx_vswitch_t *evp,
4019 __in efx_vport_id_t vport_id,
4020 __out efsys_mem_t *stats_bufferp);
4022 #endif /* EFSYS_OPT_EVB */
4024 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
4026 typedef struct efx_proxy_auth_config_s {
4027 efsys_mem_t *request_bufferp;
4028 efsys_mem_t *response_bufferp;
4029 efsys_mem_t *status_bufferp;
4033 uint32_t handled_privileges;
4034 } efx_proxy_auth_config_t;
4036 typedef struct efx_proxy_cmd_params_s {
4039 uint8_t *request_bufferp;
4040 size_t request_size;
4041 uint8_t *response_bufferp;
4042 size_t response_size;
4043 size_t *response_size_actualp;
4044 } efx_proxy_cmd_params_t;
4047 extern __checkReturn efx_rc_t
4048 efx_proxy_auth_init(
4049 __in efx_nic_t *enp);
4053 efx_proxy_auth_fini(
4054 __in efx_nic_t *enp);
4057 extern __checkReturn efx_rc_t
4058 efx_proxy_auth_configure(
4059 __in efx_nic_t *enp,
4060 __in efx_proxy_auth_config_t *configp);
4063 extern __checkReturn efx_rc_t
4064 efx_proxy_auth_destroy(
4065 __in efx_nic_t *enp,
4066 __in uint32_t handled_privileges);
4069 extern __checkReturn efx_rc_t
4070 efx_proxy_auth_complete_request(
4071 __in efx_nic_t *enp,
4072 __in uint32_t fn_index,
4073 __in uint32_t proxy_result,
4074 __in uint32_t handle);
4077 extern __checkReturn efx_rc_t
4078 efx_proxy_auth_exec_cmd(
4079 __in efx_nic_t *enp,
4080 __inout efx_proxy_cmd_params_t *paramsp);
4083 extern __checkReturn efx_rc_t
4084 efx_proxy_auth_set_privilege_mask(
4085 __in efx_nic_t *enp,
4086 __in uint32_t vf_index,
4088 __in uint32_t value);
4091 extern __checkReturn efx_rc_t
4092 efx_proxy_auth_privilege_mask_get(
4093 __in efx_nic_t *enp,
4094 __in uint32_t pf_index,
4095 __in uint32_t vf_index,
4096 __out uint32_t *maskp);
4099 extern __checkReturn efx_rc_t
4100 efx_proxy_auth_privilege_modify(
4101 __in efx_nic_t *enp,
4102 __in uint32_t pf_index,
4103 __in uint32_t vf_index,
4104 __in uint32_t add_privileges_mask,
4105 __in uint32_t remove_privileges_mask);
4107 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
4112 extern __checkReturn efx_rc_t
4114 __in efx_nic_t *enp);
4119 __in efx_nic_t *enp);
4121 typedef struct efx_mae_limits_s {
4122 uint32_t eml_max_n_action_prios;
4123 uint32_t eml_max_n_outer_prios;
4124 uint32_t eml_encap_types_supported;
4125 uint32_t eml_encap_header_size_limit;
4126 uint32_t eml_max_n_counters;
4130 extern __checkReturn efx_rc_t
4132 __in efx_nic_t *enp,
4133 __out efx_mae_limits_t *emlp);
4135 typedef enum efx_mae_rule_type_e {
4136 EFX_MAE_RULE_ACTION = 0,
4140 } efx_mae_rule_type_t;
4142 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t;
4145 extern __checkReturn efx_rc_t
4146 efx_mae_match_spec_init(
4147 __in efx_nic_t *enp,
4148 __in efx_mae_rule_type_t type,
4150 __out efx_mae_match_spec_t **specp);
4154 efx_mae_match_spec_fini(
4155 __in efx_nic_t *enp,
4156 __in efx_mae_match_spec_t *spec);
4158 typedef enum efx_mae_field_id_e {
4160 * Fields which can be set by efx_mae_match_spec_field_set()
4161 * or by using dedicated field-specific helper APIs.
4163 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
4164 EFX_MAE_FIELD_ETHER_TYPE_BE,
4165 EFX_MAE_FIELD_ETH_SADDR_BE,
4166 EFX_MAE_FIELD_ETH_DADDR_BE,
4167 EFX_MAE_FIELD_VLAN0_TCI_BE,
4168 EFX_MAE_FIELD_VLAN0_PROTO_BE,
4169 EFX_MAE_FIELD_VLAN1_TCI_BE,
4170 EFX_MAE_FIELD_VLAN1_PROTO_BE,
4171 EFX_MAE_FIELD_SRC_IP4_BE,
4172 EFX_MAE_FIELD_DST_IP4_BE,
4173 EFX_MAE_FIELD_IP_PROTO,
4174 EFX_MAE_FIELD_IP_TOS,
4175 EFX_MAE_FIELD_IP_TTL,
4176 EFX_MAE_FIELD_SRC_IP6_BE,
4177 EFX_MAE_FIELD_DST_IP6_BE,
4178 EFX_MAE_FIELD_L4_SPORT_BE,
4179 EFX_MAE_FIELD_L4_DPORT_BE,
4180 EFX_MAE_FIELD_TCP_FLAGS_BE,
4181 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE,
4182 EFX_MAE_FIELD_ENC_ETH_SADDR_BE,
4183 EFX_MAE_FIELD_ENC_ETH_DADDR_BE,
4184 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE,
4185 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE,
4186 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE,
4187 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE,
4188 EFX_MAE_FIELD_ENC_SRC_IP4_BE,
4189 EFX_MAE_FIELD_ENC_DST_IP4_BE,
4190 EFX_MAE_FIELD_ENC_IP_PROTO,
4191 EFX_MAE_FIELD_ENC_IP_TOS,
4192 EFX_MAE_FIELD_ENC_IP_TTL,
4193 EFX_MAE_FIELD_ENC_SRC_IP6_BE,
4194 EFX_MAE_FIELD_ENC_DST_IP6_BE,
4195 EFX_MAE_FIELD_ENC_L4_SPORT_BE,
4196 EFX_MAE_FIELD_ENC_L4_DPORT_BE,
4197 EFX_MAE_FIELD_ENC_VNET_ID_BE,
4198 EFX_MAE_FIELD_OUTER_RULE_ID,
4200 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */
4201 EFX_MAE_FIELD_HAS_OVLAN,
4202 EFX_MAE_FIELD_HAS_IVLAN,
4203 EFX_MAE_FIELD_ENC_HAS_OVLAN,
4204 EFX_MAE_FIELD_ENC_HAS_IVLAN,
4207 * Fields which can be set by efx_mae_match_spec_field_set()
4208 * or by using dedicated field-specific helper APIs.
4210 EFX_MAE_FIELD_RECIRC_ID,
4212 } efx_mae_field_id_t;
4214 /* MPORT selector. Used to refer to MPORTs in match/action rules. */
4215 typedef struct efx_mport_sel_s {
4220 * MPORT ID. Used to refer dynamically to a specific MPORT.
4221 * The difference between MPORT selector and MPORT ID is that
4222 * selector can specify an exact MPORT ID or it can specify a
4223 * pattern by which an exact MPORT ID can be selected. For example,
4224 * static MPORT selector can specify MPORT of a current PF, which
4225 * will be translated to the dynamic MPORT ID based on which PF is
4226 * using that MPORT selector.
4228 typedef struct efx_mport_id_s {
4232 typedef enum efx_mport_type_e {
4233 EFX_MPORT_TYPE_NET_PORT = 0,
4234 EFX_MPORT_TYPE_ALIAS,
4235 EFX_MPORT_TYPE_VNIC,
4238 typedef enum efx_mport_vnic_client_type_e {
4239 EFX_MPORT_VNIC_CLIENT_FUNCTION = 1,
4240 EFX_MPORT_VNIC_CLIENT_PLUGIN,
4241 } efx_mport_vnic_client_type_t;
4243 typedef struct efx_mport_desc_s {
4244 efx_mport_id_t emd_id;
4245 boolean_t emd_can_receive_on;
4246 boolean_t emd_can_deliver_to;
4247 boolean_t emd_can_delete;
4248 boolean_t emd_zombie;
4249 efx_mport_type_t emd_type;
4255 efx_mport_id_t ea_target_mport_id;
4258 efx_mport_vnic_client_type_t ev_client_type;
4259 efx_pcie_interface_t ev_intf;
4262 /* MCDI client handle for this VNIC. */
4268 #define EFX_MPORT_NULL (0U)
4271 * Generate an invalid MPORT selector.
4273 * The resulting MPORT selector is opaque to the caller. Requests
4274 * that attempt to use it will be rejected.
4277 extern __checkReturn efx_rc_t
4278 efx_mae_mport_invalid(
4279 __out efx_mport_sel_t *mportp);
4282 * Get MPORT selector of a physical port.
4284 * The resulting MPORT selector is opaque to the caller and can be
4285 * passed as an argument to efx_mae_match_spec_mport_set()
4286 * and efx_mae_action_set_populate_deliver().
4289 extern __checkReturn efx_rc_t
4290 efx_mae_mport_by_phy_port(
4291 __in uint32_t phy_port,
4292 __out efx_mport_sel_t *mportp);
4295 * Get MPORT selector of a PCIe function.
4297 * The resulting MPORT selector is opaque to the caller and can be
4298 * passed as an argument to efx_mae_match_spec_mport_set()
4299 * and efx_mae_action_set_populate_deliver().
4302 extern __checkReturn efx_rc_t
4303 efx_mae_mport_by_pcie_function(
4306 __out efx_mport_sel_t *mportp);
4309 * Get MPORT selector of a multi-host PCIe function.
4311 * The resulting MPORT selector is opaque to the caller and can be
4312 * passed as an argument to efx_mae_match_spec_mport_set()
4313 * and efx_mae_action_set_populate_deliver().
4316 extern __checkReturn efx_rc_t
4317 efx_mae_mport_by_pcie_mh_function(
4318 __in efx_pcie_interface_t intf,
4321 __out efx_mport_sel_t *mportp);
4324 * Get MPORT selector by an MPORT ID
4326 * The resulting MPORT selector is opaque to the caller and can be
4327 * passed as an argument to efx_mae_match_spec_mport_set()
4328 * and efx_mae_action_set_populate_deliver().
4331 extern __checkReturn efx_rc_t
4332 efx_mae_mport_by_id(
4333 __in const efx_mport_id_t *mport_idp,
4334 __out efx_mport_sel_t *mportp);
4336 /* Get MPORT ID by an MPORT selector */
4338 extern __checkReturn efx_rc_t
4339 efx_mae_mport_id_by_selector(
4340 __in efx_nic_t *enp,
4341 __in const efx_mport_sel_t *mport_selectorp,
4342 __out efx_mport_id_t *mport_idp);
4345 * Fields which have BE postfix in their named constants are expected
4346 * to be passed by callers in big-endian byte order. They will appear
4347 * in the MCDI buffer, which is a part of the match specification, in
4348 * the very same byte order, that is, no conversion will be performed.
4350 * Fields which don't have BE postfix in their named constants are in
4351 * host byte order. MCDI expects them to be little-endian, so the API
4352 * will take care to carry out conversion to little-endian byte order.
4353 * At the moment, the only field in host byte order is MPORT selector.
4356 extern __checkReturn efx_rc_t
4357 efx_mae_match_spec_field_set(
4358 __in efx_mae_match_spec_t *spec,
4359 __in efx_mae_field_id_t field_id,
4360 __in size_t value_size,
4361 __in_bcount(value_size) const uint8_t *value,
4362 __in size_t mask_size,
4363 __in_bcount(mask_size) const uint8_t *mask);
4365 /* The corresponding mask will be set to B_TRUE. */
4367 extern __checkReturn efx_rc_t
4368 efx_mae_match_spec_bit_set(
4369 __in efx_mae_match_spec_t *spec,
4370 __in efx_mae_field_id_t field_id,
4371 __in boolean_t value);
4373 /* If the mask argument is NULL, the API will use full mask by default. */
4375 extern __checkReturn efx_rc_t
4376 efx_mae_match_spec_mport_set(
4377 __in efx_mae_match_spec_t *spec,
4378 __in const efx_mport_sel_t *valuep,
4379 __in_opt const efx_mport_sel_t *maskp);
4382 extern __checkReturn efx_rc_t
4383 efx_mae_match_spec_recirc_id_set(
4384 __in efx_mae_match_spec_t *spec,
4385 __in uint8_t recirc_id);
4388 extern __checkReturn boolean_t
4389 efx_mae_match_specs_equal(
4390 __in const efx_mae_match_spec_t *left,
4391 __in const efx_mae_match_spec_t *right);
4394 * Make sure that match fields known by EFX have proper masks set
4395 * in the match specification as per requirements of SF-122526-TC.
4397 * In the case efx_mae_field_id_t lacks named identifiers for any
4398 * fields which the FW maintains with support status MATCH_ALWAYS,
4399 * the validation result may not be accurate.
4402 extern __checkReturn boolean_t
4403 efx_mae_match_spec_is_valid(
4404 __in efx_nic_t *enp,
4405 __in const efx_mae_match_spec_t *spec);
4407 typedef struct efx_mae_actions_s efx_mae_actions_t;
4410 extern __checkReturn efx_rc_t
4411 efx_mae_action_set_spec_init(
4412 __in efx_nic_t *enp,
4413 __out efx_mae_actions_t **specp);
4417 efx_mae_action_set_spec_fini(
4418 __in efx_nic_t *enp,
4419 __in efx_mae_actions_t *spec);
4422 extern __checkReturn efx_rc_t
4423 efx_mae_action_set_populate_decap(
4424 __in efx_mae_actions_t *spec);
4427 extern __checkReturn efx_rc_t
4428 efx_mae_action_set_populate_vlan_pop(
4429 __in efx_mae_actions_t *spec);
4432 extern __checkReturn efx_rc_t
4433 efx_mae_action_set_populate_vlan_push(
4434 __in efx_mae_actions_t *spec,
4435 __in uint16_t tpid_be,
4436 __in uint16_t tci_be);
4439 * Use efx_mae_action_set_fill_in_eh_id() to set ID of the allocated
4440 * encap. header in the specification prior to action set allocation.
4443 extern __checkReturn efx_rc_t
4444 efx_mae_action_set_populate_encap(
4445 __in efx_mae_actions_t *spec);
4448 * Use efx_mae_action_set_fill_in_counter_id() to set ID of a counter
4449 * in the specification prior to action set allocation.
4451 * NOTICE: the HW will conduct action COUNT after actions DECAP,
4452 * VLAN_POP, VLAN_PUSH (if any) have been applied to the packet,
4453 * but, as a workaround, this order is not validated by the API.
4455 * The workaround helps to unblock DPDK + Open vSwitch use case.
4456 * In Open vSwitch, this action is always the first to be added,
4457 * in particular, it's known to be inserted before action DECAP,
4458 * so enforcing the right order here would cause runtime errors.
4459 * The existing behaviour in Open vSwitch is unlikely to change
4460 * any time soon, and the workaround is a good solution because
4461 * in fact the real COUNT order is a don't care to Open vSwitch.
4464 extern __checkReturn efx_rc_t
4465 efx_mae_action_set_populate_count(
4466 __in efx_mae_actions_t *spec);
4469 extern __checkReturn efx_rc_t
4470 efx_mae_action_set_populate_flag(
4471 __in efx_mae_actions_t *spec);
4474 extern __checkReturn efx_rc_t
4475 efx_mae_action_set_populate_mark(
4476 __in efx_mae_actions_t *spec,
4477 __in uint32_t mark_value);
4480 extern __checkReturn efx_rc_t
4481 efx_mae_action_set_populate_deliver(
4482 __in efx_mae_actions_t *spec,
4483 __in const efx_mport_sel_t *mportp);
4486 extern __checkReturn efx_rc_t
4487 efx_mae_action_set_populate_drop(
4488 __in efx_mae_actions_t *spec);
4491 extern __checkReturn boolean_t
4492 efx_mae_action_set_specs_equal(
4493 __in const efx_mae_actions_t *left,
4494 __in const efx_mae_actions_t *right);
4497 * Conduct a comparison to check whether two match specifications
4498 * of equal rule type (action / outer) and priority would map to
4499 * the very same rule class from the firmware's standpoint.
4501 * For match specification fields that are not supported by firmware,
4502 * the rule class only matches if the mask/value pairs for that field
4503 * are equal. Clients should use efx_mae_match_spec_is_valid() before
4504 * calling this API to detect usage of unsupported fields.
4507 extern __checkReturn efx_rc_t
4508 efx_mae_match_specs_class_cmp(
4509 __in efx_nic_t *enp,
4510 __in const efx_mae_match_spec_t *left,
4511 __in const efx_mae_match_spec_t *right,
4512 __out boolean_t *have_same_classp);
4514 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX
4517 typedef struct efx_mae_rule_id_s {
4519 } efx_mae_rule_id_t;
4522 * Set the initial recirculation ID. It goes to action rule (AR) lookup.
4524 * To match on this ID in an AR, use efx_mae_match_spec_recirc_id_set().
4527 extern __checkReturn efx_rc_t
4528 efx_mae_outer_rule_recirc_id_set(
4529 __in efx_mae_match_spec_t *spec,
4530 __in uint8_t recirc_id);
4533 extern __checkReturn efx_rc_t
4534 efx_mae_outer_rule_insert(
4535 __in efx_nic_t *enp,
4536 __in const efx_mae_match_spec_t *spec,
4537 __in efx_tunnel_protocol_t encap_type,
4538 __out efx_mae_rule_id_t *or_idp);
4541 extern __checkReturn efx_rc_t
4542 efx_mae_outer_rule_remove(
4543 __in efx_nic_t *enp,
4544 __in const efx_mae_rule_id_t *or_idp);
4547 extern __checkReturn efx_rc_t
4548 efx_mae_match_spec_outer_rule_id_set(
4549 __in efx_mae_match_spec_t *spec,
4550 __in const efx_mae_rule_id_t *or_idp);
4552 /* Encap. header ID */
4553 typedef struct efx_mae_eh_id_s {
4558 extern __checkReturn efx_rc_t
4559 efx_mae_encap_header_alloc(
4560 __in efx_nic_t *enp,
4561 __in efx_tunnel_protocol_t encap_type,
4562 __in_bcount(header_size) uint8_t *header_data,
4563 __in size_t header_size,
4564 __out efx_mae_eh_id_t *eh_idp);
4567 extern __checkReturn efx_rc_t
4568 efx_mae_encap_header_free(
4569 __in efx_nic_t *enp,
4570 __in const efx_mae_eh_id_t *eh_idp);
4572 /* See description before efx_mae_action_set_populate_encap(). */
4574 extern __checkReturn efx_rc_t
4575 efx_mae_action_set_fill_in_eh_id(
4576 __in efx_mae_actions_t *spec,
4577 __in const efx_mae_eh_id_t *eh_idp);
4579 typedef struct efx_counter_s {
4584 extern __checkReturn unsigned int
4585 efx_mae_action_set_get_nb_count(
4586 __in const efx_mae_actions_t *spec);
4588 /* See description before efx_mae_action_set_populate_count(). */
4590 extern __checkReturn efx_rc_t
4591 efx_mae_action_set_fill_in_counter_id(
4592 __in efx_mae_actions_t *spec,
4593 __in const efx_counter_t *counter_idp);
4596 typedef struct efx_mae_aset_id_s {
4598 } efx_mae_aset_id_t;
4601 extern __checkReturn efx_rc_t
4602 efx_mae_action_set_alloc(
4603 __in efx_nic_t *enp,
4604 __in const efx_mae_actions_t *spec,
4605 __out efx_mae_aset_id_t *aset_idp);
4608 * Generation count has two purposes:
4610 * 1) Distinguish between counter packets that belong to freed counter
4611 * and the packets that belong to reallocated counter (with the same ID);
4612 * 2) Make sure that all packets are received for a counter that was freed;
4614 * API users should provide generation count out parameter in allocation
4615 * function if counters can be reallocated and consistent counter values are
4618 * API users that need consistent final counter values after counter
4619 * deallocation or counter stream stop should provide the parameter in
4620 * functions that free the counters and stop the counter stream.
4623 extern __checkReturn efx_rc_t
4624 efx_mae_counters_alloc(
4625 __in efx_nic_t *enp,
4626 __in uint32_t n_counters,
4627 __out uint32_t *n_allocatedp,
4628 __out_ecount(n_counters) efx_counter_t *countersp,
4629 __out_opt uint32_t *gen_countp);
4632 extern __checkReturn efx_rc_t
4633 efx_mae_counters_free(
4634 __in efx_nic_t *enp,
4635 __in uint32_t n_counters,
4636 __out uint32_t *n_freedp,
4637 __in_ecount(n_counters) const efx_counter_t *countersp,
4638 __out_opt uint32_t *gen_countp);
4640 /* When set, include counters with a value of zero */
4641 #define EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE (1U << 0)
4644 * Set if credit-based flow control is used. In this case the driver
4645 * must call efx_mae_counters_stream_give_credits() to notify the
4646 * packetiser of descriptors written.
4648 #define EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS (1U << 0)
4651 extern __checkReturn efx_rc_t
4652 efx_mae_counters_stream_start(
4653 __in efx_nic_t *enp,
4654 __in uint16_t rxq_id,
4655 __in uint16_t packet_size,
4656 __in uint32_t flags_in,
4657 __out uint32_t *flags_out);
4660 extern __checkReturn efx_rc_t
4661 efx_mae_counters_stream_stop(
4662 __in efx_nic_t *enp,
4663 __in uint16_t rxq_id,
4664 __out_opt uint32_t *gen_countp);
4667 extern __checkReturn efx_rc_t
4668 efx_mae_counters_stream_give_credits(
4669 __in efx_nic_t *enp,
4670 __in uint32_t n_credits);
4673 extern __checkReturn efx_rc_t
4674 efx_mae_action_set_free(
4675 __in efx_nic_t *enp,
4676 __in const efx_mae_aset_id_t *aset_idp);
4678 /* Action set list ID */
4679 typedef struct efx_mae_aset_list_id_s {
4681 } efx_mae_aset_list_id_t;
4684 * Either action set list ID or action set ID must be passed to this API,
4688 extern __checkReturn efx_rc_t
4689 efx_mae_action_rule_insert(
4690 __in efx_nic_t *enp,
4691 __in const efx_mae_match_spec_t *spec,
4692 __in const efx_mae_aset_list_id_t *asl_idp,
4693 __in const efx_mae_aset_id_t *as_idp,
4694 __out efx_mae_rule_id_t *ar_idp);
4697 extern __checkReturn efx_rc_t
4698 efx_mae_action_rule_remove(
4699 __in efx_nic_t *enp,
4700 __in const efx_mae_rule_id_t *ar_idp);
4703 extern __checkReturn efx_rc_t
4704 efx_mcdi_mport_alloc_alias(
4705 __in efx_nic_t *enp,
4706 __out efx_mport_id_t *mportp,
4707 __out_opt uint32_t *labelp);
4710 extern __checkReturn efx_rc_t
4712 __in efx_nic_t *enp,
4713 __in const efx_mport_id_t *mportp);
4715 typedef __checkReturn efx_rc_t
4716 (efx_mae_read_mport_journal_cb)(
4717 __in void *cb_datap,
4718 __in efx_mport_desc_t *mportp,
4719 __in size_t mport_len);
4722 * Read mport descriptions from the MAE journal (which describes added and
4723 * removed mports) and pass them to a user-supplied callback. The user gets
4724 * only one chance to process the data it's given. Once the callback function
4725 * finishes, that particular mport description will be gone.
4726 * The journal will be fully repopulated on PCI reset (efx_nic_reset function).
4729 extern __checkReturn efx_rc_t
4730 efx_mae_read_mport_journal(
4731 __in efx_nic_t *enp,
4732 __in efx_mae_read_mport_journal_cb *cbp,
4733 __in void *cb_datap);
4735 #endif /* EFSYS_OPT_MAE */
4737 #if EFSYS_OPT_VIRTIO
4739 /* A Virtio net device can have one or more pairs of Rx/Tx virtqueues
4740 * while virtio block device has a single virtqueue,
4741 * for further details refer section of 4.2.3 of SF-120734
4743 typedef enum efx_virtio_vq_type_e {
4744 EFX_VIRTIO_VQ_TYPE_NET_RXQ,
4745 EFX_VIRTIO_VQ_TYPE_NET_TXQ,
4746 EFX_VIRTIO_VQ_TYPE_BLOCK,
4747 EFX_VIRTIO_VQ_NTYPES
4748 } efx_virtio_vq_type_t;
4750 typedef struct efx_virtio_vq_dyncfg_s {
4752 * If queue is being created to be migrated then this
4753 * should be the FINAL_PIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE
4754 * of the queue being migrated from. Otherwise, it should be zero.
4756 uint32_t evvd_vq_pidx;
4758 * If this queue is being created to be migrated then this
4759 * should be the FINAL_CIDX value returned by MC_CMD_VIRTIO_FINI_QUEUE
4760 * of the queue being migrated from. Otherwise, it should be zero.
4762 uint32_t evvd_vq_cidx;
4763 } efx_virtio_vq_dyncfg_t;
4766 * Virtqueue size must be a power of 2, maximum size is 32768
4767 * (see VIRTIO v1.1 section 2.6)
4769 #define EFX_VIRTIO_MAX_VQ_SIZE 0x8000
4771 typedef struct efx_virtio_vq_cfg_s {
4772 unsigned int evvc_vq_num;
4773 efx_virtio_vq_type_t evvc_type;
4775 * vDPA as VF : It is target VF number if queue is being created on VF.
4776 * vDPA as PF : If queue to be created on PF then it should be
4777 * EFX_PCI_VF_INVALID.
4779 uint16_t evvc_target_vf;
4781 * Maximum virtqueue size is EFX_VIRTIO_MAX_VQ_SIZE and
4782 * virtqueue size 0 means the queue is unavailable.
4784 uint32_t evvc_vq_size;
4785 efsys_dma_addr_t evvc_desc_tbl_addr;
4786 efsys_dma_addr_t evvc_avail_ring_addr;
4787 efsys_dma_addr_t evvc_used_ring_addr;
4788 /* MSIX vector number for the virtqueue or 0xFFFF if MSIX is not used */
4789 uint16_t evvc_msix_vector;
4791 * evvc_pas_id contains a PCIe address space identifier if the queue
4794 boolean_t evvc_use_pasid;
4795 uint32_t evvc_pas_id;
4796 /* Negotiated virtio features to be applied to this virtqueue */
4797 uint64_t evcc_features;
4798 } efx_virtio_vq_cfg_t;
4800 typedef struct efx_virtio_vq_s efx_virtio_vq_t;
4802 typedef enum efx_virtio_device_type_e {
4803 EFX_VIRTIO_DEVICE_TYPE_RESERVED,
4804 EFX_VIRTIO_DEVICE_TYPE_NET,
4805 EFX_VIRTIO_DEVICE_TYPE_BLOCK,
4806 EFX_VIRTIO_DEVICE_NTYPES
4807 } efx_virtio_device_type_t;
4810 extern __checkReturn efx_rc_t
4812 __in efx_nic_t *enp);
4817 __in efx_nic_t *enp);
4820 * When virtio net driver in the guest sets VIRTIO_CONFIG_STATUS_DRIVER_OK bit,
4821 * hypervisor starts configuring all the virtqueues in the device. When the
4822 * vhost_user has received VHOST_USER_SET_VRING_ENABLE for all the virtqueues,
4823 * then it invokes VDPA driver callback dev_conf. APIs qstart and qcreate would
4824 * be invoked from dev_conf callback to create the virtqueues, For further
4825 * details refer SF-122427.
4828 extern __checkReturn efx_rc_t
4830 __in efx_nic_t *enp,
4831 __deref_out efx_virtio_vq_t **evvpp);
4834 extern __checkReturn efx_rc_t
4836 __in efx_virtio_vq_t *evvp,
4837 __in efx_virtio_vq_cfg_t *evvcp,
4838 __in_opt efx_virtio_vq_dyncfg_t *evvdp);
4841 extern __checkReturn efx_rc_t
4843 __in efx_virtio_vq_t *evvp,
4844 __out_opt efx_virtio_vq_dyncfg_t *evvdp);
4848 efx_virtio_qdestroy(
4849 __in efx_virtio_vq_t *evvp);
4852 * Get the offset in the BAR of the doorbells for a VI.
4853 * net device : doorbell offset of RX & TX queues
4854 * block device : request doorbell offset in the BAR.
4855 * For further details refer section of 4 of SF-119689
4858 extern __checkReturn efx_rc_t
4859 efx_virtio_get_doorbell_offset(
4860 __in efx_virtio_vq_t *evvp,
4861 __out uint32_t *offsetp);
4864 extern __checkReturn efx_rc_t
4865 efx_virtio_get_features(
4866 __in efx_nic_t *enp,
4867 __in efx_virtio_device_type_t type,
4868 __out uint64_t *featuresp);
4871 extern __checkReturn efx_rc_t
4872 efx_virtio_verify_features(
4873 __in efx_nic_t *enp,
4874 __in efx_virtio_device_type_t type,
4875 __in uint64_t features);
4877 #endif /* EFSYS_OPT_VIRTIO */
4883 #endif /* _SYS_EFX_H */