1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
62 typedef enum efx_bar_type_e {
67 typedef struct efx_bar_region_s {
68 efx_bar_type_t ebr_type;
70 efsys_dma_addr_t ebr_offset;
71 efsys_dma_addr_t ebr_length;
74 /* The function is deprecated. It is used only if Riverhead is not supported. */
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
85 /* Determine EFX family and perform lookup of the function control window
87 * The function requires PCI config handle from which all memory bars can
89 * A user of the API must be aware of memory bars indexes (not available
93 extern __checkReturn efx_rc_t
97 __in efsys_pci_config_t *espcp,
98 __out efx_family_t *efp,
99 __out efx_bar_region_t *ebrp);
101 #endif /* EFSYS_OPT_PCI */
104 #define EFX_PCI_VENID_SFC 0x1924
105 #define EFX_PCI_VENID_XILINX 0x10EE
107 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
109 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
110 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
111 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
113 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
114 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
115 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
117 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
118 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
120 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
121 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
122 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
124 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
125 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
126 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
128 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
129 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
131 #define EFX_MEM_BAR_SIENA 2
133 #define EFX_MEM_BAR_HUNTINGTON_PF 2
134 #define EFX_MEM_BAR_HUNTINGTON_VF 0
136 #define EFX_MEM_BAR_MEDFORD_PF 2
137 #define EFX_MEM_BAR_MEDFORD_VF 0
139 #define EFX_MEM_BAR_MEDFORD2 0
141 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
142 #define EFX_MEM_BAR_RIVERHEAD 2
150 EFX_ERR_BUFID_DC_OOB,
163 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
165 extern __checkReturn uint32_t
167 __in uint32_t crc_init,
168 __in_ecount(length) uint8_t const *input,
172 /* Type prototypes */
174 typedef struct efx_rxq_s efx_rxq_t;
178 typedef struct efx_nic_s efx_nic_t;
181 extern __checkReturn efx_rc_t
183 __in efx_family_t family,
184 __in efsys_identifier_t *esip,
185 __in efsys_bar_t *esbp,
186 __in uint32_t fcw_offset,
187 __in efsys_lock_t *eslp,
188 __deref_out efx_nic_t **enpp);
190 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
191 typedef enum efx_fw_variant_e {
192 EFX_FW_VARIANT_FULL_FEATURED,
193 EFX_FW_VARIANT_LOW_LATENCY,
194 EFX_FW_VARIANT_PACKED_STREAM,
195 EFX_FW_VARIANT_HIGH_TX_RATE,
196 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
197 EFX_FW_VARIANT_RULES_ENGINE,
199 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
203 extern __checkReturn efx_rc_t
206 __in efx_fw_variant_t efv);
209 extern __checkReturn efx_rc_t
211 __in efx_nic_t *enp);
214 extern __checkReturn efx_rc_t
216 __in efx_nic_t *enp);
219 extern __checkReturn boolean_t
220 efx_nic_hw_unavailable(
221 __in efx_nic_t *enp);
225 efx_nic_set_hw_unavailable(
226 __in efx_nic_t *enp);
231 extern __checkReturn efx_rc_t
232 efx_nic_register_test(
233 __in efx_nic_t *enp);
235 #endif /* EFSYS_OPT_DIAG */
240 __in efx_nic_t *enp);
245 __in efx_nic_t *enp);
250 __in efx_nic_t *enp);
252 #define EFX_PCIE_LINK_SPEED_GEN1 1
253 #define EFX_PCIE_LINK_SPEED_GEN2 2
254 #define EFX_PCIE_LINK_SPEED_GEN3 3
256 typedef enum efx_pcie_link_performance_e {
257 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
258 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
259 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
260 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
261 } efx_pcie_link_performance_t;
264 extern __checkReturn efx_rc_t
265 efx_nic_calculate_pcie_link_bandwidth(
266 __in uint32_t pcie_link_width,
267 __in uint32_t pcie_link_gen,
268 __out uint32_t *bandwidth_mbpsp);
271 extern __checkReturn efx_rc_t
272 efx_nic_check_pcie_link_speed(
274 __in uint32_t pcie_link_width,
275 __in uint32_t pcie_link_gen,
276 __out efx_pcie_link_performance_t *resultp);
280 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
281 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
282 #define WITH_MCDI_V2 1
285 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
287 typedef enum efx_mcdi_exception_e {
288 EFX_MCDI_EXCEPTION_MC_REBOOT,
289 EFX_MCDI_EXCEPTION_MC_BADASSERT,
290 } efx_mcdi_exception_t;
292 #if EFSYS_OPT_MCDI_LOGGING
293 typedef enum efx_log_msg_e {
295 EFX_LOG_MCDI_REQUEST,
296 EFX_LOG_MCDI_RESPONSE,
298 #endif /* EFSYS_OPT_MCDI_LOGGING */
300 typedef struct efx_mcdi_transport_s {
302 efsys_mem_t *emt_dma_mem;
303 void (*emt_execute)(void *, efx_mcdi_req_t *);
304 void (*emt_ev_cpl)(void *);
305 void (*emt_exception)(void *, efx_mcdi_exception_t);
306 #if EFSYS_OPT_MCDI_LOGGING
307 void (*emt_logger)(void *, efx_log_msg_t,
308 void *, size_t, void *, size_t);
309 #endif /* EFSYS_OPT_MCDI_LOGGING */
310 #if EFSYS_OPT_MCDI_PROXY_AUTH
311 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
312 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
313 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
314 void (*emt_ev_proxy_request)(void *, uint32_t);
315 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
316 } efx_mcdi_transport_t;
319 extern __checkReturn efx_rc_t
322 __in const efx_mcdi_transport_t *mtp);
325 extern __checkReturn efx_rc_t
327 __in efx_nic_t *enp);
332 __in efx_nic_t *enp);
336 efx_mcdi_get_timeout(
338 __in efx_mcdi_req_t *emrp,
339 __out uint32_t *usec_timeoutp);
343 efx_mcdi_request_start(
345 __in efx_mcdi_req_t *emrp,
346 __in boolean_t ev_cpl);
349 extern __checkReturn boolean_t
350 efx_mcdi_request_poll(
351 __in efx_nic_t *enp);
354 extern __checkReturn boolean_t
355 efx_mcdi_request_abort(
356 __in efx_nic_t *enp);
361 __in efx_nic_t *enp);
363 #endif /* EFSYS_OPT_MCDI */
367 #define EFX_NINTR_SIENA 1024
369 typedef enum efx_intr_type_e {
370 EFX_INTR_INVALID = 0,
376 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
379 extern __checkReturn efx_rc_t
382 __in efx_intr_type_t type,
383 __in_opt efsys_mem_t *esmp);
388 __in efx_nic_t *enp);
393 __in efx_nic_t *enp);
397 efx_intr_disable_unlocked(
398 __in efx_nic_t *enp);
400 #define EFX_INTR_NEVQS 32
403 extern __checkReturn efx_rc_t
406 __in unsigned int level);
410 efx_intr_status_line(
412 __out boolean_t *fatalp,
413 __out uint32_t *maskp);
417 efx_intr_status_message(
419 __in unsigned int message,
420 __out boolean_t *fatalp);
425 __in efx_nic_t *enp);
430 __in efx_nic_t *enp);
434 #if EFSYS_OPT_MAC_STATS
436 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
437 typedef enum efx_mac_stat_e {
440 EFX_MAC_RX_UNICST_PKTS,
441 EFX_MAC_RX_MULTICST_PKTS,
442 EFX_MAC_RX_BRDCST_PKTS,
443 EFX_MAC_RX_PAUSE_PKTS,
444 EFX_MAC_RX_LE_64_PKTS,
445 EFX_MAC_RX_65_TO_127_PKTS,
446 EFX_MAC_RX_128_TO_255_PKTS,
447 EFX_MAC_RX_256_TO_511_PKTS,
448 EFX_MAC_RX_512_TO_1023_PKTS,
449 EFX_MAC_RX_1024_TO_15XX_PKTS,
450 EFX_MAC_RX_GE_15XX_PKTS,
452 EFX_MAC_RX_FCS_ERRORS,
453 EFX_MAC_RX_DROP_EVENTS,
454 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
455 EFX_MAC_RX_SYMBOL_ERRORS,
456 EFX_MAC_RX_ALIGN_ERRORS,
457 EFX_MAC_RX_INTERNAL_ERRORS,
458 EFX_MAC_RX_JABBER_PKTS,
459 EFX_MAC_RX_LANE0_CHAR_ERR,
460 EFX_MAC_RX_LANE1_CHAR_ERR,
461 EFX_MAC_RX_LANE2_CHAR_ERR,
462 EFX_MAC_RX_LANE3_CHAR_ERR,
463 EFX_MAC_RX_LANE0_DISP_ERR,
464 EFX_MAC_RX_LANE1_DISP_ERR,
465 EFX_MAC_RX_LANE2_DISP_ERR,
466 EFX_MAC_RX_LANE3_DISP_ERR,
467 EFX_MAC_RX_MATCH_FAULT,
468 EFX_MAC_RX_NODESC_DROP_CNT,
471 EFX_MAC_TX_UNICST_PKTS,
472 EFX_MAC_TX_MULTICST_PKTS,
473 EFX_MAC_TX_BRDCST_PKTS,
474 EFX_MAC_TX_PAUSE_PKTS,
475 EFX_MAC_TX_LE_64_PKTS,
476 EFX_MAC_TX_65_TO_127_PKTS,
477 EFX_MAC_TX_128_TO_255_PKTS,
478 EFX_MAC_TX_256_TO_511_PKTS,
479 EFX_MAC_TX_512_TO_1023_PKTS,
480 EFX_MAC_TX_1024_TO_15XX_PKTS,
481 EFX_MAC_TX_GE_15XX_PKTS,
483 EFX_MAC_TX_SGL_COL_PKTS,
484 EFX_MAC_TX_MULT_COL_PKTS,
485 EFX_MAC_TX_EX_COL_PKTS,
486 EFX_MAC_TX_LATE_COL_PKTS,
488 EFX_MAC_TX_EX_DEF_PKTS,
489 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
490 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
491 EFX_MAC_PM_TRUNC_VFIFO_FULL,
492 EFX_MAC_PM_DISCARD_VFIFO_FULL,
493 EFX_MAC_PM_TRUNC_QBB,
494 EFX_MAC_PM_DISCARD_QBB,
495 EFX_MAC_PM_DISCARD_MAPPING,
496 EFX_MAC_RXDP_Q_DISABLED_PKTS,
497 EFX_MAC_RXDP_DI_DROPPED_PKTS,
498 EFX_MAC_RXDP_STREAMING_PKTS,
499 EFX_MAC_RXDP_HLB_FETCH,
500 EFX_MAC_RXDP_HLB_WAIT,
501 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
502 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
503 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
504 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
505 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
506 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
507 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
508 EFX_MAC_VADAPTER_RX_BAD_BYTES,
509 EFX_MAC_VADAPTER_RX_OVERFLOW,
510 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
511 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
512 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
513 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
514 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
515 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
516 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
517 EFX_MAC_VADAPTER_TX_BAD_BYTES,
518 EFX_MAC_VADAPTER_TX_OVERFLOW,
519 EFX_MAC_FEC_UNCORRECTED_ERRORS,
520 EFX_MAC_FEC_CORRECTED_ERRORS,
521 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
522 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
523 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
524 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
525 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
526 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
527 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
528 EFX_MAC_CTPIO_OVERFLOW_FAIL,
529 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
530 EFX_MAC_CTPIO_TIMEOUT_FAIL,
531 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
532 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
533 EFX_MAC_CTPIO_INVALID_WR_FAIL,
534 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
535 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
536 EFX_MAC_CTPIO_RUNT_FALLBACK,
537 EFX_MAC_CTPIO_SUCCESS,
538 EFX_MAC_CTPIO_FALLBACK,
539 EFX_MAC_CTPIO_POISON,
541 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
542 EFX_MAC_RXDP_HLB_IDLE,
543 EFX_MAC_RXDP_HLB_TIMEOUT,
547 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
549 #endif /* EFSYS_OPT_MAC_STATS */
551 typedef enum efx_link_mode_e {
552 EFX_LINK_UNKNOWN = 0,
568 #define EFX_MAC_ADDR_LEN 6
570 #define EFX_VNI_OR_VSID_LEN 3
572 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
574 #define EFX_MAC_MULTICAST_LIST_MAX 256
576 #define EFX_MAC_SDU_MAX 9202
578 #define EFX_MAC_PDU_ADJUSTMENT \
582 + /* bug16011 */ 16) \
584 #define EFX_MAC_PDU(_sdu) \
585 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
588 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
589 * the SDU rounded up slightly.
591 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
593 #define EFX_MAC_PDU_MIN 60
594 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
597 extern __checkReturn efx_rc_t
603 extern __checkReturn efx_rc_t
609 extern __checkReturn efx_rc_t
615 extern __checkReturn efx_rc_t
618 __in boolean_t all_unicst,
619 __in boolean_t mulcst,
620 __in boolean_t all_mulcst,
621 __in boolean_t brdcst);
625 efx_mac_filter_get_all_ucast_mcast(
627 __out boolean_t *all_unicst,
628 __out boolean_t *all_mulcst);
631 extern __checkReturn efx_rc_t
632 efx_mac_multicast_list_set(
634 __in_ecount(6*count) uint8_t const *addrs,
638 extern __checkReturn efx_rc_t
639 efx_mac_filter_default_rxq_set(
642 __in boolean_t using_rss);
646 efx_mac_filter_default_rxq_clear(
647 __in efx_nic_t *enp);
650 extern __checkReturn efx_rc_t
653 __in boolean_t enabled);
656 extern __checkReturn efx_rc_t
659 __out boolean_t *mac_upp);
661 #define EFX_FCNTL_RESPOND 0x00000001
662 #define EFX_FCNTL_GENERATE 0x00000002
665 extern __checkReturn efx_rc_t
668 __in unsigned int fcntl,
669 __in boolean_t autoneg);
675 __out unsigned int *fcntl_wantedp,
676 __out unsigned int *fcntl_linkp);
679 #if EFSYS_OPT_MAC_STATS
684 extern __checkReturn const char *
687 __in unsigned int id);
689 #endif /* EFSYS_OPT_NAMES */
691 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
693 #define EFX_MAC_STATS_MASK_NPAGES \
694 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
695 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
696 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
699 * Get mask of MAC statistics supported by the hardware.
701 * If mask_size is insufficient to return the mask, EINVAL error is
702 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
703 * (which is sizeof (uint32_t)) is sufficient.
706 extern __checkReturn efx_rc_t
707 efx_mac_stats_get_mask(
709 __out_bcount(mask_size) uint32_t *maskp,
710 __in size_t mask_size);
712 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
713 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
714 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
718 extern __checkReturn efx_rc_t
720 __in efx_nic_t *enp);
723 * Upload mac statistics supported by the hardware into the given buffer.
725 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
726 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
728 * The hardware will only DMA statistics that it understands (of course).
729 * Drivers should not make any assumptions about which statistics are
730 * supported, especially when the statistics are generated by firmware.
732 * Thus, drivers should zero this buffer before use, so that not-understood
733 * statistics read back as zero.
736 extern __checkReturn efx_rc_t
737 efx_mac_stats_upload(
739 __in efsys_mem_t *esmp);
742 extern __checkReturn efx_rc_t
743 efx_mac_stats_periodic(
745 __in efsys_mem_t *esmp,
746 __in uint16_t period_ms,
747 __in boolean_t events);
750 extern __checkReturn efx_rc_t
751 efx_mac_stats_update(
753 __in efsys_mem_t *esmp,
754 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
755 __inout_opt uint32_t *generationp);
757 #endif /* EFSYS_OPT_MAC_STATS */
761 typedef enum efx_mon_type_e {
774 __in efx_nic_t *enp);
776 #endif /* EFSYS_OPT_NAMES */
779 extern __checkReturn efx_rc_t
781 __in efx_nic_t *enp);
783 #if EFSYS_OPT_MON_STATS
785 #define EFX_MON_STATS_PAGE_SIZE 0x100
786 #define EFX_MON_MASK_ELEMENT_SIZE 32
788 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
789 typedef enum efx_mon_stat_e {
790 EFX_MON_STAT_CONTROLLER_TEMP,
791 EFX_MON_STAT_PHY_COMMON_TEMP,
792 EFX_MON_STAT_CONTROLLER_COOLING,
793 EFX_MON_STAT_PHY0_TEMP,
794 EFX_MON_STAT_PHY0_COOLING,
795 EFX_MON_STAT_PHY1_TEMP,
796 EFX_MON_STAT_PHY1_COOLING,
802 EFX_MON_STAT_IN_12V0,
803 EFX_MON_STAT_IN_1V2A,
804 EFX_MON_STAT_IN_VREF,
805 EFX_MON_STAT_OUT_VAOE,
806 EFX_MON_STAT_AOE_TEMP,
807 EFX_MON_STAT_PSU_AOE_TEMP,
808 EFX_MON_STAT_PSU_TEMP,
814 EFX_MON_STAT_IN_VAOE,
815 EFX_MON_STAT_OUT_IAOE,
816 EFX_MON_STAT_IN_IAOE,
817 EFX_MON_STAT_NIC_POWER,
819 EFX_MON_STAT_IN_I0V9,
820 EFX_MON_STAT_IN_I1V2,
821 EFX_MON_STAT_IN_0V9_ADC,
822 EFX_MON_STAT_CONTROLLER_2_TEMP,
823 EFX_MON_STAT_VREG_INTERNAL_TEMP,
824 EFX_MON_STAT_VREG_0V9_TEMP,
825 EFX_MON_STAT_VREG_1V2_TEMP,
826 EFX_MON_STAT_CONTROLLER_VPTAT,
827 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
828 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
829 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
830 EFX_MON_STAT_AMBIENT_TEMP,
831 EFX_MON_STAT_AIRFLOW,
832 EFX_MON_STAT_VDD08D_VSS08D_CSR,
833 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
834 EFX_MON_STAT_HOTPOINT_TEMP,
835 EFX_MON_STAT_PHY_POWER_PORT0,
836 EFX_MON_STAT_PHY_POWER_PORT1,
837 EFX_MON_STAT_MUM_VCC,
838 EFX_MON_STAT_IN_0V9_A,
839 EFX_MON_STAT_IN_I0V9_A,
840 EFX_MON_STAT_VREG_0V9_A_TEMP,
841 EFX_MON_STAT_IN_0V9_B,
842 EFX_MON_STAT_IN_I0V9_B,
843 EFX_MON_STAT_VREG_0V9_B_TEMP,
844 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
845 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
846 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
847 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
848 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
849 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
850 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
851 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
852 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
853 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
854 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
855 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
856 EFX_MON_STAT_SODIMM_VOUT,
857 EFX_MON_STAT_SODIMM_0_TEMP,
858 EFX_MON_STAT_SODIMM_1_TEMP,
859 EFX_MON_STAT_PHY0_VCC,
860 EFX_MON_STAT_PHY1_VCC,
861 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
862 EFX_MON_STAT_BOARD_FRONT_TEMP,
863 EFX_MON_STAT_BOARD_BACK_TEMP,
864 EFX_MON_STAT_IN_I1V8,
865 EFX_MON_STAT_IN_I2V5,
866 EFX_MON_STAT_IN_I3V3,
867 EFX_MON_STAT_IN_I12V0,
869 EFX_MON_STAT_IN_I1V3,
873 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
875 typedef enum efx_mon_stat_state_e {
876 EFX_MON_STAT_STATE_OK = 0,
877 EFX_MON_STAT_STATE_WARNING = 1,
878 EFX_MON_STAT_STATE_FATAL = 2,
879 EFX_MON_STAT_STATE_BROKEN = 3,
880 EFX_MON_STAT_STATE_NO_READING = 4,
881 } efx_mon_stat_state_t;
883 typedef enum efx_mon_stat_unit_e {
884 EFX_MON_STAT_UNIT_UNKNOWN = 0,
885 EFX_MON_STAT_UNIT_BOOL,
886 EFX_MON_STAT_UNIT_TEMP_C,
887 EFX_MON_STAT_UNIT_VOLTAGE_MV,
888 EFX_MON_STAT_UNIT_CURRENT_MA,
889 EFX_MON_STAT_UNIT_POWER_W,
890 EFX_MON_STAT_UNIT_RPM,
892 } efx_mon_stat_unit_t;
894 typedef struct efx_mon_stat_value_s {
896 efx_mon_stat_state_t emsv_state;
897 efx_mon_stat_unit_t emsv_unit;
898 } efx_mon_stat_value_t;
900 typedef struct efx_mon_limit_value_s {
901 uint16_t emlv_warning_min;
902 uint16_t emlv_warning_max;
903 uint16_t emlv_fatal_min;
904 uint16_t emlv_fatal_max;
905 } efx_mon_stat_limits_t;
907 typedef enum efx_mon_stat_portmask_e {
908 EFX_MON_STAT_PORTMAP_NONE = 0,
909 EFX_MON_STAT_PORTMAP_PORT0 = 1,
910 EFX_MON_STAT_PORTMAP_PORT1 = 2,
911 EFX_MON_STAT_PORTMAP_PORT2 = 3,
912 EFX_MON_STAT_PORTMAP_PORT3 = 4,
913 EFX_MON_STAT_PORTMAP_ALL = (-1),
914 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
915 } efx_mon_stat_portmask_t;
923 __in efx_mon_stat_t id);
927 efx_mon_stat_description(
929 __in efx_mon_stat_t id);
931 #endif /* EFSYS_OPT_NAMES */
934 extern __checkReturn boolean_t
935 efx_mon_mcdi_to_efx_stat(
937 __out efx_mon_stat_t *statp);
940 extern __checkReturn boolean_t
941 efx_mon_get_stat_unit(
942 __in efx_mon_stat_t stat,
943 __out efx_mon_stat_unit_t *unitp);
946 extern __checkReturn boolean_t
947 efx_mon_get_stat_portmap(
948 __in efx_mon_stat_t stat,
949 __out efx_mon_stat_portmask_t *maskp);
952 extern __checkReturn efx_rc_t
953 efx_mon_stats_update(
955 __in efsys_mem_t *esmp,
956 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
959 extern __checkReturn efx_rc_t
960 efx_mon_limits_update(
962 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
964 #endif /* EFSYS_OPT_MON_STATS */
969 __in efx_nic_t *enp);
974 extern __checkReturn efx_rc_t
976 __in efx_nic_t *enp);
978 #if EFSYS_OPT_PHY_LED_CONTROL
980 typedef enum efx_phy_led_mode_e {
981 EFX_PHY_LED_DEFAULT = 0,
986 } efx_phy_led_mode_t;
989 extern __checkReturn efx_rc_t
992 __in efx_phy_led_mode_t mode);
994 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
997 extern __checkReturn efx_rc_t
999 __in efx_nic_t *enp);
1001 #if EFSYS_OPT_LOOPBACK
1003 typedef enum efx_loopback_type_e {
1004 EFX_LOOPBACK_OFF = 0,
1005 EFX_LOOPBACK_DATA = 1,
1006 EFX_LOOPBACK_GMAC = 2,
1007 EFX_LOOPBACK_XGMII = 3,
1008 EFX_LOOPBACK_XGXS = 4,
1009 EFX_LOOPBACK_XAUI = 5,
1010 EFX_LOOPBACK_GMII = 6,
1011 EFX_LOOPBACK_SGMII = 7,
1012 EFX_LOOPBACK_XGBR = 8,
1013 EFX_LOOPBACK_XFI = 9,
1014 EFX_LOOPBACK_XAUI_FAR = 10,
1015 EFX_LOOPBACK_GMII_FAR = 11,
1016 EFX_LOOPBACK_SGMII_FAR = 12,
1017 EFX_LOOPBACK_XFI_FAR = 13,
1018 EFX_LOOPBACK_GPHY = 14,
1019 EFX_LOOPBACK_PHY_XS = 15,
1020 EFX_LOOPBACK_PCS = 16,
1021 EFX_LOOPBACK_PMA_PMD = 17,
1022 EFX_LOOPBACK_XPORT = 18,
1023 EFX_LOOPBACK_XGMII_WS = 19,
1024 EFX_LOOPBACK_XAUI_WS = 20,
1025 EFX_LOOPBACK_XAUI_WS_FAR = 21,
1026 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
1027 EFX_LOOPBACK_GMII_WS = 23,
1028 EFX_LOOPBACK_XFI_WS = 24,
1029 EFX_LOOPBACK_XFI_WS_FAR = 25,
1030 EFX_LOOPBACK_PHYXS_WS = 26,
1031 EFX_LOOPBACK_PMA_INT = 27,
1032 EFX_LOOPBACK_SD_NEAR = 28,
1033 EFX_LOOPBACK_SD_FAR = 29,
1034 EFX_LOOPBACK_PMA_INT_WS = 30,
1035 EFX_LOOPBACK_SD_FEP2_WS = 31,
1036 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1037 EFX_LOOPBACK_SD_FEP_WS = 33,
1038 EFX_LOOPBACK_SD_FES_WS = 34,
1039 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1040 EFX_LOOPBACK_DATA_WS = 36,
1041 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1043 } efx_loopback_type_t;
1045 typedef enum efx_loopback_kind_e {
1046 EFX_LOOPBACK_KIND_OFF = 0,
1047 EFX_LOOPBACK_KIND_ALL,
1048 EFX_LOOPBACK_KIND_MAC,
1049 EFX_LOOPBACK_KIND_PHY,
1051 } efx_loopback_kind_t;
1056 __in efx_loopback_kind_t loopback_kind,
1057 __out efx_qword_t *maskp);
1060 extern __checkReturn efx_rc_t
1061 efx_port_loopback_set(
1062 __in efx_nic_t *enp,
1063 __in efx_link_mode_t link_mode,
1064 __in efx_loopback_type_t type);
1069 extern __checkReturn const char *
1070 efx_loopback_type_name(
1071 __in efx_nic_t *enp,
1072 __in efx_loopback_type_t type);
1074 #endif /* EFSYS_OPT_NAMES */
1076 #endif /* EFSYS_OPT_LOOPBACK */
1079 extern __checkReturn efx_rc_t
1081 __in efx_nic_t *enp,
1082 __out_opt efx_link_mode_t *link_modep);
1087 __in efx_nic_t *enp);
1089 typedef enum efx_phy_cap_type_e {
1090 EFX_PHY_CAP_INVALID = 0,
1095 EFX_PHY_CAP_1000HDX,
1096 EFX_PHY_CAP_1000FDX,
1097 EFX_PHY_CAP_10000FDX,
1101 EFX_PHY_CAP_40000FDX,
1103 EFX_PHY_CAP_100000FDX,
1104 EFX_PHY_CAP_25000FDX,
1105 EFX_PHY_CAP_50000FDX,
1106 EFX_PHY_CAP_BASER_FEC,
1107 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1109 EFX_PHY_CAP_RS_FEC_REQUESTED,
1110 EFX_PHY_CAP_25G_BASER_FEC,
1111 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1113 } efx_phy_cap_type_t;
1116 #define EFX_PHY_CAP_CURRENT 0x00000000
1117 #define EFX_PHY_CAP_DEFAULT 0x00000001
1118 #define EFX_PHY_CAP_PERM 0x00000002
1122 efx_phy_adv_cap_get(
1123 __in efx_nic_t *enp,
1125 __out uint32_t *maskp);
1128 extern __checkReturn efx_rc_t
1129 efx_phy_adv_cap_set(
1130 __in efx_nic_t *enp,
1131 __in uint32_t mask);
1136 __in efx_nic_t *enp,
1137 __out uint32_t *maskp);
1140 extern __checkReturn efx_rc_t
1142 __in efx_nic_t *enp,
1143 __out uint32_t *ouip);
1145 typedef enum efx_phy_media_type_e {
1146 EFX_PHY_MEDIA_INVALID = 0,
1151 EFX_PHY_MEDIA_SFP_PLUS,
1152 EFX_PHY_MEDIA_BASE_T,
1153 EFX_PHY_MEDIA_QSFP_PLUS,
1154 EFX_PHY_MEDIA_NTYPES
1155 } efx_phy_media_type_t;
1158 * Get the type of medium currently used. If the board has ports for
1159 * modules, a module is present, and we recognise the media type of
1160 * the module, then this will be the media type of the module.
1161 * Otherwise it will be the media type of the port.
1165 efx_phy_media_type_get(
1166 __in efx_nic_t *enp,
1167 __out efx_phy_media_type_t *typep);
1170 * 2-wire device address of the base information in accordance with SFF-8472
1171 * Diagnostic Monitoring Interface for Optical Transceivers section
1172 * 4 Memory Organization.
1174 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1177 * 2-wire device address of the digital diagnostics monitoring interface
1178 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1179 * Transceivers section 4 Memory Organization.
1181 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1184 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1185 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1188 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1191 * Maximum accessible data offset for PHY module information.
1193 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1197 extern __checkReturn efx_rc_t
1198 efx_phy_module_get_info(
1199 __in efx_nic_t *enp,
1200 __in uint8_t dev_addr,
1203 __out_bcount(len) uint8_t *data);
1205 #if EFSYS_OPT_PHY_STATS
1207 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1208 typedef enum efx_phy_stat_e {
1210 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1211 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1212 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1213 EFX_PHY_STAT_PMA_PMD_REV_A,
1214 EFX_PHY_STAT_PMA_PMD_REV_B,
1215 EFX_PHY_STAT_PMA_PMD_REV_C,
1216 EFX_PHY_STAT_PMA_PMD_REV_D,
1217 EFX_PHY_STAT_PCS_LINK_UP,
1218 EFX_PHY_STAT_PCS_RX_FAULT,
1219 EFX_PHY_STAT_PCS_TX_FAULT,
1220 EFX_PHY_STAT_PCS_BER,
1221 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1222 EFX_PHY_STAT_PHY_XS_LINK_UP,
1223 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1224 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1225 EFX_PHY_STAT_PHY_XS_ALIGN,
1226 EFX_PHY_STAT_PHY_XS_SYNC_A,
1227 EFX_PHY_STAT_PHY_XS_SYNC_B,
1228 EFX_PHY_STAT_PHY_XS_SYNC_C,
1229 EFX_PHY_STAT_PHY_XS_SYNC_D,
1230 EFX_PHY_STAT_AN_LINK_UP,
1231 EFX_PHY_STAT_AN_MASTER,
1232 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1233 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1234 EFX_PHY_STAT_CL22EXT_LINK_UP,
1239 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1240 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1241 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1242 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1243 EFX_PHY_STAT_AN_COMPLETE,
1244 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1245 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1246 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1247 EFX_PHY_STAT_PCS_FW_VERSION_0,
1248 EFX_PHY_STAT_PCS_FW_VERSION_1,
1249 EFX_PHY_STAT_PCS_FW_VERSION_2,
1250 EFX_PHY_STAT_PCS_FW_VERSION_3,
1251 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1252 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1253 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1254 EFX_PHY_STAT_PCS_OP_MODE,
1258 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1265 __in efx_nic_t *enp,
1266 __in efx_phy_stat_t stat);
1268 #endif /* EFSYS_OPT_NAMES */
1270 #define EFX_PHY_STATS_SIZE 0x100
1273 extern __checkReturn efx_rc_t
1274 efx_phy_stats_update(
1275 __in efx_nic_t *enp,
1276 __in efsys_mem_t *esmp,
1277 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1279 #endif /* EFSYS_OPT_PHY_STATS */
1284 typedef enum efx_bist_type_e {
1285 EFX_BIST_TYPE_UNKNOWN,
1286 EFX_BIST_TYPE_PHY_NORMAL,
1287 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1288 EFX_BIST_TYPE_PHY_CABLE_LONG,
1289 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1290 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1291 EFX_BIST_TYPE_REG, /* Test the register memories */
1292 EFX_BIST_TYPE_NTYPES,
1295 typedef enum efx_bist_result_e {
1296 EFX_BIST_RESULT_UNKNOWN,
1297 EFX_BIST_RESULT_RUNNING,
1298 EFX_BIST_RESULT_PASSED,
1299 EFX_BIST_RESULT_FAILED,
1300 } efx_bist_result_t;
1302 typedef enum efx_phy_cable_status_e {
1303 EFX_PHY_CABLE_STATUS_OK,
1304 EFX_PHY_CABLE_STATUS_INVALID,
1305 EFX_PHY_CABLE_STATUS_OPEN,
1306 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1307 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1308 EFX_PHY_CABLE_STATUS_BUSY,
1309 } efx_phy_cable_status_t;
1311 typedef enum efx_bist_value_e {
1312 EFX_BIST_PHY_CABLE_LENGTH_A,
1313 EFX_BIST_PHY_CABLE_LENGTH_B,
1314 EFX_BIST_PHY_CABLE_LENGTH_C,
1315 EFX_BIST_PHY_CABLE_LENGTH_D,
1316 EFX_BIST_PHY_CABLE_STATUS_A,
1317 EFX_BIST_PHY_CABLE_STATUS_B,
1318 EFX_BIST_PHY_CABLE_STATUS_C,
1319 EFX_BIST_PHY_CABLE_STATUS_D,
1320 EFX_BIST_FAULT_CODE,
1322 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1328 EFX_BIST_MEM_EXPECT,
1329 EFX_BIST_MEM_ACTUAL,
1331 EFX_BIST_MEM_ECC_PARITY,
1332 EFX_BIST_MEM_ECC_FATAL,
1337 extern __checkReturn efx_rc_t
1338 efx_bist_enable_offline(
1339 __in efx_nic_t *enp);
1342 extern __checkReturn efx_rc_t
1344 __in efx_nic_t *enp,
1345 __in efx_bist_type_t type);
1348 extern __checkReturn efx_rc_t
1350 __in efx_nic_t *enp,
1351 __in efx_bist_type_t type,
1352 __out efx_bist_result_t *resultp,
1353 __out_opt uint32_t *value_maskp,
1354 __out_ecount_opt(count) unsigned long *valuesp,
1360 __in efx_nic_t *enp,
1361 __in efx_bist_type_t type);
1363 #endif /* EFSYS_OPT_BIST */
1365 #define EFX_FEATURE_IPV6 0x00000001
1366 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1367 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1368 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1369 #define EFX_FEATURE_MCDI 0x00000020
1370 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1371 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1372 #define EFX_FEATURE_TURBO 0x00000100
1373 #define EFX_FEATURE_MCDI_DMA 0x00000200
1374 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1375 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1376 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1377 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1378 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1379 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1381 typedef enum efx_tunnel_protocol_e {
1382 EFX_TUNNEL_PROTOCOL_NONE = 0,
1383 EFX_TUNNEL_PROTOCOL_VXLAN,
1384 EFX_TUNNEL_PROTOCOL_GENEVE,
1385 EFX_TUNNEL_PROTOCOL_NVGRE,
1387 } efx_tunnel_protocol_t;
1389 typedef enum efx_vi_window_shift_e {
1390 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1391 EFX_VI_WINDOW_SHIFT_8K = 13,
1392 EFX_VI_WINDOW_SHIFT_16K = 14,
1393 EFX_VI_WINDOW_SHIFT_64K = 16,
1394 } efx_vi_window_shift_t;
1396 typedef struct efx_nic_cfg_s {
1397 uint32_t enc_board_type;
1398 uint32_t enc_phy_type;
1400 char enc_phy_name[21];
1402 char enc_phy_revision[21];
1403 efx_mon_type_t enc_mon_type;
1404 #if EFSYS_OPT_MON_STATS
1405 uint32_t enc_mon_stat_dma_buf_size;
1406 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1408 unsigned int enc_features;
1409 efx_vi_window_shift_t enc_vi_window_shift;
1410 uint8_t enc_mac_addr[6];
1411 uint8_t enc_port; /* PHY port number */
1412 uint32_t enc_intr_vec_base;
1413 uint32_t enc_intr_limit;
1414 uint32_t enc_evq_limit;
1415 uint32_t enc_txq_limit;
1416 uint32_t enc_rxq_limit;
1417 uint32_t enc_evq_max_nevs;
1418 uint32_t enc_evq_min_nevs;
1419 uint32_t enc_rxq_max_ndescs;
1420 uint32_t enc_rxq_min_ndescs;
1421 uint32_t enc_txq_max_ndescs;
1422 uint32_t enc_txq_min_ndescs;
1423 uint32_t enc_buftbl_limit;
1424 uint32_t enc_piobuf_limit;
1425 uint32_t enc_piobuf_size;
1426 uint32_t enc_piobuf_min_alloc_size;
1427 uint32_t enc_evq_timer_quantum_ns;
1428 uint32_t enc_evq_timer_max_us;
1429 uint32_t enc_clk_mult;
1430 uint32_t enc_ev_desc_size;
1431 uint32_t enc_rx_desc_size;
1432 uint32_t enc_tx_desc_size;
1433 /* Maximum Rx prefix size if many Rx prefixes are supported */
1434 uint32_t enc_rx_prefix_size;
1435 uint32_t enc_rx_buf_align_start;
1436 uint32_t enc_rx_buf_align_end;
1437 #if EFSYS_OPT_RX_SCALE
1438 uint32_t enc_rx_scale_max_exclusive_contexts;
1440 * Mask of supported hash algorithms.
1441 * Hash algorithm types are used as the bit indices.
1443 uint32_t enc_rx_scale_hash_alg_mask;
1445 * Indicates whether port numbers can be included to the
1446 * input data for hash computation.
1448 boolean_t enc_rx_scale_l4_hash_supported;
1449 boolean_t enc_rx_scale_additional_modes_supported;
1450 #endif /* EFSYS_OPT_RX_SCALE */
1451 #if EFSYS_OPT_LOOPBACK
1452 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1453 #endif /* EFSYS_OPT_LOOPBACK */
1454 #if EFSYS_OPT_PHY_FLAGS
1455 uint32_t enc_phy_flags_mask;
1456 #endif /* EFSYS_OPT_PHY_FLAGS */
1457 #if EFSYS_OPT_PHY_LED_CONTROL
1458 uint32_t enc_led_mask;
1459 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1460 #if EFSYS_OPT_PHY_STATS
1461 uint64_t enc_phy_stat_mask;
1462 #endif /* EFSYS_OPT_PHY_STATS */
1464 uint8_t enc_mcdi_mdio_channel;
1465 #if EFSYS_OPT_PHY_STATS
1466 uint32_t enc_mcdi_phy_stat_mask;
1467 #endif /* EFSYS_OPT_PHY_STATS */
1468 #if EFSYS_OPT_MON_STATS
1469 uint32_t *enc_mcdi_sensor_maskp;
1470 uint32_t enc_mcdi_sensor_mask_size;
1471 #endif /* EFSYS_OPT_MON_STATS */
1472 #endif /* EFSYS_OPT_MCDI */
1474 uint32_t enc_bist_mask;
1475 #endif /* EFSYS_OPT_BIST */
1476 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1479 uint32_t enc_privilege_mask;
1480 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1481 boolean_t enc_evq_init_done_ev_supported;
1482 boolean_t enc_bug26807_workaround;
1483 boolean_t enc_bug35388_workaround;
1484 boolean_t enc_bug41750_workaround;
1485 boolean_t enc_bug61265_workaround;
1486 boolean_t enc_bug61297_workaround;
1487 boolean_t enc_rx_batching_enabled;
1488 /* Maximum number of descriptors completed in an rx event. */
1489 uint32_t enc_rx_batch_max;
1490 /* Number of rx descriptors the hardware requires for a push. */
1491 uint32_t enc_rx_push_align;
1492 /* Maximum amount of data in DMA descriptor */
1493 uint32_t enc_tx_dma_desc_size_max;
1495 * Boundary which DMA descriptor data must not cross or 0 if no
1498 uint32_t enc_tx_dma_desc_boundary;
1500 * Maximum number of bytes into the packet the TCP header can start for
1501 * the hardware to apply TSO packet edits.
1503 uint32_t enc_tx_tso_tcp_header_offset_limit;
1504 /* Maximum number of header DMA descriptors per TSO transaction. */
1505 uint32_t enc_tx_tso_max_header_ndescs;
1506 /* Maximum header length acceptable by TSO transaction. */
1507 uint32_t enc_tx_tso_max_header_length;
1508 /* Maximum number of payload DMA descriptors per TSO transaction. */
1509 uint32_t enc_tx_tso_max_payload_ndescs;
1510 /* Maximum payload length per TSO transaction. */
1511 uint32_t enc_tx_tso_max_payload_length;
1512 /* Maximum number of frames to be generated per TSO transaction. */
1513 uint32_t enc_tx_tso_max_nframes;
1514 boolean_t enc_fw_assisted_tso_enabled;
1515 boolean_t enc_fw_assisted_tso_v2_enabled;
1516 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1517 boolean_t enc_tso_v3_enabled;
1518 /* Number of TSO contexts on the NIC (FATSOv2) */
1519 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1520 boolean_t enc_hw_tx_insert_vlan_enabled;
1521 /* Number of PFs on the NIC */
1522 uint32_t enc_hw_pf_count;
1523 /* Datapath firmware vadapter/vport/vswitch support */
1524 boolean_t enc_datapath_cap_evb;
1525 /* Datapath firmware vport reconfigure support */
1526 boolean_t enc_vport_reconfigure_supported;
1527 boolean_t enc_rx_disable_scatter_supported;
1528 boolean_t enc_allow_set_mac_with_installed_filters;
1529 boolean_t enc_enhanced_set_mac_supported;
1530 boolean_t enc_init_evq_v2_supported;
1531 boolean_t enc_no_cont_ev_mode_supported;
1532 boolean_t enc_init_rxq_with_buffer_size;
1533 boolean_t enc_rx_packed_stream_supported;
1534 boolean_t enc_rx_var_packed_stream_supported;
1535 boolean_t enc_rx_es_super_buffer_supported;
1536 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1537 boolean_t enc_pm_and_rxdp_counters;
1538 boolean_t enc_mac_stats_40g_tx_size_bins;
1539 uint32_t enc_tunnel_encapsulations_supported;
1541 * NIC global maximum for unique UDP tunnel ports shared by all
1544 uint32_t enc_tunnel_config_udp_entries_max;
1545 /* External port identifier */
1546 uint8_t enc_external_port;
1547 uint32_t enc_mcdi_max_payload_length;
1548 /* VPD may be per-PF or global */
1549 boolean_t enc_vpd_is_global;
1550 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1551 uint32_t enc_required_pcie_bandwidth_mbps;
1552 uint32_t enc_max_pcie_link_gen;
1553 /* Firmware verifies integrity of NVRAM updates */
1554 boolean_t enc_nvram_update_verify_result_supported;
1555 /* Firmware supports polled NVRAM updates on select partitions */
1556 boolean_t enc_nvram_update_poll_verify_result_supported;
1557 /* Firmware accepts updates via the BUNDLE partition */
1558 boolean_t enc_nvram_bundle_update_supported;
1559 /* Firmware support for extended MAC_STATS buffer */
1560 uint32_t enc_mac_stats_nstats;
1561 boolean_t enc_fec_counters;
1562 boolean_t enc_hlb_counters;
1563 /* Firmware support for "FLAG" and "MARK" filter actions */
1564 boolean_t enc_filter_action_flag_supported;
1565 boolean_t enc_filter_action_mark_supported;
1566 uint32_t enc_filter_action_mark_max;
1567 /* Port assigned to this PCI function */
1568 uint32_t enc_assigned_port;
1571 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1572 ((configp)->evc_function == 0xffff)
1574 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1575 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1577 #define EFX_PCI_FUNCTION(_encp) \
1578 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1580 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1583 extern const efx_nic_cfg_t *
1585 __in const efx_nic_t *enp);
1587 /* RxDPCPU firmware id values by which FW variant can be identified */
1588 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1589 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1590 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1591 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1592 #define EFX_RXDP_DPDK_FW_ID 0x6
1594 typedef struct efx_nic_fw_info_s {
1595 /* Basic FW version information */
1596 uint16_t enfi_mc_fw_version[4];
1598 * If datapath capabilities can be detected,
1599 * additional FW information is to be shown
1601 boolean_t enfi_dpcpu_fw_ids_valid;
1602 /* Rx and Tx datapath CPU FW IDs */
1603 uint16_t enfi_rx_dpcpu_fw_id;
1604 uint16_t enfi_tx_dpcpu_fw_id;
1605 } efx_nic_fw_info_t;
1608 extern __checkReturn efx_rc_t
1609 efx_nic_get_fw_version(
1610 __in efx_nic_t *enp,
1611 __out efx_nic_fw_info_t *enfip);
1613 /* Driver resource limits (minimum required/maximum usable). */
1614 typedef struct efx_drv_limits_s {
1615 uint32_t edl_min_evq_count;
1616 uint32_t edl_max_evq_count;
1618 uint32_t edl_min_rxq_count;
1619 uint32_t edl_max_rxq_count;
1621 uint32_t edl_min_txq_count;
1622 uint32_t edl_max_txq_count;
1624 /* PIO blocks (sub-allocated from piobuf) */
1625 uint32_t edl_min_pio_alloc_size;
1626 uint32_t edl_max_pio_alloc_count;
1630 extern __checkReturn efx_rc_t
1631 efx_nic_set_drv_limits(
1632 __inout efx_nic_t *enp,
1633 __in efx_drv_limits_t *edlp);
1636 * Register the OS driver version string for management agents
1637 * (e.g. via NC-SI). The content length is provided (i.e. no
1638 * NUL terminator). Use length 0 to indicate no version string
1639 * should be advertised. It is valid to set the version string
1640 * only before efx_nic_probe() is called.
1643 extern __checkReturn efx_rc_t
1644 efx_nic_set_drv_version(
1645 __inout efx_nic_t *enp,
1646 __in_ecount(length) char const *verp,
1647 __in size_t length);
1649 typedef enum efx_nic_region_e {
1650 EFX_REGION_VI, /* Memory BAR UC mapping */
1651 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1655 extern __checkReturn efx_rc_t
1656 efx_nic_get_bar_region(
1657 __in efx_nic_t *enp,
1658 __in efx_nic_region_t region,
1659 __out uint32_t *offsetp,
1660 __out size_t *sizep);
1663 extern __checkReturn efx_rc_t
1664 efx_nic_get_vi_pool(
1665 __in efx_nic_t *enp,
1666 __out uint32_t *evq_countp,
1667 __out uint32_t *rxq_countp,
1668 __out uint32_t *txq_countp);
1673 typedef enum efx_vpd_tag_e {
1680 typedef uint16_t efx_vpd_keyword_t;
1682 typedef struct efx_vpd_value_s {
1683 efx_vpd_tag_t evv_tag;
1684 efx_vpd_keyword_t evv_keyword;
1686 uint8_t evv_value[0x100];
1690 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1693 extern __checkReturn efx_rc_t
1695 __in efx_nic_t *enp);
1698 extern __checkReturn efx_rc_t
1700 __in efx_nic_t *enp,
1701 __out size_t *sizep);
1704 extern __checkReturn efx_rc_t
1706 __in efx_nic_t *enp,
1707 __out_bcount(size) caddr_t data,
1711 extern __checkReturn efx_rc_t
1713 __in efx_nic_t *enp,
1714 __in_bcount(size) caddr_t data,
1718 extern __checkReturn efx_rc_t
1720 __in efx_nic_t *enp,
1721 __in_bcount(size) caddr_t data,
1725 extern __checkReturn efx_rc_t
1727 __in efx_nic_t *enp,
1728 __in_bcount(size) caddr_t data,
1730 __inout efx_vpd_value_t *evvp);
1733 extern __checkReturn efx_rc_t
1735 __in efx_nic_t *enp,
1736 __inout_bcount(size) caddr_t data,
1738 __in efx_vpd_value_t *evvp);
1741 extern __checkReturn efx_rc_t
1743 __in efx_nic_t *enp,
1744 __inout_bcount(size) caddr_t data,
1746 __out efx_vpd_value_t *evvp,
1747 __inout unsigned int *contp);
1750 extern __checkReturn efx_rc_t
1752 __in efx_nic_t *enp,
1753 __in_bcount(size) caddr_t data,
1759 __in efx_nic_t *enp);
1761 #endif /* EFSYS_OPT_VPD */
1767 typedef enum efx_nvram_type_e {
1768 EFX_NVRAM_INVALID = 0,
1770 EFX_NVRAM_BOOTROM_CFG,
1771 EFX_NVRAM_MC_FIRMWARE,
1772 EFX_NVRAM_MC_GOLDEN,
1778 EFX_NVRAM_FPGA_BACKUP,
1779 EFX_NVRAM_DYNAMIC_CFG,
1782 EFX_NVRAM_MUM_FIRMWARE,
1783 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1784 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1786 EFX_NVRAM_BUNDLE_METADATA,
1790 typedef struct efx_nvram_info_s {
1792 uint32_t eni_partn_size;
1793 uint32_t eni_address;
1794 uint32_t eni_erase_size;
1795 uint32_t eni_write_size;
1798 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1801 extern __checkReturn efx_rc_t
1803 __in efx_nic_t *enp);
1808 extern __checkReturn efx_rc_t
1810 __in efx_nic_t *enp);
1812 #endif /* EFSYS_OPT_DIAG */
1815 extern __checkReturn efx_rc_t
1817 __in efx_nic_t *enp,
1818 __in efx_nvram_type_t type,
1819 __out size_t *sizep);
1822 extern __checkReturn efx_rc_t
1824 __in efx_nic_t *enp,
1825 __in efx_nvram_type_t type,
1826 __out efx_nvram_info_t *enip);
1829 extern __checkReturn efx_rc_t
1831 __in efx_nic_t *enp,
1832 __in efx_nvram_type_t type,
1833 __out_opt size_t *pref_chunkp);
1836 extern __checkReturn efx_rc_t
1837 efx_nvram_rw_finish(
1838 __in efx_nic_t *enp,
1839 __in efx_nvram_type_t type,
1840 __out_opt uint32_t *verify_resultp);
1843 extern __checkReturn efx_rc_t
1844 efx_nvram_get_version(
1845 __in efx_nic_t *enp,
1846 __in efx_nvram_type_t type,
1847 __out uint32_t *subtypep,
1848 __out_ecount(4) uint16_t version[4]);
1851 extern __checkReturn efx_rc_t
1852 efx_nvram_read_chunk(
1853 __in efx_nic_t *enp,
1854 __in efx_nvram_type_t type,
1855 __in unsigned int offset,
1856 __out_bcount(size) caddr_t data,
1860 extern __checkReturn efx_rc_t
1861 efx_nvram_read_backup(
1862 __in efx_nic_t *enp,
1863 __in efx_nvram_type_t type,
1864 __in unsigned int offset,
1865 __out_bcount(size) caddr_t data,
1869 extern __checkReturn efx_rc_t
1870 efx_nvram_set_version(
1871 __in efx_nic_t *enp,
1872 __in efx_nvram_type_t type,
1873 __in_ecount(4) uint16_t version[4]);
1876 extern __checkReturn efx_rc_t
1878 __in efx_nic_t *enp,
1879 __in efx_nvram_type_t type,
1880 __in_bcount(partn_size) caddr_t partn_data,
1881 __in size_t partn_size);
1884 extern __checkReturn efx_rc_t
1886 __in efx_nic_t *enp,
1887 __in efx_nvram_type_t type);
1890 extern __checkReturn efx_rc_t
1891 efx_nvram_write_chunk(
1892 __in efx_nic_t *enp,
1893 __in efx_nvram_type_t type,
1894 __in unsigned int offset,
1895 __in_bcount(size) caddr_t data,
1901 __in efx_nic_t *enp);
1903 #endif /* EFSYS_OPT_NVRAM */
1905 #if EFSYS_OPT_BOOTCFG
1907 /* Report size and offset of bootcfg sector in NVRAM partition. */
1909 extern __checkReturn efx_rc_t
1910 efx_bootcfg_sector_info(
1911 __in efx_nic_t *enp,
1913 __out_opt uint32_t *sector_countp,
1914 __out size_t *offsetp,
1915 __out size_t *max_sizep);
1918 * Copy bootcfg sector data to a target buffer which may differ in size.
1919 * Optionally corrects format errors in source buffer.
1923 efx_bootcfg_copy_sector(
1924 __in efx_nic_t *enp,
1925 __inout_bcount(sector_length)
1927 __in size_t sector_length,
1928 __out_bcount(data_size) uint8_t *data,
1929 __in size_t data_size,
1930 __in boolean_t handle_format_errors);
1935 __in efx_nic_t *enp,
1936 __out_bcount(size) uint8_t *data,
1942 __in efx_nic_t *enp,
1943 __in_bcount(size) uint8_t *data,
1948 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1949 * (see https://tools.ietf.org/html/rfc1533)
1951 * Summarising the format: the buffer is a sequence of options. All options
1952 * begin with a tag octet, which uniquely identifies the option. Fixed-
1953 * length options without data consist of only a tag octet. Only options PAD
1954 * (0) and END (255) are fixed length. All other options are variable-length
1955 * with a length octet following the tag octet. The value of the length
1956 * octet does not include the two octets specifying the tag and length. The
1957 * length octet is followed by "length" octets of data.
1959 * Option data may be a sequence of sub-options in the same format. The data
1960 * content of the encapsulating option is one or more encapsulated sub-options,
1961 * with no terminating END tag is required.
1963 * To be valid, the top-level sequence of options should be terminated by an
1964 * END tag. The buffer should be padded with the PAD byte.
1966 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1967 * checksum octet. The full buffer (including after the END tag) contributes
1968 * to the checksum, hence the need to fill the buffer to the end with PAD.
1971 #define EFX_DHCP_END ((uint8_t)0xff)
1972 #define EFX_DHCP_PAD ((uint8_t)0)
1974 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1975 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1978 extern __checkReturn uint8_t
1980 __in_bcount(size) uint8_t const *data,
1984 extern __checkReturn efx_rc_t
1986 __in_bcount(size) uint8_t const *data,
1988 __out_opt size_t *usedp);
1991 extern __checkReturn efx_rc_t
1993 __in_bcount(buffer_length) uint8_t *bufferp,
1994 __in size_t buffer_length,
1996 __deref_out uint8_t **valuepp,
1997 __out size_t *value_lengthp);
2000 extern __checkReturn efx_rc_t
2002 __in_bcount(buffer_length) uint8_t *bufferp,
2003 __in size_t buffer_length,
2004 __deref_out uint8_t **endpp);
2008 extern __checkReturn efx_rc_t
2009 efx_dhcp_delete_tag(
2010 __inout_bcount(buffer_length) uint8_t *bufferp,
2011 __in size_t buffer_length,
2015 extern __checkReturn efx_rc_t
2017 __inout_bcount(buffer_length) uint8_t *bufferp,
2018 __in size_t buffer_length,
2020 __in_bcount_opt(value_length) uint8_t *valuep,
2021 __in size_t value_length);
2024 extern __checkReturn efx_rc_t
2025 efx_dhcp_update_tag(
2026 __inout_bcount(buffer_length) uint8_t *bufferp,
2027 __in size_t buffer_length,
2029 __in uint8_t *value_locationp,
2030 __in_bcount_opt(value_length) uint8_t *valuep,
2031 __in size_t value_length);
2034 #endif /* EFSYS_OPT_BOOTCFG */
2036 #if EFSYS_OPT_IMAGE_LAYOUT
2038 #include "ef10_signed_image_layout.h"
2041 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2044 * The image header format is extensible. However, older drivers require an
2045 * exact match of image header version and header length when validating and
2046 * writing firmware images.
2048 * To avoid breaking backward compatibility, we use the upper bits of the
2049 * controller version fields to contain an extra version number used for
2050 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2051 * version). See bug39254 and SF-102785-PS for details.
2053 typedef struct efx_image_header_s {
2055 uint32_t eih_version;
2057 uint32_t eih_subtype;
2058 uint32_t eih_code_size;
2061 uint32_t eih_controller_version_min;
2063 uint16_t eih_controller_version_min_short;
2064 uint8_t eih_extra_version_a;
2065 uint8_t eih_extra_version_b;
2069 uint32_t eih_controller_version_max;
2071 uint16_t eih_controller_version_max_short;
2072 uint8_t eih_extra_version_c;
2073 uint8_t eih_extra_version_d;
2076 uint16_t eih_code_version_a;
2077 uint16_t eih_code_version_b;
2078 uint16_t eih_code_version_c;
2079 uint16_t eih_code_version_d;
2080 } efx_image_header_t;
2082 #define EFX_IMAGE_HEADER_SIZE (40)
2083 #define EFX_IMAGE_HEADER_VERSION (4)
2084 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2087 typedef struct efx_image_trailer_s {
2089 } efx_image_trailer_t;
2091 #define EFX_IMAGE_TRAILER_SIZE (4)
2093 typedef enum efx_image_format_e {
2094 EFX_IMAGE_FORMAT_NO_IMAGE,
2095 EFX_IMAGE_FORMAT_INVALID,
2096 EFX_IMAGE_FORMAT_UNSIGNED,
2097 EFX_IMAGE_FORMAT_SIGNED,
2098 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2099 } efx_image_format_t;
2101 typedef struct efx_image_info_s {
2102 efx_image_format_t eii_format;
2103 uint8_t * eii_imagep;
2104 size_t eii_image_size;
2105 efx_image_header_t * eii_headerp;
2109 extern __checkReturn efx_rc_t
2110 efx_check_reflash_image(
2112 __in uint32_t buffer_size,
2113 __out efx_image_info_t *infop);
2116 extern __checkReturn efx_rc_t
2117 efx_build_signed_image_write_buffer(
2118 __out_bcount(buffer_size)
2120 __in uint32_t buffer_size,
2121 __in efx_image_info_t *infop,
2122 __out efx_image_header_t **headerpp);
2124 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2128 typedef enum efx_pattern_type_t {
2129 EFX_PATTERN_BYTE_INCREMENT = 0,
2130 EFX_PATTERN_ALL_THE_SAME,
2131 EFX_PATTERN_BIT_ALTERNATE,
2132 EFX_PATTERN_BYTE_ALTERNATE,
2133 EFX_PATTERN_BYTE_CHANGING,
2134 EFX_PATTERN_BIT_SWEEP,
2136 } efx_pattern_type_t;
2139 (*efx_sram_pattern_fn_t)(
2141 __in boolean_t negate,
2142 __out efx_qword_t *eqp);
2145 extern __checkReturn efx_rc_t
2147 __in efx_nic_t *enp,
2148 __in efx_pattern_type_t type);
2150 #endif /* EFSYS_OPT_DIAG */
2153 extern __checkReturn efx_rc_t
2154 efx_sram_buf_tbl_set(
2155 __in efx_nic_t *enp,
2157 __in efsys_mem_t *esmp,
2162 efx_sram_buf_tbl_clear(
2163 __in efx_nic_t *enp,
2167 #define EFX_BUF_TBL_SIZE 0x20000
2169 #define EFX_BUF_SIZE 4096
2173 typedef struct efx_evq_s efx_evq_t;
2175 #if EFSYS_OPT_QSTATS
2177 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2178 typedef enum efx_ev_qstat_e {
2184 EV_RX_PAUSE_FRM_ERR,
2185 EV_RX_BUF_OWNER_ID_ERR,
2186 EV_RX_IPV4_HDR_CHKSUM_ERR,
2187 EV_RX_TCP_UDP_CHKSUM_ERR,
2191 EV_RX_MCAST_HASH_MATCH,
2208 EV_DRIVER_SRM_UPD_DONE,
2209 EV_DRIVER_TX_DESCQ_FLS_DONE,
2210 EV_DRIVER_RX_DESCQ_FLS_DONE,
2211 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2212 EV_DRIVER_RX_DSC_ERROR,
2213 EV_DRIVER_TX_DSC_ERROR,
2216 EV_RX_PARSE_INCOMPLETE,
2220 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2222 #endif /* EFSYS_OPT_QSTATS */
2225 extern __checkReturn efx_rc_t
2227 __in efx_nic_t *enp);
2232 __in efx_nic_t *enp);
2235 extern __checkReturn size_t
2237 __in const efx_nic_t *enp,
2238 __in unsigned int ndescs);
2241 extern __checkReturn unsigned int
2243 __in const efx_nic_t *enp,
2244 __in unsigned int ndescs);
2246 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2247 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2248 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2249 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2251 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2252 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2253 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2256 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2257 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2260 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2261 * which is the case when an event queue is set to THROUGHPUT mode.
2263 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2266 extern __checkReturn efx_rc_t
2268 __in efx_nic_t *enp,
2269 __in unsigned int index,
2270 __in efsys_mem_t *esmp,
2274 __in uint32_t flags,
2275 __deref_out efx_evq_t **eepp);
2280 __in efx_evq_t *eep,
2281 __in uint16_t data);
2283 typedef __checkReturn boolean_t
2284 (*efx_initialized_ev_t)(
2285 __in_opt void *arg);
2287 #define EFX_PKT_UNICAST 0x0004
2288 #define EFX_PKT_START 0x0008
2290 #define EFX_PKT_VLAN_TAGGED 0x0010
2291 #define EFX_CKSUM_TCPUDP 0x0020
2292 #define EFX_CKSUM_IPV4 0x0040
2293 #define EFX_PKT_CONT 0x0080
2295 #define EFX_CHECK_VLAN 0x0100
2296 #define EFX_PKT_TCP 0x0200
2297 #define EFX_PKT_UDP 0x0400
2298 #define EFX_PKT_IPV4 0x0800
2300 #define EFX_PKT_IPV6 0x1000
2301 #define EFX_PKT_PREFIX_LEN 0x2000
2302 #define EFX_ADDR_MISMATCH 0x4000
2303 #define EFX_DISCARD 0x8000
2306 * The following flags are used only for packed stream
2307 * mode. The values for the flags are reused to fit into 16 bit,
2308 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2309 * packed stream mode
2311 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2312 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2315 #define EFX_EV_RX_NLABELS 32
2316 #define EFX_EV_TX_NLABELS 32
2318 typedef __checkReturn boolean_t
2321 __in uint32_t label,
2324 __in uint16_t flags);
2326 typedef __checkReturn boolean_t
2327 (*efx_rx_packets_ev_t)(
2329 __in uint32_t label,
2330 __in unsigned int num_packets,
2331 __in uint32_t flags);
2333 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2336 * Packed stream mode is documented in SF-112241-TC.
2337 * The general idea is that, instead of putting each incoming
2338 * packet into a separate buffer which is specified in a RX
2339 * descriptor, a large buffer is provided to the hardware and
2340 * packets are put there in a continuous stream.
2341 * The main advantage of such an approach is that RX queue refilling
2342 * happens much less frequently.
2344 * Equal stride packed stream mode is documented in SF-119419-TC.
2345 * The general idea is to utilize advantages of the packed stream,
2346 * but avoid indirection in packets representation.
2347 * The main advantage of such an approach is that RX queue refilling
2348 * happens much less frequently and packets buffers are independent
2349 * from upper layers point of view.
2352 typedef __checkReturn boolean_t
2355 __in uint32_t label,
2357 __in uint32_t pkt_count,
2358 __in uint16_t flags);
2362 typedef __checkReturn boolean_t
2365 __in uint32_t label,
2368 typedef __checkReturn boolean_t
2369 (*efx_tx_ndescs_ev_t)(
2371 __in uint32_t label,
2372 __in unsigned int ndescs);
2374 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2375 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2376 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2377 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2378 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2379 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2380 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2381 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2382 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2384 typedef __checkReturn boolean_t
2385 (*efx_exception_ev_t)(
2387 __in uint32_t label,
2388 __in uint32_t data);
2390 typedef __checkReturn boolean_t
2391 (*efx_rxq_flush_done_ev_t)(
2393 __in uint32_t rxq_index);
2395 typedef __checkReturn boolean_t
2396 (*efx_rxq_flush_failed_ev_t)(
2398 __in uint32_t rxq_index);
2400 typedef __checkReturn boolean_t
2401 (*efx_txq_flush_done_ev_t)(
2403 __in uint32_t txq_index);
2405 typedef __checkReturn boolean_t
2406 (*efx_software_ev_t)(
2408 __in uint16_t magic);
2410 typedef __checkReturn boolean_t
2413 __in uint32_t code);
2415 #define EFX_SRAM_CLEAR 0
2416 #define EFX_SRAM_UPDATE 1
2417 #define EFX_SRAM_ILLEGAL_CLEAR 2
2419 typedef __checkReturn boolean_t
2420 (*efx_wake_up_ev_t)(
2422 __in uint32_t label);
2424 typedef __checkReturn boolean_t
2427 __in uint32_t label);
2429 typedef __checkReturn boolean_t
2430 (*efx_link_change_ev_t)(
2432 __in efx_link_mode_t link_mode);
2434 #if EFSYS_OPT_MON_STATS
2436 typedef __checkReturn boolean_t
2437 (*efx_monitor_ev_t)(
2439 __in efx_mon_stat_t id,
2440 __in efx_mon_stat_value_t value);
2442 #endif /* EFSYS_OPT_MON_STATS */
2444 #if EFSYS_OPT_MAC_STATS
2446 typedef __checkReturn boolean_t
2447 (*efx_mac_stats_ev_t)(
2449 __in uint32_t generation);
2451 #endif /* EFSYS_OPT_MAC_STATS */
2453 typedef struct efx_ev_callbacks_s {
2454 efx_initialized_ev_t eec_initialized;
2456 efx_rx_packets_ev_t eec_rx_packets;
2457 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2458 efx_rx_ps_ev_t eec_rx_ps;
2461 efx_tx_ndescs_ev_t eec_tx_ndescs;
2462 efx_exception_ev_t eec_exception;
2463 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2464 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2465 efx_txq_flush_done_ev_t eec_txq_flush_done;
2466 efx_software_ev_t eec_software;
2467 efx_sram_ev_t eec_sram;
2468 efx_wake_up_ev_t eec_wake_up;
2469 efx_timer_ev_t eec_timer;
2470 efx_link_change_ev_t eec_link_change;
2471 #if EFSYS_OPT_MON_STATS
2472 efx_monitor_ev_t eec_monitor;
2473 #endif /* EFSYS_OPT_MON_STATS */
2474 #if EFSYS_OPT_MAC_STATS
2475 efx_mac_stats_ev_t eec_mac_stats;
2476 #endif /* EFSYS_OPT_MAC_STATS */
2477 } efx_ev_callbacks_t;
2480 extern __checkReturn boolean_t
2482 __in efx_evq_t *eep,
2483 __in unsigned int count);
2485 #if EFSYS_OPT_EV_PREFETCH
2490 __in efx_evq_t *eep,
2491 __in unsigned int count);
2493 #endif /* EFSYS_OPT_EV_PREFETCH */
2497 efx_ev_qcreate_check_init_done(
2498 __in efx_evq_t *eep,
2499 __in const efx_ev_callbacks_t *eecp,
2500 __in_opt void *arg);
2505 __in efx_evq_t *eep,
2506 __inout unsigned int *countp,
2507 __in const efx_ev_callbacks_t *eecp,
2508 __in_opt void *arg);
2511 extern __checkReturn efx_rc_t
2512 efx_ev_usecs_to_ticks(
2513 __in efx_nic_t *enp,
2514 __in unsigned int usecs,
2515 __out unsigned int *ticksp);
2518 extern __checkReturn efx_rc_t
2520 __in efx_evq_t *eep,
2521 __in unsigned int us);
2524 extern __checkReturn efx_rc_t
2526 __in efx_evq_t *eep,
2527 __in unsigned int count);
2529 #if EFSYS_OPT_QSTATS
2536 __in efx_nic_t *enp,
2537 __in unsigned int id);
2539 #endif /* EFSYS_OPT_NAMES */
2543 efx_ev_qstats_update(
2544 __in efx_evq_t *eep,
2545 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2547 #endif /* EFSYS_OPT_QSTATS */
2552 __in efx_evq_t *eep);
2557 extern __checkReturn efx_rc_t
2559 __inout efx_nic_t *enp);
2564 __in efx_nic_t *enp);
2566 #if EFSYS_OPT_RX_SCATTER
2568 extern __checkReturn efx_rc_t
2569 efx_rx_scatter_enable(
2570 __in efx_nic_t *enp,
2571 __in unsigned int buf_size);
2572 #endif /* EFSYS_OPT_RX_SCATTER */
2574 /* Handle to represent use of the default RSS context. */
2575 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2577 #if EFSYS_OPT_RX_SCALE
2579 typedef enum efx_rx_hash_alg_e {
2580 EFX_RX_HASHALG_LFSR = 0,
2581 EFX_RX_HASHALG_TOEPLITZ,
2582 EFX_RX_HASHALG_PACKED_STREAM,
2584 } efx_rx_hash_alg_t;
2587 * Legacy hash type flags.
2589 * They represent standard tuples for distinct traffic classes.
2591 #define EFX_RX_HASH_IPV4 (1U << 0)
2592 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2593 #define EFX_RX_HASH_IPV6 (1U << 2)
2594 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2596 #define EFX_RX_HASH_LEGACY_MASK \
2597 (EFX_RX_HASH_IPV4 | \
2598 EFX_RX_HASH_TCPIPV4 | \
2599 EFX_RX_HASH_IPV6 | \
2600 EFX_RX_HASH_TCPIPV6)
2603 * The type of the argument used by efx_rx_scale_mode_set() to
2604 * provide a means for the client drivers to configure hashing.
2606 * A properly constructed value can either be:
2607 * - a combination of legacy flags
2608 * - a combination of EFX_RX_HASH() flags
2610 typedef uint32_t efx_rx_hash_type_t;
2612 typedef enum efx_rx_hash_support_e {
2613 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2614 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2615 } efx_rx_hash_support_t;
2617 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2618 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2619 #define EFX_MAXRSS 64 /* RX indirection entry range */
2620 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2622 typedef enum efx_rx_scale_context_type_e {
2623 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2624 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2625 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2626 } efx_rx_scale_context_type_t;
2629 * Traffic classes eligible for hash computation.
2631 * Select packet headers used in computing the receive hash.
2632 * This uses the same encoding as the RSS_MODES field of
2633 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2635 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2636 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2637 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2638 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2639 #define EFX_RX_CLASS_IPV4_LBN 16
2640 #define EFX_RX_CLASS_IPV4_WIDTH 4
2641 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2642 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2643 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2644 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2645 #define EFX_RX_CLASS_IPV6_LBN 28
2646 #define EFX_RX_CLASS_IPV6_WIDTH 4
2648 #define EFX_RX_NCLASSES 6
2651 * Ancillary flags used to construct generic hash tuples.
2652 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2654 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2655 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2656 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2657 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2660 * Generic hash tuples.
2662 * They express combinations of packet fields
2663 * which can contribute to the hash value for
2664 * a particular traffic class.
2666 #define EFX_RX_CLASS_HASH_DISABLE 0
2668 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2669 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2671 #define EFX_RX_CLASS_HASH_2TUPLE \
2672 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2673 EFX_RX_CLASS_HASH_DST_ADDR)
2675 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2676 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2677 EFX_RX_CLASS_HASH_SRC_PORT)
2679 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2680 (EFX_RX_CLASS_HASH_DST_ADDR | \
2681 EFX_RX_CLASS_HASH_DST_PORT)
2683 #define EFX_RX_CLASS_HASH_4TUPLE \
2684 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2685 EFX_RX_CLASS_HASH_DST_ADDR | \
2686 EFX_RX_CLASS_HASH_SRC_PORT | \
2687 EFX_RX_CLASS_HASH_DST_PORT)
2689 #define EFX_RX_CLASS_HASH_NTUPLES 7
2692 * Hash flag constructor.
2694 * Resulting flags encode hash tuples for specific traffic classes.
2695 * The client drivers are encouraged to use these flags to form
2696 * a hash type value.
2698 #define EFX_RX_HASH(_class, _tuple) \
2699 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2700 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2703 * The maximum number of EFX_RX_HASH() flags.
2705 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2708 extern __checkReturn efx_rc_t
2709 efx_rx_scale_hash_flags_get(
2710 __in efx_nic_t *enp,
2711 __in efx_rx_hash_alg_t hash_alg,
2712 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2713 __in unsigned int max_nflags,
2714 __out unsigned int *nflagsp);
2717 extern __checkReturn efx_rc_t
2718 efx_rx_hash_default_support_get(
2719 __in efx_nic_t *enp,
2720 __out efx_rx_hash_support_t *supportp);
2724 extern __checkReturn efx_rc_t
2725 efx_rx_scale_default_support_get(
2726 __in efx_nic_t *enp,
2727 __out efx_rx_scale_context_type_t *typep);
2730 extern __checkReturn efx_rc_t
2731 efx_rx_scale_context_alloc(
2732 __in efx_nic_t *enp,
2733 __in efx_rx_scale_context_type_t type,
2734 __in uint32_t num_queues,
2735 __out uint32_t *rss_contextp);
2738 extern __checkReturn efx_rc_t
2739 efx_rx_scale_context_free(
2740 __in efx_nic_t *enp,
2741 __in uint32_t rss_context);
2744 extern __checkReturn efx_rc_t
2745 efx_rx_scale_mode_set(
2746 __in efx_nic_t *enp,
2747 __in uint32_t rss_context,
2748 __in efx_rx_hash_alg_t alg,
2749 __in efx_rx_hash_type_t type,
2750 __in boolean_t insert);
2753 extern __checkReturn efx_rc_t
2754 efx_rx_scale_tbl_set(
2755 __in efx_nic_t *enp,
2756 __in uint32_t rss_context,
2757 __in_ecount(n) unsigned int *table,
2761 extern __checkReturn efx_rc_t
2762 efx_rx_scale_key_set(
2763 __in efx_nic_t *enp,
2764 __in uint32_t rss_context,
2765 __in_ecount(n) uint8_t *key,
2769 extern __checkReturn uint32_t
2770 efx_pseudo_hdr_hash_get(
2771 __in efx_rxq_t *erp,
2772 __in efx_rx_hash_alg_t func,
2773 __in uint8_t *buffer);
2775 #endif /* EFSYS_OPT_RX_SCALE */
2778 extern __checkReturn efx_rc_t
2779 efx_pseudo_hdr_pkt_length_get(
2780 __in efx_rxq_t *erp,
2781 __in uint8_t *buffer,
2782 __out uint16_t *pkt_lengthp);
2785 extern __checkReturn size_t
2787 __in const efx_nic_t *enp,
2788 __in unsigned int ndescs);
2791 extern __checkReturn unsigned int
2793 __in const efx_nic_t *enp,
2794 __in unsigned int ndescs);
2796 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2799 * libefx representation of the Rx prefix layout information.
2801 * The information may be used inside libefx to implement Rx prefix fields
2802 * accessors and by drivers which process Rx prefix itself.
2806 * All known Rx prefix fields.
2808 * An Rx prefix may have a subset of these fields.
2810 typedef enum efx_rx_prefix_field_e {
2811 EFX_RX_PREFIX_FIELD_LENGTH = 0,
2812 EFX_RX_PREFIX_FIELD_ORIG_LENGTH,
2813 EFX_RX_PREFIX_FIELD_CLASS,
2814 EFX_RX_PREFIX_FIELD_RSS_HASH,
2815 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID,
2816 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP,
2817 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI,
2818 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI,
2819 EFX_RX_PREFIX_FIELD_USER_FLAG,
2820 EFX_RX_PREFIX_FIELD_USER_MARK,
2821 EFX_RX_PREFIX_FIELD_USER_MARK_VALID,
2822 EFX_RX_PREFIX_FIELD_CSUM_FRAME,
2823 EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2824 EFX_RX_PREFIX_NFIELDS
2825 } efx_rx_prefix_field_t;
2828 * Location and endianness of a field in Rx prefix.
2830 * If width is zero, the field is not present.
2832 typedef struct efx_rx_prefix_field_info_s {
2833 uint16_t erpfi_offset_bits;
2834 uint8_t erpfi_width_bits;
2835 boolean_t erpfi_big_endian;
2836 } efx_rx_prefix_field_info_t;
2838 /* Helper macro to define Rx prefix fields */
2839 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \
2840 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \
2841 .erpfi_offset_bits = EFX_LOW_BIT(_field), \
2842 .erpfi_width_bits = EFX_WIDTH(_field), \
2843 .erpfi_big_endian = (_big_endian), \
2846 typedef struct efx_rx_prefix_layout_s {
2848 uint8_t erpl_length;
2849 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS];
2850 } efx_rx_prefix_layout_t;
2853 extern __checkReturn efx_rc_t
2854 efx_rx_prefix_get_layout(
2855 __in const efx_rxq_t *erp,
2856 __out efx_rx_prefix_layout_t *erplp);
2858 typedef enum efx_rxq_type_e {
2859 EFX_RXQ_TYPE_DEFAULT,
2860 EFX_RXQ_TYPE_PACKED_STREAM,
2861 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2866 * Dummy flag to be used instead of 0 to make it clear that the argument
2867 * is receive queue flags.
2869 #define EFX_RXQ_FLAG_NONE 0x0
2870 #define EFX_RXQ_FLAG_SCATTER 0x1
2872 * If tunnels are supported and Rx event can provide information about
2873 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2874 * full-feature firmware variant running), outer classes are requested by
2875 * default. However, if the driver supports tunnels, the flag allows to
2876 * request inner classes which are required to be able to interpret inner
2877 * Rx checksum offload results.
2879 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2882 extern __checkReturn efx_rc_t
2884 __in efx_nic_t *enp,
2885 __in unsigned int index,
2886 __in unsigned int label,
2887 __in efx_rxq_type_t type,
2888 __in size_t buf_size,
2889 __in efsys_mem_t *esmp,
2892 __in unsigned int flags,
2893 __in efx_evq_t *eep,
2894 __deref_out efx_rxq_t **erpp);
2896 #if EFSYS_OPT_RX_PACKED_STREAM
2898 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2899 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2900 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2901 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2902 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2905 extern __checkReturn efx_rc_t
2906 efx_rx_qcreate_packed_stream(
2907 __in efx_nic_t *enp,
2908 __in unsigned int index,
2909 __in unsigned int label,
2910 __in uint32_t ps_buf_size,
2911 __in efsys_mem_t *esmp,
2913 __in efx_evq_t *eep,
2914 __deref_out efx_rxq_t **erpp);
2918 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2920 /* Maximum head-of-line block timeout in nanoseconds */
2921 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2924 extern __checkReturn efx_rc_t
2925 efx_rx_qcreate_es_super_buffer(
2926 __in efx_nic_t *enp,
2927 __in unsigned int index,
2928 __in unsigned int label,
2929 __in uint32_t n_bufs_per_desc,
2930 __in uint32_t max_dma_len,
2931 __in uint32_t buf_stride,
2932 __in uint32_t hol_block_timeout,
2933 __in efsys_mem_t *esmp,
2935 __in unsigned int flags,
2936 __in efx_evq_t *eep,
2937 __deref_out efx_rxq_t **erpp);
2941 typedef struct efx_buffer_s {
2942 efsys_dma_addr_t eb_addr;
2947 typedef struct efx_desc_s {
2954 __in efx_rxq_t *erp,
2955 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2957 __in unsigned int ndescs,
2958 __in unsigned int completed,
2959 __in unsigned int added);
2964 __in efx_rxq_t *erp,
2965 __in unsigned int added,
2966 __inout unsigned int *pushedp);
2968 #if EFSYS_OPT_RX_PACKED_STREAM
2972 efx_rx_qpush_ps_credits(
2973 __in efx_rxq_t *erp);
2976 extern __checkReturn uint8_t *
2977 efx_rx_qps_packet_info(
2978 __in efx_rxq_t *erp,
2979 __in uint8_t *buffer,
2980 __in uint32_t buffer_length,
2981 __in uint32_t current_offset,
2982 __out uint16_t *lengthp,
2983 __out uint32_t *next_offsetp,
2984 __out uint32_t *timestamp);
2988 extern __checkReturn efx_rc_t
2990 __in efx_rxq_t *erp);
2995 __in efx_rxq_t *erp);
3000 __in efx_rxq_t *erp);
3004 typedef struct efx_txq_s efx_txq_t;
3006 #if EFSYS_OPT_QSTATS
3008 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
3009 typedef enum efx_tx_qstat_e {
3015 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
3017 #endif /* EFSYS_OPT_QSTATS */
3020 extern __checkReturn efx_rc_t
3022 __in efx_nic_t *enp);
3027 __in efx_nic_t *enp);
3030 extern __checkReturn size_t
3032 __in const efx_nic_t *enp,
3033 __in unsigned int ndescs);
3036 extern __checkReturn unsigned int
3038 __in const efx_nic_t *enp,
3039 __in unsigned int ndescs);
3041 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
3043 #define EFX_TXQ_CKSUM_IPV4 0x0001
3044 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
3045 #define EFX_TXQ_FATSOV2 0x0004
3046 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
3047 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
3050 extern __checkReturn efx_rc_t
3052 __in efx_nic_t *enp,
3053 __in unsigned int index,
3054 __in unsigned int label,
3055 __in efsys_mem_t *esmp,
3058 __in uint16_t flags,
3059 __in efx_evq_t *eep,
3060 __deref_out efx_txq_t **etpp,
3061 __out unsigned int *addedp);
3064 extern __checkReturn efx_rc_t
3066 __in efx_txq_t *etp,
3067 __in_ecount(ndescs) efx_buffer_t *eb,
3068 __in unsigned int ndescs,
3069 __in unsigned int completed,
3070 __inout unsigned int *addedp);
3073 extern __checkReturn efx_rc_t
3075 __in efx_txq_t *etp,
3076 __in unsigned int ns);
3081 __in efx_txq_t *etp,
3082 __in unsigned int added,
3083 __in unsigned int pushed);
3086 extern __checkReturn efx_rc_t
3088 __in efx_txq_t *etp);
3093 __in efx_txq_t *etp);
3096 extern __checkReturn efx_rc_t
3098 __in efx_txq_t *etp);
3102 efx_tx_qpio_disable(
3103 __in efx_txq_t *etp);
3106 extern __checkReturn efx_rc_t
3108 __in efx_txq_t *etp,
3109 __in_ecount(buf_length) uint8_t *buffer,
3110 __in size_t buf_length,
3111 __in size_t pio_buf_offset);
3114 extern __checkReturn efx_rc_t
3116 __in efx_txq_t *etp,
3117 __in size_t pkt_length,
3118 __in unsigned int completed,
3119 __inout unsigned int *addedp);
3122 extern __checkReturn efx_rc_t
3124 __in efx_txq_t *etp,
3125 __in_ecount(n) efx_desc_t *ed,
3126 __in unsigned int n,
3127 __in unsigned int completed,
3128 __inout unsigned int *addedp);
3132 efx_tx_qdesc_dma_create(
3133 __in efx_txq_t *etp,
3134 __in efsys_dma_addr_t addr,
3137 __out efx_desc_t *edp);
3141 efx_tx_qdesc_tso_create(
3142 __in efx_txq_t *etp,
3143 __in uint16_t ipv4_id,
3144 __in uint32_t tcp_seq,
3145 __in uint8_t tcp_flags,
3146 __out efx_desc_t *edp);
3148 /* Number of FATSOv2 option descriptors */
3149 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3151 /* Maximum number of DMA segments per TSO packet (not superframe) */
3152 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3156 efx_tx_qdesc_tso2_create(
3157 __in efx_txq_t *etp,
3158 __in uint16_t ipv4_id,
3159 __in uint16_t outer_ipv4_id,
3160 __in uint32_t tcp_seq,
3161 __in uint16_t tcp_mss,
3162 __out_ecount(count) efx_desc_t *edp,
3167 efx_tx_qdesc_vlantci_create(
3168 __in efx_txq_t *etp,
3170 __out efx_desc_t *edp);
3174 efx_tx_qdesc_checksum_create(
3175 __in efx_txq_t *etp,
3176 __in uint16_t flags,
3177 __out efx_desc_t *edp);
3179 #if EFSYS_OPT_QSTATS
3186 __in efx_nic_t *etp,
3187 __in unsigned int id);
3189 #endif /* EFSYS_OPT_NAMES */
3193 efx_tx_qstats_update(
3194 __in efx_txq_t *etp,
3195 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3197 #endif /* EFSYS_OPT_QSTATS */
3202 __in efx_txq_t *etp);
3207 #if EFSYS_OPT_FILTER
3209 #define EFX_ETHER_TYPE_IPV4 0x0800
3210 #define EFX_ETHER_TYPE_IPV6 0x86DD
3212 #define EFX_IPPROTO_TCP 6
3213 #define EFX_IPPROTO_UDP 17
3214 #define EFX_IPPROTO_GRE 47
3216 /* Use RSS to spread across multiple queues */
3217 #define EFX_FILTER_FLAG_RX_RSS 0x01
3218 /* Enable RX scatter */
3219 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3221 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3222 * May only be set by the filter implementation for each type.
3223 * A removal request will restore the automatic filter in its place.
3225 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3226 /* Filter is for RX */
3227 #define EFX_FILTER_FLAG_RX 0x08
3228 /* Filter is for TX */
3229 #define EFX_FILTER_FLAG_TX 0x10
3230 /* Set match flag on the received packet */
3231 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3232 /* Set match mark on the received packet */
3233 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3235 typedef uint8_t efx_filter_flags_t;
3238 * Flags which specify the fields to match on. The values are the same as in the
3239 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3242 /* Match by remote IP host address */
3243 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3244 /* Match by local IP host address */
3245 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3246 /* Match by remote MAC address */
3247 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3248 /* Match by remote TCP/UDP port */
3249 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3250 /* Match by remote TCP/UDP port */
3251 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3252 /* Match by local TCP/UDP port */
3253 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3254 /* Match by Ether-type */
3255 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3256 /* Match by inner VLAN ID */
3257 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3258 /* Match by outer VLAN ID */
3259 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3260 /* Match by IP transport protocol */
3261 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3262 /* Match by VNI or VSID */
3263 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3264 /* For encapsulated packets, match by inner frame local MAC address */
3265 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3266 /* For encapsulated packets, match all multicast inner frames */
3267 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3268 /* For encapsulated packets, match all unicast inner frames */
3269 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3271 * Match by encap type, this flag does not correspond to
3272 * the MCDI match flags and any unoccupied value may be used
3274 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3275 /* Match otherwise-unmatched multicast and broadcast packets */
3276 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3277 /* Match otherwise-unmatched unicast packets */
3278 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3280 typedef uint32_t efx_filter_match_flags_t;
3282 /* Filter priority from lowest to highest */
3283 typedef enum efx_filter_priority_s {
3284 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3285 * address list or hardware
3286 * requirements. This may only be used
3287 * by the filter implementation for
3289 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3291 } efx_filter_priority_t;
3294 * FIXME: All these fields are assumed to be in little-endian byte order.
3295 * It may be better for some to be big-endian. See bug42804.
3298 typedef struct efx_filter_spec_s {
3299 efx_filter_match_flags_t efs_match_flags;
3300 uint8_t efs_priority;
3301 efx_filter_flags_t efs_flags;
3302 uint16_t efs_dmaq_id;
3303 uint32_t efs_rss_context;
3306 * Saved lower-priority filter. If it is set, it is restored on
3307 * filter delete operation.
3309 struct efx_filter_spec_s *efs_overridden_spec;
3310 /* Fields below here are hashed for software filter lookup */
3311 uint16_t efs_outer_vid;
3312 uint16_t efs_inner_vid;
3313 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3314 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3315 uint16_t efs_ether_type;
3316 uint8_t efs_ip_proto;
3317 efx_tunnel_protocol_t efs_encap_type;
3318 uint16_t efs_loc_port;
3319 uint16_t efs_rem_port;
3320 efx_oword_t efs_rem_host;
3321 efx_oword_t efs_loc_host;
3322 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3323 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3324 } efx_filter_spec_t;
3327 /* Default values for use in filter specifications */
3328 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3329 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3332 extern __checkReturn efx_rc_t
3334 __in efx_nic_t *enp);
3339 __in efx_nic_t *enp);
3342 extern __checkReturn efx_rc_t
3344 __in efx_nic_t *enp,
3345 __inout efx_filter_spec_t *spec);
3348 extern __checkReturn efx_rc_t
3350 __in efx_nic_t *enp,
3351 __inout efx_filter_spec_t *spec);
3354 extern __checkReturn efx_rc_t
3356 __in efx_nic_t *enp);
3359 extern __checkReturn efx_rc_t
3360 efx_filter_supported_filters(
3361 __in efx_nic_t *enp,
3362 __out_ecount(buffer_length) uint32_t *buffer,
3363 __in size_t buffer_length,
3364 __out size_t *list_lengthp);
3368 efx_filter_spec_init_rx(
3369 __out efx_filter_spec_t *spec,
3370 __in efx_filter_priority_t priority,
3371 __in efx_filter_flags_t flags,
3372 __in efx_rxq_t *erp);
3376 efx_filter_spec_init_tx(
3377 __out efx_filter_spec_t *spec,
3378 __in efx_txq_t *etp);
3381 extern __checkReturn efx_rc_t
3382 efx_filter_spec_set_ipv4_local(
3383 __inout efx_filter_spec_t *spec,
3386 __in uint16_t port);
3389 extern __checkReturn efx_rc_t
3390 efx_filter_spec_set_ipv4_full(
3391 __inout efx_filter_spec_t *spec,
3393 __in uint32_t lhost,
3394 __in uint16_t lport,
3395 __in uint32_t rhost,
3396 __in uint16_t rport);
3399 extern __checkReturn efx_rc_t
3400 efx_filter_spec_set_eth_local(
3401 __inout efx_filter_spec_t *spec,
3403 __in const uint8_t *addr);
3407 efx_filter_spec_set_ether_type(
3408 __inout efx_filter_spec_t *spec,
3409 __in uint16_t ether_type);
3412 extern __checkReturn efx_rc_t
3413 efx_filter_spec_set_uc_def(
3414 __inout efx_filter_spec_t *spec);
3417 extern __checkReturn efx_rc_t
3418 efx_filter_spec_set_mc_def(
3419 __inout efx_filter_spec_t *spec);
3421 typedef enum efx_filter_inner_frame_match_e {
3422 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3423 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3424 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3425 } efx_filter_inner_frame_match_t;
3428 extern __checkReturn efx_rc_t
3429 efx_filter_spec_set_encap_type(
3430 __inout efx_filter_spec_t *spec,
3431 __in efx_tunnel_protocol_t encap_type,
3432 __in efx_filter_inner_frame_match_t inner_frame_match);
3435 extern __checkReturn efx_rc_t
3436 efx_filter_spec_set_vxlan(
3437 __inout efx_filter_spec_t *spec,
3438 __in const uint8_t *vni,
3439 __in const uint8_t *inner_addr,
3440 __in const uint8_t *outer_addr);
3443 extern __checkReturn efx_rc_t
3444 efx_filter_spec_set_geneve(
3445 __inout efx_filter_spec_t *spec,
3446 __in const uint8_t *vni,
3447 __in const uint8_t *inner_addr,
3448 __in const uint8_t *outer_addr);
3451 extern __checkReturn efx_rc_t
3452 efx_filter_spec_set_nvgre(
3453 __inout efx_filter_spec_t *spec,
3454 __in const uint8_t *vsid,
3455 __in const uint8_t *inner_addr,
3456 __in const uint8_t *outer_addr);
3458 #if EFSYS_OPT_RX_SCALE
3460 extern __checkReturn efx_rc_t
3461 efx_filter_spec_set_rss_context(
3462 __inout efx_filter_spec_t *spec,
3463 __in uint32_t rss_context);
3465 #endif /* EFSYS_OPT_FILTER */
3470 extern __checkReturn uint32_t
3472 __in_ecount(count) uint32_t const *input,
3474 __in uint32_t init);
3477 extern __checkReturn uint32_t
3479 __in_ecount(length) uint8_t const *input,
3481 __in uint32_t init);
3483 #if EFSYS_OPT_LICENSING
3487 typedef struct efx_key_stats_s {
3489 uint32_t eks_invalid;
3490 uint32_t eks_blacklisted;
3491 uint32_t eks_unverifiable;
3492 uint32_t eks_wrong_node;
3493 uint32_t eks_licensed_apps_lo;
3494 uint32_t eks_licensed_apps_hi;
3495 uint32_t eks_licensed_features_lo;
3496 uint32_t eks_licensed_features_hi;
3500 extern __checkReturn efx_rc_t
3502 __in efx_nic_t *enp);
3507 __in efx_nic_t *enp);
3510 extern __checkReturn boolean_t
3511 efx_lic_check_support(
3512 __in efx_nic_t *enp);
3515 extern __checkReturn efx_rc_t
3516 efx_lic_update_licenses(
3517 __in efx_nic_t *enp);
3520 extern __checkReturn efx_rc_t
3521 efx_lic_get_key_stats(
3522 __in efx_nic_t *enp,
3523 __out efx_key_stats_t *ksp);
3526 extern __checkReturn efx_rc_t
3528 __in efx_nic_t *enp,
3529 __in uint64_t app_id,
3530 __out boolean_t *licensedp);
3533 extern __checkReturn efx_rc_t
3535 __in efx_nic_t *enp,
3536 __in size_t buffer_size,
3537 __out uint32_t *typep,
3538 __out size_t *lengthp,
3539 __out_opt uint8_t *bufferp);
3543 extern __checkReturn efx_rc_t
3545 __in efx_nic_t *enp,
3546 __in_bcount(buffer_size)
3548 __in size_t buffer_size,
3549 __out uint32_t *startp);
3552 extern __checkReturn efx_rc_t
3554 __in efx_nic_t *enp,
3555 __in_bcount(buffer_size)
3557 __in size_t buffer_size,
3558 __in uint32_t offset,
3559 __out uint32_t *endp);
3562 extern __checkReturn __success(return != B_FALSE) boolean_t
3564 __in efx_nic_t *enp,
3565 __in_bcount(buffer_size)
3567 __in size_t buffer_size,
3568 __in uint32_t offset,
3569 __out uint32_t *startp,
3570 __out uint32_t *lengthp);
3573 extern __checkReturn __success(return != B_FALSE) boolean_t
3574 efx_lic_validate_key(
3575 __in efx_nic_t *enp,
3576 __in_bcount(length) caddr_t keyp,
3577 __in uint32_t length);
3580 extern __checkReturn efx_rc_t
3582 __in efx_nic_t *enp,
3583 __in_bcount(buffer_size)
3585 __in size_t buffer_size,
3586 __in uint32_t offset,
3587 __in uint32_t length,
3588 __out_bcount_part(key_max_size, *lengthp)
3590 __in size_t key_max_size,
3591 __out uint32_t *lengthp);
3594 extern __checkReturn efx_rc_t
3596 __in efx_nic_t *enp,
3597 __in_bcount(buffer_size)
3599 __in size_t buffer_size,
3600 __in uint32_t offset,
3601 __in_bcount(length) caddr_t keyp,
3602 __in uint32_t length,
3603 __out uint32_t *lengthp);
3606 extern __checkReturn efx_rc_t
3608 __in efx_nic_t *enp,
3609 __in_bcount(buffer_size)
3611 __in size_t buffer_size,
3612 __in uint32_t offset,
3613 __in uint32_t length,
3615 __out uint32_t *deltap);
3618 extern __checkReturn efx_rc_t
3619 efx_lic_create_partition(
3620 __in efx_nic_t *enp,
3621 __in_bcount(buffer_size)
3623 __in size_t buffer_size);
3625 extern __checkReturn efx_rc_t
3626 efx_lic_finish_partition(
3627 __in efx_nic_t *enp,
3628 __in_bcount(buffer_size)
3630 __in size_t buffer_size);
3632 #endif /* EFSYS_OPT_LICENSING */
3636 #if EFSYS_OPT_TUNNEL
3639 extern __checkReturn efx_rc_t
3641 __in efx_nic_t *enp);
3646 __in efx_nic_t *enp);
3649 * For overlay network encapsulation using UDP, the firmware needs to know
3650 * the configured UDP port for the overlay so it can decode encapsulated
3652 * The UDP port/protocol list is global.
3656 extern __checkReturn efx_rc_t
3657 efx_tunnel_config_udp_add(
3658 __in efx_nic_t *enp,
3659 __in uint16_t port /* host/cpu-endian */,
3660 __in efx_tunnel_protocol_t protocol);
3663 extern __checkReturn efx_rc_t
3664 efx_tunnel_config_udp_remove(
3665 __in efx_nic_t *enp,
3666 __in uint16_t port /* host/cpu-endian */,
3667 __in efx_tunnel_protocol_t protocol);
3671 efx_tunnel_config_clear(
3672 __in efx_nic_t *enp);
3675 * Apply tunnel UDP ports configuration to hardware.
3677 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3681 extern __checkReturn efx_rc_t
3682 efx_tunnel_reconfigure(
3683 __in efx_nic_t *enp);
3685 #endif /* EFSYS_OPT_TUNNEL */
3687 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3690 * Firmware subvariant choice options.
3692 * It may be switched to no Tx checksum if attached drivers are either
3693 * preboot or firmware subvariant aware and no VIS are allocated.
3694 * If may be always switched to default explicitly using set request or
3695 * implicitly if unaware driver is attaching. If switching is done when
3696 * a driver is attached, it gets MC_REBOOT event and should recreate its
3699 * See SF-119419-TC DPDK Firmware Driver Interface and
3700 * SF-109306-TC EF10 for Driver Writers for details.
3702 typedef enum efx_nic_fw_subvariant_e {
3703 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3704 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3705 EFX_NIC_FW_SUBVARIANT_NTYPES
3706 } efx_nic_fw_subvariant_t;
3709 extern __checkReturn efx_rc_t
3710 efx_nic_get_fw_subvariant(
3711 __in efx_nic_t *enp,
3712 __out efx_nic_fw_subvariant_t *subvariantp);
3715 extern __checkReturn efx_rc_t
3716 efx_nic_set_fw_subvariant(
3717 __in efx_nic_t *enp,
3718 __in efx_nic_fw_subvariant_t subvariant);
3720 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3722 typedef enum efx_phy_fec_type_e {
3723 EFX_PHY_FEC_NONE = 0,
3726 } efx_phy_fec_type_t;
3729 extern __checkReturn efx_rc_t
3730 efx_phy_fec_type_get(
3731 __in efx_nic_t *enp,
3732 __out efx_phy_fec_type_t *typep);
3734 typedef struct efx_phy_link_state_s {
3735 uint32_t epls_adv_cap_mask;
3736 uint32_t epls_lp_cap_mask;
3737 uint32_t epls_ld_cap_mask;
3738 unsigned int epls_fcntl;
3739 efx_phy_fec_type_t epls_fec;
3740 efx_link_mode_t epls_link_mode;
3741 } efx_phy_link_state_t;
3744 extern __checkReturn efx_rc_t
3745 efx_phy_link_state_get(
3746 __in efx_nic_t *enp,
3747 __out efx_phy_link_state_t *eplsp);
3752 typedef uint32_t efx_vswitch_id_t;
3753 typedef uint32_t efx_vport_id_t;
3755 typedef enum efx_vswitch_type_e {
3756 EFX_VSWITCH_TYPE_VLAN = 1,
3757 EFX_VSWITCH_TYPE_VEB,
3758 /* VSWITCH_TYPE_VEPA: obsolete */
3759 EFX_VSWITCH_TYPE_MUX = 4,
3760 } efx_vswitch_type_t;
3762 typedef enum efx_vport_type_e {
3763 EFX_VPORT_TYPE_NORMAL = 4,
3764 EFX_VPORT_TYPE_EXPANSION,
3765 EFX_VPORT_TYPE_TEST,
3768 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3769 #define EFX_FILTER_VID_UNSPEC 0xffff
3770 #define EFX_DEFAULT_VSWITCH_ID 1
3772 /* Default VF VLAN ID on creation */
3773 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3774 #define EFX_VPORT_ID_INVALID 0
3776 typedef struct efx_vport_config_s {
3777 /* Either VF index or 0xffff for PF */
3778 uint16_t evc_function;
3779 /* VLAN ID of the associated function */
3781 /* vport id shared with client driver */
3782 efx_vport_id_t evc_vport_id;
3783 /* MAC address of the associated function */
3784 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3786 * vports created with this flag set may only transfer traffic on the
3787 * VLANs permitted by the vport. Also, an attempt to install filter with
3788 * VLAN will be refused unless requesting function has VLAN privilege.
3790 boolean_t evc_vlan_restrict;
3791 /* Whether this function is assigned or not */
3792 boolean_t evc_vport_assigned;
3793 } efx_vport_config_t;
3795 typedef struct efx_vswitch_s efx_vswitch_t;
3798 extern __checkReturn efx_rc_t
3800 __in efx_nic_t *enp);
3805 __in efx_nic_t *enp);
3808 extern __checkReturn efx_rc_t
3809 efx_evb_vswitch_create(
3810 __in efx_nic_t *enp,
3811 __in uint32_t num_vports,
3812 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3813 __deref_out efx_vswitch_t **evpp);
3816 extern __checkReturn efx_rc_t
3817 efx_evb_vswitch_destroy(
3818 __in efx_nic_t *enp,
3819 __in efx_vswitch_t *evp);
3822 extern __checkReturn efx_rc_t
3823 efx_evb_vport_mac_set(
3824 __in efx_nic_t *enp,
3825 __in efx_vswitch_t *evp,
3826 __in efx_vport_id_t vport_id,
3827 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3830 extern __checkReturn efx_rc_t
3831 efx_evb_vport_vlan_set(
3832 __in efx_nic_t *enp,
3833 __in efx_vswitch_t *evp,
3834 __in efx_vport_id_t vport_id,
3838 extern __checkReturn efx_rc_t
3839 efx_evb_vport_reset(
3840 __in efx_nic_t *enp,
3841 __in efx_vswitch_t *evp,
3842 __in efx_vport_id_t vport_id,
3843 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3845 __out boolean_t *is_fn_resetp);
3848 extern __checkReturn efx_rc_t
3849 efx_evb_vport_stats(
3850 __in efx_nic_t *enp,
3851 __in efx_vswitch_t *evp,
3852 __in efx_vport_id_t vport_id,
3853 __out efsys_mem_t *stats_bufferp);
3855 #endif /* EFSYS_OPT_EVB */
3857 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3859 typedef struct efx_proxy_auth_config_s {
3860 efsys_mem_t *request_bufferp;
3861 efsys_mem_t *response_bufferp;
3862 efsys_mem_t *status_bufferp;
3866 uint32_t handled_privileges;
3867 } efx_proxy_auth_config_t;
3869 typedef struct efx_proxy_cmd_params_s {
3872 uint8_t *request_bufferp;
3873 size_t request_size;
3874 uint8_t *response_bufferp;
3875 size_t response_size;
3876 size_t *response_size_actualp;
3877 } efx_proxy_cmd_params_t;
3880 extern __checkReturn efx_rc_t
3881 efx_proxy_auth_init(
3882 __in efx_nic_t *enp);
3886 efx_proxy_auth_fini(
3887 __in efx_nic_t *enp);
3890 extern __checkReturn efx_rc_t
3891 efx_proxy_auth_configure(
3892 __in efx_nic_t *enp,
3893 __in efx_proxy_auth_config_t *configp);
3896 extern __checkReturn efx_rc_t
3897 efx_proxy_auth_destroy(
3898 __in efx_nic_t *enp,
3899 __in uint32_t handled_privileges);
3902 extern __checkReturn efx_rc_t
3903 efx_proxy_auth_complete_request(
3904 __in efx_nic_t *enp,
3905 __in uint32_t fn_index,
3906 __in uint32_t proxy_result,
3907 __in uint32_t handle);
3910 extern __checkReturn efx_rc_t
3911 efx_proxy_auth_exec_cmd(
3912 __in efx_nic_t *enp,
3913 __inout efx_proxy_cmd_params_t *paramsp);
3916 extern __checkReturn efx_rc_t
3917 efx_proxy_auth_set_privilege_mask(
3918 __in efx_nic_t *enp,
3919 __in uint32_t vf_index,
3921 __in uint32_t value);
3924 extern __checkReturn efx_rc_t
3925 efx_proxy_auth_privilege_mask_get(
3926 __in efx_nic_t *enp,
3927 __in uint32_t pf_index,
3928 __in uint32_t vf_index,
3929 __out uint32_t *maskp);
3932 extern __checkReturn efx_rc_t
3933 efx_proxy_auth_privilege_modify(
3934 __in efx_nic_t *enp,
3935 __in uint32_t pf_index,
3936 __in uint32_t vf_index,
3937 __in uint32_t add_privileges_mask,
3938 __in uint32_t remove_privileges_mask);
3940 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3946 #endif /* _SYS_EFX_H */