1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
63 extern __checkReturn efx_rc_t
67 __out efx_family_t *efp,
68 __out unsigned int *membarp);
71 #define EFX_PCI_VENID_SFC 0x1924
72 #define EFX_PCI_VENID_XILINX 0x10EE
74 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
76 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
77 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
78 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
80 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
81 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
82 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
84 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
85 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
87 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
88 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
89 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
91 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
92 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
93 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
95 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
96 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
98 #define EFX_MEM_BAR_SIENA 2
100 #define EFX_MEM_BAR_HUNTINGTON_PF 2
101 #define EFX_MEM_BAR_HUNTINGTON_VF 0
103 #define EFX_MEM_BAR_MEDFORD_PF 2
104 #define EFX_MEM_BAR_MEDFORD_VF 0
106 #define EFX_MEM_BAR_MEDFORD2 0
108 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
109 #define EFX_MEM_BAR_RIVERHEAD 2
117 EFX_ERR_BUFID_DC_OOB,
130 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
132 extern __checkReturn uint32_t
134 __in uint32_t crc_init,
135 __in_ecount(length) uint8_t const *input,
139 /* Type prototypes */
141 typedef struct efx_rxq_s efx_rxq_t;
145 typedef struct efx_nic_s efx_nic_t;
148 extern __checkReturn efx_rc_t
150 __in efx_family_t family,
151 __in efsys_identifier_t *esip,
152 __in efsys_bar_t *esbp,
153 __in efsys_lock_t *eslp,
154 __deref_out efx_nic_t **enpp);
156 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
157 typedef enum efx_fw_variant_e {
158 EFX_FW_VARIANT_FULL_FEATURED,
159 EFX_FW_VARIANT_LOW_LATENCY,
160 EFX_FW_VARIANT_PACKED_STREAM,
161 EFX_FW_VARIANT_HIGH_TX_RATE,
162 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
163 EFX_FW_VARIANT_RULES_ENGINE,
165 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
169 extern __checkReturn efx_rc_t
172 __in efx_fw_variant_t efv);
175 extern __checkReturn efx_rc_t
177 __in efx_nic_t *enp);
180 extern __checkReturn efx_rc_t
182 __in efx_nic_t *enp);
185 extern __checkReturn boolean_t
186 efx_nic_hw_unavailable(
187 __in efx_nic_t *enp);
191 efx_nic_set_hw_unavailable(
192 __in efx_nic_t *enp);
197 extern __checkReturn efx_rc_t
198 efx_nic_register_test(
199 __in efx_nic_t *enp);
201 #endif /* EFSYS_OPT_DIAG */
206 __in efx_nic_t *enp);
211 __in efx_nic_t *enp);
216 __in efx_nic_t *enp);
218 #define EFX_PCIE_LINK_SPEED_GEN1 1
219 #define EFX_PCIE_LINK_SPEED_GEN2 2
220 #define EFX_PCIE_LINK_SPEED_GEN3 3
222 typedef enum efx_pcie_link_performance_e {
223 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
224 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
225 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
226 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
227 } efx_pcie_link_performance_t;
230 extern __checkReturn efx_rc_t
231 efx_nic_calculate_pcie_link_bandwidth(
232 __in uint32_t pcie_link_width,
233 __in uint32_t pcie_link_gen,
234 __out uint32_t *bandwidth_mbpsp);
237 extern __checkReturn efx_rc_t
238 efx_nic_check_pcie_link_speed(
240 __in uint32_t pcie_link_width,
241 __in uint32_t pcie_link_gen,
242 __out efx_pcie_link_performance_t *resultp);
246 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
247 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
248 #define WITH_MCDI_V2 1
251 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
253 typedef enum efx_mcdi_exception_e {
254 EFX_MCDI_EXCEPTION_MC_REBOOT,
255 EFX_MCDI_EXCEPTION_MC_BADASSERT,
256 } efx_mcdi_exception_t;
258 #if EFSYS_OPT_MCDI_LOGGING
259 typedef enum efx_log_msg_e {
261 EFX_LOG_MCDI_REQUEST,
262 EFX_LOG_MCDI_RESPONSE,
264 #endif /* EFSYS_OPT_MCDI_LOGGING */
266 typedef struct efx_mcdi_transport_s {
268 efsys_mem_t *emt_dma_mem;
269 void (*emt_execute)(void *, efx_mcdi_req_t *);
270 void (*emt_ev_cpl)(void *);
271 void (*emt_exception)(void *, efx_mcdi_exception_t);
272 #if EFSYS_OPT_MCDI_LOGGING
273 void (*emt_logger)(void *, efx_log_msg_t,
274 void *, size_t, void *, size_t);
275 #endif /* EFSYS_OPT_MCDI_LOGGING */
276 #if EFSYS_OPT_MCDI_PROXY_AUTH
277 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
278 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
279 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
280 void (*emt_ev_proxy_request)(void *, uint32_t);
281 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
282 } efx_mcdi_transport_t;
285 extern __checkReturn efx_rc_t
288 __in const efx_mcdi_transport_t *mtp);
291 extern __checkReturn efx_rc_t
293 __in efx_nic_t *enp);
298 __in efx_nic_t *enp);
302 efx_mcdi_get_timeout(
304 __in efx_mcdi_req_t *emrp,
305 __out uint32_t *usec_timeoutp);
309 efx_mcdi_request_start(
311 __in efx_mcdi_req_t *emrp,
312 __in boolean_t ev_cpl);
315 extern __checkReturn boolean_t
316 efx_mcdi_request_poll(
317 __in efx_nic_t *enp);
320 extern __checkReturn boolean_t
321 efx_mcdi_request_abort(
322 __in efx_nic_t *enp);
327 __in efx_nic_t *enp);
329 #endif /* EFSYS_OPT_MCDI */
333 #define EFX_NINTR_SIENA 1024
335 typedef enum efx_intr_type_e {
336 EFX_INTR_INVALID = 0,
342 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
345 extern __checkReturn efx_rc_t
348 __in efx_intr_type_t type,
349 __in_opt efsys_mem_t *esmp);
354 __in efx_nic_t *enp);
359 __in efx_nic_t *enp);
363 efx_intr_disable_unlocked(
364 __in efx_nic_t *enp);
366 #define EFX_INTR_NEVQS 32
369 extern __checkReturn efx_rc_t
372 __in unsigned int level);
376 efx_intr_status_line(
378 __out boolean_t *fatalp,
379 __out uint32_t *maskp);
383 efx_intr_status_message(
385 __in unsigned int message,
386 __out boolean_t *fatalp);
391 __in efx_nic_t *enp);
396 __in efx_nic_t *enp);
400 #if EFSYS_OPT_MAC_STATS
402 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
403 typedef enum efx_mac_stat_e {
406 EFX_MAC_RX_UNICST_PKTS,
407 EFX_MAC_RX_MULTICST_PKTS,
408 EFX_MAC_RX_BRDCST_PKTS,
409 EFX_MAC_RX_PAUSE_PKTS,
410 EFX_MAC_RX_LE_64_PKTS,
411 EFX_MAC_RX_65_TO_127_PKTS,
412 EFX_MAC_RX_128_TO_255_PKTS,
413 EFX_MAC_RX_256_TO_511_PKTS,
414 EFX_MAC_RX_512_TO_1023_PKTS,
415 EFX_MAC_RX_1024_TO_15XX_PKTS,
416 EFX_MAC_RX_GE_15XX_PKTS,
418 EFX_MAC_RX_FCS_ERRORS,
419 EFX_MAC_RX_DROP_EVENTS,
420 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
421 EFX_MAC_RX_SYMBOL_ERRORS,
422 EFX_MAC_RX_ALIGN_ERRORS,
423 EFX_MAC_RX_INTERNAL_ERRORS,
424 EFX_MAC_RX_JABBER_PKTS,
425 EFX_MAC_RX_LANE0_CHAR_ERR,
426 EFX_MAC_RX_LANE1_CHAR_ERR,
427 EFX_MAC_RX_LANE2_CHAR_ERR,
428 EFX_MAC_RX_LANE3_CHAR_ERR,
429 EFX_MAC_RX_LANE0_DISP_ERR,
430 EFX_MAC_RX_LANE1_DISP_ERR,
431 EFX_MAC_RX_LANE2_DISP_ERR,
432 EFX_MAC_RX_LANE3_DISP_ERR,
433 EFX_MAC_RX_MATCH_FAULT,
434 EFX_MAC_RX_NODESC_DROP_CNT,
437 EFX_MAC_TX_UNICST_PKTS,
438 EFX_MAC_TX_MULTICST_PKTS,
439 EFX_MAC_TX_BRDCST_PKTS,
440 EFX_MAC_TX_PAUSE_PKTS,
441 EFX_MAC_TX_LE_64_PKTS,
442 EFX_MAC_TX_65_TO_127_PKTS,
443 EFX_MAC_TX_128_TO_255_PKTS,
444 EFX_MAC_TX_256_TO_511_PKTS,
445 EFX_MAC_TX_512_TO_1023_PKTS,
446 EFX_MAC_TX_1024_TO_15XX_PKTS,
447 EFX_MAC_TX_GE_15XX_PKTS,
449 EFX_MAC_TX_SGL_COL_PKTS,
450 EFX_MAC_TX_MULT_COL_PKTS,
451 EFX_MAC_TX_EX_COL_PKTS,
452 EFX_MAC_TX_LATE_COL_PKTS,
454 EFX_MAC_TX_EX_DEF_PKTS,
455 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
456 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
457 EFX_MAC_PM_TRUNC_VFIFO_FULL,
458 EFX_MAC_PM_DISCARD_VFIFO_FULL,
459 EFX_MAC_PM_TRUNC_QBB,
460 EFX_MAC_PM_DISCARD_QBB,
461 EFX_MAC_PM_DISCARD_MAPPING,
462 EFX_MAC_RXDP_Q_DISABLED_PKTS,
463 EFX_MAC_RXDP_DI_DROPPED_PKTS,
464 EFX_MAC_RXDP_STREAMING_PKTS,
465 EFX_MAC_RXDP_HLB_FETCH,
466 EFX_MAC_RXDP_HLB_WAIT,
467 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
468 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
469 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
470 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
471 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
472 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
473 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
474 EFX_MAC_VADAPTER_RX_BAD_BYTES,
475 EFX_MAC_VADAPTER_RX_OVERFLOW,
476 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
477 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
478 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
479 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
480 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
481 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
482 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
483 EFX_MAC_VADAPTER_TX_BAD_BYTES,
484 EFX_MAC_VADAPTER_TX_OVERFLOW,
485 EFX_MAC_FEC_UNCORRECTED_ERRORS,
486 EFX_MAC_FEC_CORRECTED_ERRORS,
487 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
488 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
489 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
490 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
491 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
492 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
493 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
494 EFX_MAC_CTPIO_OVERFLOW_FAIL,
495 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
496 EFX_MAC_CTPIO_TIMEOUT_FAIL,
497 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
498 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
499 EFX_MAC_CTPIO_INVALID_WR_FAIL,
500 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
501 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
502 EFX_MAC_CTPIO_RUNT_FALLBACK,
503 EFX_MAC_CTPIO_SUCCESS,
504 EFX_MAC_CTPIO_FALLBACK,
505 EFX_MAC_CTPIO_POISON,
507 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
508 EFX_MAC_RXDP_HLB_IDLE,
509 EFX_MAC_RXDP_HLB_TIMEOUT,
513 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
515 #endif /* EFSYS_OPT_MAC_STATS */
517 typedef enum efx_link_mode_e {
518 EFX_LINK_UNKNOWN = 0,
534 #define EFX_MAC_ADDR_LEN 6
536 #define EFX_VNI_OR_VSID_LEN 3
538 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
540 #define EFX_MAC_MULTICAST_LIST_MAX 256
542 #define EFX_MAC_SDU_MAX 9202
544 #define EFX_MAC_PDU_ADJUSTMENT \
548 + /* bug16011 */ 16) \
550 #define EFX_MAC_PDU(_sdu) \
551 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
554 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
555 * the SDU rounded up slightly.
557 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
559 #define EFX_MAC_PDU_MIN 60
560 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
563 extern __checkReturn efx_rc_t
569 extern __checkReturn efx_rc_t
575 extern __checkReturn efx_rc_t
581 extern __checkReturn efx_rc_t
584 __in boolean_t all_unicst,
585 __in boolean_t mulcst,
586 __in boolean_t all_mulcst,
587 __in boolean_t brdcst);
591 efx_mac_filter_get_all_ucast_mcast(
593 __out boolean_t *all_unicst,
594 __out boolean_t *all_mulcst);
597 extern __checkReturn efx_rc_t
598 efx_mac_multicast_list_set(
600 __in_ecount(6*count) uint8_t const *addrs,
604 extern __checkReturn efx_rc_t
605 efx_mac_filter_default_rxq_set(
608 __in boolean_t using_rss);
612 efx_mac_filter_default_rxq_clear(
613 __in efx_nic_t *enp);
616 extern __checkReturn efx_rc_t
619 __in boolean_t enabled);
622 extern __checkReturn efx_rc_t
625 __out boolean_t *mac_upp);
627 #define EFX_FCNTL_RESPOND 0x00000001
628 #define EFX_FCNTL_GENERATE 0x00000002
631 extern __checkReturn efx_rc_t
634 __in unsigned int fcntl,
635 __in boolean_t autoneg);
641 __out unsigned int *fcntl_wantedp,
642 __out unsigned int *fcntl_linkp);
645 #if EFSYS_OPT_MAC_STATS
650 extern __checkReturn const char *
653 __in unsigned int id);
655 #endif /* EFSYS_OPT_NAMES */
657 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
659 #define EFX_MAC_STATS_MASK_NPAGES \
660 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
661 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
662 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
665 * Get mask of MAC statistics supported by the hardware.
667 * If mask_size is insufficient to return the mask, EINVAL error is
668 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
669 * (which is sizeof (uint32_t)) is sufficient.
672 extern __checkReturn efx_rc_t
673 efx_mac_stats_get_mask(
675 __out_bcount(mask_size) uint32_t *maskp,
676 __in size_t mask_size);
678 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
679 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
680 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
684 extern __checkReturn efx_rc_t
686 __in efx_nic_t *enp);
689 * Upload mac statistics supported by the hardware into the given buffer.
691 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
692 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
694 * The hardware will only DMA statistics that it understands (of course).
695 * Drivers should not make any assumptions about which statistics are
696 * supported, especially when the statistics are generated by firmware.
698 * Thus, drivers should zero this buffer before use, so that not-understood
699 * statistics read back as zero.
702 extern __checkReturn efx_rc_t
703 efx_mac_stats_upload(
705 __in efsys_mem_t *esmp);
708 extern __checkReturn efx_rc_t
709 efx_mac_stats_periodic(
711 __in efsys_mem_t *esmp,
712 __in uint16_t period_ms,
713 __in boolean_t events);
716 extern __checkReturn efx_rc_t
717 efx_mac_stats_update(
719 __in efsys_mem_t *esmp,
720 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
721 __inout_opt uint32_t *generationp);
723 #endif /* EFSYS_OPT_MAC_STATS */
727 typedef enum efx_mon_type_e {
740 __in efx_nic_t *enp);
742 #endif /* EFSYS_OPT_NAMES */
745 extern __checkReturn efx_rc_t
747 __in efx_nic_t *enp);
749 #if EFSYS_OPT_MON_STATS
751 #define EFX_MON_STATS_PAGE_SIZE 0x100
752 #define EFX_MON_MASK_ELEMENT_SIZE 32
754 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
755 typedef enum efx_mon_stat_e {
756 EFX_MON_STAT_CONTROLLER_TEMP,
757 EFX_MON_STAT_PHY_COMMON_TEMP,
758 EFX_MON_STAT_CONTROLLER_COOLING,
759 EFX_MON_STAT_PHY0_TEMP,
760 EFX_MON_STAT_PHY0_COOLING,
761 EFX_MON_STAT_PHY1_TEMP,
762 EFX_MON_STAT_PHY1_COOLING,
768 EFX_MON_STAT_IN_12V0,
769 EFX_MON_STAT_IN_1V2A,
770 EFX_MON_STAT_IN_VREF,
771 EFX_MON_STAT_OUT_VAOE,
772 EFX_MON_STAT_AOE_TEMP,
773 EFX_MON_STAT_PSU_AOE_TEMP,
774 EFX_MON_STAT_PSU_TEMP,
780 EFX_MON_STAT_IN_VAOE,
781 EFX_MON_STAT_OUT_IAOE,
782 EFX_MON_STAT_IN_IAOE,
783 EFX_MON_STAT_NIC_POWER,
785 EFX_MON_STAT_IN_I0V9,
786 EFX_MON_STAT_IN_I1V2,
787 EFX_MON_STAT_IN_0V9_ADC,
788 EFX_MON_STAT_CONTROLLER_2_TEMP,
789 EFX_MON_STAT_VREG_INTERNAL_TEMP,
790 EFX_MON_STAT_VREG_0V9_TEMP,
791 EFX_MON_STAT_VREG_1V2_TEMP,
792 EFX_MON_STAT_CONTROLLER_VPTAT,
793 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
794 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
795 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
796 EFX_MON_STAT_AMBIENT_TEMP,
797 EFX_MON_STAT_AIRFLOW,
798 EFX_MON_STAT_VDD08D_VSS08D_CSR,
799 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
800 EFX_MON_STAT_HOTPOINT_TEMP,
801 EFX_MON_STAT_PHY_POWER_PORT0,
802 EFX_MON_STAT_PHY_POWER_PORT1,
803 EFX_MON_STAT_MUM_VCC,
804 EFX_MON_STAT_IN_0V9_A,
805 EFX_MON_STAT_IN_I0V9_A,
806 EFX_MON_STAT_VREG_0V9_A_TEMP,
807 EFX_MON_STAT_IN_0V9_B,
808 EFX_MON_STAT_IN_I0V9_B,
809 EFX_MON_STAT_VREG_0V9_B_TEMP,
810 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
811 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
812 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
813 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
814 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
815 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
816 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
817 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
818 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
819 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
820 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
821 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
822 EFX_MON_STAT_SODIMM_VOUT,
823 EFX_MON_STAT_SODIMM_0_TEMP,
824 EFX_MON_STAT_SODIMM_1_TEMP,
825 EFX_MON_STAT_PHY0_VCC,
826 EFX_MON_STAT_PHY1_VCC,
827 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
828 EFX_MON_STAT_BOARD_FRONT_TEMP,
829 EFX_MON_STAT_BOARD_BACK_TEMP,
830 EFX_MON_STAT_IN_I1V8,
831 EFX_MON_STAT_IN_I2V5,
832 EFX_MON_STAT_IN_I3V3,
833 EFX_MON_STAT_IN_I12V0,
835 EFX_MON_STAT_IN_I1V3,
839 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
841 typedef enum efx_mon_stat_state_e {
842 EFX_MON_STAT_STATE_OK = 0,
843 EFX_MON_STAT_STATE_WARNING = 1,
844 EFX_MON_STAT_STATE_FATAL = 2,
845 EFX_MON_STAT_STATE_BROKEN = 3,
846 EFX_MON_STAT_STATE_NO_READING = 4,
847 } efx_mon_stat_state_t;
849 typedef enum efx_mon_stat_unit_e {
850 EFX_MON_STAT_UNIT_UNKNOWN = 0,
851 EFX_MON_STAT_UNIT_BOOL,
852 EFX_MON_STAT_UNIT_TEMP_C,
853 EFX_MON_STAT_UNIT_VOLTAGE_MV,
854 EFX_MON_STAT_UNIT_CURRENT_MA,
855 EFX_MON_STAT_UNIT_POWER_W,
856 EFX_MON_STAT_UNIT_RPM,
858 } efx_mon_stat_unit_t;
860 typedef struct efx_mon_stat_value_s {
862 efx_mon_stat_state_t emsv_state;
863 efx_mon_stat_unit_t emsv_unit;
864 } efx_mon_stat_value_t;
866 typedef struct efx_mon_limit_value_s {
867 uint16_t emlv_warning_min;
868 uint16_t emlv_warning_max;
869 uint16_t emlv_fatal_min;
870 uint16_t emlv_fatal_max;
871 } efx_mon_stat_limits_t;
873 typedef enum efx_mon_stat_portmask_e {
874 EFX_MON_STAT_PORTMAP_NONE = 0,
875 EFX_MON_STAT_PORTMAP_PORT0 = 1,
876 EFX_MON_STAT_PORTMAP_PORT1 = 2,
877 EFX_MON_STAT_PORTMAP_PORT2 = 3,
878 EFX_MON_STAT_PORTMAP_PORT3 = 4,
879 EFX_MON_STAT_PORTMAP_ALL = (-1),
880 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
881 } efx_mon_stat_portmask_t;
889 __in efx_mon_stat_t id);
893 efx_mon_stat_description(
895 __in efx_mon_stat_t id);
897 #endif /* EFSYS_OPT_NAMES */
900 extern __checkReturn boolean_t
901 efx_mon_mcdi_to_efx_stat(
903 __out efx_mon_stat_t *statp);
906 extern __checkReturn boolean_t
907 efx_mon_get_stat_unit(
908 __in efx_mon_stat_t stat,
909 __out efx_mon_stat_unit_t *unitp);
912 extern __checkReturn boolean_t
913 efx_mon_get_stat_portmap(
914 __in efx_mon_stat_t stat,
915 __out efx_mon_stat_portmask_t *maskp);
918 extern __checkReturn efx_rc_t
919 efx_mon_stats_update(
921 __in efsys_mem_t *esmp,
922 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
925 extern __checkReturn efx_rc_t
926 efx_mon_limits_update(
928 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
930 #endif /* EFSYS_OPT_MON_STATS */
935 __in efx_nic_t *enp);
940 extern __checkReturn efx_rc_t
942 __in efx_nic_t *enp);
944 #if EFSYS_OPT_PHY_LED_CONTROL
946 typedef enum efx_phy_led_mode_e {
947 EFX_PHY_LED_DEFAULT = 0,
952 } efx_phy_led_mode_t;
955 extern __checkReturn efx_rc_t
958 __in efx_phy_led_mode_t mode);
960 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
963 extern __checkReturn efx_rc_t
965 __in efx_nic_t *enp);
967 #if EFSYS_OPT_LOOPBACK
969 typedef enum efx_loopback_type_e {
970 EFX_LOOPBACK_OFF = 0,
971 EFX_LOOPBACK_DATA = 1,
972 EFX_LOOPBACK_GMAC = 2,
973 EFX_LOOPBACK_XGMII = 3,
974 EFX_LOOPBACK_XGXS = 4,
975 EFX_LOOPBACK_XAUI = 5,
976 EFX_LOOPBACK_GMII = 6,
977 EFX_LOOPBACK_SGMII = 7,
978 EFX_LOOPBACK_XGBR = 8,
979 EFX_LOOPBACK_XFI = 9,
980 EFX_LOOPBACK_XAUI_FAR = 10,
981 EFX_LOOPBACK_GMII_FAR = 11,
982 EFX_LOOPBACK_SGMII_FAR = 12,
983 EFX_LOOPBACK_XFI_FAR = 13,
984 EFX_LOOPBACK_GPHY = 14,
985 EFX_LOOPBACK_PHY_XS = 15,
986 EFX_LOOPBACK_PCS = 16,
987 EFX_LOOPBACK_PMA_PMD = 17,
988 EFX_LOOPBACK_XPORT = 18,
989 EFX_LOOPBACK_XGMII_WS = 19,
990 EFX_LOOPBACK_XAUI_WS = 20,
991 EFX_LOOPBACK_XAUI_WS_FAR = 21,
992 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
993 EFX_LOOPBACK_GMII_WS = 23,
994 EFX_LOOPBACK_XFI_WS = 24,
995 EFX_LOOPBACK_XFI_WS_FAR = 25,
996 EFX_LOOPBACK_PHYXS_WS = 26,
997 EFX_LOOPBACK_PMA_INT = 27,
998 EFX_LOOPBACK_SD_NEAR = 28,
999 EFX_LOOPBACK_SD_FAR = 29,
1000 EFX_LOOPBACK_PMA_INT_WS = 30,
1001 EFX_LOOPBACK_SD_FEP2_WS = 31,
1002 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1003 EFX_LOOPBACK_SD_FEP_WS = 33,
1004 EFX_LOOPBACK_SD_FES_WS = 34,
1005 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1006 EFX_LOOPBACK_DATA_WS = 36,
1007 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1009 } efx_loopback_type_t;
1011 typedef enum efx_loopback_kind_e {
1012 EFX_LOOPBACK_KIND_OFF = 0,
1013 EFX_LOOPBACK_KIND_ALL,
1014 EFX_LOOPBACK_KIND_MAC,
1015 EFX_LOOPBACK_KIND_PHY,
1017 } efx_loopback_kind_t;
1022 __in efx_loopback_kind_t loopback_kind,
1023 __out efx_qword_t *maskp);
1026 extern __checkReturn efx_rc_t
1027 efx_port_loopback_set(
1028 __in efx_nic_t *enp,
1029 __in efx_link_mode_t link_mode,
1030 __in efx_loopback_type_t type);
1035 extern __checkReturn const char *
1036 efx_loopback_type_name(
1037 __in efx_nic_t *enp,
1038 __in efx_loopback_type_t type);
1040 #endif /* EFSYS_OPT_NAMES */
1042 #endif /* EFSYS_OPT_LOOPBACK */
1045 extern __checkReturn efx_rc_t
1047 __in efx_nic_t *enp,
1048 __out_opt efx_link_mode_t *link_modep);
1053 __in efx_nic_t *enp);
1055 typedef enum efx_phy_cap_type_e {
1056 EFX_PHY_CAP_INVALID = 0,
1061 EFX_PHY_CAP_1000HDX,
1062 EFX_PHY_CAP_1000FDX,
1063 EFX_PHY_CAP_10000FDX,
1067 EFX_PHY_CAP_40000FDX,
1069 EFX_PHY_CAP_100000FDX,
1070 EFX_PHY_CAP_25000FDX,
1071 EFX_PHY_CAP_50000FDX,
1072 EFX_PHY_CAP_BASER_FEC,
1073 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1075 EFX_PHY_CAP_RS_FEC_REQUESTED,
1076 EFX_PHY_CAP_25G_BASER_FEC,
1077 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1079 } efx_phy_cap_type_t;
1082 #define EFX_PHY_CAP_CURRENT 0x00000000
1083 #define EFX_PHY_CAP_DEFAULT 0x00000001
1084 #define EFX_PHY_CAP_PERM 0x00000002
1088 efx_phy_adv_cap_get(
1089 __in efx_nic_t *enp,
1091 __out uint32_t *maskp);
1094 extern __checkReturn efx_rc_t
1095 efx_phy_adv_cap_set(
1096 __in efx_nic_t *enp,
1097 __in uint32_t mask);
1102 __in efx_nic_t *enp,
1103 __out uint32_t *maskp);
1106 extern __checkReturn efx_rc_t
1108 __in efx_nic_t *enp,
1109 __out uint32_t *ouip);
1111 typedef enum efx_phy_media_type_e {
1112 EFX_PHY_MEDIA_INVALID = 0,
1117 EFX_PHY_MEDIA_SFP_PLUS,
1118 EFX_PHY_MEDIA_BASE_T,
1119 EFX_PHY_MEDIA_QSFP_PLUS,
1120 EFX_PHY_MEDIA_NTYPES
1121 } efx_phy_media_type_t;
1124 * Get the type of medium currently used. If the board has ports for
1125 * modules, a module is present, and we recognise the media type of
1126 * the module, then this will be the media type of the module.
1127 * Otherwise it will be the media type of the port.
1131 efx_phy_media_type_get(
1132 __in efx_nic_t *enp,
1133 __out efx_phy_media_type_t *typep);
1136 * 2-wire device address of the base information in accordance with SFF-8472
1137 * Diagnostic Monitoring Interface for Optical Transceivers section
1138 * 4 Memory Organization.
1140 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1143 * 2-wire device address of the digital diagnostics monitoring interface
1144 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1145 * Transceivers section 4 Memory Organization.
1147 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1150 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1151 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1154 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1157 * Maximum accessible data offset for PHY module information.
1159 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1163 extern __checkReturn efx_rc_t
1164 efx_phy_module_get_info(
1165 __in efx_nic_t *enp,
1166 __in uint8_t dev_addr,
1169 __out_bcount(len) uint8_t *data);
1171 #if EFSYS_OPT_PHY_STATS
1173 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1174 typedef enum efx_phy_stat_e {
1176 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1177 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1178 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1179 EFX_PHY_STAT_PMA_PMD_REV_A,
1180 EFX_PHY_STAT_PMA_PMD_REV_B,
1181 EFX_PHY_STAT_PMA_PMD_REV_C,
1182 EFX_PHY_STAT_PMA_PMD_REV_D,
1183 EFX_PHY_STAT_PCS_LINK_UP,
1184 EFX_PHY_STAT_PCS_RX_FAULT,
1185 EFX_PHY_STAT_PCS_TX_FAULT,
1186 EFX_PHY_STAT_PCS_BER,
1187 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1188 EFX_PHY_STAT_PHY_XS_LINK_UP,
1189 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1190 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1191 EFX_PHY_STAT_PHY_XS_ALIGN,
1192 EFX_PHY_STAT_PHY_XS_SYNC_A,
1193 EFX_PHY_STAT_PHY_XS_SYNC_B,
1194 EFX_PHY_STAT_PHY_XS_SYNC_C,
1195 EFX_PHY_STAT_PHY_XS_SYNC_D,
1196 EFX_PHY_STAT_AN_LINK_UP,
1197 EFX_PHY_STAT_AN_MASTER,
1198 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1199 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1200 EFX_PHY_STAT_CL22EXT_LINK_UP,
1205 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1206 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1207 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1208 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1209 EFX_PHY_STAT_AN_COMPLETE,
1210 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1211 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1212 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1213 EFX_PHY_STAT_PCS_FW_VERSION_0,
1214 EFX_PHY_STAT_PCS_FW_VERSION_1,
1215 EFX_PHY_STAT_PCS_FW_VERSION_2,
1216 EFX_PHY_STAT_PCS_FW_VERSION_3,
1217 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1218 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1219 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1220 EFX_PHY_STAT_PCS_OP_MODE,
1224 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1231 __in efx_nic_t *enp,
1232 __in efx_phy_stat_t stat);
1234 #endif /* EFSYS_OPT_NAMES */
1236 #define EFX_PHY_STATS_SIZE 0x100
1239 extern __checkReturn efx_rc_t
1240 efx_phy_stats_update(
1241 __in efx_nic_t *enp,
1242 __in efsys_mem_t *esmp,
1243 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1245 #endif /* EFSYS_OPT_PHY_STATS */
1250 typedef enum efx_bist_type_e {
1251 EFX_BIST_TYPE_UNKNOWN,
1252 EFX_BIST_TYPE_PHY_NORMAL,
1253 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1254 EFX_BIST_TYPE_PHY_CABLE_LONG,
1255 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1256 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1257 EFX_BIST_TYPE_REG, /* Test the register memories */
1258 EFX_BIST_TYPE_NTYPES,
1261 typedef enum efx_bist_result_e {
1262 EFX_BIST_RESULT_UNKNOWN,
1263 EFX_BIST_RESULT_RUNNING,
1264 EFX_BIST_RESULT_PASSED,
1265 EFX_BIST_RESULT_FAILED,
1266 } efx_bist_result_t;
1268 typedef enum efx_phy_cable_status_e {
1269 EFX_PHY_CABLE_STATUS_OK,
1270 EFX_PHY_CABLE_STATUS_INVALID,
1271 EFX_PHY_CABLE_STATUS_OPEN,
1272 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1273 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1274 EFX_PHY_CABLE_STATUS_BUSY,
1275 } efx_phy_cable_status_t;
1277 typedef enum efx_bist_value_e {
1278 EFX_BIST_PHY_CABLE_LENGTH_A,
1279 EFX_BIST_PHY_CABLE_LENGTH_B,
1280 EFX_BIST_PHY_CABLE_LENGTH_C,
1281 EFX_BIST_PHY_CABLE_LENGTH_D,
1282 EFX_BIST_PHY_CABLE_STATUS_A,
1283 EFX_BIST_PHY_CABLE_STATUS_B,
1284 EFX_BIST_PHY_CABLE_STATUS_C,
1285 EFX_BIST_PHY_CABLE_STATUS_D,
1286 EFX_BIST_FAULT_CODE,
1288 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1294 EFX_BIST_MEM_EXPECT,
1295 EFX_BIST_MEM_ACTUAL,
1297 EFX_BIST_MEM_ECC_PARITY,
1298 EFX_BIST_MEM_ECC_FATAL,
1303 extern __checkReturn efx_rc_t
1304 efx_bist_enable_offline(
1305 __in efx_nic_t *enp);
1308 extern __checkReturn efx_rc_t
1310 __in efx_nic_t *enp,
1311 __in efx_bist_type_t type);
1314 extern __checkReturn efx_rc_t
1316 __in efx_nic_t *enp,
1317 __in efx_bist_type_t type,
1318 __out efx_bist_result_t *resultp,
1319 __out_opt uint32_t *value_maskp,
1320 __out_ecount_opt(count) unsigned long *valuesp,
1326 __in efx_nic_t *enp,
1327 __in efx_bist_type_t type);
1329 #endif /* EFSYS_OPT_BIST */
1331 #define EFX_FEATURE_IPV6 0x00000001
1332 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1333 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1334 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1335 #define EFX_FEATURE_MCDI 0x00000020
1336 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1337 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1338 #define EFX_FEATURE_TURBO 0x00000100
1339 #define EFX_FEATURE_MCDI_DMA 0x00000200
1340 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1341 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1342 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1343 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1344 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1345 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1347 typedef enum efx_tunnel_protocol_e {
1348 EFX_TUNNEL_PROTOCOL_NONE = 0,
1349 EFX_TUNNEL_PROTOCOL_VXLAN,
1350 EFX_TUNNEL_PROTOCOL_GENEVE,
1351 EFX_TUNNEL_PROTOCOL_NVGRE,
1353 } efx_tunnel_protocol_t;
1355 typedef enum efx_vi_window_shift_e {
1356 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1357 EFX_VI_WINDOW_SHIFT_8K = 13,
1358 EFX_VI_WINDOW_SHIFT_16K = 14,
1359 EFX_VI_WINDOW_SHIFT_64K = 16,
1360 } efx_vi_window_shift_t;
1362 typedef struct efx_nic_cfg_s {
1363 uint32_t enc_board_type;
1364 uint32_t enc_phy_type;
1366 char enc_phy_name[21];
1368 char enc_phy_revision[21];
1369 efx_mon_type_t enc_mon_type;
1370 #if EFSYS_OPT_MON_STATS
1371 uint32_t enc_mon_stat_dma_buf_size;
1372 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1374 unsigned int enc_features;
1375 efx_vi_window_shift_t enc_vi_window_shift;
1376 uint8_t enc_mac_addr[6];
1377 uint8_t enc_port; /* PHY port number */
1378 uint32_t enc_intr_vec_base;
1379 uint32_t enc_intr_limit;
1380 uint32_t enc_evq_limit;
1381 uint32_t enc_txq_limit;
1382 uint32_t enc_rxq_limit;
1383 uint32_t enc_evq_max_nevs;
1384 uint32_t enc_evq_min_nevs;
1385 uint32_t enc_rxq_max_ndescs;
1386 uint32_t enc_rxq_min_ndescs;
1387 uint32_t enc_txq_max_ndescs;
1388 uint32_t enc_txq_min_ndescs;
1389 uint32_t enc_buftbl_limit;
1390 uint32_t enc_piobuf_limit;
1391 uint32_t enc_piobuf_size;
1392 uint32_t enc_piobuf_min_alloc_size;
1393 uint32_t enc_evq_timer_quantum_ns;
1394 uint32_t enc_evq_timer_max_us;
1395 uint32_t enc_clk_mult;
1396 uint32_t enc_ev_desc_size;
1397 uint32_t enc_rx_desc_size;
1398 uint32_t enc_tx_desc_size;
1399 uint32_t enc_rx_prefix_size;
1400 uint32_t enc_rx_buf_align_start;
1401 uint32_t enc_rx_buf_align_end;
1402 #if EFSYS_OPT_RX_SCALE
1403 uint32_t enc_rx_scale_max_exclusive_contexts;
1405 * Mask of supported hash algorithms.
1406 * Hash algorithm types are used as the bit indices.
1408 uint32_t enc_rx_scale_hash_alg_mask;
1410 * Indicates whether port numbers can be included to the
1411 * input data for hash computation.
1413 boolean_t enc_rx_scale_l4_hash_supported;
1414 boolean_t enc_rx_scale_additional_modes_supported;
1415 #endif /* EFSYS_OPT_RX_SCALE */
1416 #if EFSYS_OPT_LOOPBACK
1417 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1418 #endif /* EFSYS_OPT_LOOPBACK */
1419 #if EFSYS_OPT_PHY_FLAGS
1420 uint32_t enc_phy_flags_mask;
1421 #endif /* EFSYS_OPT_PHY_FLAGS */
1422 #if EFSYS_OPT_PHY_LED_CONTROL
1423 uint32_t enc_led_mask;
1424 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1425 #if EFSYS_OPT_PHY_STATS
1426 uint64_t enc_phy_stat_mask;
1427 #endif /* EFSYS_OPT_PHY_STATS */
1429 uint8_t enc_mcdi_mdio_channel;
1430 #if EFSYS_OPT_PHY_STATS
1431 uint32_t enc_mcdi_phy_stat_mask;
1432 #endif /* EFSYS_OPT_PHY_STATS */
1433 #if EFSYS_OPT_MON_STATS
1434 uint32_t *enc_mcdi_sensor_maskp;
1435 uint32_t enc_mcdi_sensor_mask_size;
1436 #endif /* EFSYS_OPT_MON_STATS */
1437 #endif /* EFSYS_OPT_MCDI */
1439 uint32_t enc_bist_mask;
1440 #endif /* EFSYS_OPT_BIST */
1441 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1444 uint32_t enc_privilege_mask;
1445 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1446 boolean_t enc_evq_init_done_ev_supported;
1447 boolean_t enc_bug26807_workaround;
1448 boolean_t enc_bug35388_workaround;
1449 boolean_t enc_bug41750_workaround;
1450 boolean_t enc_bug61265_workaround;
1451 boolean_t enc_bug61297_workaround;
1452 boolean_t enc_rx_batching_enabled;
1453 /* Maximum number of descriptors completed in an rx event. */
1454 uint32_t enc_rx_batch_max;
1455 /* Number of rx descriptors the hardware requires for a push. */
1456 uint32_t enc_rx_push_align;
1457 /* Maximum amount of data in DMA descriptor */
1458 uint32_t enc_tx_dma_desc_size_max;
1460 * Boundary which DMA descriptor data must not cross or 0 if no
1463 uint32_t enc_tx_dma_desc_boundary;
1465 * Maximum number of bytes into the packet the TCP header can start for
1466 * the hardware to apply TSO packet edits.
1468 uint32_t enc_tx_tso_tcp_header_offset_limit;
1469 /* Maximum number of header DMA descriptors per TSO transaction. */
1470 uint32_t enc_tx_tso_max_header_ndescs;
1471 /* Maximum header length acceptable by TSO transaction. */
1472 uint32_t enc_tx_tso_max_header_length;
1473 /* Maximum number of payload DMA descriptors per TSO transaction. */
1474 uint32_t enc_tx_tso_max_payload_ndescs;
1475 /* Maximum payload length per TSO transaction. */
1476 uint32_t enc_tx_tso_max_payload_length;
1477 /* Maximum number of frames to be generated per TSO transaction. */
1478 uint32_t enc_tx_tso_max_nframes;
1479 boolean_t enc_fw_assisted_tso_enabled;
1480 boolean_t enc_fw_assisted_tso_v2_enabled;
1481 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1482 boolean_t enc_tso_v3_enabled;
1483 /* Number of TSO contexts on the NIC (FATSOv2) */
1484 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1485 boolean_t enc_hw_tx_insert_vlan_enabled;
1486 /* Number of PFs on the NIC */
1487 uint32_t enc_hw_pf_count;
1488 /* Datapath firmware vadapter/vport/vswitch support */
1489 boolean_t enc_datapath_cap_evb;
1490 /* Datapath firmware vport reconfigure support */
1491 boolean_t enc_vport_reconfigure_supported;
1492 boolean_t enc_rx_disable_scatter_supported;
1493 boolean_t enc_allow_set_mac_with_installed_filters;
1494 boolean_t enc_enhanced_set_mac_supported;
1495 boolean_t enc_init_evq_v2_supported;
1496 boolean_t enc_no_cont_ev_mode_supported;
1497 boolean_t enc_init_rxq_with_buffer_size;
1498 boolean_t enc_rx_packed_stream_supported;
1499 boolean_t enc_rx_var_packed_stream_supported;
1500 boolean_t enc_rx_es_super_buffer_supported;
1501 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1502 boolean_t enc_pm_and_rxdp_counters;
1503 boolean_t enc_mac_stats_40g_tx_size_bins;
1504 uint32_t enc_tunnel_encapsulations_supported;
1506 * NIC global maximum for unique UDP tunnel ports shared by all
1509 uint32_t enc_tunnel_config_udp_entries_max;
1510 /* External port identifier */
1511 uint8_t enc_external_port;
1512 uint32_t enc_mcdi_max_payload_length;
1513 /* VPD may be per-PF or global */
1514 boolean_t enc_vpd_is_global;
1515 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1516 uint32_t enc_required_pcie_bandwidth_mbps;
1517 uint32_t enc_max_pcie_link_gen;
1518 /* Firmware verifies integrity of NVRAM updates */
1519 boolean_t enc_nvram_update_verify_result_supported;
1520 /* Firmware supports polled NVRAM updates on select partitions */
1521 boolean_t enc_nvram_update_poll_verify_result_supported;
1522 /* Firmware accepts updates via the BUNDLE partition */
1523 boolean_t enc_nvram_bundle_update_supported;
1524 /* Firmware support for extended MAC_STATS buffer */
1525 uint32_t enc_mac_stats_nstats;
1526 boolean_t enc_fec_counters;
1527 boolean_t enc_hlb_counters;
1528 /* Firmware support for "FLAG" and "MARK" filter actions */
1529 boolean_t enc_filter_action_flag_supported;
1530 boolean_t enc_filter_action_mark_supported;
1531 uint32_t enc_filter_action_mark_max;
1532 /* Port assigned to this PCI function */
1533 uint32_t enc_assigned_port;
1536 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1537 ((configp)->evc_function == 0xffff)
1539 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1540 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1542 #define EFX_PCI_FUNCTION(_encp) \
1543 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1545 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1548 extern const efx_nic_cfg_t *
1550 __in const efx_nic_t *enp);
1552 /* RxDPCPU firmware id values by which FW variant can be identified */
1553 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1554 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1555 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1556 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1557 #define EFX_RXDP_DPDK_FW_ID 0x6
1559 typedef struct efx_nic_fw_info_s {
1560 /* Basic FW version information */
1561 uint16_t enfi_mc_fw_version[4];
1563 * If datapath capabilities can be detected,
1564 * additional FW information is to be shown
1566 boolean_t enfi_dpcpu_fw_ids_valid;
1567 /* Rx and Tx datapath CPU FW IDs */
1568 uint16_t enfi_rx_dpcpu_fw_id;
1569 uint16_t enfi_tx_dpcpu_fw_id;
1570 } efx_nic_fw_info_t;
1573 extern __checkReturn efx_rc_t
1574 efx_nic_get_fw_version(
1575 __in efx_nic_t *enp,
1576 __out efx_nic_fw_info_t *enfip);
1578 /* Driver resource limits (minimum required/maximum usable). */
1579 typedef struct efx_drv_limits_s {
1580 uint32_t edl_min_evq_count;
1581 uint32_t edl_max_evq_count;
1583 uint32_t edl_min_rxq_count;
1584 uint32_t edl_max_rxq_count;
1586 uint32_t edl_min_txq_count;
1587 uint32_t edl_max_txq_count;
1589 /* PIO blocks (sub-allocated from piobuf) */
1590 uint32_t edl_min_pio_alloc_size;
1591 uint32_t edl_max_pio_alloc_count;
1595 extern __checkReturn efx_rc_t
1596 efx_nic_set_drv_limits(
1597 __inout efx_nic_t *enp,
1598 __in efx_drv_limits_t *edlp);
1601 * Register the OS driver version string for management agents
1602 * (e.g. via NC-SI). The content length is provided (i.e. no
1603 * NUL terminator). Use length 0 to indicate no version string
1604 * should be advertised. It is valid to set the version string
1605 * only before efx_nic_probe() is called.
1608 extern __checkReturn efx_rc_t
1609 efx_nic_set_drv_version(
1610 __inout efx_nic_t *enp,
1611 __in_ecount(length) char const *verp,
1612 __in size_t length);
1614 typedef enum efx_nic_region_e {
1615 EFX_REGION_VI, /* Memory BAR UC mapping */
1616 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1620 extern __checkReturn efx_rc_t
1621 efx_nic_get_bar_region(
1622 __in efx_nic_t *enp,
1623 __in efx_nic_region_t region,
1624 __out uint32_t *offsetp,
1625 __out size_t *sizep);
1628 extern __checkReturn efx_rc_t
1629 efx_nic_get_vi_pool(
1630 __in efx_nic_t *enp,
1631 __out uint32_t *evq_countp,
1632 __out uint32_t *rxq_countp,
1633 __out uint32_t *txq_countp);
1638 typedef enum efx_vpd_tag_e {
1645 typedef uint16_t efx_vpd_keyword_t;
1647 typedef struct efx_vpd_value_s {
1648 efx_vpd_tag_t evv_tag;
1649 efx_vpd_keyword_t evv_keyword;
1651 uint8_t evv_value[0x100];
1655 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1658 extern __checkReturn efx_rc_t
1660 __in efx_nic_t *enp);
1663 extern __checkReturn efx_rc_t
1665 __in efx_nic_t *enp,
1666 __out size_t *sizep);
1669 extern __checkReturn efx_rc_t
1671 __in efx_nic_t *enp,
1672 __out_bcount(size) caddr_t data,
1676 extern __checkReturn efx_rc_t
1678 __in efx_nic_t *enp,
1679 __in_bcount(size) caddr_t data,
1683 extern __checkReturn efx_rc_t
1685 __in efx_nic_t *enp,
1686 __in_bcount(size) caddr_t data,
1690 extern __checkReturn efx_rc_t
1692 __in efx_nic_t *enp,
1693 __in_bcount(size) caddr_t data,
1695 __inout efx_vpd_value_t *evvp);
1698 extern __checkReturn efx_rc_t
1700 __in efx_nic_t *enp,
1701 __inout_bcount(size) caddr_t data,
1703 __in efx_vpd_value_t *evvp);
1706 extern __checkReturn efx_rc_t
1708 __in efx_nic_t *enp,
1709 __inout_bcount(size) caddr_t data,
1711 __out efx_vpd_value_t *evvp,
1712 __inout unsigned int *contp);
1715 extern __checkReturn efx_rc_t
1717 __in efx_nic_t *enp,
1718 __in_bcount(size) caddr_t data,
1724 __in efx_nic_t *enp);
1726 #endif /* EFSYS_OPT_VPD */
1732 typedef enum efx_nvram_type_e {
1733 EFX_NVRAM_INVALID = 0,
1735 EFX_NVRAM_BOOTROM_CFG,
1736 EFX_NVRAM_MC_FIRMWARE,
1737 EFX_NVRAM_MC_GOLDEN,
1743 EFX_NVRAM_FPGA_BACKUP,
1744 EFX_NVRAM_DYNAMIC_CFG,
1747 EFX_NVRAM_MUM_FIRMWARE,
1748 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1749 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1751 EFX_NVRAM_BUNDLE_METADATA,
1755 typedef struct efx_nvram_info_s {
1757 uint32_t eni_partn_size;
1758 uint32_t eni_address;
1759 uint32_t eni_erase_size;
1760 uint32_t eni_write_size;
1763 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1766 extern __checkReturn efx_rc_t
1768 __in efx_nic_t *enp);
1773 extern __checkReturn efx_rc_t
1775 __in efx_nic_t *enp);
1777 #endif /* EFSYS_OPT_DIAG */
1780 extern __checkReturn efx_rc_t
1782 __in efx_nic_t *enp,
1783 __in efx_nvram_type_t type,
1784 __out size_t *sizep);
1787 extern __checkReturn efx_rc_t
1789 __in efx_nic_t *enp,
1790 __in efx_nvram_type_t type,
1791 __out efx_nvram_info_t *enip);
1794 extern __checkReturn efx_rc_t
1796 __in efx_nic_t *enp,
1797 __in efx_nvram_type_t type,
1798 __out_opt size_t *pref_chunkp);
1801 extern __checkReturn efx_rc_t
1802 efx_nvram_rw_finish(
1803 __in efx_nic_t *enp,
1804 __in efx_nvram_type_t type,
1805 __out_opt uint32_t *verify_resultp);
1808 extern __checkReturn efx_rc_t
1809 efx_nvram_get_version(
1810 __in efx_nic_t *enp,
1811 __in efx_nvram_type_t type,
1812 __out uint32_t *subtypep,
1813 __out_ecount(4) uint16_t version[4]);
1816 extern __checkReturn efx_rc_t
1817 efx_nvram_read_chunk(
1818 __in efx_nic_t *enp,
1819 __in efx_nvram_type_t type,
1820 __in unsigned int offset,
1821 __out_bcount(size) caddr_t data,
1825 extern __checkReturn efx_rc_t
1826 efx_nvram_read_backup(
1827 __in efx_nic_t *enp,
1828 __in efx_nvram_type_t type,
1829 __in unsigned int offset,
1830 __out_bcount(size) caddr_t data,
1834 extern __checkReturn efx_rc_t
1835 efx_nvram_set_version(
1836 __in efx_nic_t *enp,
1837 __in efx_nvram_type_t type,
1838 __in_ecount(4) uint16_t version[4]);
1841 extern __checkReturn efx_rc_t
1843 __in efx_nic_t *enp,
1844 __in efx_nvram_type_t type,
1845 __in_bcount(partn_size) caddr_t partn_data,
1846 __in size_t partn_size);
1849 extern __checkReturn efx_rc_t
1851 __in efx_nic_t *enp,
1852 __in efx_nvram_type_t type);
1855 extern __checkReturn efx_rc_t
1856 efx_nvram_write_chunk(
1857 __in efx_nic_t *enp,
1858 __in efx_nvram_type_t type,
1859 __in unsigned int offset,
1860 __in_bcount(size) caddr_t data,
1866 __in efx_nic_t *enp);
1868 #endif /* EFSYS_OPT_NVRAM */
1870 #if EFSYS_OPT_BOOTCFG
1872 /* Report size and offset of bootcfg sector in NVRAM partition. */
1874 extern __checkReturn efx_rc_t
1875 efx_bootcfg_sector_info(
1876 __in efx_nic_t *enp,
1878 __out_opt uint32_t *sector_countp,
1879 __out size_t *offsetp,
1880 __out size_t *max_sizep);
1883 * Copy bootcfg sector data to a target buffer which may differ in size.
1884 * Optionally corrects format errors in source buffer.
1888 efx_bootcfg_copy_sector(
1889 __in efx_nic_t *enp,
1890 __inout_bcount(sector_length)
1892 __in size_t sector_length,
1893 __out_bcount(data_size) uint8_t *data,
1894 __in size_t data_size,
1895 __in boolean_t handle_format_errors);
1900 __in efx_nic_t *enp,
1901 __out_bcount(size) uint8_t *data,
1907 __in efx_nic_t *enp,
1908 __in_bcount(size) uint8_t *data,
1913 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1914 * (see https://tools.ietf.org/html/rfc1533)
1916 * Summarising the format: the buffer is a sequence of options. All options
1917 * begin with a tag octet, which uniquely identifies the option. Fixed-
1918 * length options without data consist of only a tag octet. Only options PAD
1919 * (0) and END (255) are fixed length. All other options are variable-length
1920 * with a length octet following the tag octet. The value of the length
1921 * octet does not include the two octets specifying the tag and length. The
1922 * length octet is followed by "length" octets of data.
1924 * Option data may be a sequence of sub-options in the same format. The data
1925 * content of the encapsulating option is one or more encapsulated sub-options,
1926 * with no terminating END tag is required.
1928 * To be valid, the top-level sequence of options should be terminated by an
1929 * END tag. The buffer should be padded with the PAD byte.
1931 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1932 * checksum octet. The full buffer (including after the END tag) contributes
1933 * to the checksum, hence the need to fill the buffer to the end with PAD.
1936 #define EFX_DHCP_END ((uint8_t)0xff)
1937 #define EFX_DHCP_PAD ((uint8_t)0)
1939 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1940 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1943 extern __checkReturn uint8_t
1945 __in_bcount(size) uint8_t const *data,
1949 extern __checkReturn efx_rc_t
1951 __in_bcount(size) uint8_t const *data,
1953 __out_opt size_t *usedp);
1956 extern __checkReturn efx_rc_t
1958 __in_bcount(buffer_length) uint8_t *bufferp,
1959 __in size_t buffer_length,
1961 __deref_out uint8_t **valuepp,
1962 __out size_t *value_lengthp);
1965 extern __checkReturn efx_rc_t
1967 __in_bcount(buffer_length) uint8_t *bufferp,
1968 __in size_t buffer_length,
1969 __deref_out uint8_t **endpp);
1973 extern __checkReturn efx_rc_t
1974 efx_dhcp_delete_tag(
1975 __inout_bcount(buffer_length) uint8_t *bufferp,
1976 __in size_t buffer_length,
1980 extern __checkReturn efx_rc_t
1982 __inout_bcount(buffer_length) uint8_t *bufferp,
1983 __in size_t buffer_length,
1985 __in_bcount_opt(value_length) uint8_t *valuep,
1986 __in size_t value_length);
1989 extern __checkReturn efx_rc_t
1990 efx_dhcp_update_tag(
1991 __inout_bcount(buffer_length) uint8_t *bufferp,
1992 __in size_t buffer_length,
1994 __in uint8_t *value_locationp,
1995 __in_bcount_opt(value_length) uint8_t *valuep,
1996 __in size_t value_length);
1999 #endif /* EFSYS_OPT_BOOTCFG */
2001 #if EFSYS_OPT_IMAGE_LAYOUT
2003 #include "ef10_signed_image_layout.h"
2006 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2009 * The image header format is extensible. However, older drivers require an
2010 * exact match of image header version and header length when validating and
2011 * writing firmware images.
2013 * To avoid breaking backward compatibility, we use the upper bits of the
2014 * controller version fields to contain an extra version number used for
2015 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2016 * version). See bug39254 and SF-102785-PS for details.
2018 typedef struct efx_image_header_s {
2020 uint32_t eih_version;
2022 uint32_t eih_subtype;
2023 uint32_t eih_code_size;
2026 uint32_t eih_controller_version_min;
2028 uint16_t eih_controller_version_min_short;
2029 uint8_t eih_extra_version_a;
2030 uint8_t eih_extra_version_b;
2034 uint32_t eih_controller_version_max;
2036 uint16_t eih_controller_version_max_short;
2037 uint8_t eih_extra_version_c;
2038 uint8_t eih_extra_version_d;
2041 uint16_t eih_code_version_a;
2042 uint16_t eih_code_version_b;
2043 uint16_t eih_code_version_c;
2044 uint16_t eih_code_version_d;
2045 } efx_image_header_t;
2047 #define EFX_IMAGE_HEADER_SIZE (40)
2048 #define EFX_IMAGE_HEADER_VERSION (4)
2049 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2052 typedef struct efx_image_trailer_s {
2054 } efx_image_trailer_t;
2056 #define EFX_IMAGE_TRAILER_SIZE (4)
2058 typedef enum efx_image_format_e {
2059 EFX_IMAGE_FORMAT_NO_IMAGE,
2060 EFX_IMAGE_FORMAT_INVALID,
2061 EFX_IMAGE_FORMAT_UNSIGNED,
2062 EFX_IMAGE_FORMAT_SIGNED,
2063 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2064 } efx_image_format_t;
2066 typedef struct efx_image_info_s {
2067 efx_image_format_t eii_format;
2068 uint8_t * eii_imagep;
2069 size_t eii_image_size;
2070 efx_image_header_t * eii_headerp;
2074 extern __checkReturn efx_rc_t
2075 efx_check_reflash_image(
2077 __in uint32_t buffer_size,
2078 __out efx_image_info_t *infop);
2081 extern __checkReturn efx_rc_t
2082 efx_build_signed_image_write_buffer(
2083 __out_bcount(buffer_size)
2085 __in uint32_t buffer_size,
2086 __in efx_image_info_t *infop,
2087 __out efx_image_header_t **headerpp);
2089 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2093 typedef enum efx_pattern_type_t {
2094 EFX_PATTERN_BYTE_INCREMENT = 0,
2095 EFX_PATTERN_ALL_THE_SAME,
2096 EFX_PATTERN_BIT_ALTERNATE,
2097 EFX_PATTERN_BYTE_ALTERNATE,
2098 EFX_PATTERN_BYTE_CHANGING,
2099 EFX_PATTERN_BIT_SWEEP,
2101 } efx_pattern_type_t;
2104 (*efx_sram_pattern_fn_t)(
2106 __in boolean_t negate,
2107 __out efx_qword_t *eqp);
2110 extern __checkReturn efx_rc_t
2112 __in efx_nic_t *enp,
2113 __in efx_pattern_type_t type);
2115 #endif /* EFSYS_OPT_DIAG */
2118 extern __checkReturn efx_rc_t
2119 efx_sram_buf_tbl_set(
2120 __in efx_nic_t *enp,
2122 __in efsys_mem_t *esmp,
2127 efx_sram_buf_tbl_clear(
2128 __in efx_nic_t *enp,
2132 #define EFX_BUF_TBL_SIZE 0x20000
2134 #define EFX_BUF_SIZE 4096
2138 typedef struct efx_evq_s efx_evq_t;
2140 #if EFSYS_OPT_QSTATS
2142 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2143 typedef enum efx_ev_qstat_e {
2149 EV_RX_PAUSE_FRM_ERR,
2150 EV_RX_BUF_OWNER_ID_ERR,
2151 EV_RX_IPV4_HDR_CHKSUM_ERR,
2152 EV_RX_TCP_UDP_CHKSUM_ERR,
2156 EV_RX_MCAST_HASH_MATCH,
2173 EV_DRIVER_SRM_UPD_DONE,
2174 EV_DRIVER_TX_DESCQ_FLS_DONE,
2175 EV_DRIVER_RX_DESCQ_FLS_DONE,
2176 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2177 EV_DRIVER_RX_DSC_ERROR,
2178 EV_DRIVER_TX_DSC_ERROR,
2181 EV_RX_PARSE_INCOMPLETE,
2185 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2187 #endif /* EFSYS_OPT_QSTATS */
2190 extern __checkReturn efx_rc_t
2192 __in efx_nic_t *enp);
2197 __in efx_nic_t *enp);
2200 extern __checkReturn size_t
2202 __in const efx_nic_t *enp,
2203 __in unsigned int ndescs);
2206 extern __checkReturn unsigned int
2208 __in const efx_nic_t *enp,
2209 __in unsigned int ndescs);
2211 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2212 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2213 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2214 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2216 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2217 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2218 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2221 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2222 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2225 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2226 * which is the case when an event queue is set to THROUGHPUT mode.
2228 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2231 extern __checkReturn efx_rc_t
2233 __in efx_nic_t *enp,
2234 __in unsigned int index,
2235 __in efsys_mem_t *esmp,
2239 __in uint32_t flags,
2240 __deref_out efx_evq_t **eepp);
2245 __in efx_evq_t *eep,
2246 __in uint16_t data);
2248 typedef __checkReturn boolean_t
2249 (*efx_initialized_ev_t)(
2250 __in_opt void *arg);
2252 #define EFX_PKT_UNICAST 0x0004
2253 #define EFX_PKT_START 0x0008
2255 #define EFX_PKT_VLAN_TAGGED 0x0010
2256 #define EFX_CKSUM_TCPUDP 0x0020
2257 #define EFX_CKSUM_IPV4 0x0040
2258 #define EFX_PKT_CONT 0x0080
2260 #define EFX_CHECK_VLAN 0x0100
2261 #define EFX_PKT_TCP 0x0200
2262 #define EFX_PKT_UDP 0x0400
2263 #define EFX_PKT_IPV4 0x0800
2265 #define EFX_PKT_IPV6 0x1000
2266 #define EFX_PKT_PREFIX_LEN 0x2000
2267 #define EFX_ADDR_MISMATCH 0x4000
2268 #define EFX_DISCARD 0x8000
2271 * The following flags are used only for packed stream
2272 * mode. The values for the flags are reused to fit into 16 bit,
2273 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2274 * packed stream mode
2276 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2277 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2280 #define EFX_EV_RX_NLABELS 32
2281 #define EFX_EV_TX_NLABELS 32
2283 typedef __checkReturn boolean_t
2286 __in uint32_t label,
2289 __in uint16_t flags);
2291 typedef __checkReturn boolean_t
2292 (*efx_rx_packets_ev_t)(
2294 __in uint32_t label,
2295 __in unsigned int num_packets,
2296 __in uint32_t flags);
2298 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2301 * Packed stream mode is documented in SF-112241-TC.
2302 * The general idea is that, instead of putting each incoming
2303 * packet into a separate buffer which is specified in a RX
2304 * descriptor, a large buffer is provided to the hardware and
2305 * packets are put there in a continuous stream.
2306 * The main advantage of such an approach is that RX queue refilling
2307 * happens much less frequently.
2309 * Equal stride packed stream mode is documented in SF-119419-TC.
2310 * The general idea is to utilize advantages of the packed stream,
2311 * but avoid indirection in packets representation.
2312 * The main advantage of such an approach is that RX queue refilling
2313 * happens much less frequently and packets buffers are independent
2314 * from upper layers point of view.
2317 typedef __checkReturn boolean_t
2320 __in uint32_t label,
2322 __in uint32_t pkt_count,
2323 __in uint16_t flags);
2327 typedef __checkReturn boolean_t
2330 __in uint32_t label,
2333 typedef __checkReturn boolean_t
2334 (*efx_tx_ndescs_ev_t)(
2336 __in uint32_t label,
2337 __in unsigned int ndescs);
2339 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2340 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2341 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2342 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2343 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2344 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2345 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2346 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2347 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2349 typedef __checkReturn boolean_t
2350 (*efx_exception_ev_t)(
2352 __in uint32_t label,
2353 __in uint32_t data);
2355 typedef __checkReturn boolean_t
2356 (*efx_rxq_flush_done_ev_t)(
2358 __in uint32_t rxq_index);
2360 typedef __checkReturn boolean_t
2361 (*efx_rxq_flush_failed_ev_t)(
2363 __in uint32_t rxq_index);
2365 typedef __checkReturn boolean_t
2366 (*efx_txq_flush_done_ev_t)(
2368 __in uint32_t txq_index);
2370 typedef __checkReturn boolean_t
2371 (*efx_software_ev_t)(
2373 __in uint16_t magic);
2375 typedef __checkReturn boolean_t
2378 __in uint32_t code);
2380 #define EFX_SRAM_CLEAR 0
2381 #define EFX_SRAM_UPDATE 1
2382 #define EFX_SRAM_ILLEGAL_CLEAR 2
2384 typedef __checkReturn boolean_t
2385 (*efx_wake_up_ev_t)(
2387 __in uint32_t label);
2389 typedef __checkReturn boolean_t
2392 __in uint32_t label);
2394 typedef __checkReturn boolean_t
2395 (*efx_link_change_ev_t)(
2397 __in efx_link_mode_t link_mode);
2399 #if EFSYS_OPT_MON_STATS
2401 typedef __checkReturn boolean_t
2402 (*efx_monitor_ev_t)(
2404 __in efx_mon_stat_t id,
2405 __in efx_mon_stat_value_t value);
2407 #endif /* EFSYS_OPT_MON_STATS */
2409 #if EFSYS_OPT_MAC_STATS
2411 typedef __checkReturn boolean_t
2412 (*efx_mac_stats_ev_t)(
2414 __in uint32_t generation);
2416 #endif /* EFSYS_OPT_MAC_STATS */
2418 typedef struct efx_ev_callbacks_s {
2419 efx_initialized_ev_t eec_initialized;
2421 efx_rx_packets_ev_t eec_rx_packets;
2422 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2423 efx_rx_ps_ev_t eec_rx_ps;
2426 efx_tx_ndescs_ev_t eec_tx_ndescs;
2427 efx_exception_ev_t eec_exception;
2428 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2429 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2430 efx_txq_flush_done_ev_t eec_txq_flush_done;
2431 efx_software_ev_t eec_software;
2432 efx_sram_ev_t eec_sram;
2433 efx_wake_up_ev_t eec_wake_up;
2434 efx_timer_ev_t eec_timer;
2435 efx_link_change_ev_t eec_link_change;
2436 #if EFSYS_OPT_MON_STATS
2437 efx_monitor_ev_t eec_monitor;
2438 #endif /* EFSYS_OPT_MON_STATS */
2439 #if EFSYS_OPT_MAC_STATS
2440 efx_mac_stats_ev_t eec_mac_stats;
2441 #endif /* EFSYS_OPT_MAC_STATS */
2442 } efx_ev_callbacks_t;
2445 extern __checkReturn boolean_t
2447 __in efx_evq_t *eep,
2448 __in unsigned int count);
2450 #if EFSYS_OPT_EV_PREFETCH
2455 __in efx_evq_t *eep,
2456 __in unsigned int count);
2458 #endif /* EFSYS_OPT_EV_PREFETCH */
2462 efx_ev_qcreate_check_init_done(
2463 __in efx_evq_t *eep,
2464 __in const efx_ev_callbacks_t *eecp,
2465 __in_opt void *arg);
2470 __in efx_evq_t *eep,
2471 __inout unsigned int *countp,
2472 __in const efx_ev_callbacks_t *eecp,
2473 __in_opt void *arg);
2476 extern __checkReturn efx_rc_t
2477 efx_ev_usecs_to_ticks(
2478 __in efx_nic_t *enp,
2479 __in unsigned int usecs,
2480 __out unsigned int *ticksp);
2483 extern __checkReturn efx_rc_t
2485 __in efx_evq_t *eep,
2486 __in unsigned int us);
2489 extern __checkReturn efx_rc_t
2491 __in efx_evq_t *eep,
2492 __in unsigned int count);
2494 #if EFSYS_OPT_QSTATS
2501 __in efx_nic_t *enp,
2502 __in unsigned int id);
2504 #endif /* EFSYS_OPT_NAMES */
2508 efx_ev_qstats_update(
2509 __in efx_evq_t *eep,
2510 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2512 #endif /* EFSYS_OPT_QSTATS */
2517 __in efx_evq_t *eep);
2522 extern __checkReturn efx_rc_t
2524 __inout efx_nic_t *enp);
2529 __in efx_nic_t *enp);
2531 #if EFSYS_OPT_RX_SCATTER
2533 extern __checkReturn efx_rc_t
2534 efx_rx_scatter_enable(
2535 __in efx_nic_t *enp,
2536 __in unsigned int buf_size);
2537 #endif /* EFSYS_OPT_RX_SCATTER */
2539 /* Handle to represent use of the default RSS context. */
2540 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2542 #if EFSYS_OPT_RX_SCALE
2544 typedef enum efx_rx_hash_alg_e {
2545 EFX_RX_HASHALG_LFSR = 0,
2546 EFX_RX_HASHALG_TOEPLITZ,
2547 EFX_RX_HASHALG_PACKED_STREAM,
2549 } efx_rx_hash_alg_t;
2552 * Legacy hash type flags.
2554 * They represent standard tuples for distinct traffic classes.
2556 #define EFX_RX_HASH_IPV4 (1U << 0)
2557 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2558 #define EFX_RX_HASH_IPV6 (1U << 2)
2559 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2561 #define EFX_RX_HASH_LEGACY_MASK \
2562 (EFX_RX_HASH_IPV4 | \
2563 EFX_RX_HASH_TCPIPV4 | \
2564 EFX_RX_HASH_IPV6 | \
2565 EFX_RX_HASH_TCPIPV6)
2568 * The type of the argument used by efx_rx_scale_mode_set() to
2569 * provide a means for the client drivers to configure hashing.
2571 * A properly constructed value can either be:
2572 * - a combination of legacy flags
2573 * - a combination of EFX_RX_HASH() flags
2575 typedef uint32_t efx_rx_hash_type_t;
2577 typedef enum efx_rx_hash_support_e {
2578 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2579 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2580 } efx_rx_hash_support_t;
2582 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2583 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2584 #define EFX_MAXRSS 64 /* RX indirection entry range */
2585 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2587 typedef enum efx_rx_scale_context_type_e {
2588 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2589 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2590 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2591 } efx_rx_scale_context_type_t;
2594 * Traffic classes eligible for hash computation.
2596 * Select packet headers used in computing the receive hash.
2597 * This uses the same encoding as the RSS_MODES field of
2598 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2600 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2601 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2602 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2603 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2604 #define EFX_RX_CLASS_IPV4_LBN 16
2605 #define EFX_RX_CLASS_IPV4_WIDTH 4
2606 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2607 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2608 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2609 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2610 #define EFX_RX_CLASS_IPV6_LBN 28
2611 #define EFX_RX_CLASS_IPV6_WIDTH 4
2613 #define EFX_RX_NCLASSES 6
2616 * Ancillary flags used to construct generic hash tuples.
2617 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2619 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2620 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2621 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2622 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2625 * Generic hash tuples.
2627 * They express combinations of packet fields
2628 * which can contribute to the hash value for
2629 * a particular traffic class.
2631 #define EFX_RX_CLASS_HASH_DISABLE 0
2633 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2634 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2636 #define EFX_RX_CLASS_HASH_2TUPLE \
2637 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2638 EFX_RX_CLASS_HASH_DST_ADDR)
2640 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2641 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2642 EFX_RX_CLASS_HASH_SRC_PORT)
2644 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2645 (EFX_RX_CLASS_HASH_DST_ADDR | \
2646 EFX_RX_CLASS_HASH_DST_PORT)
2648 #define EFX_RX_CLASS_HASH_4TUPLE \
2649 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2650 EFX_RX_CLASS_HASH_DST_ADDR | \
2651 EFX_RX_CLASS_HASH_SRC_PORT | \
2652 EFX_RX_CLASS_HASH_DST_PORT)
2654 #define EFX_RX_CLASS_HASH_NTUPLES 7
2657 * Hash flag constructor.
2659 * Resulting flags encode hash tuples for specific traffic classes.
2660 * The client drivers are encouraged to use these flags to form
2661 * a hash type value.
2663 #define EFX_RX_HASH(_class, _tuple) \
2664 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2665 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2668 * The maximum number of EFX_RX_HASH() flags.
2670 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2673 extern __checkReturn efx_rc_t
2674 efx_rx_scale_hash_flags_get(
2675 __in efx_nic_t *enp,
2676 __in efx_rx_hash_alg_t hash_alg,
2677 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2678 __in unsigned int max_nflags,
2679 __out unsigned int *nflagsp);
2682 extern __checkReturn efx_rc_t
2683 efx_rx_hash_default_support_get(
2684 __in efx_nic_t *enp,
2685 __out efx_rx_hash_support_t *supportp);
2689 extern __checkReturn efx_rc_t
2690 efx_rx_scale_default_support_get(
2691 __in efx_nic_t *enp,
2692 __out efx_rx_scale_context_type_t *typep);
2695 extern __checkReturn efx_rc_t
2696 efx_rx_scale_context_alloc(
2697 __in efx_nic_t *enp,
2698 __in efx_rx_scale_context_type_t type,
2699 __in uint32_t num_queues,
2700 __out uint32_t *rss_contextp);
2703 extern __checkReturn efx_rc_t
2704 efx_rx_scale_context_free(
2705 __in efx_nic_t *enp,
2706 __in uint32_t rss_context);
2709 extern __checkReturn efx_rc_t
2710 efx_rx_scale_mode_set(
2711 __in efx_nic_t *enp,
2712 __in uint32_t rss_context,
2713 __in efx_rx_hash_alg_t alg,
2714 __in efx_rx_hash_type_t type,
2715 __in boolean_t insert);
2718 extern __checkReturn efx_rc_t
2719 efx_rx_scale_tbl_set(
2720 __in efx_nic_t *enp,
2721 __in uint32_t rss_context,
2722 __in_ecount(n) unsigned int *table,
2726 extern __checkReturn efx_rc_t
2727 efx_rx_scale_key_set(
2728 __in efx_nic_t *enp,
2729 __in uint32_t rss_context,
2730 __in_ecount(n) uint8_t *key,
2734 extern __checkReturn uint32_t
2735 efx_pseudo_hdr_hash_get(
2736 __in efx_rxq_t *erp,
2737 __in efx_rx_hash_alg_t func,
2738 __in uint8_t *buffer);
2740 #endif /* EFSYS_OPT_RX_SCALE */
2743 extern __checkReturn efx_rc_t
2744 efx_pseudo_hdr_pkt_length_get(
2745 __in efx_rxq_t *erp,
2746 __in uint8_t *buffer,
2747 __out uint16_t *pkt_lengthp);
2750 extern __checkReturn size_t
2752 __in const efx_nic_t *enp,
2753 __in unsigned int ndescs);
2756 extern __checkReturn unsigned int
2758 __in const efx_nic_t *enp,
2759 __in unsigned int ndescs);
2761 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2763 typedef enum efx_rxq_type_e {
2764 EFX_RXQ_TYPE_DEFAULT,
2765 EFX_RXQ_TYPE_PACKED_STREAM,
2766 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2771 * Dummy flag to be used instead of 0 to make it clear that the argument
2772 * is receive queue flags.
2774 #define EFX_RXQ_FLAG_NONE 0x0
2775 #define EFX_RXQ_FLAG_SCATTER 0x1
2777 * If tunnels are supported and Rx event can provide information about
2778 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2779 * full-feature firmware variant running), outer classes are requested by
2780 * default. However, if the driver supports tunnels, the flag allows to
2781 * request inner classes which are required to be able to interpret inner
2782 * Rx checksum offload results.
2784 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2787 extern __checkReturn efx_rc_t
2789 __in efx_nic_t *enp,
2790 __in unsigned int index,
2791 __in unsigned int label,
2792 __in efx_rxq_type_t type,
2793 __in size_t buf_size,
2794 __in efsys_mem_t *esmp,
2797 __in unsigned int flags,
2798 __in efx_evq_t *eep,
2799 __deref_out efx_rxq_t **erpp);
2801 #if EFSYS_OPT_RX_PACKED_STREAM
2803 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2804 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2805 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2806 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2807 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2810 extern __checkReturn efx_rc_t
2811 efx_rx_qcreate_packed_stream(
2812 __in efx_nic_t *enp,
2813 __in unsigned int index,
2814 __in unsigned int label,
2815 __in uint32_t ps_buf_size,
2816 __in efsys_mem_t *esmp,
2818 __in efx_evq_t *eep,
2819 __deref_out efx_rxq_t **erpp);
2823 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2825 /* Maximum head-of-line block timeout in nanoseconds */
2826 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2829 extern __checkReturn efx_rc_t
2830 efx_rx_qcreate_es_super_buffer(
2831 __in efx_nic_t *enp,
2832 __in unsigned int index,
2833 __in unsigned int label,
2834 __in uint32_t n_bufs_per_desc,
2835 __in uint32_t max_dma_len,
2836 __in uint32_t buf_stride,
2837 __in uint32_t hol_block_timeout,
2838 __in efsys_mem_t *esmp,
2840 __in unsigned int flags,
2841 __in efx_evq_t *eep,
2842 __deref_out efx_rxq_t **erpp);
2846 typedef struct efx_buffer_s {
2847 efsys_dma_addr_t eb_addr;
2852 typedef struct efx_desc_s {
2859 __in efx_rxq_t *erp,
2860 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2862 __in unsigned int ndescs,
2863 __in unsigned int completed,
2864 __in unsigned int added);
2869 __in efx_rxq_t *erp,
2870 __in unsigned int added,
2871 __inout unsigned int *pushedp);
2873 #if EFSYS_OPT_RX_PACKED_STREAM
2877 efx_rx_qpush_ps_credits(
2878 __in efx_rxq_t *erp);
2881 extern __checkReturn uint8_t *
2882 efx_rx_qps_packet_info(
2883 __in efx_rxq_t *erp,
2884 __in uint8_t *buffer,
2885 __in uint32_t buffer_length,
2886 __in uint32_t current_offset,
2887 __out uint16_t *lengthp,
2888 __out uint32_t *next_offsetp,
2889 __out uint32_t *timestamp);
2893 extern __checkReturn efx_rc_t
2895 __in efx_rxq_t *erp);
2900 __in efx_rxq_t *erp);
2905 __in efx_rxq_t *erp);
2909 typedef struct efx_txq_s efx_txq_t;
2911 #if EFSYS_OPT_QSTATS
2913 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2914 typedef enum efx_tx_qstat_e {
2920 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2922 #endif /* EFSYS_OPT_QSTATS */
2925 extern __checkReturn efx_rc_t
2927 __in efx_nic_t *enp);
2932 __in efx_nic_t *enp);
2935 extern __checkReturn size_t
2937 __in const efx_nic_t *enp,
2938 __in unsigned int ndescs);
2941 extern __checkReturn unsigned int
2943 __in const efx_nic_t *enp,
2944 __in unsigned int ndescs);
2946 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2948 #define EFX_TXQ_CKSUM_IPV4 0x0001
2949 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2950 #define EFX_TXQ_FATSOV2 0x0004
2951 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2952 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2955 extern __checkReturn efx_rc_t
2957 __in efx_nic_t *enp,
2958 __in unsigned int index,
2959 __in unsigned int label,
2960 __in efsys_mem_t *esmp,
2963 __in uint16_t flags,
2964 __in efx_evq_t *eep,
2965 __deref_out efx_txq_t **etpp,
2966 __out unsigned int *addedp);
2969 extern __checkReturn efx_rc_t
2971 __in efx_txq_t *etp,
2972 __in_ecount(ndescs) efx_buffer_t *eb,
2973 __in unsigned int ndescs,
2974 __in unsigned int completed,
2975 __inout unsigned int *addedp);
2978 extern __checkReturn efx_rc_t
2980 __in efx_txq_t *etp,
2981 __in unsigned int ns);
2986 __in efx_txq_t *etp,
2987 __in unsigned int added,
2988 __in unsigned int pushed);
2991 extern __checkReturn efx_rc_t
2993 __in efx_txq_t *etp);
2998 __in efx_txq_t *etp);
3001 extern __checkReturn efx_rc_t
3003 __in efx_txq_t *etp);
3007 efx_tx_qpio_disable(
3008 __in efx_txq_t *etp);
3011 extern __checkReturn efx_rc_t
3013 __in efx_txq_t *etp,
3014 __in_ecount(buf_length) uint8_t *buffer,
3015 __in size_t buf_length,
3016 __in size_t pio_buf_offset);
3019 extern __checkReturn efx_rc_t
3021 __in efx_txq_t *etp,
3022 __in size_t pkt_length,
3023 __in unsigned int completed,
3024 __inout unsigned int *addedp);
3027 extern __checkReturn efx_rc_t
3029 __in efx_txq_t *etp,
3030 __in_ecount(n) efx_desc_t *ed,
3031 __in unsigned int n,
3032 __in unsigned int completed,
3033 __inout unsigned int *addedp);
3037 efx_tx_qdesc_dma_create(
3038 __in efx_txq_t *etp,
3039 __in efsys_dma_addr_t addr,
3042 __out efx_desc_t *edp);
3046 efx_tx_qdesc_tso_create(
3047 __in efx_txq_t *etp,
3048 __in uint16_t ipv4_id,
3049 __in uint32_t tcp_seq,
3050 __in uint8_t tcp_flags,
3051 __out efx_desc_t *edp);
3053 /* Number of FATSOv2 option descriptors */
3054 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3056 /* Maximum number of DMA segments per TSO packet (not superframe) */
3057 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3061 efx_tx_qdesc_tso2_create(
3062 __in efx_txq_t *etp,
3063 __in uint16_t ipv4_id,
3064 __in uint16_t outer_ipv4_id,
3065 __in uint32_t tcp_seq,
3066 __in uint16_t tcp_mss,
3067 __out_ecount(count) efx_desc_t *edp,
3072 efx_tx_qdesc_vlantci_create(
3073 __in efx_txq_t *etp,
3075 __out efx_desc_t *edp);
3079 efx_tx_qdesc_checksum_create(
3080 __in efx_txq_t *etp,
3081 __in uint16_t flags,
3082 __out efx_desc_t *edp);
3084 #if EFSYS_OPT_QSTATS
3091 __in efx_nic_t *etp,
3092 __in unsigned int id);
3094 #endif /* EFSYS_OPT_NAMES */
3098 efx_tx_qstats_update(
3099 __in efx_txq_t *etp,
3100 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3102 #endif /* EFSYS_OPT_QSTATS */
3107 __in efx_txq_t *etp);
3112 #if EFSYS_OPT_FILTER
3114 #define EFX_ETHER_TYPE_IPV4 0x0800
3115 #define EFX_ETHER_TYPE_IPV6 0x86DD
3117 #define EFX_IPPROTO_TCP 6
3118 #define EFX_IPPROTO_UDP 17
3119 #define EFX_IPPROTO_GRE 47
3121 /* Use RSS to spread across multiple queues */
3122 #define EFX_FILTER_FLAG_RX_RSS 0x01
3123 /* Enable RX scatter */
3124 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3126 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3127 * May only be set by the filter implementation for each type.
3128 * A removal request will restore the automatic filter in its place.
3130 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3131 /* Filter is for RX */
3132 #define EFX_FILTER_FLAG_RX 0x08
3133 /* Filter is for TX */
3134 #define EFX_FILTER_FLAG_TX 0x10
3135 /* Set match flag on the received packet */
3136 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3137 /* Set match mark on the received packet */
3138 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3140 typedef uint8_t efx_filter_flags_t;
3143 * Flags which specify the fields to match on. The values are the same as in the
3144 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3147 /* Match by remote IP host address */
3148 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3149 /* Match by local IP host address */
3150 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3151 /* Match by remote MAC address */
3152 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3153 /* Match by remote TCP/UDP port */
3154 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3155 /* Match by remote TCP/UDP port */
3156 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3157 /* Match by local TCP/UDP port */
3158 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3159 /* Match by Ether-type */
3160 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3161 /* Match by inner VLAN ID */
3162 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3163 /* Match by outer VLAN ID */
3164 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3165 /* Match by IP transport protocol */
3166 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3167 /* Match by VNI or VSID */
3168 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3169 /* For encapsulated packets, match by inner frame local MAC address */
3170 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3171 /* For encapsulated packets, match all multicast inner frames */
3172 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3173 /* For encapsulated packets, match all unicast inner frames */
3174 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3176 * Match by encap type, this flag does not correspond to
3177 * the MCDI match flags and any unoccupied value may be used
3179 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3180 /* Match otherwise-unmatched multicast and broadcast packets */
3181 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3182 /* Match otherwise-unmatched unicast packets */
3183 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3185 typedef uint32_t efx_filter_match_flags_t;
3187 /* Filter priority from lowest to highest */
3188 typedef enum efx_filter_priority_s {
3189 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3190 * address list or hardware
3191 * requirements. This may only be used
3192 * by the filter implementation for
3194 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3196 } efx_filter_priority_t;
3199 * FIXME: All these fields are assumed to be in little-endian byte order.
3200 * It may be better for some to be big-endian. See bug42804.
3203 typedef struct efx_filter_spec_s {
3204 efx_filter_match_flags_t efs_match_flags;
3205 uint8_t efs_priority;
3206 efx_filter_flags_t efs_flags;
3207 uint16_t efs_dmaq_id;
3208 uint32_t efs_rss_context;
3211 * Saved lower-priority filter. If it is set, it is restored on
3212 * filter delete operation.
3214 struct efx_filter_spec_s *efs_overridden_spec;
3215 /* Fields below here are hashed for software filter lookup */
3216 uint16_t efs_outer_vid;
3217 uint16_t efs_inner_vid;
3218 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3219 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3220 uint16_t efs_ether_type;
3221 uint8_t efs_ip_proto;
3222 efx_tunnel_protocol_t efs_encap_type;
3223 uint16_t efs_loc_port;
3224 uint16_t efs_rem_port;
3225 efx_oword_t efs_rem_host;
3226 efx_oword_t efs_loc_host;
3227 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3228 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3229 } efx_filter_spec_t;
3232 /* Default values for use in filter specifications */
3233 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3234 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3237 extern __checkReturn efx_rc_t
3239 __in efx_nic_t *enp);
3244 __in efx_nic_t *enp);
3247 extern __checkReturn efx_rc_t
3249 __in efx_nic_t *enp,
3250 __inout efx_filter_spec_t *spec);
3253 extern __checkReturn efx_rc_t
3255 __in efx_nic_t *enp,
3256 __inout efx_filter_spec_t *spec);
3259 extern __checkReturn efx_rc_t
3261 __in efx_nic_t *enp);
3264 extern __checkReturn efx_rc_t
3265 efx_filter_supported_filters(
3266 __in efx_nic_t *enp,
3267 __out_ecount(buffer_length) uint32_t *buffer,
3268 __in size_t buffer_length,
3269 __out size_t *list_lengthp);
3273 efx_filter_spec_init_rx(
3274 __out efx_filter_spec_t *spec,
3275 __in efx_filter_priority_t priority,
3276 __in efx_filter_flags_t flags,
3277 __in efx_rxq_t *erp);
3281 efx_filter_spec_init_tx(
3282 __out efx_filter_spec_t *spec,
3283 __in efx_txq_t *etp);
3286 extern __checkReturn efx_rc_t
3287 efx_filter_spec_set_ipv4_local(
3288 __inout efx_filter_spec_t *spec,
3291 __in uint16_t port);
3294 extern __checkReturn efx_rc_t
3295 efx_filter_spec_set_ipv4_full(
3296 __inout efx_filter_spec_t *spec,
3298 __in uint32_t lhost,
3299 __in uint16_t lport,
3300 __in uint32_t rhost,
3301 __in uint16_t rport);
3304 extern __checkReturn efx_rc_t
3305 efx_filter_spec_set_eth_local(
3306 __inout efx_filter_spec_t *spec,
3308 __in const uint8_t *addr);
3312 efx_filter_spec_set_ether_type(
3313 __inout efx_filter_spec_t *spec,
3314 __in uint16_t ether_type);
3317 extern __checkReturn efx_rc_t
3318 efx_filter_spec_set_uc_def(
3319 __inout efx_filter_spec_t *spec);
3322 extern __checkReturn efx_rc_t
3323 efx_filter_spec_set_mc_def(
3324 __inout efx_filter_spec_t *spec);
3326 typedef enum efx_filter_inner_frame_match_e {
3327 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3328 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3329 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3330 } efx_filter_inner_frame_match_t;
3333 extern __checkReturn efx_rc_t
3334 efx_filter_spec_set_encap_type(
3335 __inout efx_filter_spec_t *spec,
3336 __in efx_tunnel_protocol_t encap_type,
3337 __in efx_filter_inner_frame_match_t inner_frame_match);
3340 extern __checkReturn efx_rc_t
3341 efx_filter_spec_set_vxlan(
3342 __inout efx_filter_spec_t *spec,
3343 __in const uint8_t *vni,
3344 __in const uint8_t *inner_addr,
3345 __in const uint8_t *outer_addr);
3348 extern __checkReturn efx_rc_t
3349 efx_filter_spec_set_geneve(
3350 __inout efx_filter_spec_t *spec,
3351 __in const uint8_t *vni,
3352 __in const uint8_t *inner_addr,
3353 __in const uint8_t *outer_addr);
3356 extern __checkReturn efx_rc_t
3357 efx_filter_spec_set_nvgre(
3358 __inout efx_filter_spec_t *spec,
3359 __in const uint8_t *vsid,
3360 __in const uint8_t *inner_addr,
3361 __in const uint8_t *outer_addr);
3363 #if EFSYS_OPT_RX_SCALE
3365 extern __checkReturn efx_rc_t
3366 efx_filter_spec_set_rss_context(
3367 __inout efx_filter_spec_t *spec,
3368 __in uint32_t rss_context);
3370 #endif /* EFSYS_OPT_FILTER */
3375 extern __checkReturn uint32_t
3377 __in_ecount(count) uint32_t const *input,
3379 __in uint32_t init);
3382 extern __checkReturn uint32_t
3384 __in_ecount(length) uint8_t const *input,
3386 __in uint32_t init);
3388 #if EFSYS_OPT_LICENSING
3392 typedef struct efx_key_stats_s {
3394 uint32_t eks_invalid;
3395 uint32_t eks_blacklisted;
3396 uint32_t eks_unverifiable;
3397 uint32_t eks_wrong_node;
3398 uint32_t eks_licensed_apps_lo;
3399 uint32_t eks_licensed_apps_hi;
3400 uint32_t eks_licensed_features_lo;
3401 uint32_t eks_licensed_features_hi;
3405 extern __checkReturn efx_rc_t
3407 __in efx_nic_t *enp);
3412 __in efx_nic_t *enp);
3415 extern __checkReturn boolean_t
3416 efx_lic_check_support(
3417 __in efx_nic_t *enp);
3420 extern __checkReturn efx_rc_t
3421 efx_lic_update_licenses(
3422 __in efx_nic_t *enp);
3425 extern __checkReturn efx_rc_t
3426 efx_lic_get_key_stats(
3427 __in efx_nic_t *enp,
3428 __out efx_key_stats_t *ksp);
3431 extern __checkReturn efx_rc_t
3433 __in efx_nic_t *enp,
3434 __in uint64_t app_id,
3435 __out boolean_t *licensedp);
3438 extern __checkReturn efx_rc_t
3440 __in efx_nic_t *enp,
3441 __in size_t buffer_size,
3442 __out uint32_t *typep,
3443 __out size_t *lengthp,
3444 __out_opt uint8_t *bufferp);
3448 extern __checkReturn efx_rc_t
3450 __in efx_nic_t *enp,
3451 __in_bcount(buffer_size)
3453 __in size_t buffer_size,
3454 __out uint32_t *startp);
3457 extern __checkReturn efx_rc_t
3459 __in efx_nic_t *enp,
3460 __in_bcount(buffer_size)
3462 __in size_t buffer_size,
3463 __in uint32_t offset,
3464 __out uint32_t *endp);
3467 extern __checkReturn __success(return != B_FALSE) boolean_t
3469 __in efx_nic_t *enp,
3470 __in_bcount(buffer_size)
3472 __in size_t buffer_size,
3473 __in uint32_t offset,
3474 __out uint32_t *startp,
3475 __out uint32_t *lengthp);
3478 extern __checkReturn __success(return != B_FALSE) boolean_t
3479 efx_lic_validate_key(
3480 __in efx_nic_t *enp,
3481 __in_bcount(length) caddr_t keyp,
3482 __in uint32_t length);
3485 extern __checkReturn efx_rc_t
3487 __in efx_nic_t *enp,
3488 __in_bcount(buffer_size)
3490 __in size_t buffer_size,
3491 __in uint32_t offset,
3492 __in uint32_t length,
3493 __out_bcount_part(key_max_size, *lengthp)
3495 __in size_t key_max_size,
3496 __out uint32_t *lengthp);
3499 extern __checkReturn efx_rc_t
3501 __in efx_nic_t *enp,
3502 __in_bcount(buffer_size)
3504 __in size_t buffer_size,
3505 __in uint32_t offset,
3506 __in_bcount(length) caddr_t keyp,
3507 __in uint32_t length,
3508 __out uint32_t *lengthp);
3511 extern __checkReturn efx_rc_t
3513 __in efx_nic_t *enp,
3514 __in_bcount(buffer_size)
3516 __in size_t buffer_size,
3517 __in uint32_t offset,
3518 __in uint32_t length,
3520 __out uint32_t *deltap);
3523 extern __checkReturn efx_rc_t
3524 efx_lic_create_partition(
3525 __in efx_nic_t *enp,
3526 __in_bcount(buffer_size)
3528 __in size_t buffer_size);
3530 extern __checkReturn efx_rc_t
3531 efx_lic_finish_partition(
3532 __in efx_nic_t *enp,
3533 __in_bcount(buffer_size)
3535 __in size_t buffer_size);
3537 #endif /* EFSYS_OPT_LICENSING */
3541 #if EFSYS_OPT_TUNNEL
3544 extern __checkReturn efx_rc_t
3546 __in efx_nic_t *enp);
3551 __in efx_nic_t *enp);
3554 * For overlay network encapsulation using UDP, the firmware needs to know
3555 * the configured UDP port for the overlay so it can decode encapsulated
3557 * The UDP port/protocol list is global.
3561 extern __checkReturn efx_rc_t
3562 efx_tunnel_config_udp_add(
3563 __in efx_nic_t *enp,
3564 __in uint16_t port /* host/cpu-endian */,
3565 __in efx_tunnel_protocol_t protocol);
3568 extern __checkReturn efx_rc_t
3569 efx_tunnel_config_udp_remove(
3570 __in efx_nic_t *enp,
3571 __in uint16_t port /* host/cpu-endian */,
3572 __in efx_tunnel_protocol_t protocol);
3576 efx_tunnel_config_clear(
3577 __in efx_nic_t *enp);
3580 * Apply tunnel UDP ports configuration to hardware.
3582 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3586 extern __checkReturn efx_rc_t
3587 efx_tunnel_reconfigure(
3588 __in efx_nic_t *enp);
3590 #endif /* EFSYS_OPT_TUNNEL */
3592 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3595 * Firmware subvariant choice options.
3597 * It may be switched to no Tx checksum if attached drivers are either
3598 * preboot or firmware subvariant aware and no VIS are allocated.
3599 * If may be always switched to default explicitly using set request or
3600 * implicitly if unaware driver is attaching. If switching is done when
3601 * a driver is attached, it gets MC_REBOOT event and should recreate its
3604 * See SF-119419-TC DPDK Firmware Driver Interface and
3605 * SF-109306-TC EF10 for Driver Writers for details.
3607 typedef enum efx_nic_fw_subvariant_e {
3608 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3609 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3610 EFX_NIC_FW_SUBVARIANT_NTYPES
3611 } efx_nic_fw_subvariant_t;
3614 extern __checkReturn efx_rc_t
3615 efx_nic_get_fw_subvariant(
3616 __in efx_nic_t *enp,
3617 __out efx_nic_fw_subvariant_t *subvariantp);
3620 extern __checkReturn efx_rc_t
3621 efx_nic_set_fw_subvariant(
3622 __in efx_nic_t *enp,
3623 __in efx_nic_fw_subvariant_t subvariant);
3625 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3627 typedef enum efx_phy_fec_type_e {
3628 EFX_PHY_FEC_NONE = 0,
3631 } efx_phy_fec_type_t;
3634 extern __checkReturn efx_rc_t
3635 efx_phy_fec_type_get(
3636 __in efx_nic_t *enp,
3637 __out efx_phy_fec_type_t *typep);
3639 typedef struct efx_phy_link_state_s {
3640 uint32_t epls_adv_cap_mask;
3641 uint32_t epls_lp_cap_mask;
3642 uint32_t epls_ld_cap_mask;
3643 unsigned int epls_fcntl;
3644 efx_phy_fec_type_t epls_fec;
3645 efx_link_mode_t epls_link_mode;
3646 } efx_phy_link_state_t;
3649 extern __checkReturn efx_rc_t
3650 efx_phy_link_state_get(
3651 __in efx_nic_t *enp,
3652 __out efx_phy_link_state_t *eplsp);
3657 typedef uint32_t efx_vswitch_id_t;
3658 typedef uint32_t efx_vport_id_t;
3660 typedef enum efx_vswitch_type_e {
3661 EFX_VSWITCH_TYPE_VLAN = 1,
3662 EFX_VSWITCH_TYPE_VEB,
3663 /* VSWITCH_TYPE_VEPA: obsolete */
3664 EFX_VSWITCH_TYPE_MUX = 4,
3665 } efx_vswitch_type_t;
3667 typedef enum efx_vport_type_e {
3668 EFX_VPORT_TYPE_NORMAL = 4,
3669 EFX_VPORT_TYPE_EXPANSION,
3670 EFX_VPORT_TYPE_TEST,
3673 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3674 #define EFX_FILTER_VID_UNSPEC 0xffff
3675 #define EFX_DEFAULT_VSWITCH_ID 1
3677 /* Default VF VLAN ID on creation */
3678 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3679 #define EFX_VPORT_ID_INVALID 0
3681 typedef struct efx_vport_config_s {
3682 /* Either VF index or 0xffff for PF */
3683 uint16_t evc_function;
3684 /* VLAN ID of the associated function */
3686 /* vport id shared with client driver */
3687 efx_vport_id_t evc_vport_id;
3688 /* MAC address of the associated function */
3689 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3691 * vports created with this flag set may only transfer traffic on the
3692 * VLANs permitted by the vport. Also, an attempt to install filter with
3693 * VLAN will be refused unless requesting function has VLAN privilege.
3695 boolean_t evc_vlan_restrict;
3696 /* Whether this function is assigned or not */
3697 boolean_t evc_vport_assigned;
3698 } efx_vport_config_t;
3700 typedef struct efx_vswitch_s efx_vswitch_t;
3703 extern __checkReturn efx_rc_t
3705 __in efx_nic_t *enp);
3710 __in efx_nic_t *enp);
3713 extern __checkReturn efx_rc_t
3714 efx_evb_vswitch_create(
3715 __in efx_nic_t *enp,
3716 __in uint32_t num_vports,
3717 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3718 __deref_out efx_vswitch_t **evpp);
3721 extern __checkReturn efx_rc_t
3722 efx_evb_vswitch_destroy(
3723 __in efx_nic_t *enp,
3724 __in efx_vswitch_t *evp);
3727 extern __checkReturn efx_rc_t
3728 efx_evb_vport_mac_set(
3729 __in efx_nic_t *enp,
3730 __in efx_vswitch_t *evp,
3731 __in efx_vport_id_t vport_id,
3732 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3735 extern __checkReturn efx_rc_t
3736 efx_evb_vport_vlan_set(
3737 __in efx_nic_t *enp,
3738 __in efx_vswitch_t *evp,
3739 __in efx_vport_id_t vport_id,
3743 extern __checkReturn efx_rc_t
3744 efx_evb_vport_reset(
3745 __in efx_nic_t *enp,
3746 __in efx_vswitch_t *evp,
3747 __in efx_vport_id_t vport_id,
3748 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3750 __out boolean_t *is_fn_resetp);
3753 extern __checkReturn efx_rc_t
3754 efx_evb_vport_stats(
3755 __in efx_nic_t *enp,
3756 __in efx_vswitch_t *evp,
3757 __in efx_vport_id_t vport_id,
3758 __out efsys_mem_t *stats_bufferp);
3760 #endif /* EFSYS_OPT_EVB */
3762 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3764 typedef struct efx_proxy_auth_config_s {
3765 efsys_mem_t *request_bufferp;
3766 efsys_mem_t *response_bufferp;
3767 efsys_mem_t *status_bufferp;
3771 uint32_t handled_privileges;
3772 } efx_proxy_auth_config_t;
3774 typedef struct efx_proxy_cmd_params_s {
3777 uint8_t *request_bufferp;
3778 size_t request_size;
3779 uint8_t *response_bufferp;
3780 size_t response_size;
3781 size_t *response_size_actualp;
3782 } efx_proxy_cmd_params_t;
3785 extern __checkReturn efx_rc_t
3786 efx_proxy_auth_init(
3787 __in efx_nic_t *enp);
3791 efx_proxy_auth_fini(
3792 __in efx_nic_t *enp);
3795 extern __checkReturn efx_rc_t
3796 efx_proxy_auth_configure(
3797 __in efx_nic_t *enp,
3798 __in efx_proxy_auth_config_t *configp);
3801 extern __checkReturn efx_rc_t
3802 efx_proxy_auth_destroy(
3803 __in efx_nic_t *enp,
3804 __in uint32_t handled_privileges);
3807 extern __checkReturn efx_rc_t
3808 efx_proxy_auth_complete_request(
3809 __in efx_nic_t *enp,
3810 __in uint32_t fn_index,
3811 __in uint32_t proxy_result,
3812 __in uint32_t handle);
3815 extern __checkReturn efx_rc_t
3816 efx_proxy_auth_exec_cmd(
3817 __in efx_nic_t *enp,
3818 __inout efx_proxy_cmd_params_t *paramsp);
3821 extern __checkReturn efx_rc_t
3822 efx_proxy_auth_set_privilege_mask(
3823 __in efx_nic_t *enp,
3824 __in uint32_t vf_index,
3826 __in uint32_t value);
3829 extern __checkReturn efx_rc_t
3830 efx_proxy_auth_privilege_mask_get(
3831 __in efx_nic_t *enp,
3832 __in uint32_t pf_index,
3833 __in uint32_t vf_index,
3834 __out uint32_t *maskp);
3837 extern __checkReturn efx_rc_t
3838 efx_proxy_auth_privilege_modify(
3839 __in efx_nic_t *enp,
3840 __in uint32_t pf_index,
3841 __in uint32_t vf_index,
3842 __in uint32_t add_privileges_mask,
3843 __in uint32_t remove_privileges_mask);
3845 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3851 #endif /* _SYS_EFX_H */