1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
62 extern __checkReturn efx_rc_t
66 __out efx_family_t *efp,
67 __out unsigned int *membarp);
70 #define EFX_PCI_VENID_SFC 0x1924
72 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
74 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
75 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
76 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
78 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
79 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
80 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
82 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
83 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
85 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
86 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
87 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
89 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
90 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
91 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
94 #define EFX_MEM_BAR_SIENA 2
96 #define EFX_MEM_BAR_HUNTINGTON_PF 2
97 #define EFX_MEM_BAR_HUNTINGTON_VF 0
99 #define EFX_MEM_BAR_MEDFORD_PF 2
100 #define EFX_MEM_BAR_MEDFORD_VF 0
102 #define EFX_MEM_BAR_MEDFORD2 0
110 EFX_ERR_BUFID_DC_OOB,
123 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
125 extern __checkReturn uint32_t
127 __in uint32_t crc_init,
128 __in_ecount(length) uint8_t const *input,
132 /* Type prototypes */
134 typedef struct efx_rxq_s efx_rxq_t;
138 typedef struct efx_nic_s efx_nic_t;
141 extern __checkReturn efx_rc_t
143 __in efx_family_t family,
144 __in efsys_identifier_t *esip,
145 __in efsys_bar_t *esbp,
146 __in efsys_lock_t *eslp,
147 __deref_out efx_nic_t **enpp);
149 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
150 typedef enum efx_fw_variant_e {
151 EFX_FW_VARIANT_FULL_FEATURED,
152 EFX_FW_VARIANT_LOW_LATENCY,
153 EFX_FW_VARIANT_PACKED_STREAM,
154 EFX_FW_VARIANT_HIGH_TX_RATE,
155 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
156 EFX_FW_VARIANT_RULES_ENGINE,
158 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
162 extern __checkReturn efx_rc_t
165 __in efx_fw_variant_t efv);
168 extern __checkReturn efx_rc_t
170 __in efx_nic_t *enp);
173 extern __checkReturn efx_rc_t
175 __in efx_nic_t *enp);
178 extern __checkReturn boolean_t
179 efx_nic_hw_unavailable(
180 __in efx_nic_t *enp);
184 efx_nic_set_hw_unavailable(
185 __in efx_nic_t *enp);
190 extern __checkReturn efx_rc_t
191 efx_nic_register_test(
192 __in efx_nic_t *enp);
194 #endif /* EFSYS_OPT_DIAG */
199 __in efx_nic_t *enp);
204 __in efx_nic_t *enp);
209 __in efx_nic_t *enp);
211 #define EFX_PCIE_LINK_SPEED_GEN1 1
212 #define EFX_PCIE_LINK_SPEED_GEN2 2
213 #define EFX_PCIE_LINK_SPEED_GEN3 3
215 typedef enum efx_pcie_link_performance_e {
216 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
217 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
218 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
219 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
220 } efx_pcie_link_performance_t;
223 extern __checkReturn efx_rc_t
224 efx_nic_calculate_pcie_link_bandwidth(
225 __in uint32_t pcie_link_width,
226 __in uint32_t pcie_link_gen,
227 __out uint32_t *bandwidth_mbpsp);
230 extern __checkReturn efx_rc_t
231 efx_nic_check_pcie_link_speed(
233 __in uint32_t pcie_link_width,
234 __in uint32_t pcie_link_gen,
235 __out efx_pcie_link_performance_t *resultp);
240 /* EF10 architecture NICs require MCDIv2 commands */
241 #define WITH_MCDI_V2 1
244 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
246 typedef enum efx_mcdi_exception_e {
247 EFX_MCDI_EXCEPTION_MC_REBOOT,
248 EFX_MCDI_EXCEPTION_MC_BADASSERT,
249 } efx_mcdi_exception_t;
251 #if EFSYS_OPT_MCDI_LOGGING
252 typedef enum efx_log_msg_e {
254 EFX_LOG_MCDI_REQUEST,
255 EFX_LOG_MCDI_RESPONSE,
257 #endif /* EFSYS_OPT_MCDI_LOGGING */
259 typedef struct efx_mcdi_transport_s {
261 efsys_mem_t *emt_dma_mem;
262 void (*emt_execute)(void *, efx_mcdi_req_t *);
263 void (*emt_ev_cpl)(void *);
264 void (*emt_exception)(void *, efx_mcdi_exception_t);
265 #if EFSYS_OPT_MCDI_LOGGING
266 void (*emt_logger)(void *, efx_log_msg_t,
267 void *, size_t, void *, size_t);
268 #endif /* EFSYS_OPT_MCDI_LOGGING */
269 #if EFSYS_OPT_MCDI_PROXY_AUTH
270 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
271 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
272 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
273 void (*emt_ev_proxy_request)(void *, uint32_t);
274 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
275 } efx_mcdi_transport_t;
278 extern __checkReturn efx_rc_t
281 __in const efx_mcdi_transport_t *mtp);
284 extern __checkReturn efx_rc_t
286 __in efx_nic_t *enp);
291 __in efx_nic_t *enp);
295 efx_mcdi_get_timeout(
297 __in efx_mcdi_req_t *emrp,
298 __out uint32_t *usec_timeoutp);
302 efx_mcdi_request_start(
304 __in efx_mcdi_req_t *emrp,
305 __in boolean_t ev_cpl);
308 extern __checkReturn boolean_t
309 efx_mcdi_request_poll(
310 __in efx_nic_t *enp);
313 extern __checkReturn boolean_t
314 efx_mcdi_request_abort(
315 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
322 #endif /* EFSYS_OPT_MCDI */
326 #define EFX_NINTR_SIENA 1024
328 typedef enum efx_intr_type_e {
329 EFX_INTR_INVALID = 0,
335 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
338 extern __checkReturn efx_rc_t
341 __in efx_intr_type_t type,
342 __in_opt efsys_mem_t *esmp);
347 __in efx_nic_t *enp);
352 __in efx_nic_t *enp);
356 efx_intr_disable_unlocked(
357 __in efx_nic_t *enp);
359 #define EFX_INTR_NEVQS 32
362 extern __checkReturn efx_rc_t
365 __in unsigned int level);
369 efx_intr_status_line(
371 __out boolean_t *fatalp,
372 __out uint32_t *maskp);
376 efx_intr_status_message(
378 __in unsigned int message,
379 __out boolean_t *fatalp);
384 __in efx_nic_t *enp);
389 __in efx_nic_t *enp);
393 #if EFSYS_OPT_MAC_STATS
395 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
396 typedef enum efx_mac_stat_e {
399 EFX_MAC_RX_UNICST_PKTS,
400 EFX_MAC_RX_MULTICST_PKTS,
401 EFX_MAC_RX_BRDCST_PKTS,
402 EFX_MAC_RX_PAUSE_PKTS,
403 EFX_MAC_RX_LE_64_PKTS,
404 EFX_MAC_RX_65_TO_127_PKTS,
405 EFX_MAC_RX_128_TO_255_PKTS,
406 EFX_MAC_RX_256_TO_511_PKTS,
407 EFX_MAC_RX_512_TO_1023_PKTS,
408 EFX_MAC_RX_1024_TO_15XX_PKTS,
409 EFX_MAC_RX_GE_15XX_PKTS,
411 EFX_MAC_RX_FCS_ERRORS,
412 EFX_MAC_RX_DROP_EVENTS,
413 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
414 EFX_MAC_RX_SYMBOL_ERRORS,
415 EFX_MAC_RX_ALIGN_ERRORS,
416 EFX_MAC_RX_INTERNAL_ERRORS,
417 EFX_MAC_RX_JABBER_PKTS,
418 EFX_MAC_RX_LANE0_CHAR_ERR,
419 EFX_MAC_RX_LANE1_CHAR_ERR,
420 EFX_MAC_RX_LANE2_CHAR_ERR,
421 EFX_MAC_RX_LANE3_CHAR_ERR,
422 EFX_MAC_RX_LANE0_DISP_ERR,
423 EFX_MAC_RX_LANE1_DISP_ERR,
424 EFX_MAC_RX_LANE2_DISP_ERR,
425 EFX_MAC_RX_LANE3_DISP_ERR,
426 EFX_MAC_RX_MATCH_FAULT,
427 EFX_MAC_RX_NODESC_DROP_CNT,
430 EFX_MAC_TX_UNICST_PKTS,
431 EFX_MAC_TX_MULTICST_PKTS,
432 EFX_MAC_TX_BRDCST_PKTS,
433 EFX_MAC_TX_PAUSE_PKTS,
434 EFX_MAC_TX_LE_64_PKTS,
435 EFX_MAC_TX_65_TO_127_PKTS,
436 EFX_MAC_TX_128_TO_255_PKTS,
437 EFX_MAC_TX_256_TO_511_PKTS,
438 EFX_MAC_TX_512_TO_1023_PKTS,
439 EFX_MAC_TX_1024_TO_15XX_PKTS,
440 EFX_MAC_TX_GE_15XX_PKTS,
442 EFX_MAC_TX_SGL_COL_PKTS,
443 EFX_MAC_TX_MULT_COL_PKTS,
444 EFX_MAC_TX_EX_COL_PKTS,
445 EFX_MAC_TX_LATE_COL_PKTS,
447 EFX_MAC_TX_EX_DEF_PKTS,
448 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
449 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
450 EFX_MAC_PM_TRUNC_VFIFO_FULL,
451 EFX_MAC_PM_DISCARD_VFIFO_FULL,
452 EFX_MAC_PM_TRUNC_QBB,
453 EFX_MAC_PM_DISCARD_QBB,
454 EFX_MAC_PM_DISCARD_MAPPING,
455 EFX_MAC_RXDP_Q_DISABLED_PKTS,
456 EFX_MAC_RXDP_DI_DROPPED_PKTS,
457 EFX_MAC_RXDP_STREAMING_PKTS,
458 EFX_MAC_RXDP_HLB_FETCH,
459 EFX_MAC_RXDP_HLB_WAIT,
460 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
461 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
462 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
463 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
464 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
465 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
466 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
467 EFX_MAC_VADAPTER_RX_BAD_BYTES,
468 EFX_MAC_VADAPTER_RX_OVERFLOW,
469 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
470 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
471 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
472 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
473 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
474 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
475 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
476 EFX_MAC_VADAPTER_TX_BAD_BYTES,
477 EFX_MAC_VADAPTER_TX_OVERFLOW,
478 EFX_MAC_FEC_UNCORRECTED_ERRORS,
479 EFX_MAC_FEC_CORRECTED_ERRORS,
480 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
481 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
482 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
483 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
484 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
485 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
486 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
487 EFX_MAC_CTPIO_OVERFLOW_FAIL,
488 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
489 EFX_MAC_CTPIO_TIMEOUT_FAIL,
490 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
491 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
492 EFX_MAC_CTPIO_INVALID_WR_FAIL,
493 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
494 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
495 EFX_MAC_CTPIO_RUNT_FALLBACK,
496 EFX_MAC_CTPIO_SUCCESS,
497 EFX_MAC_CTPIO_FALLBACK,
498 EFX_MAC_CTPIO_POISON,
500 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
501 EFX_MAC_RXDP_HLB_IDLE,
502 EFX_MAC_RXDP_HLB_TIMEOUT,
506 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
508 #endif /* EFSYS_OPT_MAC_STATS */
510 typedef enum efx_link_mode_e {
511 EFX_LINK_UNKNOWN = 0,
527 #define EFX_MAC_ADDR_LEN 6
529 #define EFX_VNI_OR_VSID_LEN 3
531 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
533 #define EFX_MAC_MULTICAST_LIST_MAX 256
535 #define EFX_MAC_SDU_MAX 9202
537 #define EFX_MAC_PDU_ADJUSTMENT \
541 + /* bug16011 */ 16) \
543 #define EFX_MAC_PDU(_sdu) \
544 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
547 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
548 * the SDU rounded up slightly.
550 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
552 #define EFX_MAC_PDU_MIN 60
553 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
556 extern __checkReturn efx_rc_t
562 extern __checkReturn efx_rc_t
568 extern __checkReturn efx_rc_t
574 extern __checkReturn efx_rc_t
577 __in boolean_t all_unicst,
578 __in boolean_t mulcst,
579 __in boolean_t all_mulcst,
580 __in boolean_t brdcst);
584 efx_mac_filter_get_all_ucast_mcast(
586 __out boolean_t *all_unicst,
587 __out boolean_t *all_mulcst);
590 extern __checkReturn efx_rc_t
591 efx_mac_multicast_list_set(
593 __in_ecount(6*count) uint8_t const *addrs,
597 extern __checkReturn efx_rc_t
598 efx_mac_filter_default_rxq_set(
601 __in boolean_t using_rss);
605 efx_mac_filter_default_rxq_clear(
606 __in efx_nic_t *enp);
609 extern __checkReturn efx_rc_t
612 __in boolean_t enabled);
615 extern __checkReturn efx_rc_t
618 __out boolean_t *mac_upp);
620 #define EFX_FCNTL_RESPOND 0x00000001
621 #define EFX_FCNTL_GENERATE 0x00000002
624 extern __checkReturn efx_rc_t
627 __in unsigned int fcntl,
628 __in boolean_t autoneg);
634 __out unsigned int *fcntl_wantedp,
635 __out unsigned int *fcntl_linkp);
638 #if EFSYS_OPT_MAC_STATS
643 extern __checkReturn const char *
646 __in unsigned int id);
648 #endif /* EFSYS_OPT_NAMES */
650 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
652 #define EFX_MAC_STATS_MASK_NPAGES \
653 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
654 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
655 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
658 * Get mask of MAC statistics supported by the hardware.
660 * If mask_size is insufficient to return the mask, EINVAL error is
661 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
662 * (which is sizeof (uint32_t)) is sufficient.
665 extern __checkReturn efx_rc_t
666 efx_mac_stats_get_mask(
668 __out_bcount(mask_size) uint32_t *maskp,
669 __in size_t mask_size);
671 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
672 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
673 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
677 extern __checkReturn efx_rc_t
679 __in efx_nic_t *enp);
682 * Upload mac statistics supported by the hardware into the given buffer.
684 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
685 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
687 * The hardware will only DMA statistics that it understands (of course).
688 * Drivers should not make any assumptions about which statistics are
689 * supported, especially when the statistics are generated by firmware.
691 * Thus, drivers should zero this buffer before use, so that not-understood
692 * statistics read back as zero.
695 extern __checkReturn efx_rc_t
696 efx_mac_stats_upload(
698 __in efsys_mem_t *esmp);
701 extern __checkReturn efx_rc_t
702 efx_mac_stats_periodic(
704 __in efsys_mem_t *esmp,
705 __in uint16_t period_ms,
706 __in boolean_t events);
709 extern __checkReturn efx_rc_t
710 efx_mac_stats_update(
712 __in efsys_mem_t *esmp,
713 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
714 __inout_opt uint32_t *generationp);
716 #endif /* EFSYS_OPT_MAC_STATS */
720 typedef enum efx_mon_type_e {
733 __in efx_nic_t *enp);
735 #endif /* EFSYS_OPT_NAMES */
738 extern __checkReturn efx_rc_t
740 __in efx_nic_t *enp);
742 #if EFSYS_OPT_MON_STATS
744 #define EFX_MON_STATS_PAGE_SIZE 0x100
745 #define EFX_MON_MASK_ELEMENT_SIZE 32
747 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
748 typedef enum efx_mon_stat_e {
749 EFX_MON_STAT_CONTROLLER_TEMP,
750 EFX_MON_STAT_PHY_COMMON_TEMP,
751 EFX_MON_STAT_CONTROLLER_COOLING,
752 EFX_MON_STAT_PHY0_TEMP,
753 EFX_MON_STAT_PHY0_COOLING,
754 EFX_MON_STAT_PHY1_TEMP,
755 EFX_MON_STAT_PHY1_COOLING,
761 EFX_MON_STAT_IN_12V0,
762 EFX_MON_STAT_IN_1V2A,
763 EFX_MON_STAT_IN_VREF,
764 EFX_MON_STAT_OUT_VAOE,
765 EFX_MON_STAT_AOE_TEMP,
766 EFX_MON_STAT_PSU_AOE_TEMP,
767 EFX_MON_STAT_PSU_TEMP,
773 EFX_MON_STAT_IN_VAOE,
774 EFX_MON_STAT_OUT_IAOE,
775 EFX_MON_STAT_IN_IAOE,
776 EFX_MON_STAT_NIC_POWER,
778 EFX_MON_STAT_IN_I0V9,
779 EFX_MON_STAT_IN_I1V2,
780 EFX_MON_STAT_IN_0V9_ADC,
781 EFX_MON_STAT_CONTROLLER_2_TEMP,
782 EFX_MON_STAT_VREG_INTERNAL_TEMP,
783 EFX_MON_STAT_VREG_0V9_TEMP,
784 EFX_MON_STAT_VREG_1V2_TEMP,
785 EFX_MON_STAT_CONTROLLER_VPTAT,
786 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
787 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
788 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
789 EFX_MON_STAT_AMBIENT_TEMP,
790 EFX_MON_STAT_AIRFLOW,
791 EFX_MON_STAT_VDD08D_VSS08D_CSR,
792 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
793 EFX_MON_STAT_HOTPOINT_TEMP,
794 EFX_MON_STAT_PHY_POWER_PORT0,
795 EFX_MON_STAT_PHY_POWER_PORT1,
796 EFX_MON_STAT_MUM_VCC,
797 EFX_MON_STAT_IN_0V9_A,
798 EFX_MON_STAT_IN_I0V9_A,
799 EFX_MON_STAT_VREG_0V9_A_TEMP,
800 EFX_MON_STAT_IN_0V9_B,
801 EFX_MON_STAT_IN_I0V9_B,
802 EFX_MON_STAT_VREG_0V9_B_TEMP,
803 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
804 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
805 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
806 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
807 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
808 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
809 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
810 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
811 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
812 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
813 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
814 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
815 EFX_MON_STAT_SODIMM_VOUT,
816 EFX_MON_STAT_SODIMM_0_TEMP,
817 EFX_MON_STAT_SODIMM_1_TEMP,
818 EFX_MON_STAT_PHY0_VCC,
819 EFX_MON_STAT_PHY1_VCC,
820 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
821 EFX_MON_STAT_BOARD_FRONT_TEMP,
822 EFX_MON_STAT_BOARD_BACK_TEMP,
823 EFX_MON_STAT_IN_I1V8,
824 EFX_MON_STAT_IN_I2V5,
825 EFX_MON_STAT_IN_I3V3,
826 EFX_MON_STAT_IN_I12V0,
828 EFX_MON_STAT_IN_I1V3,
832 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
834 typedef enum efx_mon_stat_state_e {
835 EFX_MON_STAT_STATE_OK = 0,
836 EFX_MON_STAT_STATE_WARNING = 1,
837 EFX_MON_STAT_STATE_FATAL = 2,
838 EFX_MON_STAT_STATE_BROKEN = 3,
839 EFX_MON_STAT_STATE_NO_READING = 4,
840 } efx_mon_stat_state_t;
842 typedef enum efx_mon_stat_unit_e {
843 EFX_MON_STAT_UNIT_UNKNOWN = 0,
844 EFX_MON_STAT_UNIT_BOOL,
845 EFX_MON_STAT_UNIT_TEMP_C,
846 EFX_MON_STAT_UNIT_VOLTAGE_MV,
847 EFX_MON_STAT_UNIT_CURRENT_MA,
848 EFX_MON_STAT_UNIT_POWER_W,
849 EFX_MON_STAT_UNIT_RPM,
851 } efx_mon_stat_unit_t;
853 typedef struct efx_mon_stat_value_s {
855 efx_mon_stat_state_t emsv_state;
856 efx_mon_stat_unit_t emsv_unit;
857 } efx_mon_stat_value_t;
859 typedef struct efx_mon_limit_value_s {
860 uint16_t emlv_warning_min;
861 uint16_t emlv_warning_max;
862 uint16_t emlv_fatal_min;
863 uint16_t emlv_fatal_max;
864 } efx_mon_stat_limits_t;
866 typedef enum efx_mon_stat_portmask_e {
867 EFX_MON_STAT_PORTMAP_NONE = 0,
868 EFX_MON_STAT_PORTMAP_PORT0 = 1,
869 EFX_MON_STAT_PORTMAP_PORT1 = 2,
870 EFX_MON_STAT_PORTMAP_PORT2 = 3,
871 EFX_MON_STAT_PORTMAP_PORT3 = 4,
872 EFX_MON_STAT_PORTMAP_ALL = (-1),
873 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
874 } efx_mon_stat_portmask_t;
882 __in efx_mon_stat_t id);
886 efx_mon_stat_description(
888 __in efx_mon_stat_t id);
890 #endif /* EFSYS_OPT_NAMES */
893 extern __checkReturn boolean_t
894 efx_mon_mcdi_to_efx_stat(
896 __out efx_mon_stat_t *statp);
899 extern __checkReturn boolean_t
900 efx_mon_get_stat_unit(
901 __in efx_mon_stat_t stat,
902 __out efx_mon_stat_unit_t *unitp);
905 extern __checkReturn boolean_t
906 efx_mon_get_stat_portmap(
907 __in efx_mon_stat_t stat,
908 __out efx_mon_stat_portmask_t *maskp);
911 extern __checkReturn efx_rc_t
912 efx_mon_stats_update(
914 __in efsys_mem_t *esmp,
915 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
918 extern __checkReturn efx_rc_t
919 efx_mon_limits_update(
921 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
923 #endif /* EFSYS_OPT_MON_STATS */
928 __in efx_nic_t *enp);
933 extern __checkReturn efx_rc_t
935 __in efx_nic_t *enp);
937 #if EFSYS_OPT_PHY_LED_CONTROL
939 typedef enum efx_phy_led_mode_e {
940 EFX_PHY_LED_DEFAULT = 0,
945 } efx_phy_led_mode_t;
948 extern __checkReturn efx_rc_t
951 __in efx_phy_led_mode_t mode);
953 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
956 extern __checkReturn efx_rc_t
958 __in efx_nic_t *enp);
960 #if EFSYS_OPT_LOOPBACK
962 typedef enum efx_loopback_type_e {
963 EFX_LOOPBACK_OFF = 0,
964 EFX_LOOPBACK_DATA = 1,
965 EFX_LOOPBACK_GMAC = 2,
966 EFX_LOOPBACK_XGMII = 3,
967 EFX_LOOPBACK_XGXS = 4,
968 EFX_LOOPBACK_XAUI = 5,
969 EFX_LOOPBACK_GMII = 6,
970 EFX_LOOPBACK_SGMII = 7,
971 EFX_LOOPBACK_XGBR = 8,
972 EFX_LOOPBACK_XFI = 9,
973 EFX_LOOPBACK_XAUI_FAR = 10,
974 EFX_LOOPBACK_GMII_FAR = 11,
975 EFX_LOOPBACK_SGMII_FAR = 12,
976 EFX_LOOPBACK_XFI_FAR = 13,
977 EFX_LOOPBACK_GPHY = 14,
978 EFX_LOOPBACK_PHY_XS = 15,
979 EFX_LOOPBACK_PCS = 16,
980 EFX_LOOPBACK_PMA_PMD = 17,
981 EFX_LOOPBACK_XPORT = 18,
982 EFX_LOOPBACK_XGMII_WS = 19,
983 EFX_LOOPBACK_XAUI_WS = 20,
984 EFX_LOOPBACK_XAUI_WS_FAR = 21,
985 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
986 EFX_LOOPBACK_GMII_WS = 23,
987 EFX_LOOPBACK_XFI_WS = 24,
988 EFX_LOOPBACK_XFI_WS_FAR = 25,
989 EFX_LOOPBACK_PHYXS_WS = 26,
990 EFX_LOOPBACK_PMA_INT = 27,
991 EFX_LOOPBACK_SD_NEAR = 28,
992 EFX_LOOPBACK_SD_FAR = 29,
993 EFX_LOOPBACK_PMA_INT_WS = 30,
994 EFX_LOOPBACK_SD_FEP2_WS = 31,
995 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
996 EFX_LOOPBACK_SD_FEP_WS = 33,
997 EFX_LOOPBACK_SD_FES_WS = 34,
998 EFX_LOOPBACK_AOE_INT_NEAR = 35,
999 EFX_LOOPBACK_DATA_WS = 36,
1000 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1002 } efx_loopback_type_t;
1004 typedef enum efx_loopback_kind_e {
1005 EFX_LOOPBACK_KIND_OFF = 0,
1006 EFX_LOOPBACK_KIND_ALL,
1007 EFX_LOOPBACK_KIND_MAC,
1008 EFX_LOOPBACK_KIND_PHY,
1010 } efx_loopback_kind_t;
1015 __in efx_loopback_kind_t loopback_kind,
1016 __out efx_qword_t *maskp);
1019 extern __checkReturn efx_rc_t
1020 efx_port_loopback_set(
1021 __in efx_nic_t *enp,
1022 __in efx_link_mode_t link_mode,
1023 __in efx_loopback_type_t type);
1028 extern __checkReturn const char *
1029 efx_loopback_type_name(
1030 __in efx_nic_t *enp,
1031 __in efx_loopback_type_t type);
1033 #endif /* EFSYS_OPT_NAMES */
1035 #endif /* EFSYS_OPT_LOOPBACK */
1038 extern __checkReturn efx_rc_t
1040 __in efx_nic_t *enp,
1041 __out_opt efx_link_mode_t *link_modep);
1046 __in efx_nic_t *enp);
1048 typedef enum efx_phy_cap_type_e {
1049 EFX_PHY_CAP_INVALID = 0,
1054 EFX_PHY_CAP_1000HDX,
1055 EFX_PHY_CAP_1000FDX,
1056 EFX_PHY_CAP_10000FDX,
1060 EFX_PHY_CAP_40000FDX,
1062 EFX_PHY_CAP_100000FDX,
1063 EFX_PHY_CAP_25000FDX,
1064 EFX_PHY_CAP_50000FDX,
1065 EFX_PHY_CAP_BASER_FEC,
1066 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1068 EFX_PHY_CAP_RS_FEC_REQUESTED,
1069 EFX_PHY_CAP_25G_BASER_FEC,
1070 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1072 } efx_phy_cap_type_t;
1075 #define EFX_PHY_CAP_CURRENT 0x00000000
1076 #define EFX_PHY_CAP_DEFAULT 0x00000001
1077 #define EFX_PHY_CAP_PERM 0x00000002
1081 efx_phy_adv_cap_get(
1082 __in efx_nic_t *enp,
1084 __out uint32_t *maskp);
1087 extern __checkReturn efx_rc_t
1088 efx_phy_adv_cap_set(
1089 __in efx_nic_t *enp,
1090 __in uint32_t mask);
1095 __in efx_nic_t *enp,
1096 __out uint32_t *maskp);
1099 extern __checkReturn efx_rc_t
1101 __in efx_nic_t *enp,
1102 __out uint32_t *ouip);
1104 typedef enum efx_phy_media_type_e {
1105 EFX_PHY_MEDIA_INVALID = 0,
1110 EFX_PHY_MEDIA_SFP_PLUS,
1111 EFX_PHY_MEDIA_BASE_T,
1112 EFX_PHY_MEDIA_QSFP_PLUS,
1113 EFX_PHY_MEDIA_NTYPES
1114 } efx_phy_media_type_t;
1117 * Get the type of medium currently used. If the board has ports for
1118 * modules, a module is present, and we recognise the media type of
1119 * the module, then this will be the media type of the module.
1120 * Otherwise it will be the media type of the port.
1124 efx_phy_media_type_get(
1125 __in efx_nic_t *enp,
1126 __out efx_phy_media_type_t *typep);
1129 * 2-wire device address of the base information in accordance with SFF-8472
1130 * Diagnostic Monitoring Interface for Optical Transceivers section
1131 * 4 Memory Organization.
1133 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1136 * 2-wire device address of the digital diagnostics monitoring interface
1137 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1138 * Transceivers section 4 Memory Organization.
1140 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1143 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1144 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1147 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1150 * Maximum accessible data offset for PHY module information.
1152 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1156 extern __checkReturn efx_rc_t
1157 efx_phy_module_get_info(
1158 __in efx_nic_t *enp,
1159 __in uint8_t dev_addr,
1162 __out_bcount(len) uint8_t *data);
1164 #if EFSYS_OPT_PHY_STATS
1166 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1167 typedef enum efx_phy_stat_e {
1169 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1170 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1171 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1172 EFX_PHY_STAT_PMA_PMD_REV_A,
1173 EFX_PHY_STAT_PMA_PMD_REV_B,
1174 EFX_PHY_STAT_PMA_PMD_REV_C,
1175 EFX_PHY_STAT_PMA_PMD_REV_D,
1176 EFX_PHY_STAT_PCS_LINK_UP,
1177 EFX_PHY_STAT_PCS_RX_FAULT,
1178 EFX_PHY_STAT_PCS_TX_FAULT,
1179 EFX_PHY_STAT_PCS_BER,
1180 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1181 EFX_PHY_STAT_PHY_XS_LINK_UP,
1182 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1183 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1184 EFX_PHY_STAT_PHY_XS_ALIGN,
1185 EFX_PHY_STAT_PHY_XS_SYNC_A,
1186 EFX_PHY_STAT_PHY_XS_SYNC_B,
1187 EFX_PHY_STAT_PHY_XS_SYNC_C,
1188 EFX_PHY_STAT_PHY_XS_SYNC_D,
1189 EFX_PHY_STAT_AN_LINK_UP,
1190 EFX_PHY_STAT_AN_MASTER,
1191 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1192 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1193 EFX_PHY_STAT_CL22EXT_LINK_UP,
1198 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1199 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1200 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1201 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1202 EFX_PHY_STAT_AN_COMPLETE,
1203 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1204 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1205 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1206 EFX_PHY_STAT_PCS_FW_VERSION_0,
1207 EFX_PHY_STAT_PCS_FW_VERSION_1,
1208 EFX_PHY_STAT_PCS_FW_VERSION_2,
1209 EFX_PHY_STAT_PCS_FW_VERSION_3,
1210 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1211 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1212 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1213 EFX_PHY_STAT_PCS_OP_MODE,
1217 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1224 __in efx_nic_t *enp,
1225 __in efx_phy_stat_t stat);
1227 #endif /* EFSYS_OPT_NAMES */
1229 #define EFX_PHY_STATS_SIZE 0x100
1232 extern __checkReturn efx_rc_t
1233 efx_phy_stats_update(
1234 __in efx_nic_t *enp,
1235 __in efsys_mem_t *esmp,
1236 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1238 #endif /* EFSYS_OPT_PHY_STATS */
1243 typedef enum efx_bist_type_e {
1244 EFX_BIST_TYPE_UNKNOWN,
1245 EFX_BIST_TYPE_PHY_NORMAL,
1246 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1247 EFX_BIST_TYPE_PHY_CABLE_LONG,
1248 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1249 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1250 EFX_BIST_TYPE_REG, /* Test the register memories */
1251 EFX_BIST_TYPE_NTYPES,
1254 typedef enum efx_bist_result_e {
1255 EFX_BIST_RESULT_UNKNOWN,
1256 EFX_BIST_RESULT_RUNNING,
1257 EFX_BIST_RESULT_PASSED,
1258 EFX_BIST_RESULT_FAILED,
1259 } efx_bist_result_t;
1261 typedef enum efx_phy_cable_status_e {
1262 EFX_PHY_CABLE_STATUS_OK,
1263 EFX_PHY_CABLE_STATUS_INVALID,
1264 EFX_PHY_CABLE_STATUS_OPEN,
1265 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1266 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1267 EFX_PHY_CABLE_STATUS_BUSY,
1268 } efx_phy_cable_status_t;
1270 typedef enum efx_bist_value_e {
1271 EFX_BIST_PHY_CABLE_LENGTH_A,
1272 EFX_BIST_PHY_CABLE_LENGTH_B,
1273 EFX_BIST_PHY_CABLE_LENGTH_C,
1274 EFX_BIST_PHY_CABLE_LENGTH_D,
1275 EFX_BIST_PHY_CABLE_STATUS_A,
1276 EFX_BIST_PHY_CABLE_STATUS_B,
1277 EFX_BIST_PHY_CABLE_STATUS_C,
1278 EFX_BIST_PHY_CABLE_STATUS_D,
1279 EFX_BIST_FAULT_CODE,
1281 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1287 EFX_BIST_MEM_EXPECT,
1288 EFX_BIST_MEM_ACTUAL,
1290 EFX_BIST_MEM_ECC_PARITY,
1291 EFX_BIST_MEM_ECC_FATAL,
1296 extern __checkReturn efx_rc_t
1297 efx_bist_enable_offline(
1298 __in efx_nic_t *enp);
1301 extern __checkReturn efx_rc_t
1303 __in efx_nic_t *enp,
1304 __in efx_bist_type_t type);
1307 extern __checkReturn efx_rc_t
1309 __in efx_nic_t *enp,
1310 __in efx_bist_type_t type,
1311 __out efx_bist_result_t *resultp,
1312 __out_opt uint32_t *value_maskp,
1313 __out_ecount_opt(count) unsigned long *valuesp,
1319 __in efx_nic_t *enp,
1320 __in efx_bist_type_t type);
1322 #endif /* EFSYS_OPT_BIST */
1324 #define EFX_FEATURE_IPV6 0x00000001
1325 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1326 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1327 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1328 #define EFX_FEATURE_MCDI 0x00000020
1329 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1330 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1331 #define EFX_FEATURE_TURBO 0x00000100
1332 #define EFX_FEATURE_MCDI_DMA 0x00000200
1333 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1334 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1335 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1336 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1337 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1338 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1340 typedef enum efx_tunnel_protocol_e {
1341 EFX_TUNNEL_PROTOCOL_NONE = 0,
1342 EFX_TUNNEL_PROTOCOL_VXLAN,
1343 EFX_TUNNEL_PROTOCOL_GENEVE,
1344 EFX_TUNNEL_PROTOCOL_NVGRE,
1346 } efx_tunnel_protocol_t;
1348 typedef enum efx_vi_window_shift_e {
1349 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1350 EFX_VI_WINDOW_SHIFT_8K = 13,
1351 EFX_VI_WINDOW_SHIFT_16K = 14,
1352 EFX_VI_WINDOW_SHIFT_64K = 16,
1353 } efx_vi_window_shift_t;
1355 typedef struct efx_nic_cfg_s {
1356 uint32_t enc_board_type;
1357 uint32_t enc_phy_type;
1359 char enc_phy_name[21];
1361 char enc_phy_revision[21];
1362 efx_mon_type_t enc_mon_type;
1363 #if EFSYS_OPT_MON_STATS
1364 uint32_t enc_mon_stat_dma_buf_size;
1365 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1367 unsigned int enc_features;
1368 efx_vi_window_shift_t enc_vi_window_shift;
1369 uint8_t enc_mac_addr[6];
1370 uint8_t enc_port; /* PHY port number */
1371 uint32_t enc_intr_vec_base;
1372 uint32_t enc_intr_limit;
1373 uint32_t enc_evq_limit;
1374 uint32_t enc_txq_limit;
1375 uint32_t enc_rxq_limit;
1376 uint32_t enc_evq_max_nevs;
1377 uint32_t enc_evq_min_nevs;
1378 uint32_t enc_rxq_max_ndescs;
1379 uint32_t enc_rxq_min_ndescs;
1380 uint32_t enc_txq_max_ndescs;
1381 uint32_t enc_txq_min_ndescs;
1382 uint32_t enc_buftbl_limit;
1383 uint32_t enc_piobuf_limit;
1384 uint32_t enc_piobuf_size;
1385 uint32_t enc_piobuf_min_alloc_size;
1386 uint32_t enc_evq_timer_quantum_ns;
1387 uint32_t enc_evq_timer_max_us;
1388 uint32_t enc_clk_mult;
1389 uint32_t enc_ev_desc_size;
1390 uint32_t enc_rx_desc_size;
1391 uint32_t enc_tx_desc_size;
1392 uint32_t enc_rx_prefix_size;
1393 uint32_t enc_rx_buf_align_start;
1394 uint32_t enc_rx_buf_align_end;
1395 #if EFSYS_OPT_RX_SCALE
1396 uint32_t enc_rx_scale_max_exclusive_contexts;
1398 * Mask of supported hash algorithms.
1399 * Hash algorithm types are used as the bit indices.
1401 uint32_t enc_rx_scale_hash_alg_mask;
1403 * Indicates whether port numbers can be included to the
1404 * input data for hash computation.
1406 boolean_t enc_rx_scale_l4_hash_supported;
1407 boolean_t enc_rx_scale_additional_modes_supported;
1408 #endif /* EFSYS_OPT_RX_SCALE */
1409 #if EFSYS_OPT_LOOPBACK
1410 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1411 #endif /* EFSYS_OPT_LOOPBACK */
1412 #if EFSYS_OPT_PHY_FLAGS
1413 uint32_t enc_phy_flags_mask;
1414 #endif /* EFSYS_OPT_PHY_FLAGS */
1415 #if EFSYS_OPT_PHY_LED_CONTROL
1416 uint32_t enc_led_mask;
1417 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1418 #if EFSYS_OPT_PHY_STATS
1419 uint64_t enc_phy_stat_mask;
1420 #endif /* EFSYS_OPT_PHY_STATS */
1422 uint8_t enc_mcdi_mdio_channel;
1423 #if EFSYS_OPT_PHY_STATS
1424 uint32_t enc_mcdi_phy_stat_mask;
1425 #endif /* EFSYS_OPT_PHY_STATS */
1426 #if EFSYS_OPT_MON_STATS
1427 uint32_t *enc_mcdi_sensor_maskp;
1428 uint32_t enc_mcdi_sensor_mask_size;
1429 #endif /* EFSYS_OPT_MON_STATS */
1430 #endif /* EFSYS_OPT_MCDI */
1432 uint32_t enc_bist_mask;
1433 #endif /* EFSYS_OPT_BIST */
1437 uint32_t enc_privilege_mask;
1438 #endif /* EFX_OPTS_EF10() */
1439 boolean_t enc_bug26807_workaround;
1440 boolean_t enc_bug35388_workaround;
1441 boolean_t enc_bug41750_workaround;
1442 boolean_t enc_bug61265_workaround;
1443 boolean_t enc_bug61297_workaround;
1444 boolean_t enc_rx_batching_enabled;
1445 /* Maximum number of descriptors completed in an rx event. */
1446 uint32_t enc_rx_batch_max;
1447 /* Number of rx descriptors the hardware requires for a push. */
1448 uint32_t enc_rx_push_align;
1449 /* Maximum amount of data in DMA descriptor */
1450 uint32_t enc_tx_dma_desc_size_max;
1452 * Boundary which DMA descriptor data must not cross or 0 if no
1455 uint32_t enc_tx_dma_desc_boundary;
1457 * Maximum number of bytes into the packet the TCP header can start for
1458 * the hardware to apply TSO packet edits.
1460 uint32_t enc_tx_tso_tcp_header_offset_limit;
1461 boolean_t enc_fw_assisted_tso_enabled;
1462 boolean_t enc_fw_assisted_tso_v2_enabled;
1463 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1464 /* Number of TSO contexts on the NIC (FATSOv2) */
1465 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1466 boolean_t enc_hw_tx_insert_vlan_enabled;
1467 /* Number of PFs on the NIC */
1468 uint32_t enc_hw_pf_count;
1469 /* Datapath firmware vadapter/vport/vswitch support */
1470 boolean_t enc_datapath_cap_evb;
1471 /* Datapath firmware vport reconfigure support */
1472 boolean_t enc_vport_reconfigure_supported;
1473 boolean_t enc_rx_disable_scatter_supported;
1474 boolean_t enc_allow_set_mac_with_installed_filters;
1475 boolean_t enc_enhanced_set_mac_supported;
1476 boolean_t enc_init_evq_v2_supported;
1477 boolean_t enc_no_cont_ev_mode_supported;
1478 boolean_t enc_init_rxq_with_buffer_size;
1479 boolean_t enc_rx_packed_stream_supported;
1480 boolean_t enc_rx_var_packed_stream_supported;
1481 boolean_t enc_rx_es_super_buffer_supported;
1482 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1483 boolean_t enc_pm_and_rxdp_counters;
1484 boolean_t enc_mac_stats_40g_tx_size_bins;
1485 uint32_t enc_tunnel_encapsulations_supported;
1487 * NIC global maximum for unique UDP tunnel ports shared by all
1490 uint32_t enc_tunnel_config_udp_entries_max;
1491 /* External port identifier */
1492 uint8_t enc_external_port;
1493 uint32_t enc_mcdi_max_payload_length;
1494 /* VPD may be per-PF or global */
1495 boolean_t enc_vpd_is_global;
1496 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1497 uint32_t enc_required_pcie_bandwidth_mbps;
1498 uint32_t enc_max_pcie_link_gen;
1499 /* Firmware verifies integrity of NVRAM updates */
1500 boolean_t enc_nvram_update_verify_result_supported;
1501 /* Firmware supports polled NVRAM updates on select partitions */
1502 boolean_t enc_nvram_update_poll_verify_result_supported;
1503 /* Firmware accepts updates via the BUNDLE partition */
1504 boolean_t enc_nvram_bundle_update_supported;
1505 /* Firmware support for extended MAC_STATS buffer */
1506 uint32_t enc_mac_stats_nstats;
1507 boolean_t enc_fec_counters;
1508 boolean_t enc_hlb_counters;
1509 /* Firmware support for "FLAG" and "MARK" filter actions */
1510 boolean_t enc_filter_action_flag_supported;
1511 boolean_t enc_filter_action_mark_supported;
1512 uint32_t enc_filter_action_mark_max;
1513 /* Port assigned to this PCI function */
1514 uint32_t enc_assigned_port;
1517 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1518 ((configp)->evc_function == 0xffff)
1520 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1521 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1523 #define EFX_PCI_FUNCTION(_encp) \
1524 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1526 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1529 extern const efx_nic_cfg_t *
1531 __in const efx_nic_t *enp);
1533 /* RxDPCPU firmware id values by which FW variant can be identified */
1534 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1535 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1536 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1537 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1538 #define EFX_RXDP_DPDK_FW_ID 0x6
1540 typedef struct efx_nic_fw_info_s {
1541 /* Basic FW version information */
1542 uint16_t enfi_mc_fw_version[4];
1544 * If datapath capabilities can be detected,
1545 * additional FW information is to be shown
1547 boolean_t enfi_dpcpu_fw_ids_valid;
1548 /* Rx and Tx datapath CPU FW IDs */
1549 uint16_t enfi_rx_dpcpu_fw_id;
1550 uint16_t enfi_tx_dpcpu_fw_id;
1551 } efx_nic_fw_info_t;
1554 extern __checkReturn efx_rc_t
1555 efx_nic_get_fw_version(
1556 __in efx_nic_t *enp,
1557 __out efx_nic_fw_info_t *enfip);
1559 /* Driver resource limits (minimum required/maximum usable). */
1560 typedef struct efx_drv_limits_s {
1561 uint32_t edl_min_evq_count;
1562 uint32_t edl_max_evq_count;
1564 uint32_t edl_min_rxq_count;
1565 uint32_t edl_max_rxq_count;
1567 uint32_t edl_min_txq_count;
1568 uint32_t edl_max_txq_count;
1570 /* PIO blocks (sub-allocated from piobuf) */
1571 uint32_t edl_min_pio_alloc_size;
1572 uint32_t edl_max_pio_alloc_count;
1576 extern __checkReturn efx_rc_t
1577 efx_nic_set_drv_limits(
1578 __inout efx_nic_t *enp,
1579 __in efx_drv_limits_t *edlp);
1582 * Register the OS driver version string for management agents
1583 * (e.g. via NC-SI). The content length is provided (i.e. no
1584 * NUL terminator). Use length 0 to indicate no version string
1585 * should be advertised. It is valid to set the version string
1586 * only before efx_nic_probe() is called.
1589 extern __checkReturn efx_rc_t
1590 efx_nic_set_drv_version(
1591 __inout efx_nic_t *enp,
1592 __in_ecount(length) char const *verp,
1593 __in size_t length);
1595 typedef enum efx_nic_region_e {
1596 EFX_REGION_VI, /* Memory BAR UC mapping */
1597 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1601 extern __checkReturn efx_rc_t
1602 efx_nic_get_bar_region(
1603 __in efx_nic_t *enp,
1604 __in efx_nic_region_t region,
1605 __out uint32_t *offsetp,
1606 __out size_t *sizep);
1609 extern __checkReturn efx_rc_t
1610 efx_nic_get_vi_pool(
1611 __in efx_nic_t *enp,
1612 __out uint32_t *evq_countp,
1613 __out uint32_t *rxq_countp,
1614 __out uint32_t *txq_countp);
1619 typedef enum efx_vpd_tag_e {
1626 typedef uint16_t efx_vpd_keyword_t;
1628 typedef struct efx_vpd_value_s {
1629 efx_vpd_tag_t evv_tag;
1630 efx_vpd_keyword_t evv_keyword;
1632 uint8_t evv_value[0x100];
1636 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1639 extern __checkReturn efx_rc_t
1641 __in efx_nic_t *enp);
1644 extern __checkReturn efx_rc_t
1646 __in efx_nic_t *enp,
1647 __out size_t *sizep);
1650 extern __checkReturn efx_rc_t
1652 __in efx_nic_t *enp,
1653 __out_bcount(size) caddr_t data,
1657 extern __checkReturn efx_rc_t
1659 __in efx_nic_t *enp,
1660 __in_bcount(size) caddr_t data,
1664 extern __checkReturn efx_rc_t
1666 __in efx_nic_t *enp,
1667 __in_bcount(size) caddr_t data,
1671 extern __checkReturn efx_rc_t
1673 __in efx_nic_t *enp,
1674 __in_bcount(size) caddr_t data,
1676 __inout efx_vpd_value_t *evvp);
1679 extern __checkReturn efx_rc_t
1681 __in efx_nic_t *enp,
1682 __inout_bcount(size) caddr_t data,
1684 __in efx_vpd_value_t *evvp);
1687 extern __checkReturn efx_rc_t
1689 __in efx_nic_t *enp,
1690 __inout_bcount(size) caddr_t data,
1692 __out efx_vpd_value_t *evvp,
1693 __inout unsigned int *contp);
1696 extern __checkReturn efx_rc_t
1698 __in efx_nic_t *enp,
1699 __in_bcount(size) caddr_t data,
1705 __in efx_nic_t *enp);
1707 #endif /* EFSYS_OPT_VPD */
1713 typedef enum efx_nvram_type_e {
1714 EFX_NVRAM_INVALID = 0,
1716 EFX_NVRAM_BOOTROM_CFG,
1717 EFX_NVRAM_MC_FIRMWARE,
1718 EFX_NVRAM_MC_GOLDEN,
1724 EFX_NVRAM_FPGA_BACKUP,
1725 EFX_NVRAM_DYNAMIC_CFG,
1728 EFX_NVRAM_MUM_FIRMWARE,
1729 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1730 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1732 EFX_NVRAM_BUNDLE_METADATA,
1736 typedef struct efx_nvram_info_s {
1738 uint32_t eni_partn_size;
1739 uint32_t eni_address;
1740 uint32_t eni_erase_size;
1741 uint32_t eni_write_size;
1744 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1747 extern __checkReturn efx_rc_t
1749 __in efx_nic_t *enp);
1754 extern __checkReturn efx_rc_t
1756 __in efx_nic_t *enp);
1758 #endif /* EFSYS_OPT_DIAG */
1761 extern __checkReturn efx_rc_t
1763 __in efx_nic_t *enp,
1764 __in efx_nvram_type_t type,
1765 __out size_t *sizep);
1768 extern __checkReturn efx_rc_t
1770 __in efx_nic_t *enp,
1771 __in efx_nvram_type_t type,
1772 __out efx_nvram_info_t *enip);
1775 extern __checkReturn efx_rc_t
1777 __in efx_nic_t *enp,
1778 __in efx_nvram_type_t type,
1779 __out_opt size_t *pref_chunkp);
1782 extern __checkReturn efx_rc_t
1783 efx_nvram_rw_finish(
1784 __in efx_nic_t *enp,
1785 __in efx_nvram_type_t type,
1786 __out_opt uint32_t *verify_resultp);
1789 extern __checkReturn efx_rc_t
1790 efx_nvram_get_version(
1791 __in efx_nic_t *enp,
1792 __in efx_nvram_type_t type,
1793 __out uint32_t *subtypep,
1794 __out_ecount(4) uint16_t version[4]);
1797 extern __checkReturn efx_rc_t
1798 efx_nvram_read_chunk(
1799 __in efx_nic_t *enp,
1800 __in efx_nvram_type_t type,
1801 __in unsigned int offset,
1802 __out_bcount(size) caddr_t data,
1806 extern __checkReturn efx_rc_t
1807 efx_nvram_read_backup(
1808 __in efx_nic_t *enp,
1809 __in efx_nvram_type_t type,
1810 __in unsigned int offset,
1811 __out_bcount(size) caddr_t data,
1815 extern __checkReturn efx_rc_t
1816 efx_nvram_set_version(
1817 __in efx_nic_t *enp,
1818 __in efx_nvram_type_t type,
1819 __in_ecount(4) uint16_t version[4]);
1822 extern __checkReturn efx_rc_t
1824 __in efx_nic_t *enp,
1825 __in efx_nvram_type_t type,
1826 __in_bcount(partn_size) caddr_t partn_data,
1827 __in size_t partn_size);
1830 extern __checkReturn efx_rc_t
1832 __in efx_nic_t *enp,
1833 __in efx_nvram_type_t type);
1836 extern __checkReturn efx_rc_t
1837 efx_nvram_write_chunk(
1838 __in efx_nic_t *enp,
1839 __in efx_nvram_type_t type,
1840 __in unsigned int offset,
1841 __in_bcount(size) caddr_t data,
1847 __in efx_nic_t *enp);
1849 #endif /* EFSYS_OPT_NVRAM */
1851 #if EFSYS_OPT_BOOTCFG
1853 /* Report size and offset of bootcfg sector in NVRAM partition. */
1855 extern __checkReturn efx_rc_t
1856 efx_bootcfg_sector_info(
1857 __in efx_nic_t *enp,
1859 __out_opt uint32_t *sector_countp,
1860 __out size_t *offsetp,
1861 __out size_t *max_sizep);
1864 * Copy bootcfg sector data to a target buffer which may differ in size.
1865 * Optionally corrects format errors in source buffer.
1869 efx_bootcfg_copy_sector(
1870 __in efx_nic_t *enp,
1871 __inout_bcount(sector_length)
1873 __in size_t sector_length,
1874 __out_bcount(data_size) uint8_t *data,
1875 __in size_t data_size,
1876 __in boolean_t handle_format_errors);
1881 __in efx_nic_t *enp,
1882 __out_bcount(size) uint8_t *data,
1888 __in efx_nic_t *enp,
1889 __in_bcount(size) uint8_t *data,
1894 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1895 * (see https://tools.ietf.org/html/rfc1533)
1897 * Summarising the format: the buffer is a sequence of options. All options
1898 * begin with a tag octet, which uniquely identifies the option. Fixed-
1899 * length options without data consist of only a tag octet. Only options PAD
1900 * (0) and END (255) are fixed length. All other options are variable-length
1901 * with a length octet following the tag octet. The value of the length
1902 * octet does not include the two octets specifying the tag and length. The
1903 * length octet is followed by "length" octets of data.
1905 * Option data may be a sequence of sub-options in the same format. The data
1906 * content of the encapsulating option is one or more encapsulated sub-options,
1907 * with no terminating END tag is required.
1909 * To be valid, the top-level sequence of options should be terminated by an
1910 * END tag. The buffer should be padded with the PAD byte.
1912 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1913 * checksum octet. The full buffer (including after the END tag) contributes
1914 * to the checksum, hence the need to fill the buffer to the end with PAD.
1917 #define EFX_DHCP_END ((uint8_t)0xff)
1918 #define EFX_DHCP_PAD ((uint8_t)0)
1920 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1921 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1924 extern __checkReturn uint8_t
1926 __in_bcount(size) uint8_t const *data,
1930 extern __checkReturn efx_rc_t
1932 __in_bcount(size) uint8_t const *data,
1934 __out_opt size_t *usedp);
1937 extern __checkReturn efx_rc_t
1939 __in_bcount(buffer_length) uint8_t *bufferp,
1940 __in size_t buffer_length,
1942 __deref_out uint8_t **valuepp,
1943 __out size_t *value_lengthp);
1946 extern __checkReturn efx_rc_t
1948 __in_bcount(buffer_length) uint8_t *bufferp,
1949 __in size_t buffer_length,
1950 __deref_out uint8_t **endpp);
1954 extern __checkReturn efx_rc_t
1955 efx_dhcp_delete_tag(
1956 __inout_bcount(buffer_length) uint8_t *bufferp,
1957 __in size_t buffer_length,
1961 extern __checkReturn efx_rc_t
1963 __inout_bcount(buffer_length) uint8_t *bufferp,
1964 __in size_t buffer_length,
1966 __in_bcount_opt(value_length) uint8_t *valuep,
1967 __in size_t value_length);
1970 extern __checkReturn efx_rc_t
1971 efx_dhcp_update_tag(
1972 __inout_bcount(buffer_length) uint8_t *bufferp,
1973 __in size_t buffer_length,
1975 __in uint8_t *value_locationp,
1976 __in_bcount_opt(value_length) uint8_t *valuep,
1977 __in size_t value_length);
1980 #endif /* EFSYS_OPT_BOOTCFG */
1982 #if EFSYS_OPT_IMAGE_LAYOUT
1984 #include "ef10_signed_image_layout.h"
1987 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1990 * The image header format is extensible. However, older drivers require an
1991 * exact match of image header version and header length when validating and
1992 * writing firmware images.
1994 * To avoid breaking backward compatibility, we use the upper bits of the
1995 * controller version fields to contain an extra version number used for
1996 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1997 * version). See bug39254 and SF-102785-PS for details.
1999 typedef struct efx_image_header_s {
2001 uint32_t eih_version;
2003 uint32_t eih_subtype;
2004 uint32_t eih_code_size;
2007 uint32_t eih_controller_version_min;
2009 uint16_t eih_controller_version_min_short;
2010 uint8_t eih_extra_version_a;
2011 uint8_t eih_extra_version_b;
2015 uint32_t eih_controller_version_max;
2017 uint16_t eih_controller_version_max_short;
2018 uint8_t eih_extra_version_c;
2019 uint8_t eih_extra_version_d;
2022 uint16_t eih_code_version_a;
2023 uint16_t eih_code_version_b;
2024 uint16_t eih_code_version_c;
2025 uint16_t eih_code_version_d;
2026 } efx_image_header_t;
2028 #define EFX_IMAGE_HEADER_SIZE (40)
2029 #define EFX_IMAGE_HEADER_VERSION (4)
2030 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2033 typedef struct efx_image_trailer_s {
2035 } efx_image_trailer_t;
2037 #define EFX_IMAGE_TRAILER_SIZE (4)
2039 typedef enum efx_image_format_e {
2040 EFX_IMAGE_FORMAT_NO_IMAGE,
2041 EFX_IMAGE_FORMAT_INVALID,
2042 EFX_IMAGE_FORMAT_UNSIGNED,
2043 EFX_IMAGE_FORMAT_SIGNED,
2044 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2045 } efx_image_format_t;
2047 typedef struct efx_image_info_s {
2048 efx_image_format_t eii_format;
2049 uint8_t * eii_imagep;
2050 size_t eii_image_size;
2051 efx_image_header_t * eii_headerp;
2055 extern __checkReturn efx_rc_t
2056 efx_check_reflash_image(
2058 __in uint32_t buffer_size,
2059 __out efx_image_info_t *infop);
2062 extern __checkReturn efx_rc_t
2063 efx_build_signed_image_write_buffer(
2064 __out_bcount(buffer_size)
2066 __in uint32_t buffer_size,
2067 __in efx_image_info_t *infop,
2068 __out efx_image_header_t **headerpp);
2070 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2074 typedef enum efx_pattern_type_t {
2075 EFX_PATTERN_BYTE_INCREMENT = 0,
2076 EFX_PATTERN_ALL_THE_SAME,
2077 EFX_PATTERN_BIT_ALTERNATE,
2078 EFX_PATTERN_BYTE_ALTERNATE,
2079 EFX_PATTERN_BYTE_CHANGING,
2080 EFX_PATTERN_BIT_SWEEP,
2082 } efx_pattern_type_t;
2085 (*efx_sram_pattern_fn_t)(
2087 __in boolean_t negate,
2088 __out efx_qword_t *eqp);
2091 extern __checkReturn efx_rc_t
2093 __in efx_nic_t *enp,
2094 __in efx_pattern_type_t type);
2096 #endif /* EFSYS_OPT_DIAG */
2099 extern __checkReturn efx_rc_t
2100 efx_sram_buf_tbl_set(
2101 __in efx_nic_t *enp,
2103 __in efsys_mem_t *esmp,
2108 efx_sram_buf_tbl_clear(
2109 __in efx_nic_t *enp,
2113 #define EFX_BUF_TBL_SIZE 0x20000
2115 #define EFX_BUF_SIZE 4096
2119 typedef struct efx_evq_s efx_evq_t;
2121 #if EFSYS_OPT_QSTATS
2123 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2124 typedef enum efx_ev_qstat_e {
2130 EV_RX_PAUSE_FRM_ERR,
2131 EV_RX_BUF_OWNER_ID_ERR,
2132 EV_RX_IPV4_HDR_CHKSUM_ERR,
2133 EV_RX_TCP_UDP_CHKSUM_ERR,
2137 EV_RX_MCAST_HASH_MATCH,
2154 EV_DRIVER_SRM_UPD_DONE,
2155 EV_DRIVER_TX_DESCQ_FLS_DONE,
2156 EV_DRIVER_RX_DESCQ_FLS_DONE,
2157 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2158 EV_DRIVER_RX_DSC_ERROR,
2159 EV_DRIVER_TX_DSC_ERROR,
2162 EV_RX_PARSE_INCOMPLETE,
2166 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2168 #endif /* EFSYS_OPT_QSTATS */
2171 extern __checkReturn efx_rc_t
2173 __in efx_nic_t *enp);
2178 __in efx_nic_t *enp);
2181 extern __checkReturn size_t
2183 __in const efx_nic_t *enp,
2184 __in unsigned int ndescs);
2187 extern __checkReturn unsigned int
2189 __in const efx_nic_t *enp,
2190 __in unsigned int ndescs);
2192 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2193 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2194 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2195 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2197 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2198 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2199 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2202 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2203 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2206 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2207 * which is the case when an event queue is set to THROUGHPUT mode.
2209 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2212 extern __checkReturn efx_rc_t
2214 __in efx_nic_t *enp,
2215 __in unsigned int index,
2216 __in efsys_mem_t *esmp,
2220 __in uint32_t flags,
2221 __deref_out efx_evq_t **eepp);
2226 __in efx_evq_t *eep,
2227 __in uint16_t data);
2229 typedef __checkReturn boolean_t
2230 (*efx_initialized_ev_t)(
2231 __in_opt void *arg);
2233 #define EFX_PKT_UNICAST 0x0004
2234 #define EFX_PKT_START 0x0008
2236 #define EFX_PKT_VLAN_TAGGED 0x0010
2237 #define EFX_CKSUM_TCPUDP 0x0020
2238 #define EFX_CKSUM_IPV4 0x0040
2239 #define EFX_PKT_CONT 0x0080
2241 #define EFX_CHECK_VLAN 0x0100
2242 #define EFX_PKT_TCP 0x0200
2243 #define EFX_PKT_UDP 0x0400
2244 #define EFX_PKT_IPV4 0x0800
2246 #define EFX_PKT_IPV6 0x1000
2247 #define EFX_PKT_PREFIX_LEN 0x2000
2248 #define EFX_ADDR_MISMATCH 0x4000
2249 #define EFX_DISCARD 0x8000
2252 * The following flags are used only for packed stream
2253 * mode. The values for the flags are reused to fit into 16 bit,
2254 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2255 * packed stream mode
2257 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2258 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2261 #define EFX_EV_RX_NLABELS 32
2262 #define EFX_EV_TX_NLABELS 32
2264 typedef __checkReturn boolean_t
2267 __in uint32_t label,
2270 __in uint16_t flags);
2272 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2275 * Packed stream mode is documented in SF-112241-TC.
2276 * The general idea is that, instead of putting each incoming
2277 * packet into a separate buffer which is specified in a RX
2278 * descriptor, a large buffer is provided to the hardware and
2279 * packets are put there in a continuous stream.
2280 * The main advantage of such an approach is that RX queue refilling
2281 * happens much less frequently.
2283 * Equal stride packed stream mode is documented in SF-119419-TC.
2284 * The general idea is to utilize advantages of the packed stream,
2285 * but avoid indirection in packets representation.
2286 * The main advantage of such an approach is that RX queue refilling
2287 * happens much less frequently and packets buffers are independent
2288 * from upper layers point of view.
2291 typedef __checkReturn boolean_t
2294 __in uint32_t label,
2296 __in uint32_t pkt_count,
2297 __in uint16_t flags);
2301 typedef __checkReturn boolean_t
2304 __in uint32_t label,
2307 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2308 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2309 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2310 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2311 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2312 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2313 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2314 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2315 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2317 typedef __checkReturn boolean_t
2318 (*efx_exception_ev_t)(
2320 __in uint32_t label,
2321 __in uint32_t data);
2323 typedef __checkReturn boolean_t
2324 (*efx_rxq_flush_done_ev_t)(
2326 __in uint32_t rxq_index);
2328 typedef __checkReturn boolean_t
2329 (*efx_rxq_flush_failed_ev_t)(
2331 __in uint32_t rxq_index);
2333 typedef __checkReturn boolean_t
2334 (*efx_txq_flush_done_ev_t)(
2336 __in uint32_t txq_index);
2338 typedef __checkReturn boolean_t
2339 (*efx_software_ev_t)(
2341 __in uint16_t magic);
2343 typedef __checkReturn boolean_t
2346 __in uint32_t code);
2348 #define EFX_SRAM_CLEAR 0
2349 #define EFX_SRAM_UPDATE 1
2350 #define EFX_SRAM_ILLEGAL_CLEAR 2
2352 typedef __checkReturn boolean_t
2353 (*efx_wake_up_ev_t)(
2355 __in uint32_t label);
2357 typedef __checkReturn boolean_t
2360 __in uint32_t label);
2362 typedef __checkReturn boolean_t
2363 (*efx_link_change_ev_t)(
2365 __in efx_link_mode_t link_mode);
2367 #if EFSYS_OPT_MON_STATS
2369 typedef __checkReturn boolean_t
2370 (*efx_monitor_ev_t)(
2372 __in efx_mon_stat_t id,
2373 __in efx_mon_stat_value_t value);
2375 #endif /* EFSYS_OPT_MON_STATS */
2377 #if EFSYS_OPT_MAC_STATS
2379 typedef __checkReturn boolean_t
2380 (*efx_mac_stats_ev_t)(
2382 __in uint32_t generation);
2384 #endif /* EFSYS_OPT_MAC_STATS */
2386 typedef struct efx_ev_callbacks_s {
2387 efx_initialized_ev_t eec_initialized;
2389 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2390 efx_rx_ps_ev_t eec_rx_ps;
2393 efx_exception_ev_t eec_exception;
2394 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2395 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2396 efx_txq_flush_done_ev_t eec_txq_flush_done;
2397 efx_software_ev_t eec_software;
2398 efx_sram_ev_t eec_sram;
2399 efx_wake_up_ev_t eec_wake_up;
2400 efx_timer_ev_t eec_timer;
2401 efx_link_change_ev_t eec_link_change;
2402 #if EFSYS_OPT_MON_STATS
2403 efx_monitor_ev_t eec_monitor;
2404 #endif /* EFSYS_OPT_MON_STATS */
2405 #if EFSYS_OPT_MAC_STATS
2406 efx_mac_stats_ev_t eec_mac_stats;
2407 #endif /* EFSYS_OPT_MAC_STATS */
2408 } efx_ev_callbacks_t;
2411 extern __checkReturn boolean_t
2413 __in efx_evq_t *eep,
2414 __in unsigned int count);
2416 #if EFSYS_OPT_EV_PREFETCH
2421 __in efx_evq_t *eep,
2422 __in unsigned int count);
2424 #endif /* EFSYS_OPT_EV_PREFETCH */
2429 __in efx_evq_t *eep,
2430 __inout unsigned int *countp,
2431 __in const efx_ev_callbacks_t *eecp,
2432 __in_opt void *arg);
2435 extern __checkReturn efx_rc_t
2436 efx_ev_usecs_to_ticks(
2437 __in efx_nic_t *enp,
2438 __in unsigned int usecs,
2439 __out unsigned int *ticksp);
2442 extern __checkReturn efx_rc_t
2444 __in efx_evq_t *eep,
2445 __in unsigned int us);
2448 extern __checkReturn efx_rc_t
2450 __in efx_evq_t *eep,
2451 __in unsigned int count);
2453 #if EFSYS_OPT_QSTATS
2460 __in efx_nic_t *enp,
2461 __in unsigned int id);
2463 #endif /* EFSYS_OPT_NAMES */
2467 efx_ev_qstats_update(
2468 __in efx_evq_t *eep,
2469 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2471 #endif /* EFSYS_OPT_QSTATS */
2476 __in efx_evq_t *eep);
2481 extern __checkReturn efx_rc_t
2483 __inout efx_nic_t *enp);
2488 __in efx_nic_t *enp);
2490 #if EFSYS_OPT_RX_SCATTER
2492 extern __checkReturn efx_rc_t
2493 efx_rx_scatter_enable(
2494 __in efx_nic_t *enp,
2495 __in unsigned int buf_size);
2496 #endif /* EFSYS_OPT_RX_SCATTER */
2498 /* Handle to represent use of the default RSS context. */
2499 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2501 #if EFSYS_OPT_RX_SCALE
2503 typedef enum efx_rx_hash_alg_e {
2504 EFX_RX_HASHALG_LFSR = 0,
2505 EFX_RX_HASHALG_TOEPLITZ,
2506 EFX_RX_HASHALG_PACKED_STREAM,
2508 } efx_rx_hash_alg_t;
2511 * Legacy hash type flags.
2513 * They represent standard tuples for distinct traffic classes.
2515 #define EFX_RX_HASH_IPV4 (1U << 0)
2516 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2517 #define EFX_RX_HASH_IPV6 (1U << 2)
2518 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2520 #define EFX_RX_HASH_LEGACY_MASK \
2521 (EFX_RX_HASH_IPV4 | \
2522 EFX_RX_HASH_TCPIPV4 | \
2523 EFX_RX_HASH_IPV6 | \
2524 EFX_RX_HASH_TCPIPV6)
2527 * The type of the argument used by efx_rx_scale_mode_set() to
2528 * provide a means for the client drivers to configure hashing.
2530 * A properly constructed value can either be:
2531 * - a combination of legacy flags
2532 * - a combination of EFX_RX_HASH() flags
2534 typedef uint32_t efx_rx_hash_type_t;
2536 typedef enum efx_rx_hash_support_e {
2537 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2538 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2539 } efx_rx_hash_support_t;
2541 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2542 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2543 #define EFX_MAXRSS 64 /* RX indirection entry range */
2544 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2546 typedef enum efx_rx_scale_context_type_e {
2547 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2548 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2549 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2550 } efx_rx_scale_context_type_t;
2553 * Traffic classes eligible for hash computation.
2555 * Select packet headers used in computing the receive hash.
2556 * This uses the same encoding as the RSS_MODES field of
2557 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2559 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2560 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2561 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2562 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2563 #define EFX_RX_CLASS_IPV4_LBN 16
2564 #define EFX_RX_CLASS_IPV4_WIDTH 4
2565 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2566 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2567 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2568 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2569 #define EFX_RX_CLASS_IPV6_LBN 28
2570 #define EFX_RX_CLASS_IPV6_WIDTH 4
2572 #define EFX_RX_NCLASSES 6
2575 * Ancillary flags used to construct generic hash tuples.
2576 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2578 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2579 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2580 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2581 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2584 * Generic hash tuples.
2586 * They express combinations of packet fields
2587 * which can contribute to the hash value for
2588 * a particular traffic class.
2590 #define EFX_RX_CLASS_HASH_DISABLE 0
2592 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2593 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2595 #define EFX_RX_CLASS_HASH_2TUPLE \
2596 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2597 EFX_RX_CLASS_HASH_DST_ADDR)
2599 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2600 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2601 EFX_RX_CLASS_HASH_SRC_PORT)
2603 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2604 (EFX_RX_CLASS_HASH_DST_ADDR | \
2605 EFX_RX_CLASS_HASH_DST_PORT)
2607 #define EFX_RX_CLASS_HASH_4TUPLE \
2608 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2609 EFX_RX_CLASS_HASH_DST_ADDR | \
2610 EFX_RX_CLASS_HASH_SRC_PORT | \
2611 EFX_RX_CLASS_HASH_DST_PORT)
2613 #define EFX_RX_CLASS_HASH_NTUPLES 7
2616 * Hash flag constructor.
2618 * Resulting flags encode hash tuples for specific traffic classes.
2619 * The client drivers are encouraged to use these flags to form
2620 * a hash type value.
2622 #define EFX_RX_HASH(_class, _tuple) \
2623 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2624 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2627 * The maximum number of EFX_RX_HASH() flags.
2629 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2632 extern __checkReturn efx_rc_t
2633 efx_rx_scale_hash_flags_get(
2634 __in efx_nic_t *enp,
2635 __in efx_rx_hash_alg_t hash_alg,
2636 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2637 __in unsigned int max_nflags,
2638 __out unsigned int *nflagsp);
2641 extern __checkReturn efx_rc_t
2642 efx_rx_hash_default_support_get(
2643 __in efx_nic_t *enp,
2644 __out efx_rx_hash_support_t *supportp);
2648 extern __checkReturn efx_rc_t
2649 efx_rx_scale_default_support_get(
2650 __in efx_nic_t *enp,
2651 __out efx_rx_scale_context_type_t *typep);
2654 extern __checkReturn efx_rc_t
2655 efx_rx_scale_context_alloc(
2656 __in efx_nic_t *enp,
2657 __in efx_rx_scale_context_type_t type,
2658 __in uint32_t num_queues,
2659 __out uint32_t *rss_contextp);
2662 extern __checkReturn efx_rc_t
2663 efx_rx_scale_context_free(
2664 __in efx_nic_t *enp,
2665 __in uint32_t rss_context);
2668 extern __checkReturn efx_rc_t
2669 efx_rx_scale_mode_set(
2670 __in efx_nic_t *enp,
2671 __in uint32_t rss_context,
2672 __in efx_rx_hash_alg_t alg,
2673 __in efx_rx_hash_type_t type,
2674 __in boolean_t insert);
2677 extern __checkReturn efx_rc_t
2678 efx_rx_scale_tbl_set(
2679 __in efx_nic_t *enp,
2680 __in uint32_t rss_context,
2681 __in_ecount(n) unsigned int *table,
2685 extern __checkReturn efx_rc_t
2686 efx_rx_scale_key_set(
2687 __in efx_nic_t *enp,
2688 __in uint32_t rss_context,
2689 __in_ecount(n) uint8_t *key,
2693 extern __checkReturn uint32_t
2694 efx_pseudo_hdr_hash_get(
2695 __in efx_rxq_t *erp,
2696 __in efx_rx_hash_alg_t func,
2697 __in uint8_t *buffer);
2699 #endif /* EFSYS_OPT_RX_SCALE */
2702 extern __checkReturn efx_rc_t
2703 efx_pseudo_hdr_pkt_length_get(
2704 __in efx_rxq_t *erp,
2705 __in uint8_t *buffer,
2706 __out uint16_t *pkt_lengthp);
2709 extern __checkReturn size_t
2711 __in const efx_nic_t *enp,
2712 __in unsigned int ndescs);
2715 extern __checkReturn unsigned int
2717 __in const efx_nic_t *enp,
2718 __in unsigned int ndescs);
2720 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2722 typedef enum efx_rxq_type_e {
2723 EFX_RXQ_TYPE_DEFAULT,
2724 EFX_RXQ_TYPE_PACKED_STREAM,
2725 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2730 * Dummy flag to be used instead of 0 to make it clear that the argument
2731 * is receive queue flags.
2733 #define EFX_RXQ_FLAG_NONE 0x0
2734 #define EFX_RXQ_FLAG_SCATTER 0x1
2736 * If tunnels are supported and Rx event can provide information about
2737 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2738 * full-feature firmware variant running), outer classes are requested by
2739 * default. However, if the driver supports tunnels, the flag allows to
2740 * request inner classes which are required to be able to interpret inner
2741 * Rx checksum offload results.
2743 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2746 extern __checkReturn efx_rc_t
2748 __in efx_nic_t *enp,
2749 __in unsigned int index,
2750 __in unsigned int label,
2751 __in efx_rxq_type_t type,
2752 __in size_t buf_size,
2753 __in efsys_mem_t *esmp,
2756 __in unsigned int flags,
2757 __in efx_evq_t *eep,
2758 __deref_out efx_rxq_t **erpp);
2760 #if EFSYS_OPT_RX_PACKED_STREAM
2762 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2763 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2764 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2765 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2766 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2769 extern __checkReturn efx_rc_t
2770 efx_rx_qcreate_packed_stream(
2771 __in efx_nic_t *enp,
2772 __in unsigned int index,
2773 __in unsigned int label,
2774 __in uint32_t ps_buf_size,
2775 __in efsys_mem_t *esmp,
2777 __in efx_evq_t *eep,
2778 __deref_out efx_rxq_t **erpp);
2782 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2784 /* Maximum head-of-line block timeout in nanoseconds */
2785 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2788 extern __checkReturn efx_rc_t
2789 efx_rx_qcreate_es_super_buffer(
2790 __in efx_nic_t *enp,
2791 __in unsigned int index,
2792 __in unsigned int label,
2793 __in uint32_t n_bufs_per_desc,
2794 __in uint32_t max_dma_len,
2795 __in uint32_t buf_stride,
2796 __in uint32_t hol_block_timeout,
2797 __in efsys_mem_t *esmp,
2799 __in unsigned int flags,
2800 __in efx_evq_t *eep,
2801 __deref_out efx_rxq_t **erpp);
2805 typedef struct efx_buffer_s {
2806 efsys_dma_addr_t eb_addr;
2811 typedef struct efx_desc_s {
2818 __in efx_rxq_t *erp,
2819 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2821 __in unsigned int ndescs,
2822 __in unsigned int completed,
2823 __in unsigned int added);
2828 __in efx_rxq_t *erp,
2829 __in unsigned int added,
2830 __inout unsigned int *pushedp);
2832 #if EFSYS_OPT_RX_PACKED_STREAM
2836 efx_rx_qpush_ps_credits(
2837 __in efx_rxq_t *erp);
2840 extern __checkReturn uint8_t *
2841 efx_rx_qps_packet_info(
2842 __in efx_rxq_t *erp,
2843 __in uint8_t *buffer,
2844 __in uint32_t buffer_length,
2845 __in uint32_t current_offset,
2846 __out uint16_t *lengthp,
2847 __out uint32_t *next_offsetp,
2848 __out uint32_t *timestamp);
2852 extern __checkReturn efx_rc_t
2854 __in efx_rxq_t *erp);
2859 __in efx_rxq_t *erp);
2864 __in efx_rxq_t *erp);
2868 typedef struct efx_txq_s efx_txq_t;
2870 #if EFSYS_OPT_QSTATS
2872 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2873 typedef enum efx_tx_qstat_e {
2879 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2881 #endif /* EFSYS_OPT_QSTATS */
2884 extern __checkReturn efx_rc_t
2886 __in efx_nic_t *enp);
2891 __in efx_nic_t *enp);
2894 extern __checkReturn size_t
2896 __in const efx_nic_t *enp,
2897 __in unsigned int ndescs);
2900 extern __checkReturn unsigned int
2902 __in const efx_nic_t *enp,
2903 __in unsigned int ndescs);
2905 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2907 #define EFX_TXQ_CKSUM_IPV4 0x0001
2908 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2909 #define EFX_TXQ_FATSOV2 0x0004
2910 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2911 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2914 extern __checkReturn efx_rc_t
2916 __in efx_nic_t *enp,
2917 __in unsigned int index,
2918 __in unsigned int label,
2919 __in efsys_mem_t *esmp,
2922 __in uint16_t flags,
2923 __in efx_evq_t *eep,
2924 __deref_out efx_txq_t **etpp,
2925 __out unsigned int *addedp);
2928 extern __checkReturn efx_rc_t
2930 __in efx_txq_t *etp,
2931 __in_ecount(ndescs) efx_buffer_t *eb,
2932 __in unsigned int ndescs,
2933 __in unsigned int completed,
2934 __inout unsigned int *addedp);
2937 extern __checkReturn efx_rc_t
2939 __in efx_txq_t *etp,
2940 __in unsigned int ns);
2945 __in efx_txq_t *etp,
2946 __in unsigned int added,
2947 __in unsigned int pushed);
2950 extern __checkReturn efx_rc_t
2952 __in efx_txq_t *etp);
2957 __in efx_txq_t *etp);
2960 extern __checkReturn efx_rc_t
2962 __in efx_txq_t *etp);
2966 efx_tx_qpio_disable(
2967 __in efx_txq_t *etp);
2970 extern __checkReturn efx_rc_t
2972 __in efx_txq_t *etp,
2973 __in_ecount(buf_length) uint8_t *buffer,
2974 __in size_t buf_length,
2975 __in size_t pio_buf_offset);
2978 extern __checkReturn efx_rc_t
2980 __in efx_txq_t *etp,
2981 __in size_t pkt_length,
2982 __in unsigned int completed,
2983 __inout unsigned int *addedp);
2986 extern __checkReturn efx_rc_t
2988 __in efx_txq_t *etp,
2989 __in_ecount(n) efx_desc_t *ed,
2990 __in unsigned int n,
2991 __in unsigned int completed,
2992 __inout unsigned int *addedp);
2996 efx_tx_qdesc_dma_create(
2997 __in efx_txq_t *etp,
2998 __in efsys_dma_addr_t addr,
3001 __out efx_desc_t *edp);
3005 efx_tx_qdesc_tso_create(
3006 __in efx_txq_t *etp,
3007 __in uint16_t ipv4_id,
3008 __in uint32_t tcp_seq,
3009 __in uint8_t tcp_flags,
3010 __out efx_desc_t *edp);
3012 /* Number of FATSOv2 option descriptors */
3013 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3015 /* Maximum number of DMA segments per TSO packet (not superframe) */
3016 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3020 efx_tx_qdesc_tso2_create(
3021 __in efx_txq_t *etp,
3022 __in uint16_t ipv4_id,
3023 __in uint16_t outer_ipv4_id,
3024 __in uint32_t tcp_seq,
3025 __in uint16_t tcp_mss,
3026 __out_ecount(count) efx_desc_t *edp,
3031 efx_tx_qdesc_vlantci_create(
3032 __in efx_txq_t *etp,
3034 __out efx_desc_t *edp);
3038 efx_tx_qdesc_checksum_create(
3039 __in efx_txq_t *etp,
3040 __in uint16_t flags,
3041 __out efx_desc_t *edp);
3043 #if EFSYS_OPT_QSTATS
3050 __in efx_nic_t *etp,
3051 __in unsigned int id);
3053 #endif /* EFSYS_OPT_NAMES */
3057 efx_tx_qstats_update(
3058 __in efx_txq_t *etp,
3059 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3061 #endif /* EFSYS_OPT_QSTATS */
3066 __in efx_txq_t *etp);
3071 #if EFSYS_OPT_FILTER
3073 #define EFX_ETHER_TYPE_IPV4 0x0800
3074 #define EFX_ETHER_TYPE_IPV6 0x86DD
3076 #define EFX_IPPROTO_TCP 6
3077 #define EFX_IPPROTO_UDP 17
3078 #define EFX_IPPROTO_GRE 47
3080 /* Use RSS to spread across multiple queues */
3081 #define EFX_FILTER_FLAG_RX_RSS 0x01
3082 /* Enable RX scatter */
3083 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3085 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3086 * May only be set by the filter implementation for each type.
3087 * A removal request will restore the automatic filter in its place.
3089 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3090 /* Filter is for RX */
3091 #define EFX_FILTER_FLAG_RX 0x08
3092 /* Filter is for TX */
3093 #define EFX_FILTER_FLAG_TX 0x10
3094 /* Set match flag on the received packet */
3095 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3096 /* Set match mark on the received packet */
3097 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3099 typedef uint8_t efx_filter_flags_t;
3102 * Flags which specify the fields to match on. The values are the same as in the
3103 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3106 /* Match by remote IP host address */
3107 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3108 /* Match by local IP host address */
3109 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3110 /* Match by remote MAC address */
3111 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3112 /* Match by remote TCP/UDP port */
3113 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3114 /* Match by remote TCP/UDP port */
3115 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3116 /* Match by local TCP/UDP port */
3117 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3118 /* Match by Ether-type */
3119 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3120 /* Match by inner VLAN ID */
3121 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3122 /* Match by outer VLAN ID */
3123 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3124 /* Match by IP transport protocol */
3125 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3126 /* Match by VNI or VSID */
3127 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3128 /* For encapsulated packets, match by inner frame local MAC address */
3129 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3130 /* For encapsulated packets, match all multicast inner frames */
3131 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3132 /* For encapsulated packets, match all unicast inner frames */
3133 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3135 * Match by encap type, this flag does not correspond to
3136 * the MCDI match flags and any unoccupied value may be used
3138 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3139 /* Match otherwise-unmatched multicast and broadcast packets */
3140 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3141 /* Match otherwise-unmatched unicast packets */
3142 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3144 typedef uint32_t efx_filter_match_flags_t;
3146 /* Filter priority from lowest to highest */
3147 typedef enum efx_filter_priority_s {
3148 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3149 * address list or hardware
3150 * requirements. This may only be used
3151 * by the filter implementation for
3153 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3155 } efx_filter_priority_t;
3158 * FIXME: All these fields are assumed to be in little-endian byte order.
3159 * It may be better for some to be big-endian. See bug42804.
3162 typedef struct efx_filter_spec_s {
3163 efx_filter_match_flags_t efs_match_flags;
3164 uint8_t efs_priority;
3165 efx_filter_flags_t efs_flags;
3166 uint16_t efs_dmaq_id;
3167 uint32_t efs_rss_context;
3170 * Saved lower-priority filter. If it is set, it is restored on
3171 * filter delete operation.
3173 struct efx_filter_spec_s *efs_overridden_spec;
3174 /* Fields below here are hashed for software filter lookup */
3175 uint16_t efs_outer_vid;
3176 uint16_t efs_inner_vid;
3177 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3178 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3179 uint16_t efs_ether_type;
3180 uint8_t efs_ip_proto;
3181 efx_tunnel_protocol_t efs_encap_type;
3182 uint16_t efs_loc_port;
3183 uint16_t efs_rem_port;
3184 efx_oword_t efs_rem_host;
3185 efx_oword_t efs_loc_host;
3186 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3187 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3188 } efx_filter_spec_t;
3191 /* Default values for use in filter specifications */
3192 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3193 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3196 extern __checkReturn efx_rc_t
3198 __in efx_nic_t *enp);
3203 __in efx_nic_t *enp);
3206 extern __checkReturn efx_rc_t
3208 __in efx_nic_t *enp,
3209 __inout efx_filter_spec_t *spec);
3212 extern __checkReturn efx_rc_t
3214 __in efx_nic_t *enp,
3215 __inout efx_filter_spec_t *spec);
3218 extern __checkReturn efx_rc_t
3220 __in efx_nic_t *enp);
3223 extern __checkReturn efx_rc_t
3224 efx_filter_supported_filters(
3225 __in efx_nic_t *enp,
3226 __out_ecount(buffer_length) uint32_t *buffer,
3227 __in size_t buffer_length,
3228 __out size_t *list_lengthp);
3232 efx_filter_spec_init_rx(
3233 __out efx_filter_spec_t *spec,
3234 __in efx_filter_priority_t priority,
3235 __in efx_filter_flags_t flags,
3236 __in efx_rxq_t *erp);
3240 efx_filter_spec_init_tx(
3241 __out efx_filter_spec_t *spec,
3242 __in efx_txq_t *etp);
3245 extern __checkReturn efx_rc_t
3246 efx_filter_spec_set_ipv4_local(
3247 __inout efx_filter_spec_t *spec,
3250 __in uint16_t port);
3253 extern __checkReturn efx_rc_t
3254 efx_filter_spec_set_ipv4_full(
3255 __inout efx_filter_spec_t *spec,
3257 __in uint32_t lhost,
3258 __in uint16_t lport,
3259 __in uint32_t rhost,
3260 __in uint16_t rport);
3263 extern __checkReturn efx_rc_t
3264 efx_filter_spec_set_eth_local(
3265 __inout efx_filter_spec_t *spec,
3267 __in const uint8_t *addr);
3271 efx_filter_spec_set_ether_type(
3272 __inout efx_filter_spec_t *spec,
3273 __in uint16_t ether_type);
3276 extern __checkReturn efx_rc_t
3277 efx_filter_spec_set_uc_def(
3278 __inout efx_filter_spec_t *spec);
3281 extern __checkReturn efx_rc_t
3282 efx_filter_spec_set_mc_def(
3283 __inout efx_filter_spec_t *spec);
3285 typedef enum efx_filter_inner_frame_match_e {
3286 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3287 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3288 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3289 } efx_filter_inner_frame_match_t;
3292 extern __checkReturn efx_rc_t
3293 efx_filter_spec_set_encap_type(
3294 __inout efx_filter_spec_t *spec,
3295 __in efx_tunnel_protocol_t encap_type,
3296 __in efx_filter_inner_frame_match_t inner_frame_match);
3299 extern __checkReturn efx_rc_t
3300 efx_filter_spec_set_vxlan(
3301 __inout efx_filter_spec_t *spec,
3302 __in const uint8_t *vni,
3303 __in const uint8_t *inner_addr,
3304 __in const uint8_t *outer_addr);
3307 extern __checkReturn efx_rc_t
3308 efx_filter_spec_set_geneve(
3309 __inout efx_filter_spec_t *spec,
3310 __in const uint8_t *vni,
3311 __in const uint8_t *inner_addr,
3312 __in const uint8_t *outer_addr);
3315 extern __checkReturn efx_rc_t
3316 efx_filter_spec_set_nvgre(
3317 __inout efx_filter_spec_t *spec,
3318 __in const uint8_t *vsid,
3319 __in const uint8_t *inner_addr,
3320 __in const uint8_t *outer_addr);
3322 #if EFSYS_OPT_RX_SCALE
3324 extern __checkReturn efx_rc_t
3325 efx_filter_spec_set_rss_context(
3326 __inout efx_filter_spec_t *spec,
3327 __in uint32_t rss_context);
3329 #endif /* EFSYS_OPT_FILTER */
3334 extern __checkReturn uint32_t
3336 __in_ecount(count) uint32_t const *input,
3338 __in uint32_t init);
3341 extern __checkReturn uint32_t
3343 __in_ecount(length) uint8_t const *input,
3345 __in uint32_t init);
3347 #if EFSYS_OPT_LICENSING
3351 typedef struct efx_key_stats_s {
3353 uint32_t eks_invalid;
3354 uint32_t eks_blacklisted;
3355 uint32_t eks_unverifiable;
3356 uint32_t eks_wrong_node;
3357 uint32_t eks_licensed_apps_lo;
3358 uint32_t eks_licensed_apps_hi;
3359 uint32_t eks_licensed_features_lo;
3360 uint32_t eks_licensed_features_hi;
3364 extern __checkReturn efx_rc_t
3366 __in efx_nic_t *enp);
3371 __in efx_nic_t *enp);
3374 extern __checkReturn boolean_t
3375 efx_lic_check_support(
3376 __in efx_nic_t *enp);
3379 extern __checkReturn efx_rc_t
3380 efx_lic_update_licenses(
3381 __in efx_nic_t *enp);
3384 extern __checkReturn efx_rc_t
3385 efx_lic_get_key_stats(
3386 __in efx_nic_t *enp,
3387 __out efx_key_stats_t *ksp);
3390 extern __checkReturn efx_rc_t
3392 __in efx_nic_t *enp,
3393 __in uint64_t app_id,
3394 __out boolean_t *licensedp);
3397 extern __checkReturn efx_rc_t
3399 __in efx_nic_t *enp,
3400 __in size_t buffer_size,
3401 __out uint32_t *typep,
3402 __out size_t *lengthp,
3403 __out_opt uint8_t *bufferp);
3407 extern __checkReturn efx_rc_t
3409 __in efx_nic_t *enp,
3410 __in_bcount(buffer_size)
3412 __in size_t buffer_size,
3413 __out uint32_t *startp);
3416 extern __checkReturn efx_rc_t
3418 __in efx_nic_t *enp,
3419 __in_bcount(buffer_size)
3421 __in size_t buffer_size,
3422 __in uint32_t offset,
3423 __out uint32_t *endp);
3426 extern __checkReturn __success(return != B_FALSE) boolean_t
3428 __in efx_nic_t *enp,
3429 __in_bcount(buffer_size)
3431 __in size_t buffer_size,
3432 __in uint32_t offset,
3433 __out uint32_t *startp,
3434 __out uint32_t *lengthp);
3437 extern __checkReturn __success(return != B_FALSE) boolean_t
3438 efx_lic_validate_key(
3439 __in efx_nic_t *enp,
3440 __in_bcount(length) caddr_t keyp,
3441 __in uint32_t length);
3444 extern __checkReturn efx_rc_t
3446 __in efx_nic_t *enp,
3447 __in_bcount(buffer_size)
3449 __in size_t buffer_size,
3450 __in uint32_t offset,
3451 __in uint32_t length,
3452 __out_bcount_part(key_max_size, *lengthp)
3454 __in size_t key_max_size,
3455 __out uint32_t *lengthp);
3458 extern __checkReturn efx_rc_t
3460 __in efx_nic_t *enp,
3461 __in_bcount(buffer_size)
3463 __in size_t buffer_size,
3464 __in uint32_t offset,
3465 __in_bcount(length) caddr_t keyp,
3466 __in uint32_t length,
3467 __out uint32_t *lengthp);
3470 extern __checkReturn efx_rc_t
3472 __in efx_nic_t *enp,
3473 __in_bcount(buffer_size)
3475 __in size_t buffer_size,
3476 __in uint32_t offset,
3477 __in uint32_t length,
3479 __out uint32_t *deltap);
3482 extern __checkReturn efx_rc_t
3483 efx_lic_create_partition(
3484 __in efx_nic_t *enp,
3485 __in_bcount(buffer_size)
3487 __in size_t buffer_size);
3489 extern __checkReturn efx_rc_t
3490 efx_lic_finish_partition(
3491 __in efx_nic_t *enp,
3492 __in_bcount(buffer_size)
3494 __in size_t buffer_size);
3496 #endif /* EFSYS_OPT_LICENSING */
3500 #if EFSYS_OPT_TUNNEL
3503 extern __checkReturn efx_rc_t
3505 __in efx_nic_t *enp);
3510 __in efx_nic_t *enp);
3513 * For overlay network encapsulation using UDP, the firmware needs to know
3514 * the configured UDP port for the overlay so it can decode encapsulated
3516 * The UDP port/protocol list is global.
3520 extern __checkReturn efx_rc_t
3521 efx_tunnel_config_udp_add(
3522 __in efx_nic_t *enp,
3523 __in uint16_t port /* host/cpu-endian */,
3524 __in efx_tunnel_protocol_t protocol);
3527 extern __checkReturn efx_rc_t
3528 efx_tunnel_config_udp_remove(
3529 __in efx_nic_t *enp,
3530 __in uint16_t port /* host/cpu-endian */,
3531 __in efx_tunnel_protocol_t protocol);
3535 efx_tunnel_config_clear(
3536 __in efx_nic_t *enp);
3539 * Apply tunnel UDP ports configuration to hardware.
3541 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3545 extern __checkReturn efx_rc_t
3546 efx_tunnel_reconfigure(
3547 __in efx_nic_t *enp);
3549 #endif /* EFSYS_OPT_TUNNEL */
3551 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3554 * Firmware subvariant choice options.
3556 * It may be switched to no Tx checksum if attached drivers are either
3557 * preboot or firmware subvariant aware and no VIS are allocated.
3558 * If may be always switched to default explicitly using set request or
3559 * implicitly if unaware driver is attaching. If switching is done when
3560 * a driver is attached, it gets MC_REBOOT event and should recreate its
3563 * See SF-119419-TC DPDK Firmware Driver Interface and
3564 * SF-109306-TC EF10 for Driver Writers for details.
3566 typedef enum efx_nic_fw_subvariant_e {
3567 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3568 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3569 EFX_NIC_FW_SUBVARIANT_NTYPES
3570 } efx_nic_fw_subvariant_t;
3573 extern __checkReturn efx_rc_t
3574 efx_nic_get_fw_subvariant(
3575 __in efx_nic_t *enp,
3576 __out efx_nic_fw_subvariant_t *subvariantp);
3579 extern __checkReturn efx_rc_t
3580 efx_nic_set_fw_subvariant(
3581 __in efx_nic_t *enp,
3582 __in efx_nic_fw_subvariant_t subvariant);
3584 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3586 typedef enum efx_phy_fec_type_e {
3587 EFX_PHY_FEC_NONE = 0,
3590 } efx_phy_fec_type_t;
3593 extern __checkReturn efx_rc_t
3594 efx_phy_fec_type_get(
3595 __in efx_nic_t *enp,
3596 __out efx_phy_fec_type_t *typep);
3598 typedef struct efx_phy_link_state_s {
3599 uint32_t epls_adv_cap_mask;
3600 uint32_t epls_lp_cap_mask;
3601 uint32_t epls_ld_cap_mask;
3602 unsigned int epls_fcntl;
3603 efx_phy_fec_type_t epls_fec;
3604 efx_link_mode_t epls_link_mode;
3605 } efx_phy_link_state_t;
3608 extern __checkReturn efx_rc_t
3609 efx_phy_link_state_get(
3610 __in efx_nic_t *enp,
3611 __out efx_phy_link_state_t *eplsp);
3616 typedef uint32_t efx_vswitch_id_t;
3617 typedef uint32_t efx_vport_id_t;
3619 typedef enum efx_vswitch_type_e {
3620 EFX_VSWITCH_TYPE_VLAN = 1,
3621 EFX_VSWITCH_TYPE_VEB,
3622 /* VSWITCH_TYPE_VEPA: obsolete */
3623 EFX_VSWITCH_TYPE_MUX = 4,
3624 } efx_vswitch_type_t;
3626 typedef enum efx_vport_type_e {
3627 EFX_VPORT_TYPE_NORMAL = 4,
3628 EFX_VPORT_TYPE_EXPANSION,
3629 EFX_VPORT_TYPE_TEST,
3632 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3633 #define EFX_FILTER_VID_UNSPEC 0xffff
3634 #define EFX_DEFAULT_VSWITCH_ID 1
3636 /* Default VF VLAN ID on creation */
3637 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3638 #define EFX_VPORT_ID_INVALID 0
3640 typedef struct efx_vport_config_s {
3641 /* Either VF index or 0xffff for PF */
3642 uint16_t evc_function;
3643 /* VLAN ID of the associated function */
3645 /* vport id shared with client driver */
3646 efx_vport_id_t evc_vport_id;
3647 /* MAC address of the associated function */
3648 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3650 * vports created with this flag set may only transfer traffic on the
3651 * VLANs permitted by the vport. Also, an attempt to install filter with
3652 * VLAN will be refused unless requesting function has VLAN privilege.
3654 boolean_t evc_vlan_restrict;
3655 /* Whether this function is assigned or not */
3656 boolean_t evc_vport_assigned;
3657 } efx_vport_config_t;
3659 typedef struct efx_vswitch_s efx_vswitch_t;
3662 extern __checkReturn efx_rc_t
3664 __in efx_nic_t *enp);
3669 __in efx_nic_t *enp);
3672 extern __checkReturn efx_rc_t
3673 efx_evb_vswitch_create(
3674 __in efx_nic_t *enp,
3675 __in uint32_t num_vports,
3676 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3677 __deref_out efx_vswitch_t **evpp);
3680 extern __checkReturn efx_rc_t
3681 efx_evb_vswitch_destroy(
3682 __in efx_nic_t *enp,
3683 __in efx_vswitch_t *evp);
3686 extern __checkReturn efx_rc_t
3687 efx_evb_vport_mac_set(
3688 __in efx_nic_t *enp,
3689 __in efx_vswitch_t *evp,
3690 __in efx_vport_id_t vport_id,
3691 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3694 extern __checkReturn efx_rc_t
3695 efx_evb_vport_vlan_set(
3696 __in efx_nic_t *enp,
3697 __in efx_vswitch_t *evp,
3698 __in efx_vport_id_t vport_id,
3702 extern __checkReturn efx_rc_t
3703 efx_evb_vport_reset(
3704 __in efx_nic_t *enp,
3705 __in efx_vswitch_t *evp,
3706 __in efx_vport_id_t vport_id,
3707 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3709 __out boolean_t *is_fn_resetp);
3712 extern __checkReturn efx_rc_t
3713 efx_evb_vport_stats(
3714 __in efx_nic_t *enp,
3715 __in efx_vswitch_t *evp,
3716 __in efx_vport_id_t vport_id,
3717 __out efsys_mem_t *stats_bufferp);
3719 #endif /* EFSYS_OPT_EVB */
3721 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3723 typedef struct efx_proxy_auth_config_s {
3724 efsys_mem_t *request_bufferp;
3725 efsys_mem_t *response_bufferp;
3726 efsys_mem_t *status_bufferp;
3730 uint32_t handled_privileges;
3731 } efx_proxy_auth_config_t;
3733 typedef struct efx_proxy_cmd_params_s {
3736 uint8_t *request_bufferp;
3737 size_t request_size;
3738 uint8_t *response_bufferp;
3739 size_t response_size;
3740 size_t *response_size_actualp;
3741 } efx_proxy_cmd_params_t;
3744 extern __checkReturn efx_rc_t
3745 efx_proxy_auth_init(
3746 __in efx_nic_t *enp);
3750 efx_proxy_auth_fini(
3751 __in efx_nic_t *enp);
3754 extern __checkReturn efx_rc_t
3755 efx_proxy_auth_configure(
3756 __in efx_nic_t *enp,
3757 __in efx_proxy_auth_config_t *configp);
3760 extern __checkReturn efx_rc_t
3761 efx_proxy_auth_destroy(
3762 __in efx_nic_t *enp,
3763 __in uint32_t handled_privileges);
3766 extern __checkReturn efx_rc_t
3767 efx_proxy_auth_complete_request(
3768 __in efx_nic_t *enp,
3769 __in uint32_t fn_index,
3770 __in uint32_t proxy_result,
3771 __in uint32_t handle);
3774 extern __checkReturn efx_rc_t
3775 efx_proxy_auth_exec_cmd(
3776 __in efx_nic_t *enp,
3777 __inout efx_proxy_cmd_params_t *paramsp);
3780 extern __checkReturn efx_rc_t
3781 efx_proxy_auth_set_privilege_mask(
3782 __in efx_nic_t *enp,
3783 __in uint32_t vf_index,
3785 __in uint32_t value);
3788 extern __checkReturn efx_rc_t
3789 efx_proxy_auth_privilege_mask_get(
3790 __in efx_nic_t *enp,
3791 __in uint32_t pf_index,
3792 __in uint32_t vf_index,
3793 __out uint32_t *maskp);
3796 extern __checkReturn efx_rc_t
3797 efx_proxy_auth_privilege_modify(
3798 __in efx_nic_t *enp,
3799 __in uint32_t pf_index,
3800 __in uint32_t vf_index,
3801 __in uint32_t add_privileges_mask,
3802 __in uint32_t remove_privileges_mask);
3804 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3810 #endif /* _SYS_EFX_H */