1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
13 #define EFX_EV_PRESENT(_qword) \
14 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
15 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
21 static __checkReturn efx_rc_t
29 static __checkReturn efx_rc_t
32 __in unsigned int index,
33 __in efsys_mem_t *esmp,
44 static __checkReturn efx_rc_t
47 __in unsigned int count);
54 static __checkReturn efx_rc_t
57 __in unsigned int us);
61 siena_ev_qstats_update(
63 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
67 #endif /* EFSYS_OPT_SIENA */
69 #if EFX_OPTS_EF10() || EFSYS_OPT_SIENA
74 __inout unsigned int *countp,
75 __in const efx_ev_callbacks_t *eecp,
78 #endif /* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */
81 static const efx_ev_ops_t __efx_ev_siena_ops = {
82 siena_ev_init, /* eevo_init */
83 siena_ev_fini, /* eevo_fini */
84 siena_ev_qcreate, /* eevo_qcreate */
85 siena_ev_qdestroy, /* eevo_qdestroy */
86 siena_ev_qprime, /* eevo_qprime */
87 siena_ev_qpost, /* eevo_qpost */
88 siena_ef10_ev_qpoll, /* eevo_qpoll */
89 siena_ev_qmoderate, /* eevo_qmoderate */
91 siena_ev_qstats_update, /* eevo_qstats_update */
94 #endif /* EFSYS_OPT_SIENA */
97 static const efx_ev_ops_t __efx_ev_ef10_ops = {
98 ef10_ev_init, /* eevo_init */
99 ef10_ev_fini, /* eevo_fini */
100 ef10_ev_qcreate, /* eevo_qcreate */
101 ef10_ev_qdestroy, /* eevo_qdestroy */
102 ef10_ev_qprime, /* eevo_qprime */
103 ef10_ev_qpost, /* eevo_qpost */
104 siena_ef10_ev_qpoll, /* eevo_qpoll */
105 ef10_ev_qmoderate, /* eevo_qmoderate */
107 ef10_ev_qstats_update, /* eevo_qstats_update */
110 #endif /* EFX_OPTS_EF10() */
113 __checkReturn efx_rc_t
117 const efx_ev_ops_t *eevop;
120 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
121 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
123 if (enp->en_mod_flags & EFX_MOD_EV) {
128 switch (enp->en_family) {
130 case EFX_FAMILY_SIENA:
131 eevop = &__efx_ev_siena_ops;
133 #endif /* EFSYS_OPT_SIENA */
135 #if EFSYS_OPT_HUNTINGTON
136 case EFX_FAMILY_HUNTINGTON:
137 eevop = &__efx_ev_ef10_ops;
139 #endif /* EFSYS_OPT_HUNTINGTON */
141 #if EFSYS_OPT_MEDFORD
142 case EFX_FAMILY_MEDFORD:
143 eevop = &__efx_ev_ef10_ops;
145 #endif /* EFSYS_OPT_MEDFORD */
147 #if EFSYS_OPT_MEDFORD2
148 case EFX_FAMILY_MEDFORD2:
149 eevop = &__efx_ev_ef10_ops;
151 #endif /* EFSYS_OPT_MEDFORD2 */
159 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
161 if ((rc = eevop->eevo_init(enp)) != 0)
164 enp->en_eevop = eevop;
165 enp->en_mod_flags |= EFX_MOD_EV;
172 EFSYS_PROBE1(fail1, efx_rc_t, rc);
174 enp->en_eevop = NULL;
175 enp->en_mod_flags &= ~EFX_MOD_EV;
181 __in const efx_nic_t *enp,
182 __in unsigned int ndescs)
184 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
186 return (ndescs * encp->enc_ev_desc_size);
189 __checkReturn unsigned int
191 __in const efx_nic_t *enp,
192 __in unsigned int ndescs)
194 return (EFX_DIV_ROUND_UP(efx_evq_size(enp, ndescs), EFX_BUF_SIZE));
201 const efx_ev_ops_t *eevop = enp->en_eevop;
203 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
204 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
205 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
206 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
207 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
208 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
210 eevop->eevo_fini(enp);
212 enp->en_eevop = NULL;
213 enp->en_mod_flags &= ~EFX_MOD_EV;
217 __checkReturn efx_rc_t
220 __in unsigned int index,
221 __in efsys_mem_t *esmp,
226 __deref_out efx_evq_t **eepp)
228 const efx_ev_ops_t *eevop = enp->en_eevop;
230 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
233 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
234 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
236 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
237 enp->en_nic_cfg.enc_evq_limit);
239 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
240 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
242 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
253 EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
254 EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
257 ndescs < encp->enc_evq_min_nevs ||
258 ndescs > encp->enc_evq_max_nevs) {
263 /* Allocate an EVQ object */
264 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
270 eep->ee_magic = EFX_EVQ_MAGIC;
272 eep->ee_index = index;
273 eep->ee_mask = ndescs - 1;
274 eep->ee_flags = flags;
278 * Set outputs before the queue is created because interrupts may be
279 * raised for events immediately after the queue is created, before the
280 * function call below returns. See bug58606.
282 * The eepp pointer passed in by the client must therefore point to data
283 * shared with the client's event processing context.
288 if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
299 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
307 EFSYS_PROBE1(fail1, efx_rc_t, rc);
315 efx_nic_t *enp = eep->ee_enp;
316 const efx_ev_ops_t *eevop = enp->en_eevop;
318 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
320 EFSYS_ASSERT(enp->en_ev_qcount != 0);
323 eevop->eevo_qdestroy(eep);
325 /* Free the EVQ object */
326 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
329 __checkReturn efx_rc_t
332 __in unsigned int count)
334 efx_nic_t *enp = eep->ee_enp;
335 const efx_ev_ops_t *eevop = enp->en_eevop;
338 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
340 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
345 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
353 EFSYS_PROBE1(fail1, efx_rc_t, rc);
357 __checkReturn boolean_t
360 __in unsigned int count)
365 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
367 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
368 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
370 return (EFX_EV_PRESENT(qword));
373 #if EFSYS_OPT_EV_PREFETCH
378 __in unsigned int count)
382 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
384 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
385 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
388 #endif /* EFSYS_OPT_EV_PREFETCH */
393 __inout unsigned int *countp,
394 __in const efx_ev_callbacks_t *eecp,
397 efx_nic_t *enp = eep->ee_enp;
398 const efx_ev_ops_t *eevop = enp->en_eevop;
400 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
402 EFSYS_ASSERT(eevop != NULL &&
403 eevop->eevo_qpoll != NULL);
405 eevop->eevo_qpoll(eep, countp, eecp, arg);
413 efx_nic_t *enp = eep->ee_enp;
414 const efx_ev_ops_t *eevop = enp->en_eevop;
416 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
418 EFSYS_ASSERT(eevop != NULL &&
419 eevop->eevo_qpost != NULL);
421 eevop->eevo_qpost(eep, data);
424 __checkReturn efx_rc_t
425 efx_ev_usecs_to_ticks(
427 __in unsigned int us,
428 __out unsigned int *ticksp)
430 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
434 if (encp->enc_evq_timer_quantum_ns == 0) {
439 /* Convert microseconds to a timer tick count */
442 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
443 ticks = 1; /* Never round down to zero */
445 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
451 EFSYS_PROBE1(fail1, efx_rc_t, rc);
455 __checkReturn efx_rc_t
458 __in unsigned int us)
460 efx_nic_t *enp = eep->ee_enp;
461 const efx_ev_ops_t *eevop = enp->en_eevop;
464 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
466 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
467 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
472 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
480 EFSYS_PROBE1(fail1, efx_rc_t, rc);
486 efx_ev_qstats_update(
488 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
490 { efx_nic_t *enp = eep->ee_enp;
491 const efx_ev_ops_t *eevop = enp->en_eevop;
493 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
495 eevop->eevo_qstats_update(eep, stat);
498 #endif /* EFSYS_OPT_QSTATS */
502 static __checkReturn efx_rc_t
509 * Program the event queue for receive and transmit queue
512 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
513 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
514 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
520 static __checkReturn boolean_t
523 __in efx_qword_t *eqp,
526 __inout uint16_t *flagsp)
528 boolean_t ignore = B_FALSE;
530 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
531 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
532 EFSYS_PROBE(tobe_disc);
534 * Assume this is a unicast address mismatch, unless below
535 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
536 * EV_RX_PAUSE_FRM_ERR is set.
538 (*flagsp) |= EFX_ADDR_MISMATCH;
541 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
542 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
543 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
544 (*flagsp) |= EFX_DISCARD;
546 #if EFSYS_OPT_RX_SCATTER
548 * Lookout for payload queue ran dry errors and ignore them.
550 * Sadly for the header/data split cases, the descriptor
551 * pointer in this event refers to the header queue and
552 * therefore cannot be easily detected as duplicate.
553 * So we drop these and rely on the receive processing seeing
554 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
555 * the partially received packet.
557 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
558 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
559 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
561 #endif /* EFSYS_OPT_RX_SCATTER */
564 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
565 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
566 EFSYS_PROBE(crc_err);
567 (*flagsp) &= ~EFX_ADDR_MISMATCH;
568 (*flagsp) |= EFX_DISCARD;
571 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
572 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
573 EFSYS_PROBE(pause_frm_err);
574 (*flagsp) &= ~EFX_ADDR_MISMATCH;
575 (*flagsp) |= EFX_DISCARD;
578 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
579 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
580 EFSYS_PROBE(owner_id_err);
581 (*flagsp) |= EFX_DISCARD;
584 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
585 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
586 EFSYS_PROBE(ipv4_err);
587 (*flagsp) &= ~EFX_CKSUM_IPV4;
590 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
591 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
592 EFSYS_PROBE(udp_chk_err);
593 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
596 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
597 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
600 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
601 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
604 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
610 static __checkReturn boolean_t
613 __in efx_qword_t *eqp,
614 __in const efx_ev_callbacks_t *eecp,
621 #if EFSYS_OPT_RX_SCATTER
623 boolean_t jumbo_cont;
624 #endif /* EFSYS_OPT_RX_SCATTER */
629 boolean_t should_abort;
631 EFX_EV_QSTAT_INCR(eep, EV_RX);
633 /* Basic packet information */
634 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
635 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
636 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
637 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
639 #if EFSYS_OPT_RX_SCATTER
640 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
641 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
642 #endif /* EFSYS_OPT_RX_SCATTER */
644 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
646 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
649 * If packet is marked as OK and packet type is TCP/IP or
650 * UDP/IP or other IP, then we can rely on the hardware checksums.
653 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
654 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
656 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
657 flags |= EFX_PKT_IPV6;
659 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
660 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
664 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
665 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
667 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
668 flags |= EFX_PKT_IPV6;
670 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
671 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
675 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
677 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
678 flags = EFX_PKT_IPV6;
680 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
681 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
685 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
686 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
691 EFSYS_ASSERT(B_FALSE);
696 #if EFSYS_OPT_RX_SCATTER
697 /* Report scatter and header/lookahead split buffer flags */
699 flags |= EFX_PKT_START;
701 flags |= EFX_PKT_CONT;
702 #endif /* EFSYS_OPT_RX_SCATTER */
704 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
706 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
708 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
709 uint32_t, size, uint16_t, flags);
715 /* If we're not discarding the packet then it is ok */
716 if (~flags & EFX_DISCARD)
717 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
719 /* Detect multicast packets that didn't match the filter */
720 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
721 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
723 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
724 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
726 EFSYS_PROBE(mcast_mismatch);
727 flags |= EFX_ADDR_MISMATCH;
730 flags |= EFX_PKT_UNICAST;
734 * The packet parser in Siena can abort parsing packets under
735 * certain error conditions, setting the PKT_NOT_PARSED bit
736 * (which clears PKT_OK). If this is set, then don't trust
737 * the PKT_TYPE field.
742 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
744 flags |= EFX_CHECK_VLAN;
747 if (~flags & EFX_CHECK_VLAN) {
750 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
751 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
752 flags |= EFX_PKT_VLAN_TAGGED;
755 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
756 uint32_t, size, uint16_t, flags);
758 EFSYS_ASSERT(eecp->eec_rx != NULL);
759 should_abort = eecp->eec_rx(arg, label, id, size, flags);
761 return (should_abort);
764 static __checkReturn boolean_t
767 __in efx_qword_t *eqp,
768 __in const efx_ev_callbacks_t *eecp,
773 boolean_t should_abort;
775 EFX_EV_QSTAT_INCR(eep, EV_TX);
777 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
778 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
779 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
780 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
782 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
783 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
785 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
787 EFSYS_ASSERT(eecp->eec_tx != NULL);
788 should_abort = eecp->eec_tx(arg, label, id);
790 return (should_abort);
793 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
794 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
795 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
796 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
798 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
799 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
801 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
802 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
804 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
805 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
807 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
811 static __checkReturn boolean_t
814 __in efx_qword_t *eqp,
815 __in const efx_ev_callbacks_t *eecp,
818 _NOTE(ARGUNUSED(eqp, eecp, arg))
820 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
825 static __checkReturn boolean_t
828 __in efx_qword_t *eqp,
829 __in const efx_ev_callbacks_t *eecp,
832 boolean_t should_abort;
834 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
835 should_abort = B_FALSE;
837 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
838 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
841 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
843 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
845 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
847 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
848 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
852 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
856 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
857 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
859 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
860 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
863 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
865 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
867 should_abort = eecp->eec_rxq_flush_failed(arg,
870 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
872 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
874 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
879 case FSE_AZ_EVQ_INIT_DONE_EV:
880 EFSYS_ASSERT(eecp->eec_initialized != NULL);
881 should_abort = eecp->eec_initialized(arg);
885 case FSE_AZ_EVQ_NOT_EN_EV:
886 EFSYS_PROBE(evq_not_en);
889 case FSE_AZ_SRM_UPD_DONE_EV: {
892 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
894 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
896 EFSYS_ASSERT(eecp->eec_sram != NULL);
897 should_abort = eecp->eec_sram(arg, code);
901 case FSE_AZ_WAKE_UP_EV: {
904 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
906 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
907 should_abort = eecp->eec_wake_up(arg, id);
911 case FSE_AZ_TX_PKT_NON_TCP_UDP:
912 EFSYS_PROBE(tx_pkt_non_tcp_udp);
915 case FSE_AZ_TIMER_EV: {
918 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
920 EFSYS_ASSERT(eecp->eec_timer != NULL);
921 should_abort = eecp->eec_timer(arg, id);
925 case FSE_AZ_RX_DSC_ERROR_EV:
926 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
928 EFSYS_PROBE(rx_dsc_error);
930 EFSYS_ASSERT(eecp->eec_exception != NULL);
931 should_abort = eecp->eec_exception(arg,
932 EFX_EXCEPTION_RX_DSC_ERROR, 0);
936 case FSE_AZ_TX_DSC_ERROR_EV:
937 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
939 EFSYS_PROBE(tx_dsc_error);
941 EFSYS_ASSERT(eecp->eec_exception != NULL);
942 should_abort = eecp->eec_exception(arg,
943 EFX_EXCEPTION_TX_DSC_ERROR, 0);
951 return (should_abort);
954 static __checkReturn boolean_t
957 __in efx_qword_t *eqp,
958 __in const efx_ev_callbacks_t *eecp,
962 boolean_t should_abort;
964 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
966 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
967 if (data >= ((uint32_t)1 << 16)) {
968 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
969 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
970 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
974 EFSYS_ASSERT(eecp->eec_software != NULL);
975 should_abort = eecp->eec_software(arg, (uint16_t)data);
977 return (should_abort);
982 static __checkReturn boolean_t
985 __in efx_qword_t *eqp,
986 __in const efx_ev_callbacks_t *eecp,
989 efx_nic_t *enp = eep->ee_enp;
991 boolean_t should_abort = B_FALSE;
993 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
995 if (enp->en_family != EFX_FAMILY_SIENA)
998 EFSYS_ASSERT(eecp->eec_link_change != NULL);
999 EFSYS_ASSERT(eecp->eec_exception != NULL);
1000 #if EFSYS_OPT_MON_STATS
1001 EFSYS_ASSERT(eecp->eec_monitor != NULL);
1004 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1006 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1008 case MCDI_EVENT_CODE_BADSSERT:
1009 efx_mcdi_ev_death(enp, EINTR);
1012 case MCDI_EVENT_CODE_CMDDONE:
1013 efx_mcdi_ev_cpl(enp,
1014 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1015 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1016 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1019 case MCDI_EVENT_CODE_LINKCHANGE: {
1020 efx_link_mode_t link_mode;
1022 siena_phy_link_ev(enp, eqp, &link_mode);
1023 should_abort = eecp->eec_link_change(arg, link_mode);
1026 case MCDI_EVENT_CODE_SENSOREVT: {
1027 #if EFSYS_OPT_MON_STATS
1029 efx_mon_stat_value_t value;
1032 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1033 should_abort = eecp->eec_monitor(arg, id, value);
1034 else if (rc == ENOTSUP) {
1035 should_abort = eecp->eec_exception(arg,
1036 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1037 MCDI_EV_FIELD(eqp, DATA));
1039 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1041 should_abort = B_FALSE;
1045 case MCDI_EVENT_CODE_SCHEDERR:
1046 /* Informational only */
1049 case MCDI_EVENT_CODE_REBOOT:
1050 efx_mcdi_ev_death(enp, EIO);
1053 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1054 #if EFSYS_OPT_MAC_STATS
1055 if (eecp->eec_mac_stats != NULL) {
1056 eecp->eec_mac_stats(arg,
1057 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1062 case MCDI_EVENT_CODE_FWALERT: {
1063 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1065 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1066 should_abort = eecp->eec_exception(arg,
1067 EFX_EXCEPTION_FWALERT_SRAM,
1068 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1070 should_abort = eecp->eec_exception(arg,
1071 EFX_EXCEPTION_UNKNOWN_FWALERT,
1072 MCDI_EV_FIELD(eqp, DATA));
1077 EFSYS_PROBE1(mc_pcol_error, int, code);
1082 return (should_abort);
1085 #endif /* EFSYS_OPT_MCDI */
1087 static __checkReturn efx_rc_t
1089 __in efx_evq_t *eep,
1090 __in unsigned int count)
1092 efx_nic_t *enp = eep->ee_enp;
1096 rptr = count & eep->ee_mask;
1098 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1100 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1108 __in efx_evq_t *eep,
1111 efx_nic_t *enp = eep->ee_enp;
1115 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1116 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1118 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1119 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1120 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1122 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1125 static __checkReturn efx_rc_t
1127 __in efx_evq_t *eep,
1128 __in unsigned int us)
1130 efx_nic_t *enp = eep->ee_enp;
1131 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1132 unsigned int locked;
1136 if (us > encp->enc_evq_timer_max_us) {
1141 /* If the value is zero then disable the timer */
1143 EFX_POPULATE_DWORD_2(dword,
1144 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1145 FRF_CZ_TC_TIMER_VAL, 0);
1149 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1152 EFSYS_ASSERT(ticks > 0);
1153 EFX_POPULATE_DWORD_2(dword,
1154 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1155 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1158 locked = (eep->ee_index == 0) ? 1 : 0;
1160 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1161 eep->ee_index, &dword, locked);
1168 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1173 static __checkReturn efx_rc_t
1175 __in efx_nic_t *enp,
1176 __in unsigned int index,
1177 __in efsys_mem_t *esmp,
1181 __in uint32_t flags,
1182 __in efx_evq_t *eep)
1184 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1188 boolean_t notify_mode;
1190 _NOTE(ARGUNUSED(esmp))
1192 if (index >= encp->enc_evq_limit) {
1196 #if EFSYS_OPT_RX_SCALE
1197 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1198 index >= EFX_MAXRSS_LEGACY) {
1204 (1U << size) <= encp->enc_evq_max_nevs / encp->enc_evq_min_nevs;
1206 if ((1U << size) == (uint32_t)ndescs / encp->enc_evq_min_nevs)
1208 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1213 /* Set up the handler table */
1214 eep->ee_rx = siena_ev_rx;
1215 eep->ee_tx = siena_ev_tx;
1216 eep->ee_driver = siena_ev_driver;
1217 eep->ee_global = siena_ev_global;
1218 eep->ee_drv_gen = siena_ev_drv_gen;
1220 eep->ee_mcdi = siena_ev_mcdi;
1221 #endif /* EFSYS_OPT_MCDI */
1223 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1224 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1226 /* Set up the new event queue */
1227 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1228 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1229 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1230 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1232 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1233 FRF_AZ_EVQ_BUF_BASE_ID, id);
1235 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1237 /* Set initial interrupt moderation */
1238 siena_ev_qmoderate(eep, us);
1244 #if EFSYS_OPT_RX_SCALE
1249 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1254 #endif /* EFSYS_OPT_SIENA */
1256 #if EFSYS_OPT_QSTATS
1258 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock ac223f7134058b4f */
1259 static const char * const __efx_ev_qstat_name[] = {
1266 "rx_buf_owner_id_err",
1267 "rx_ipv4_hdr_chksum_err",
1268 "rx_tcp_udp_chksum_err",
1272 "rx_mcast_hash_match",
1289 "driver_srm_upd_done",
1290 "driver_tx_descq_fls_done",
1291 "driver_rx_descq_fls_done",
1292 "driver_rx_descq_fls_failed",
1293 "driver_rx_dsc_error",
1294 "driver_tx_dsc_error",
1297 "rx_parse_incomplete",
1299 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1303 __in efx_nic_t *enp,
1304 __in unsigned int id)
1306 _NOTE(ARGUNUSED(enp))
1308 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1309 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1311 return (__efx_ev_qstat_name[id]);
1313 #endif /* EFSYS_OPT_NAMES */
1314 #endif /* EFSYS_OPT_QSTATS */
1318 #if EFSYS_OPT_QSTATS
1320 siena_ev_qstats_update(
1321 __in efx_evq_t *eep,
1322 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1326 for (id = 0; id < EV_NQSTATS; id++) {
1327 efsys_stat_t *essp = &stat[id];
1329 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1330 eep->ee_stat[id] = 0;
1333 #endif /* EFSYS_OPT_QSTATS */
1337 __in efx_evq_t *eep)
1339 efx_nic_t *enp = eep->ee_enp;
1342 /* Purge event queue */
1343 EFX_ZERO_OWORD(oword);
1345 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1346 eep->ee_index, &oword, B_TRUE);
1348 EFX_ZERO_OWORD(oword);
1349 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1354 __in efx_nic_t *enp)
1356 _NOTE(ARGUNUSED(enp))
1359 #endif /* EFSYS_OPT_SIENA */
1361 #if EFX_OPTS_EF10() || EFSYS_OPT_SIENA
1363 #define EFX_EV_BATCH 8
1366 siena_ef10_ev_qpoll(
1367 __in efx_evq_t *eep,
1368 __inout unsigned int *countp,
1369 __in const efx_ev_callbacks_t *eecp,
1372 efx_qword_t ev[EFX_EV_BATCH];
1379 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
1380 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
1381 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
1383 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
1384 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
1385 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
1386 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
1387 FSE_AZ_EV_CODE_DRV_GEN_EV);
1389 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
1390 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
1393 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
1394 EFSYS_ASSERT(countp != NULL);
1395 EFSYS_ASSERT(eecp != NULL);
1399 /* Read up until the end of the batch period */
1400 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1401 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1402 for (total = 0; total < batch; ++total) {
1403 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1405 if (!EFX_EV_PRESENT(ev[total]))
1408 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1409 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1410 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1412 offset += sizeof (efx_qword_t);
1415 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1417 * Prefetch the next batch when we get within PREFETCH_PERIOD
1418 * of a completed batch. If the batch is smaller, then prefetch
1421 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1422 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1423 #endif /* EFSYS_OPT_EV_PREFETCH */
1425 /* Process the batch of events */
1426 for (index = 0; index < total; ++index) {
1427 boolean_t should_abort;
1430 #if EFSYS_OPT_EV_PREFETCH
1431 /* Prefetch if we've now reached the batch period */
1432 if (total == batch &&
1433 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1434 offset = (count + batch) & eep->ee_mask;
1435 offset *= sizeof (efx_qword_t);
1437 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1439 #endif /* EFSYS_OPT_EV_PREFETCH */
1441 EFX_EV_QSTAT_INCR(eep, EV_ALL);
1443 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1445 case FSE_AZ_EV_CODE_RX_EV:
1446 should_abort = eep->ee_rx(eep,
1447 &(ev[index]), eecp, arg);
1449 case FSE_AZ_EV_CODE_TX_EV:
1450 should_abort = eep->ee_tx(eep,
1451 &(ev[index]), eecp, arg);
1453 case FSE_AZ_EV_CODE_DRIVER_EV:
1454 should_abort = eep->ee_driver(eep,
1455 &(ev[index]), eecp, arg);
1457 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1458 should_abort = eep->ee_drv_gen(eep,
1459 &(ev[index]), eecp, arg);
1462 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1463 should_abort = eep->ee_mcdi(eep,
1464 &(ev[index]), eecp, arg);
1467 case FSE_AZ_EV_CODE_GLOBAL_EV:
1468 if (eep->ee_global) {
1469 should_abort = eep->ee_global(eep,
1470 &(ev[index]), eecp, arg);
1473 /* else fallthrough */
1475 EFSYS_PROBE3(bad_event,
1476 unsigned int, eep->ee_index,
1478 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1480 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1482 EFSYS_ASSERT(eecp->eec_exception != NULL);
1483 (void) eecp->eec_exception(arg,
1484 EFX_EXCEPTION_EV_ERROR, code);
1485 should_abort = B_TRUE;
1488 /* Ignore subsequent events */
1492 * Poison batch to ensure the outer
1493 * loop is broken out of.
1495 EFSYS_ASSERT(batch <= EFX_EV_BATCH);
1496 batch += (EFX_EV_BATCH << 1);
1497 EFSYS_ASSERT(total != batch);
1503 * Now that the hardware has most likely moved onto dma'ing
1504 * into the next cache line, clear the processed events. Take
1505 * care to only clear out events that we've processed
1507 EFX_SET_QWORD(ev[0]);
1508 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1509 for (index = 0; index < total; ++index) {
1510 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1511 offset += sizeof (efx_qword_t);
1516 } while (total == batch);
1521 #endif /* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */