1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
13 #define EFX_EV_PRESENT(_qword) \
14 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
15 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
21 static __checkReturn efx_rc_t
29 static __checkReturn efx_rc_t
32 __in unsigned int index,
33 __in efsys_mem_t *esmp,
44 static __checkReturn efx_rc_t
47 __in unsigned int count);
54 static __checkReturn efx_rc_t
57 __in unsigned int us);
61 siena_ev_qstats_update(
63 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
67 #endif /* EFSYS_OPT_SIENA */
69 #if EFX_OPTS_EF10() || EFSYS_OPT_SIENA
74 __inout unsigned int *countp,
75 __in const efx_ev_callbacks_t *eecp,
78 #endif /* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */
81 static const efx_ev_ops_t __efx_ev_siena_ops = {
82 siena_ev_init, /* eevo_init */
83 siena_ev_fini, /* eevo_fini */
84 siena_ev_qcreate, /* eevo_qcreate */
85 siena_ev_qdestroy, /* eevo_qdestroy */
86 siena_ev_qprime, /* eevo_qprime */
87 siena_ev_qpost, /* eevo_qpost */
88 siena_ef10_ev_qpoll, /* eevo_qpoll */
89 siena_ev_qmoderate, /* eevo_qmoderate */
91 siena_ev_qstats_update, /* eevo_qstats_update */
94 #endif /* EFSYS_OPT_SIENA */
97 static const efx_ev_ops_t __efx_ev_ef10_ops = {
98 ef10_ev_init, /* eevo_init */
99 ef10_ev_fini, /* eevo_fini */
100 ef10_ev_qcreate, /* eevo_qcreate */
101 ef10_ev_qdestroy, /* eevo_qdestroy */
102 ef10_ev_qprime, /* eevo_qprime */
103 ef10_ev_qpost, /* eevo_qpost */
104 siena_ef10_ev_qpoll, /* eevo_qpoll */
105 ef10_ev_qmoderate, /* eevo_qmoderate */
107 ef10_ev_qstats_update, /* eevo_qstats_update */
110 #endif /* EFX_OPTS_EF10() */
112 #if EFSYS_OPT_RIVERHEAD
113 static const efx_ev_ops_t __efx_ev_rhead_ops = {
114 rhead_ev_init, /* eevo_init */
115 rhead_ev_fini, /* eevo_fini */
116 rhead_ev_qcreate, /* eevo_qcreate */
117 rhead_ev_qdestroy, /* eevo_qdestroy */
118 rhead_ev_qprime, /* eevo_qprime */
119 rhead_ev_qpost, /* eevo_qpost */
120 rhead_ev_qpoll, /* eevo_qpoll */
121 rhead_ev_qmoderate, /* eevo_qmoderate */
123 rhead_ev_qstats_update, /* eevo_qstats_update */
126 #endif /* EFSYS_OPT_RIVERHEAD */
129 __checkReturn efx_rc_t
133 const efx_ev_ops_t *eevop;
136 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
137 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
139 if (enp->en_mod_flags & EFX_MOD_EV) {
144 switch (enp->en_family) {
146 case EFX_FAMILY_SIENA:
147 eevop = &__efx_ev_siena_ops;
149 #endif /* EFSYS_OPT_SIENA */
151 #if EFSYS_OPT_HUNTINGTON
152 case EFX_FAMILY_HUNTINGTON:
153 eevop = &__efx_ev_ef10_ops;
155 #endif /* EFSYS_OPT_HUNTINGTON */
157 #if EFSYS_OPT_MEDFORD
158 case EFX_FAMILY_MEDFORD:
159 eevop = &__efx_ev_ef10_ops;
161 #endif /* EFSYS_OPT_MEDFORD */
163 #if EFSYS_OPT_MEDFORD2
164 case EFX_FAMILY_MEDFORD2:
165 eevop = &__efx_ev_ef10_ops;
167 #endif /* EFSYS_OPT_MEDFORD2 */
169 #if EFSYS_OPT_RIVERHEAD
170 case EFX_FAMILY_RIVERHEAD:
171 eevop = &__efx_ev_rhead_ops;
173 #endif /* EFSYS_OPT_RIVERHEAD */
181 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
183 if ((rc = eevop->eevo_init(enp)) != 0)
186 enp->en_eevop = eevop;
187 enp->en_mod_flags |= EFX_MOD_EV;
194 EFSYS_PROBE1(fail1, efx_rc_t, rc);
196 enp->en_eevop = NULL;
197 enp->en_mod_flags &= ~EFX_MOD_EV;
203 __in const efx_nic_t *enp,
204 __in unsigned int ndescs)
206 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
208 return (ndescs * encp->enc_ev_desc_size);
211 __checkReturn unsigned int
213 __in const efx_nic_t *enp,
214 __in unsigned int ndescs)
216 return (EFX_DIV_ROUND_UP(efx_evq_size(enp, ndescs), EFX_BUF_SIZE));
223 const efx_ev_ops_t *eevop = enp->en_eevop;
225 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
226 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
227 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
228 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
229 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
230 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
232 eevop->eevo_fini(enp);
234 enp->en_eevop = NULL;
235 enp->en_mod_flags &= ~EFX_MOD_EV;
239 __checkReturn efx_rc_t
242 __in unsigned int index,
243 __in efsys_mem_t *esmp,
248 __deref_out efx_evq_t **eepp)
250 const efx_ev_ops_t *eevop = enp->en_eevop;
252 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
255 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
256 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
258 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
259 enp->en_nic_cfg.enc_evq_limit);
261 if (index >= encp->enc_evq_limit) {
266 if (us > encp->enc_evq_timer_max_us) {
271 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
272 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
274 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
285 EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
286 EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
289 ndescs < encp->enc_evq_min_nevs ||
290 ndescs > encp->enc_evq_max_nevs) {
295 /* Allocate an EVQ object */
296 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
302 eep->ee_magic = EFX_EVQ_MAGIC;
304 eep->ee_index = index;
305 eep->ee_mask = ndescs - 1;
306 eep->ee_flags = flags;
310 * Set outputs before the queue is created because interrupts may be
311 * raised for events immediately after the queue is created, before the
312 * function call below returns. See bug58606.
314 * The eepp pointer passed in by the client must therefore point to data
315 * shared with the client's event processing context.
320 if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
331 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
343 EFSYS_PROBE1(fail1, efx_rc_t, rc);
351 efx_nic_t *enp = eep->ee_enp;
352 const efx_ev_ops_t *eevop = enp->en_eevop;
354 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
356 EFSYS_ASSERT(enp->en_ev_qcount != 0);
359 eevop->eevo_qdestroy(eep);
361 /* Free the EVQ object */
362 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
365 __checkReturn efx_rc_t
368 __in unsigned int count)
370 efx_nic_t *enp = eep->ee_enp;
371 const efx_ev_ops_t *eevop = enp->en_eevop;
374 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
376 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
381 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
389 EFSYS_PROBE1(fail1, efx_rc_t, rc);
393 __checkReturn boolean_t
396 __in unsigned int count)
401 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
403 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
404 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
406 return (EFX_EV_PRESENT(qword));
409 #if EFSYS_OPT_EV_PREFETCH
414 __in unsigned int count)
418 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
420 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
421 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
424 #endif /* EFSYS_OPT_EV_PREFETCH */
427 * This method is needed to ensure that eec_initialized callback
428 * is invoked after queue creation. The callback will be invoked
429 * on Riverhead boards which have no support for INIT_DONE events
430 * and will do nothing on other boards.
432 * The client drivers must call this method after calling efx_ev_create().
433 * The call must be done with the same locks being held (if any) which are
434 * normally acquired around efx_ev_qpoll() calls to ensure that
435 * eec_initialized callback is invoked within the same locking context.
438 efx_ev_qcreate_check_init_done(
440 __in const efx_ev_callbacks_t *eecp,
443 const efx_nic_cfg_t *encp;
445 EFSYS_ASSERT(eep != NULL);
446 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
447 EFSYS_ASSERT(eecp != NULL);
448 EFSYS_ASSERT(eecp->eec_initialized != NULL);
450 encp = efx_nic_cfg_get(eep->ee_enp);
452 if (encp->enc_evq_init_done_ev_supported == B_FALSE)
453 (void) eecp->eec_initialized(arg);
459 __inout unsigned int *countp,
460 __in const efx_ev_callbacks_t *eecp,
463 efx_nic_t *enp = eep->ee_enp;
464 const efx_ev_ops_t *eevop = enp->en_eevop;
466 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
468 EFSYS_ASSERT(eevop != NULL &&
469 eevop->eevo_qpoll != NULL);
471 eevop->eevo_qpoll(eep, countp, eecp, arg);
479 efx_nic_t *enp = eep->ee_enp;
480 const efx_ev_ops_t *eevop = enp->en_eevop;
482 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
484 EFSYS_ASSERT(eevop != NULL &&
485 eevop->eevo_qpost != NULL);
487 eevop->eevo_qpost(eep, data);
490 __checkReturn efx_rc_t
491 efx_ev_usecs_to_ticks(
493 __in unsigned int us,
494 __out unsigned int *ticksp)
496 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
500 if (encp->enc_evq_timer_quantum_ns == 0) {
505 /* Convert microseconds to a timer tick count */
508 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
509 ticks = 1; /* Never round down to zero */
511 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
517 EFSYS_PROBE1(fail1, efx_rc_t, rc);
521 __checkReturn efx_rc_t
524 __in unsigned int us)
526 efx_nic_t *enp = eep->ee_enp;
527 const efx_ev_ops_t *eevop = enp->en_eevop;
530 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
532 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
533 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
538 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
546 EFSYS_PROBE1(fail1, efx_rc_t, rc);
552 efx_ev_qstats_update(
554 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
556 { efx_nic_t *enp = eep->ee_enp;
557 const efx_ev_ops_t *eevop = enp->en_eevop;
559 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
561 eevop->eevo_qstats_update(eep, stat);
564 #endif /* EFSYS_OPT_QSTATS */
568 static __checkReturn efx_rc_t
575 * Program the event queue for receive and transmit queue
578 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
579 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
580 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
586 static __checkReturn boolean_t
589 __in efx_qword_t *eqp,
592 __inout uint16_t *flagsp)
594 boolean_t ignore = B_FALSE;
596 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
597 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
598 EFSYS_PROBE(tobe_disc);
600 * Assume this is a unicast address mismatch, unless below
601 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
602 * EV_RX_PAUSE_FRM_ERR is set.
604 (*flagsp) |= EFX_ADDR_MISMATCH;
607 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
608 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
609 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
610 (*flagsp) |= EFX_DISCARD;
612 #if EFSYS_OPT_RX_SCATTER
614 * Lookout for payload queue ran dry errors and ignore them.
616 * Sadly for the header/data split cases, the descriptor
617 * pointer in this event refers to the header queue and
618 * therefore cannot be easily detected as duplicate.
619 * So we drop these and rely on the receive processing seeing
620 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
621 * the partially received packet.
623 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
624 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
625 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
627 #endif /* EFSYS_OPT_RX_SCATTER */
630 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
631 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
632 EFSYS_PROBE(crc_err);
633 (*flagsp) &= ~EFX_ADDR_MISMATCH;
634 (*flagsp) |= EFX_DISCARD;
637 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
638 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
639 EFSYS_PROBE(pause_frm_err);
640 (*flagsp) &= ~EFX_ADDR_MISMATCH;
641 (*flagsp) |= EFX_DISCARD;
644 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
645 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
646 EFSYS_PROBE(owner_id_err);
647 (*flagsp) |= EFX_DISCARD;
650 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
651 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
652 EFSYS_PROBE(ipv4_err);
653 (*flagsp) &= ~EFX_CKSUM_IPV4;
656 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
657 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
658 EFSYS_PROBE(udp_chk_err);
659 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
662 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
663 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
666 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
667 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
670 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
676 static __checkReturn boolean_t
679 __in efx_qword_t *eqp,
680 __in const efx_ev_callbacks_t *eecp,
687 #if EFSYS_OPT_RX_SCATTER
689 boolean_t jumbo_cont;
690 #endif /* EFSYS_OPT_RX_SCATTER */
695 boolean_t should_abort;
697 EFX_EV_QSTAT_INCR(eep, EV_RX);
699 /* Basic packet information */
700 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
701 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
702 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
703 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
705 #if EFSYS_OPT_RX_SCATTER
706 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
707 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
708 #endif /* EFSYS_OPT_RX_SCATTER */
710 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
712 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
715 * If packet is marked as OK and packet type is TCP/IP or
716 * UDP/IP or other IP, then we can rely on the hardware checksums.
719 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
720 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
722 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
723 flags |= EFX_PKT_IPV6;
725 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
726 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
730 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
731 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
733 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
734 flags |= EFX_PKT_IPV6;
736 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
737 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
741 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
743 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
744 flags = EFX_PKT_IPV6;
746 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
747 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
751 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
752 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
757 EFSYS_ASSERT(B_FALSE);
762 #if EFSYS_OPT_RX_SCATTER
763 /* Report scatter and header/lookahead split buffer flags */
765 flags |= EFX_PKT_START;
767 flags |= EFX_PKT_CONT;
768 #endif /* EFSYS_OPT_RX_SCATTER */
770 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
772 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
774 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
775 uint32_t, size, uint16_t, flags);
781 /* If we're not discarding the packet then it is ok */
782 if (~flags & EFX_DISCARD)
783 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
785 /* Detect multicast packets that didn't match the filter */
786 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
787 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
789 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
790 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
792 EFSYS_PROBE(mcast_mismatch);
793 flags |= EFX_ADDR_MISMATCH;
796 flags |= EFX_PKT_UNICAST;
800 * The packet parser in Siena can abort parsing packets under
801 * certain error conditions, setting the PKT_NOT_PARSED bit
802 * (which clears PKT_OK). If this is set, then don't trust
803 * the PKT_TYPE field.
808 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
810 flags |= EFX_CHECK_VLAN;
813 if (~flags & EFX_CHECK_VLAN) {
816 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
817 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
818 flags |= EFX_PKT_VLAN_TAGGED;
821 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
822 uint32_t, size, uint16_t, flags);
824 EFSYS_ASSERT(eecp->eec_rx != NULL);
825 should_abort = eecp->eec_rx(arg, label, id, size, flags);
827 return (should_abort);
830 static __checkReturn boolean_t
833 __in efx_qword_t *eqp,
834 __in const efx_ev_callbacks_t *eecp,
839 boolean_t should_abort;
841 EFX_EV_QSTAT_INCR(eep, EV_TX);
843 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
844 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
845 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
846 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
848 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
849 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
851 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
853 EFSYS_ASSERT(eecp->eec_tx != NULL);
854 should_abort = eecp->eec_tx(arg, label, id);
856 return (should_abort);
859 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
860 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
861 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
862 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
864 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
865 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
867 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
868 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
870 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
871 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
873 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
877 static __checkReturn boolean_t
880 __in efx_qword_t *eqp,
881 __in const efx_ev_callbacks_t *eecp,
884 _NOTE(ARGUNUSED(eqp, eecp, arg))
886 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
891 static __checkReturn boolean_t
894 __in efx_qword_t *eqp,
895 __in const efx_ev_callbacks_t *eecp,
898 boolean_t should_abort;
900 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
901 should_abort = B_FALSE;
903 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
904 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
907 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
909 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
911 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
913 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
914 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
918 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
922 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
923 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
925 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
926 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
929 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
931 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
933 should_abort = eecp->eec_rxq_flush_failed(arg,
936 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
938 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
940 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
945 case FSE_AZ_EVQ_INIT_DONE_EV:
946 EFSYS_ASSERT(eecp->eec_initialized != NULL);
947 should_abort = eecp->eec_initialized(arg);
951 case FSE_AZ_EVQ_NOT_EN_EV:
952 EFSYS_PROBE(evq_not_en);
955 case FSE_AZ_SRM_UPD_DONE_EV: {
958 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
960 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
962 EFSYS_ASSERT(eecp->eec_sram != NULL);
963 should_abort = eecp->eec_sram(arg, code);
967 case FSE_AZ_WAKE_UP_EV: {
970 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
972 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
973 should_abort = eecp->eec_wake_up(arg, id);
977 case FSE_AZ_TX_PKT_NON_TCP_UDP:
978 EFSYS_PROBE(tx_pkt_non_tcp_udp);
981 case FSE_AZ_TIMER_EV: {
984 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
986 EFSYS_ASSERT(eecp->eec_timer != NULL);
987 should_abort = eecp->eec_timer(arg, id);
991 case FSE_AZ_RX_DSC_ERROR_EV:
992 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
994 EFSYS_PROBE(rx_dsc_error);
996 EFSYS_ASSERT(eecp->eec_exception != NULL);
997 should_abort = eecp->eec_exception(arg,
998 EFX_EXCEPTION_RX_DSC_ERROR, 0);
1002 case FSE_AZ_TX_DSC_ERROR_EV:
1003 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1005 EFSYS_PROBE(tx_dsc_error);
1007 EFSYS_ASSERT(eecp->eec_exception != NULL);
1008 should_abort = eecp->eec_exception(arg,
1009 EFX_EXCEPTION_TX_DSC_ERROR, 0);
1017 return (should_abort);
1020 static __checkReturn boolean_t
1022 __in efx_evq_t *eep,
1023 __in efx_qword_t *eqp,
1024 __in const efx_ev_callbacks_t *eecp,
1028 boolean_t should_abort;
1030 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1032 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1033 if (data >= ((uint32_t)1 << 16)) {
1034 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1035 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1036 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1040 EFSYS_ASSERT(eecp->eec_software != NULL);
1041 should_abort = eecp->eec_software(arg, (uint16_t)data);
1043 return (should_abort);
1048 static __checkReturn boolean_t
1050 __in efx_evq_t *eep,
1051 __in efx_qword_t *eqp,
1052 __in const efx_ev_callbacks_t *eecp,
1055 efx_nic_t *enp = eep->ee_enp;
1057 boolean_t should_abort = B_FALSE;
1059 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1061 if (enp->en_family != EFX_FAMILY_SIENA)
1064 EFSYS_ASSERT(eecp->eec_link_change != NULL);
1065 EFSYS_ASSERT(eecp->eec_exception != NULL);
1066 #if EFSYS_OPT_MON_STATS
1067 EFSYS_ASSERT(eecp->eec_monitor != NULL);
1070 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1072 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1074 case MCDI_EVENT_CODE_BADSSERT:
1075 efx_mcdi_ev_death(enp, EINTR);
1078 case MCDI_EVENT_CODE_CMDDONE:
1079 efx_mcdi_ev_cpl(enp,
1080 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1081 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1082 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1085 case MCDI_EVENT_CODE_LINKCHANGE: {
1086 efx_link_mode_t link_mode;
1088 siena_phy_link_ev(enp, eqp, &link_mode);
1089 should_abort = eecp->eec_link_change(arg, link_mode);
1092 case MCDI_EVENT_CODE_SENSOREVT: {
1093 #if EFSYS_OPT_MON_STATS
1095 efx_mon_stat_value_t value;
1098 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1099 should_abort = eecp->eec_monitor(arg, id, value);
1100 else if (rc == ENOTSUP) {
1101 should_abort = eecp->eec_exception(arg,
1102 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1103 MCDI_EV_FIELD(eqp, DATA));
1105 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1107 should_abort = B_FALSE;
1111 case MCDI_EVENT_CODE_SCHEDERR:
1112 /* Informational only */
1115 case MCDI_EVENT_CODE_REBOOT:
1116 efx_mcdi_ev_death(enp, EIO);
1119 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1120 #if EFSYS_OPT_MAC_STATS
1121 if (eecp->eec_mac_stats != NULL) {
1122 eecp->eec_mac_stats(arg,
1123 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1128 case MCDI_EVENT_CODE_FWALERT: {
1129 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1131 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1132 should_abort = eecp->eec_exception(arg,
1133 EFX_EXCEPTION_FWALERT_SRAM,
1134 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1136 should_abort = eecp->eec_exception(arg,
1137 EFX_EXCEPTION_UNKNOWN_FWALERT,
1138 MCDI_EV_FIELD(eqp, DATA));
1143 EFSYS_PROBE1(mc_pcol_error, int, code);
1148 return (should_abort);
1151 #endif /* EFSYS_OPT_MCDI */
1153 static __checkReturn efx_rc_t
1155 __in efx_evq_t *eep,
1156 __in unsigned int count)
1158 efx_nic_t *enp = eep->ee_enp;
1162 rptr = count & eep->ee_mask;
1164 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1166 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1174 __in efx_evq_t *eep,
1177 efx_nic_t *enp = eep->ee_enp;
1181 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1182 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1184 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1185 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1186 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1188 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1191 static __checkReturn efx_rc_t
1193 __in efx_evq_t *eep,
1194 __in unsigned int us)
1196 efx_nic_t *enp = eep->ee_enp;
1197 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1198 unsigned int locked;
1202 if (us > encp->enc_evq_timer_max_us) {
1207 /* If the value is zero then disable the timer */
1209 EFX_POPULATE_DWORD_2(dword,
1210 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1211 FRF_CZ_TC_TIMER_VAL, 0);
1215 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1218 EFSYS_ASSERT(ticks > 0);
1219 EFX_POPULATE_DWORD_2(dword,
1220 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1221 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1224 locked = (eep->ee_index == 0) ? 1 : 0;
1226 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1227 eep->ee_index, &dword, locked);
1234 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1239 static __checkReturn efx_rc_t
1241 __in efx_nic_t *enp,
1242 __in unsigned int index,
1243 __in efsys_mem_t *esmp,
1247 __in uint32_t flags,
1248 __in efx_evq_t *eep)
1250 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1254 boolean_t notify_mode;
1256 _NOTE(ARGUNUSED(esmp))
1258 #if EFSYS_OPT_RX_SCALE
1259 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1260 index >= EFX_MAXRSS_LEGACY) {
1266 (1U << size) <= encp->enc_evq_max_nevs / encp->enc_evq_min_nevs;
1268 if ((1U << size) == (uint32_t)ndescs / encp->enc_evq_min_nevs)
1270 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1275 /* Set up the handler table */
1276 eep->ee_rx = siena_ev_rx;
1277 eep->ee_tx = siena_ev_tx;
1278 eep->ee_driver = siena_ev_driver;
1279 eep->ee_global = siena_ev_global;
1280 eep->ee_drv_gen = siena_ev_drv_gen;
1282 eep->ee_mcdi = siena_ev_mcdi;
1283 #endif /* EFSYS_OPT_MCDI */
1285 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1286 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1288 /* Set up the new event queue */
1289 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1290 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1291 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1292 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1294 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1295 FRF_AZ_EVQ_BUF_BASE_ID, id);
1297 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1299 /* Set initial interrupt moderation */
1300 siena_ev_qmoderate(eep, us);
1306 #if EFSYS_OPT_RX_SCALE
1309 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1314 #endif /* EFSYS_OPT_SIENA */
1316 #if EFSYS_OPT_QSTATS
1318 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock ac223f7134058b4f */
1319 static const char * const __efx_ev_qstat_name[] = {
1326 "rx_buf_owner_id_err",
1327 "rx_ipv4_hdr_chksum_err",
1328 "rx_tcp_udp_chksum_err",
1332 "rx_mcast_hash_match",
1349 "driver_srm_upd_done",
1350 "driver_tx_descq_fls_done",
1351 "driver_rx_descq_fls_done",
1352 "driver_rx_descq_fls_failed",
1353 "driver_rx_dsc_error",
1354 "driver_tx_dsc_error",
1357 "rx_parse_incomplete",
1359 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1363 __in efx_nic_t *enp,
1364 __in unsigned int id)
1366 _NOTE(ARGUNUSED(enp))
1368 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1369 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1371 return (__efx_ev_qstat_name[id]);
1373 #endif /* EFSYS_OPT_NAMES */
1374 #endif /* EFSYS_OPT_QSTATS */
1378 #if EFSYS_OPT_QSTATS
1380 siena_ev_qstats_update(
1381 __in efx_evq_t *eep,
1382 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1386 for (id = 0; id < EV_NQSTATS; id++) {
1387 efsys_stat_t *essp = &stat[id];
1389 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1390 eep->ee_stat[id] = 0;
1393 #endif /* EFSYS_OPT_QSTATS */
1397 __in efx_evq_t *eep)
1399 efx_nic_t *enp = eep->ee_enp;
1402 /* Purge event queue */
1403 EFX_ZERO_OWORD(oword);
1405 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1406 eep->ee_index, &oword, B_TRUE);
1408 EFX_ZERO_OWORD(oword);
1409 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1414 __in efx_nic_t *enp)
1416 _NOTE(ARGUNUSED(enp))
1419 #endif /* EFSYS_OPT_SIENA */
1421 #if EFX_OPTS_EF10() || EFSYS_OPT_SIENA
1423 #define EFX_EV_BATCH 8
1426 siena_ef10_ev_qpoll(
1427 __in efx_evq_t *eep,
1428 __inout unsigned int *countp,
1429 __in const efx_ev_callbacks_t *eecp,
1432 efx_qword_t ev[EFX_EV_BATCH];
1439 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
1440 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
1441 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
1443 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
1444 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
1445 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
1446 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
1447 FSE_AZ_EV_CODE_DRV_GEN_EV);
1449 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
1450 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
1453 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
1454 EFSYS_ASSERT(countp != NULL);
1455 EFSYS_ASSERT(eecp != NULL);
1459 /* Read up until the end of the batch period */
1460 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1461 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1462 for (total = 0; total < batch; ++total) {
1463 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1465 if (!EFX_EV_PRESENT(ev[total]))
1468 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1469 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1470 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1472 offset += sizeof (efx_qword_t);
1475 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1477 * Prefetch the next batch when we get within PREFETCH_PERIOD
1478 * of a completed batch. If the batch is smaller, then prefetch
1481 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1482 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1483 #endif /* EFSYS_OPT_EV_PREFETCH */
1485 /* Process the batch of events */
1486 for (index = 0; index < total; ++index) {
1487 boolean_t should_abort;
1490 #if EFSYS_OPT_EV_PREFETCH
1491 /* Prefetch if we've now reached the batch period */
1492 if (total == batch &&
1493 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1494 offset = (count + batch) & eep->ee_mask;
1495 offset *= sizeof (efx_qword_t);
1497 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1499 #endif /* EFSYS_OPT_EV_PREFETCH */
1501 EFX_EV_QSTAT_INCR(eep, EV_ALL);
1503 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1505 case FSE_AZ_EV_CODE_RX_EV:
1506 should_abort = eep->ee_rx(eep,
1507 &(ev[index]), eecp, arg);
1509 case FSE_AZ_EV_CODE_TX_EV:
1510 should_abort = eep->ee_tx(eep,
1511 &(ev[index]), eecp, arg);
1513 case FSE_AZ_EV_CODE_DRIVER_EV:
1514 should_abort = eep->ee_driver(eep,
1515 &(ev[index]), eecp, arg);
1517 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1518 should_abort = eep->ee_drv_gen(eep,
1519 &(ev[index]), eecp, arg);
1522 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1523 should_abort = eep->ee_mcdi(eep,
1524 &(ev[index]), eecp, arg);
1527 case FSE_AZ_EV_CODE_GLOBAL_EV:
1528 if (eep->ee_global) {
1529 should_abort = eep->ee_global(eep,
1530 &(ev[index]), eecp, arg);
1533 /* else fallthrough */
1535 EFSYS_PROBE3(bad_event,
1536 unsigned int, eep->ee_index,
1538 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1540 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1542 EFSYS_ASSERT(eecp->eec_exception != NULL);
1543 (void) eecp->eec_exception(arg,
1544 EFX_EXCEPTION_EV_ERROR, code);
1545 should_abort = B_TRUE;
1548 /* Ignore subsequent events */
1552 * Poison batch to ensure the outer
1553 * loop is broken out of.
1555 EFSYS_ASSERT(batch <= EFX_EV_BATCH);
1556 batch += (EFX_EV_BATCH << 1);
1557 EFSYS_ASSERT(total != batch);
1563 * Now that the hardware has most likely moved onto dma'ing
1564 * into the next cache line, clear the processed events. Take
1565 * care to only clear out events that we've processed
1567 EFX_SET_QWORD(ev[0]);
1568 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1569 for (index = 0; index < total; ++index) {
1570 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1571 offset += sizeof (efx_qword_t);
1576 } while (total == batch);
1581 #endif /* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */