drivers/common/sfc_efx/base/efx_ev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9 #if EFSYS_OPT_MON_MCDI
  10 #include "mcdi_mon.h"
  11 #endif
  12
  13 #define EFX_EV_PRESENT(_qword)                                          \
  14         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  15         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  16
  17
  18
  19 #if EFSYS_OPT_SIENA
  20
  21 static  __checkReturn   efx_rc_t
  22 siena_ev_init(
  23         __in            efx_nic_t *enp);
  24
  25 static                  void
  26 siena_ev_fini(
  27         __in            efx_nic_t *enp);
  28
  29 static  __checkReturn   efx_rc_t
  30 siena_ev_qcreate(
  31         __in            efx_nic_t *enp,
  32         __in            unsigned int index,
  33         __in            efsys_mem_t *esmp,
  34         __in            size_t ndescs,
  35         __in            uint32_t id,
  36         __in            uint32_t us,
  37         __in            uint32_t flags,
  38         __in            efx_evq_t *eep);
  39
  40 static                  void
  41 siena_ev_qdestroy(
  42         __in            efx_evq_t *eep);
  43
  44 static  __checkReturn   efx_rc_t
  45 siena_ev_qprime(
  46         __in            efx_evq_t *eep,
  47         __in            unsigned int count);
  48
  49 static                  void
  50 siena_ev_qpost(
  51         __in    efx_evq_t *eep,
  52         __in    uint16_t data);
  53
  54 static  __checkReturn   efx_rc_t
  55 siena_ev_qmoderate(
  56         __in            efx_evq_t *eep,
  57         __in            unsigned int us);
  58
  59 #if EFSYS_OPT_QSTATS
  60 static                  void
  61 siena_ev_qstats_update(
  62         __in                            efx_evq_t *eep,
  63         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
  64
  65 #endif
  66
  67 #endif /* EFSYS_OPT_SIENA */
  68
  69 #if EFX_OPTS_EF10() || EFSYS_OPT_SIENA
  70
  71 static                  void
  72 siena_ef10_ev_qpoll(
  73         __in            efx_evq_t *eep,
  74         __inout         unsigned int *countp,
  75         __in            const efx_ev_callbacks_t *eecp,
  76         __in_opt        void *arg);
  77
  78 #endif  /* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */
  79
  80 #if EFSYS_OPT_SIENA
  81 static const efx_ev_ops_t       __efx_ev_siena_ops = {
  82         siena_ev_init,                          /* eevo_init */
  83         siena_ev_fini,                          /* eevo_fini */
  84         siena_ev_qcreate,                       /* eevo_qcreate */
  85         siena_ev_qdestroy,                      /* eevo_qdestroy */
  86         siena_ev_qprime,                        /* eevo_qprime */
  87         siena_ev_qpost,                         /* eevo_qpost */
  88         siena_ef10_ev_qpoll,                    /* eevo_qpoll */
  89         siena_ev_qmoderate,                     /* eevo_qmoderate */
  90 #if EFSYS_OPT_QSTATS
  91         siena_ev_qstats_update,                 /* eevo_qstats_update */
  92 #endif
  93 };
  94 #endif /* EFSYS_OPT_SIENA */
  95
  96 #if EFX_OPTS_EF10()
  97 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
  98         ef10_ev_init,                           /* eevo_init */
  99         ef10_ev_fini,                           /* eevo_fini */
 100         ef10_ev_qcreate,                        /* eevo_qcreate */
 101         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 102         ef10_ev_qprime,                         /* eevo_qprime */
 103         ef10_ev_qpost,                          /* eevo_qpost */
 104         siena_ef10_ev_qpoll,                    /* eevo_qpoll */
 105         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 106 #if EFSYS_OPT_QSTATS
 107         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 108 #endif
 109 };
 110 #endif /* EFX_OPTS_EF10() */
 111
 112 #if EFSYS_OPT_RIVERHEAD
 113 static const efx_ev_ops_t       __efx_ev_rhead_ops = {
 114         rhead_ev_init,                          /* eevo_init */
 115         rhead_ev_fini,                          /* eevo_fini */
 116         rhead_ev_qcreate,                       /* eevo_qcreate */
 117         rhead_ev_qdestroy,                      /* eevo_qdestroy */
 118         rhead_ev_qprime,                        /* eevo_qprime */
 119         rhead_ev_qpost,                         /* eevo_qpost */
 120         rhead_ev_qpoll,                         /* eevo_qpoll */
 121         rhead_ev_qmoderate,                     /* eevo_qmoderate */
 122 #if EFSYS_OPT_QSTATS
 123         rhead_ev_qstats_update,                 /* eevo_qstats_update */
 124 #endif
 125 };
 126 #endif /* EFSYS_OPT_RIVERHEAD */
 127
 128
 129         __checkReturn   efx_rc_t
 130 efx_ev_init(
 131         __in            efx_nic_t *enp)
 132 {
 133         const efx_ev_ops_t *eevop;
 134         efx_rc_t rc;
 135
 136         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 137         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 138
 139         if (enp->en_mod_flags & EFX_MOD_EV) {
 140                 rc = EINVAL;
 141                 goto fail1;
 142         }
 143
 144         switch (enp->en_family) {
 145 #if EFSYS_OPT_SIENA
 146         case EFX_FAMILY_SIENA:
 147                 eevop = &__efx_ev_siena_ops;
 148                 break;
 149 #endif /* EFSYS_OPT_SIENA */
 150
 151 #if EFSYS_OPT_HUNTINGTON
 152         case EFX_FAMILY_HUNTINGTON:
 153                 eevop = &__efx_ev_ef10_ops;
 154                 break;
 155 #endif /* EFSYS_OPT_HUNTINGTON */
 156
 157 #if EFSYS_OPT_MEDFORD
 158         case EFX_FAMILY_MEDFORD:
 159                 eevop = &__efx_ev_ef10_ops;
 160                 break;
 161 #endif /* EFSYS_OPT_MEDFORD */
 162
 163 #if EFSYS_OPT_MEDFORD2
 164         case EFX_FAMILY_MEDFORD2:
 165                 eevop = &__efx_ev_ef10_ops;
 166                 break;
 167 #endif /* EFSYS_OPT_MEDFORD2 */
 168
 169 #if EFSYS_OPT_RIVERHEAD
 170         case EFX_FAMILY_RIVERHEAD:
 171                 eevop = &__efx_ev_rhead_ops;
 172                 break;
 173 #endif /* EFSYS_OPT_RIVERHEAD */
 174
 175         default:
 176                 EFSYS_ASSERT(0);
 177                 rc = ENOTSUP;
 178                 goto fail1;
 179         }
 180
 181         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 182
 183         if ((rc = eevop->eevo_init(enp)) != 0)
 184                 goto fail2;
 185
 186         enp->en_eevop = eevop;
 187         enp->en_mod_flags |= EFX_MOD_EV;
 188         return (0);
 189
 190 fail2:
 191         EFSYS_PROBE(fail2);
 192
 193 fail1:
 194         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 195
 196         enp->en_eevop = NULL;
 197         enp->en_mod_flags &= ~EFX_MOD_EV;
 198         return (rc);
 199 }
 200
 201         __checkReturn   size_t
 202 efx_evq_size(
 203         __in    const efx_nic_t *enp,
 204         __in    unsigned int ndescs)
 205 {
 206         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 207
 208         return (ndescs * encp->enc_ev_desc_size);
 209 }
 210
 211         __checkReturn   unsigned int
 212 efx_evq_nbufs(
 213         __in    const efx_nic_t *enp,
 214         __in    unsigned int ndescs)
 215 {
 216         return (EFX_DIV_ROUND_UP(efx_evq_size(enp, ndescs), EFX_BUF_SIZE));
 217 }
 218
 219                 void
 220 efx_ev_fini(
 221         __in    efx_nic_t *enp)
 222 {
 223         const efx_ev_ops_t *eevop = enp->en_eevop;
 224
 225         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 226         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 227         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 228         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 229         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 230         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 231
 232         eevop->eevo_fini(enp);
 233
 234         enp->en_eevop = NULL;
 235         enp->en_mod_flags &= ~EFX_MOD_EV;
 236 }
 237
 238
 239         __checkReturn   efx_rc_t
 240 efx_ev_qcreate(
 241         __in            efx_nic_t *enp,
 242         __in            unsigned int index,
 243         __in            efsys_mem_t *esmp,
 244         __in            size_t ndescs,
 245         __in            uint32_t id,
 246         __in            uint32_t us,
 247         __in            uint32_t flags,
 248         __deref_out     efx_evq_t **eepp)
 249 {
 250         const efx_ev_ops_t *eevop = enp->en_eevop;
 251         efx_evq_t *eep;
 252         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 253         efx_rc_t rc;
 254
 255         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 256         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 257
 258         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
 259             enp->en_nic_cfg.enc_evq_limit);
 260
 261         if (index >= encp->enc_evq_limit) {
 262                 rc = EINVAL;
 263                 goto fail1;
 264         }
 265
 266         if (us > encp->enc_evq_timer_max_us) {
 267                 rc = EINVAL;
 268                 goto fail2;
 269         }
 270
 271         switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
 272         case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
 273                 break;
 274         case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
 275                 if (us != 0) {
 276                         rc = EINVAL;
 277                         goto fail3;
 278                 }
 279                 break;
 280         default:
 281                 rc = EINVAL;
 282                 goto fail4;
 283         }
 284
 285         EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
 286         EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
 287
 288         if (!ISP2(ndescs) ||
 289             ndescs < encp->enc_evq_min_nevs ||
 290             ndescs > encp->enc_evq_max_nevs) {
 291                 rc = EINVAL;
 292                 goto fail5;
 293         }
 294
 295         /* Allocate an EVQ object */
 296         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 297         if (eep == NULL) {
 298                 rc = ENOMEM;
 299                 goto fail6;
 300         }
 301
 302         eep->ee_magic = EFX_EVQ_MAGIC;
 303         eep->ee_enp = enp;
 304         eep->ee_index = index;
 305         eep->ee_mask = ndescs - 1;
 306         eep->ee_flags = flags;
 307         eep->ee_esmp = esmp;
 308
 309         /*
 310          * Set outputs before the queue is created because interrupts may be
 311          * raised for events immediately after the queue is created, before the
 312          * function call below returns. See bug58606.
 313          *
 314          * The eepp pointer passed in by the client must therefore point to data
 315          * shared with the client's event processing context.
 316          */
 317         enp->en_ev_qcount++;
 318         *eepp = eep;
 319
 320         if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
 321             eep)) != 0)
 322                 goto fail7;
 323
 324         return (0);
 325
 326 fail7:
 327         EFSYS_PROBE(fail7);
 328
 329         *eepp = NULL;
 330         enp->en_ev_qcount--;
 331         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 332 fail6:
 333         EFSYS_PROBE(fail6);
 334 fail5:
 335         EFSYS_PROBE(fail5);
 336 fail4:
 337         EFSYS_PROBE(fail4);
 338 fail3:
 339         EFSYS_PROBE(fail3);
 340 fail2:
 341         EFSYS_PROBE(fail2);
 342 fail1:
 343         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 344         return (rc);
 345 }
 346
 347                 void
 348 efx_ev_qdestroy(
 349         __in    efx_evq_t *eep)
 350 {
 351         efx_nic_t *enp = eep->ee_enp;
 352         const efx_ev_ops_t *eevop = enp->en_eevop;
 353
 354         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 355
 356         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 357         --enp->en_ev_qcount;
 358
 359         eevop->eevo_qdestroy(eep);
 360
 361         /* Free the EVQ object */
 362         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 363 }
 364
 365         __checkReturn   efx_rc_t
 366 efx_ev_qprime(
 367         __in            efx_evq_t *eep,
 368         __in            unsigned int count)
 369 {
 370         efx_nic_t *enp = eep->ee_enp;
 371         const efx_ev_ops_t *eevop = enp->en_eevop;
 372         efx_rc_t rc;
 373
 374         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 375
 376         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 377                 rc = EINVAL;
 378                 goto fail1;
 379         }
 380
 381         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 382                 goto fail2;
 383
 384         return (0);
 385
 386 fail2:
 387         EFSYS_PROBE(fail2);
 388 fail1:
 389         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 390         return (rc);
 391 }
 392
 393         __checkReturn   boolean_t
 394 efx_ev_qpending(
 395         __in            efx_evq_t *eep,
 396         __in            unsigned int count)
 397 {
 398         size_t offset;
 399         efx_qword_t qword;
 400
 401         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 402
 403         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 404         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 405
 406         return (EFX_EV_PRESENT(qword));
 407 }
 408
 409 #if EFSYS_OPT_EV_PREFETCH
 410
 411                         void
 412 efx_ev_qprefetch(
 413         __in            efx_evq_t *eep,
 414         __in            unsigned int count)
 415 {
 416         unsigned int offset;
 417
 418         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 419
 420         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 421         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 422 }
 423
 424 #endif  /* EFSYS_OPT_EV_PREFETCH */
 425
 426                         void
 427 efx_ev_qpoll(
 428         __in            efx_evq_t *eep,
 429         __inout         unsigned int *countp,
 430         __in            const efx_ev_callbacks_t *eecp,
 431         __in_opt        void *arg)
 432 {
 433         efx_nic_t *enp = eep->ee_enp;
 434         const efx_ev_ops_t *eevop = enp->en_eevop;
 435
 436         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 437
 438         EFSYS_ASSERT(eevop != NULL &&
 439             eevop->eevo_qpoll != NULL);
 440
 441         eevop->eevo_qpoll(eep, countp, eecp, arg);
 442 }
 443
 444                         void
 445 efx_ev_qpost(
 446         __in    efx_evq_t *eep,
 447         __in    uint16_t data)
 448 {
 449         efx_nic_t *enp = eep->ee_enp;
 450         const efx_ev_ops_t *eevop = enp->en_eevop;
 451
 452         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 453
 454         EFSYS_ASSERT(eevop != NULL &&
 455             eevop->eevo_qpost != NULL);
 456
 457         eevop->eevo_qpost(eep, data);
 458 }
 459
 460         __checkReturn   efx_rc_t
 461 efx_ev_usecs_to_ticks(
 462         __in            efx_nic_t *enp,
 463         __in            unsigned int us,
 464         __out           unsigned int *ticksp)
 465 {
 466         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 467         unsigned int ticks;
 468         efx_rc_t rc;
 469
 470         if (encp->enc_evq_timer_quantum_ns == 0) {
 471                 rc = ENOTSUP;
 472                 goto fail1;
 473         }
 474
 475         /* Convert microseconds to a timer tick count */
 476         if (us == 0)
 477                 ticks = 0;
 478         else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
 479                 ticks = 1;      /* Never round down to zero */
 480         else
 481                 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
 482
 483         *ticksp = ticks;
 484         return (0);
 485
 486 fail1:
 487         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 488         return (rc);
 489 }
 490
 491         __checkReturn   efx_rc_t
 492 efx_ev_qmoderate(
 493         __in            efx_evq_t *eep,
 494         __in            unsigned int us)
 495 {
 496         efx_nic_t *enp = eep->ee_enp;
 497         const efx_ev_ops_t *eevop = enp->en_eevop;
 498         efx_rc_t rc;
 499
 500         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 501
 502         if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
 503             EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
 504                 rc = EINVAL;
 505                 goto fail1;
 506         }
 507
 508         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 509                 goto fail2;
 510
 511         return (0);
 512
 513 fail2:
 514         EFSYS_PROBE(fail2);
 515 fail1:
 516         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 517         return (rc);
 518 }
 519
 520 #if EFSYS_OPT_QSTATS
 521                                         void
 522 efx_ev_qstats_update(
 523         __in                            efx_evq_t *eep,
 524         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 525
 526 {       efx_nic_t *enp = eep->ee_enp;
 527         const efx_ev_ops_t *eevop = enp->en_eevop;
 528
 529         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 530
 531         eevop->eevo_qstats_update(eep, stat);
 532 }
 533
 534 #endif  /* EFSYS_OPT_QSTATS */
 535
 536 #if EFSYS_OPT_SIENA
 537
 538 static  __checkReturn   efx_rc_t
 539 siena_ev_init(
 540         __in            efx_nic_t *enp)
 541 {
 542         efx_oword_t oword;
 543
 544         /*
 545          * Program the event queue for receive and transmit queue
 546          * flush events.
 547          */
 548         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 549         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 550         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 551
 552         return (0);
 553
 554 }
 555
 556 static  __checkReturn   boolean_t
 557 siena_ev_rx_not_ok(
 558         __in            efx_evq_t *eep,
 559         __in            efx_qword_t *eqp,
 560         __in            uint32_t label,
 561         __in            uint32_t id,
 562         __inout         uint16_t *flagsp)
 563 {
 564         boolean_t ignore = B_FALSE;
 565
 566         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 567                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 568                 EFSYS_PROBE(tobe_disc);
 569                 /*
 570                  * Assume this is a unicast address mismatch, unless below
 571                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 572                  * EV_RX_PAUSE_FRM_ERR is set.
 573                  */
 574                 (*flagsp) |= EFX_ADDR_MISMATCH;
 575         }
 576
 577         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 578                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 579                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 580                 (*flagsp) |= EFX_DISCARD;
 581
 582 #if EFSYS_OPT_RX_SCATTER
 583                 /*
 584                  * Lookout for payload queue ran dry errors and ignore them.
 585                  *
 586                  * Sadly for the header/data split cases, the descriptor
 587                  * pointer in this event refers to the header queue and
 588                  * therefore cannot be easily detected as duplicate.
 589                  * So we drop these and rely on the receive processing seeing
 590                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
 591                  * the partially received packet.
 592                  */
 593                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
 594                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
 595                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
 596                         ignore = B_TRUE;
 597 #endif  /* EFSYS_OPT_RX_SCATTER */
 598         }
 599
 600         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 601                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 602                 EFSYS_PROBE(crc_err);
 603                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 604                 (*flagsp) |= EFX_DISCARD;
 605         }
 606
 607         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 608                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 609                 EFSYS_PROBE(pause_frm_err);
 610                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 611                 (*flagsp) |= EFX_DISCARD;
 612         }
 613
 614         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 615                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 616                 EFSYS_PROBE(owner_id_err);
 617                 (*flagsp) |= EFX_DISCARD;
 618         }
 619
 620         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 621                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 622                 EFSYS_PROBE(ipv4_err);
 623                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 624         }
 625
 626         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 627                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 628                 EFSYS_PROBE(udp_chk_err);
 629                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 630         }
 631
 632         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 633                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 634
 635                 /*
 636                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 637                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 638                  * condition.
 639                  */
 640                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 641         }
 642
 643         return (ignore);
 644 }
 645
 646 static  __checkReturn   boolean_t
 647 siena_ev_rx(
 648         __in            efx_evq_t *eep,
 649         __in            efx_qword_t *eqp,
 650         __in            const efx_ev_callbacks_t *eecp,
 651         __in_opt        void *arg)
 652 {
 653         uint32_t id;
 654         uint32_t size;
 655         uint32_t label;
 656         boolean_t ok;
 657 #if EFSYS_OPT_RX_SCATTER
 658         boolean_t sop;
 659         boolean_t jumbo_cont;
 660 #endif  /* EFSYS_OPT_RX_SCATTER */
 661         uint32_t hdr_type;
 662         boolean_t is_v6;
 663         uint16_t flags;
 664         boolean_t ignore;
 665         boolean_t should_abort;
 666
 667         EFX_EV_QSTAT_INCR(eep, EV_RX);
 668
 669         /* Basic packet information */
 670         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 671         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 672         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 673         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 674
 675 #if EFSYS_OPT_RX_SCATTER
 676         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
 677         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
 678 #endif  /* EFSYS_OPT_RX_SCATTER */
 679
 680         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 681
 682         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 683
 684         /*
 685          * If packet is marked as OK and packet type is TCP/IP or
 686          * UDP/IP or other IP, then we can rely on the hardware checksums.
 687          */
 688         switch (hdr_type) {
 689         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 690                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 691                 if (is_v6) {
 692                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 693                         flags |= EFX_PKT_IPV6;
 694                 } else {
 695                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 696                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 697                 }
 698                 break;
 699
 700         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 701                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 702                 if (is_v6) {
 703                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 704                         flags |= EFX_PKT_IPV6;
 705                 } else {
 706                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 707                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 708                 }
 709                 break;
 710
 711         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 712                 if (is_v6) {
 713                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 714                         flags = EFX_PKT_IPV6;
 715                 } else {
 716                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 717                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 718                 }
 719                 break;
 720
 721         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 722                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 723                 flags = 0;
 724                 break;
 725
 726         default:
 727                 EFSYS_ASSERT(B_FALSE);
 728                 flags = 0;
 729                 break;
 730         }
 731
 732 #if EFSYS_OPT_RX_SCATTER
 733         /* Report scatter and header/lookahead split buffer flags */
 734         if (sop)
 735                 flags |= EFX_PKT_START;
 736         if (jumbo_cont)
 737                 flags |= EFX_PKT_CONT;
 738 #endif  /* EFSYS_OPT_RX_SCATTER */
 739
 740         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 741         if (!ok) {
 742                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 743                 if (ignore) {
 744                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 745                             uint32_t, size, uint16_t, flags);
 746
 747                         return (B_FALSE);
 748                 }
 749         }
 750
 751         /* If we're not discarding the packet then it is ok */
 752         if (~flags & EFX_DISCARD)
 753                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 754
 755         /* Detect multicast packets that didn't match the filter */
 756         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 757                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 758
 759                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 760                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 761                 } else {
 762                         EFSYS_PROBE(mcast_mismatch);
 763                         flags |= EFX_ADDR_MISMATCH;
 764                 }
 765         } else {
 766                 flags |= EFX_PKT_UNICAST;
 767         }
 768
 769         /*
 770          * The packet parser in Siena can abort parsing packets under
 771          * certain error conditions, setting the PKT_NOT_PARSED bit
 772          * (which clears PKT_OK). If this is set, then don't trust
 773          * the PKT_TYPE field.
 774          */
 775         if (!ok) {
 776                 uint32_t parse_err;
 777
 778                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 779                 if (parse_err != 0)
 780                         flags |= EFX_CHECK_VLAN;
 781         }
 782
 783         if (~flags & EFX_CHECK_VLAN) {
 784                 uint32_t pkt_type;
 785
 786                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 787                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 788                         flags |= EFX_PKT_VLAN_TAGGED;
 789         }
 790
 791         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 792             uint32_t, size, uint16_t, flags);
 793
 794         EFSYS_ASSERT(eecp->eec_rx != NULL);
 795         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 796
 797         return (should_abort);
 798 }
 799
 800 static  __checkReturn   boolean_t
 801 siena_ev_tx(
 802         __in            efx_evq_t *eep,
 803         __in            efx_qword_t *eqp,
 804         __in            const efx_ev_callbacks_t *eecp,
 805         __in_opt        void *arg)
 806 {
 807         uint32_t id;
 808         uint32_t label;
 809         boolean_t should_abort;
 810
 811         EFX_EV_QSTAT_INCR(eep, EV_TX);
 812
 813         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 814             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 815             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 816             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 817
 818                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 819                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 820
 821                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 822
 823                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 824                 should_abort = eecp->eec_tx(arg, label, id);
 825
 826                 return (should_abort);
 827         }
 828
 829         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 830                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 831                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 832                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 833
 834         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 835                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 836
 837         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 838                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 839
 840         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 841                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 842
 843         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 844         return (B_FALSE);
 845 }
 846
 847 static  __checkReturn   boolean_t
 848 siena_ev_global(
 849         __in            efx_evq_t *eep,
 850         __in            efx_qword_t *eqp,
 851         __in            const efx_ev_callbacks_t *eecp,
 852         __in_opt        void *arg)
 853 {
 854         _NOTE(ARGUNUSED(eqp, eecp, arg))
 855
 856         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 857
 858         return (B_FALSE);
 859 }
 860
 861 static  __checkReturn   boolean_t
 862 siena_ev_driver(
 863         __in            efx_evq_t *eep,
 864         __in            efx_qword_t *eqp,
 865         __in            const efx_ev_callbacks_t *eecp,
 866         __in_opt        void *arg)
 867 {
 868         boolean_t should_abort;
 869
 870         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 871         should_abort = B_FALSE;
 872
 873         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 874         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 875                 uint32_t txq_index;
 876
 877                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 878
 879                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 880
 881                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 882
 883                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 884                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 885
 886                 break;
 887         }
 888         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 889                 uint32_t rxq_index;
 890                 uint32_t failed;
 891
 892                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 893                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 894
 895                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 896                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 897
 898                 if (failed) {
 899                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 900
 901                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 902
 903                         should_abort = eecp->eec_rxq_flush_failed(arg,
 904                                                                     rxq_index);
 905                 } else {
 906                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 907
 908                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 909
 910                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
 911                 }
 912
 913                 break;
 914         }
 915         case FSE_AZ_EVQ_INIT_DONE_EV:
 916                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
 917                 should_abort = eecp->eec_initialized(arg);
 918
 919                 break;
 920
 921         case FSE_AZ_EVQ_NOT_EN_EV:
 922                 EFSYS_PROBE(evq_not_en);
 923                 break;
 924
 925         case FSE_AZ_SRM_UPD_DONE_EV: {
 926                 uint32_t code;
 927
 928                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
 929
 930                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 931
 932                 EFSYS_ASSERT(eecp->eec_sram != NULL);
 933                 should_abort = eecp->eec_sram(arg, code);
 934
 935                 break;
 936         }
 937         case FSE_AZ_WAKE_UP_EV: {
 938                 uint32_t id;
 939
 940                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 941
 942                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
 943                 should_abort = eecp->eec_wake_up(arg, id);
 944
 945                 break;
 946         }
 947         case FSE_AZ_TX_PKT_NON_TCP_UDP:
 948                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
 949                 break;
 950
 951         case FSE_AZ_TIMER_EV: {
 952                 uint32_t id;
 953
 954                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 955
 956                 EFSYS_ASSERT(eecp->eec_timer != NULL);
 957                 should_abort = eecp->eec_timer(arg, id);
 958
 959                 break;
 960         }
 961         case FSE_AZ_RX_DSC_ERROR_EV:
 962                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
 963
 964                 EFSYS_PROBE(rx_dsc_error);
 965
 966                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 967                 should_abort = eecp->eec_exception(arg,
 968                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
 969
 970                 break;
 971
 972         case FSE_AZ_TX_DSC_ERROR_EV:
 973                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
 974
 975                 EFSYS_PROBE(tx_dsc_error);
 976
 977                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 978                 should_abort = eecp->eec_exception(arg,
 979                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
 980
 981                 break;
 982
 983         default:
 984                 break;
 985         }
 986
 987         return (should_abort);
 988 }
 989
 990 static  __checkReturn   boolean_t
 991 siena_ev_drv_gen(
 992         __in            efx_evq_t *eep,
 993         __in            efx_qword_t *eqp,
 994         __in            const efx_ev_callbacks_t *eecp,
 995         __in_opt        void *arg)
 996 {
 997         uint32_t data;
 998         boolean_t should_abort;
 999
1000         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1001
1002         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1003         if (data >= ((uint32_t)1 << 16)) {
1004                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1005                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1006                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1007                 return (B_TRUE);
1008         }
1009
1010         EFSYS_ASSERT(eecp->eec_software != NULL);
1011         should_abort = eecp->eec_software(arg, (uint16_t)data);
1012
1013         return (should_abort);
1014 }
1015
1016 #if EFSYS_OPT_MCDI
1017
1018 static  __checkReturn   boolean_t
1019 siena_ev_mcdi(
1020         __in            efx_evq_t *eep,
1021         __in            efx_qword_t *eqp,
1022         __in            const efx_ev_callbacks_t *eecp,
1023         __in_opt        void *arg)
1024 {
1025         efx_nic_t *enp = eep->ee_enp;
1026         unsigned int code;
1027         boolean_t should_abort = B_FALSE;
1028
1029         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1030
1031         if (enp->en_family != EFX_FAMILY_SIENA)
1032                 goto out;
1033
1034         EFSYS_ASSERT(eecp->eec_link_change != NULL);
1035         EFSYS_ASSERT(eecp->eec_exception != NULL);
1036 #if EFSYS_OPT_MON_STATS
1037         EFSYS_ASSERT(eecp->eec_monitor != NULL);
1038 #endif
1039
1040         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1041
1042         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1043         switch (code) {
1044         case MCDI_EVENT_CODE_BADSSERT:
1045                 efx_mcdi_ev_death(enp, EINTR);
1046                 break;
1047
1048         case MCDI_EVENT_CODE_CMDDONE:
1049                 efx_mcdi_ev_cpl(enp,
1050                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1051                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1052                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1053                 break;
1054
1055         case MCDI_EVENT_CODE_LINKCHANGE: {
1056                 efx_link_mode_t link_mode;
1057
1058                 siena_phy_link_ev(enp, eqp, &link_mode);
1059                 should_abort = eecp->eec_link_change(arg, link_mode);
1060                 break;
1061         }
1062         case MCDI_EVENT_CODE_SENSOREVT: {
1063 #if EFSYS_OPT_MON_STATS
1064                 efx_mon_stat_t id;
1065                 efx_mon_stat_value_t value;
1066                 efx_rc_t rc;
1067
1068                 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1069                         should_abort = eecp->eec_monitor(arg, id, value);
1070                 else if (rc == ENOTSUP) {
1071                         should_abort = eecp->eec_exception(arg,
1072                                 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1073                                 MCDI_EV_FIELD(eqp, DATA));
1074                 } else
1075                         EFSYS_ASSERT(rc == ENODEV);     /* Wrong port */
1076 #else
1077                 should_abort = B_FALSE;
1078 #endif
1079                 break;
1080         }
1081         case MCDI_EVENT_CODE_SCHEDERR:
1082                 /* Informational only */
1083                 break;
1084
1085         case MCDI_EVENT_CODE_REBOOT:
1086                 efx_mcdi_ev_death(enp, EIO);
1087                 break;
1088
1089         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1090 #if EFSYS_OPT_MAC_STATS
1091                 if (eecp->eec_mac_stats != NULL) {
1092                         eecp->eec_mac_stats(arg,
1093                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1094                 }
1095 #endif
1096                 break;
1097
1098         case MCDI_EVENT_CODE_FWALERT: {
1099                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1100
1101                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1102                         should_abort = eecp->eec_exception(arg,
1103                                 EFX_EXCEPTION_FWALERT_SRAM,
1104                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1105                 else
1106                         should_abort = eecp->eec_exception(arg,
1107                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1108                                 MCDI_EV_FIELD(eqp, DATA));
1109                 break;
1110         }
1111
1112         default:
1113                 EFSYS_PROBE1(mc_pcol_error, int, code);
1114                 break;
1115         }
1116
1117 out:
1118         return (should_abort);
1119 }
1120
1121 #endif  /* EFSYS_OPT_MCDI */
1122
1123 static  __checkReturn   efx_rc_t
1124 siena_ev_qprime(
1125         __in            efx_evq_t *eep,
1126         __in            unsigned int count)
1127 {
1128         efx_nic_t *enp = eep->ee_enp;
1129         uint32_t rptr;
1130         efx_dword_t dword;
1131
1132         rptr = count & eep->ee_mask;
1133
1134         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1135
1136         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1137                             &dword, B_FALSE);
1138
1139         return (0);
1140 }
1141
1142 static          void
1143 siena_ev_qpost(
1144         __in    efx_evq_t *eep,
1145         __in    uint16_t data)
1146 {
1147         efx_nic_t *enp = eep->ee_enp;
1148         efx_qword_t ev;
1149         efx_oword_t oword;
1150
1151         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1152             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1153
1154         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1155             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1156             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1157
1158         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1159 }
1160
1161 static  __checkReturn   efx_rc_t
1162 siena_ev_qmoderate(
1163         __in            efx_evq_t *eep,
1164         __in            unsigned int us)
1165 {
1166         efx_nic_t *enp = eep->ee_enp;
1167         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1168         unsigned int locked;
1169         efx_dword_t dword;
1170         efx_rc_t rc;
1171
1172         if (us > encp->enc_evq_timer_max_us) {
1173                 rc = EINVAL;
1174                 goto fail1;
1175         }
1176
1177         /* If the value is zero then disable the timer */
1178         if (us == 0) {
1179                 EFX_POPULATE_DWORD_2(dword,
1180                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1181                     FRF_CZ_TC_TIMER_VAL, 0);
1182         } else {
1183                 unsigned int ticks;
1184
1185                 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1186                         goto fail2;
1187
1188                 EFSYS_ASSERT(ticks > 0);
1189                 EFX_POPULATE_DWORD_2(dword,
1190                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1191                     FRF_CZ_TC_TIMER_VAL, ticks - 1);
1192         }
1193
1194         locked = (eep->ee_index == 0) ? 1 : 0;
1195
1196         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1197             eep->ee_index, &dword, locked);
1198
1199         return (0);
1200
1201 fail2:
1202         EFSYS_PROBE(fail2);
1203 fail1:
1204         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1205
1206         return (rc);
1207 }
1208
1209 static  __checkReturn   efx_rc_t
1210 siena_ev_qcreate(
1211         __in            efx_nic_t *enp,
1212         __in            unsigned int index,
1213         __in            efsys_mem_t *esmp,
1214         __in            size_t ndescs,
1215         __in            uint32_t id,
1216         __in            uint32_t us,
1217         __in            uint32_t flags,
1218         __in            efx_evq_t *eep)
1219 {
1220         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1221         uint32_t size;
1222         efx_oword_t oword;
1223         efx_rc_t rc;
1224         boolean_t notify_mode;
1225
1226         _NOTE(ARGUNUSED(esmp))
1227
1228 #if EFSYS_OPT_RX_SCALE
1229         if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1230             index >= EFX_MAXRSS_LEGACY) {
1231                 rc = EINVAL;
1232                 goto fail1;
1233         }
1234 #endif
1235         for (size = 0;
1236             (1U << size) <= encp->enc_evq_max_nevs / encp->enc_evq_min_nevs;
1237             size++)
1238                 if ((1U << size) == (uint32_t)ndescs / encp->enc_evq_min_nevs)
1239                         break;
1240         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1241                 rc = EINVAL;
1242                 goto fail2;
1243         }
1244
1245         /* Set up the handler table */
1246         eep->ee_rx      = siena_ev_rx;
1247         eep->ee_tx      = siena_ev_tx;
1248         eep->ee_driver  = siena_ev_driver;
1249         eep->ee_global  = siena_ev_global;
1250         eep->ee_drv_gen = siena_ev_drv_gen;
1251 #if EFSYS_OPT_MCDI
1252         eep->ee_mcdi    = siena_ev_mcdi;
1253 #endif  /* EFSYS_OPT_MCDI */
1254
1255         notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1256             EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1257
1258         /* Set up the new event queue */
1259         EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1260             FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1261             FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1262         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1263
1264         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1265             FRF_AZ_EVQ_BUF_BASE_ID, id);
1266
1267         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1268
1269         /* Set initial interrupt moderation */
1270         siena_ev_qmoderate(eep, us);
1271
1272         return (0);
1273
1274 fail2:
1275         EFSYS_PROBE(fail2);
1276 #if EFSYS_OPT_RX_SCALE
1277 fail1:
1278 #endif
1279         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1280
1281         return (rc);
1282 }
1283
1284 #endif /* EFSYS_OPT_SIENA */
1285
1286 #if EFSYS_OPT_QSTATS
1287 #if EFSYS_OPT_NAMES
1288 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock ac223f7134058b4f */
1289 static const char * const __efx_ev_qstat_name[] = {
1290         "all",
1291         "rx",
1292         "rx_ok",
1293         "rx_frm_trunc",
1294         "rx_tobe_disc",
1295         "rx_pause_frm_err",
1296         "rx_buf_owner_id_err",
1297         "rx_ipv4_hdr_chksum_err",
1298         "rx_tcp_udp_chksum_err",
1299         "rx_eth_crc_err",
1300         "rx_ip_frag_err",
1301         "rx_mcast_pkt",
1302         "rx_mcast_hash_match",
1303         "rx_tcp_ipv4",
1304         "rx_tcp_ipv6",
1305         "rx_udp_ipv4",
1306         "rx_udp_ipv6",
1307         "rx_other_ipv4",
1308         "rx_other_ipv6",
1309         "rx_non_ip",
1310         "rx_batch",
1311         "tx",
1312         "tx_wq_ff_full",
1313         "tx_pkt_err",
1314         "tx_pkt_too_big",
1315         "tx_unexpected",
1316         "global",
1317         "global_mnt",
1318         "driver",
1319         "driver_srm_upd_done",
1320         "driver_tx_descq_fls_done",
1321         "driver_rx_descq_fls_done",
1322         "driver_rx_descq_fls_failed",
1323         "driver_rx_dsc_error",
1324         "driver_tx_dsc_error",
1325         "drv_gen",
1326         "mcdi_response",
1327         "rx_parse_incomplete",
1328 };
1329 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1330
1331                 const char *
1332 efx_ev_qstat_name(
1333         __in    efx_nic_t *enp,
1334         __in    unsigned int id)
1335 {
1336         _NOTE(ARGUNUSED(enp))
1337
1338         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1339         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1340
1341         return (__efx_ev_qstat_name[id]);
1342 }
1343 #endif  /* EFSYS_OPT_NAMES */
1344 #endif  /* EFSYS_OPT_QSTATS */
1345
1346 #if EFSYS_OPT_SIENA
1347
1348 #if EFSYS_OPT_QSTATS
1349 static                                  void
1350 siena_ev_qstats_update(
1351         __in                            efx_evq_t *eep,
1352         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1353 {
1354         unsigned int id;
1355
1356         for (id = 0; id < EV_NQSTATS; id++) {
1357                 efsys_stat_t *essp = &stat[id];
1358
1359                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1360                 eep->ee_stat[id] = 0;
1361         }
1362 }
1363 #endif  /* EFSYS_OPT_QSTATS */
1364
1365 static          void
1366 siena_ev_qdestroy(
1367         __in    efx_evq_t *eep)
1368 {
1369         efx_nic_t *enp = eep->ee_enp;
1370         efx_oword_t oword;
1371
1372         /* Purge event queue */
1373         EFX_ZERO_OWORD(oword);
1374
1375         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1376             eep->ee_index, &oword, B_TRUE);
1377
1378         EFX_ZERO_OWORD(oword);
1379         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1380 }
1381
1382 static          void
1383 siena_ev_fini(
1384         __in    efx_nic_t *enp)
1385 {
1386         _NOTE(ARGUNUSED(enp))
1387 }
1388
1389 #endif /* EFSYS_OPT_SIENA */
1390
1391 #if EFX_OPTS_EF10() || EFSYS_OPT_SIENA
1392
1393 #define EFX_EV_BATCH    8
1394
1395 static                  void
1396 siena_ef10_ev_qpoll(
1397         __in            efx_evq_t *eep,
1398         __inout         unsigned int *countp,
1399         __in            const efx_ev_callbacks_t *eecp,
1400         __in_opt        void *arg)
1401 {
1402         efx_qword_t ev[EFX_EV_BATCH];
1403         unsigned int batch;
1404         unsigned int total;
1405         unsigned int count;
1406         unsigned int index;
1407         size_t offset;
1408
1409         /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
1410         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
1411         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
1412
1413         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
1414         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
1415         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
1416         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
1417             FSE_AZ_EV_CODE_DRV_GEN_EV);
1418 #if EFSYS_OPT_MCDI
1419         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
1420             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
1421 #endif
1422
1423         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
1424         EFSYS_ASSERT(countp != NULL);
1425         EFSYS_ASSERT(eecp != NULL);
1426
1427         count = *countp;
1428         do {
1429                 /* Read up until the end of the batch period */
1430                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1431                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1432                 for (total = 0; total < batch; ++total) {
1433                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1434
1435                         if (!EFX_EV_PRESENT(ev[total]))
1436                                 break;
1437
1438                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1439                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1440                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1441
1442                         offset += sizeof (efx_qword_t);
1443                 }
1444
1445 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1446                 /*
1447                  * Prefetch the next batch when we get within PREFETCH_PERIOD
1448                  * of a completed batch. If the batch is smaller, then prefetch
1449                  * immediately.
1450                  */
1451                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1452                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1453 #endif  /* EFSYS_OPT_EV_PREFETCH */
1454
1455                 /* Process the batch of events */
1456                 for (index = 0; index < total; ++index) {
1457                         boolean_t should_abort;
1458                         uint32_t code;
1459
1460 #if EFSYS_OPT_EV_PREFETCH
1461                         /* Prefetch if we've now reached the batch period */
1462                         if (total == batch &&
1463                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1464                                 offset = (count + batch) & eep->ee_mask;
1465                                 offset *= sizeof (efx_qword_t);
1466
1467                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1468                         }
1469 #endif  /* EFSYS_OPT_EV_PREFETCH */
1470
1471                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
1472
1473                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1474                         switch (code) {
1475                         case FSE_AZ_EV_CODE_RX_EV:
1476                                 should_abort = eep->ee_rx(eep,
1477                                     &(ev[index]), eecp, arg);
1478                                 break;
1479                         case FSE_AZ_EV_CODE_TX_EV:
1480                                 should_abort = eep->ee_tx(eep,
1481                                     &(ev[index]), eecp, arg);
1482                                 break;
1483                         case FSE_AZ_EV_CODE_DRIVER_EV:
1484                                 should_abort = eep->ee_driver(eep,
1485                                     &(ev[index]), eecp, arg);
1486                                 break;
1487                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
1488                                 should_abort = eep->ee_drv_gen(eep,
1489                                     &(ev[index]), eecp, arg);
1490                                 break;
1491 #if EFSYS_OPT_MCDI
1492                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1493                                 should_abort = eep->ee_mcdi(eep,
1494                                     &(ev[index]), eecp, arg);
1495                                 break;
1496 #endif
1497                         case FSE_AZ_EV_CODE_GLOBAL_EV:
1498                                 if (eep->ee_global) {
1499                                         should_abort = eep->ee_global(eep,
1500                                             &(ev[index]), eecp, arg);
1501                                         break;
1502                                 }
1503                                 /* else fallthrough */
1504                         default:
1505                                 EFSYS_PROBE3(bad_event,
1506                                     unsigned int, eep->ee_index,
1507                                     uint32_t,
1508                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1509                                     uint32_t,
1510                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1511
1512                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1513                                 (void) eecp->eec_exception(arg,
1514                                         EFX_EXCEPTION_EV_ERROR, code);
1515                                 should_abort = B_TRUE;
1516                         }
1517                         if (should_abort) {
1518                                 /* Ignore subsequent events */
1519                                 total = index + 1;
1520
1521                                 /*
1522                                  * Poison batch to ensure the outer
1523                                  * loop is broken out of.
1524                                  */
1525                                 EFSYS_ASSERT(batch <= EFX_EV_BATCH);
1526                                 batch += (EFX_EV_BATCH << 1);
1527                                 EFSYS_ASSERT(total != batch);
1528                                 break;
1529                         }
1530                 }
1531
1532                 /*
1533                  * Now that the hardware has most likely moved onto dma'ing
1534                  * into the next cache line, clear the processed events. Take
1535                  * care to only clear out events that we've processed
1536                  */
1537                 EFX_SET_QWORD(ev[0]);
1538                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1539                 for (index = 0; index < total; ++index) {
1540                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1541                         offset += sizeof (efx_qword_t);
1542                 }
1543
1544                 count += total;
1545
1546         } while (total == batch);
1547
1548         *countp = count;
1549 }
1550
1551 #endif  /* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */