1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
15 static __checkReturn efx_rc_t
23 static __checkReturn efx_rc_t
27 static __checkReturn efx_rc_t
30 __inout efx_filter_spec_t *spec,
31 __in efx_filter_replacement_policy_t policy);
33 static __checkReturn efx_rc_t
36 __inout efx_filter_spec_t *spec);
38 static __checkReturn efx_rc_t
39 siena_filter_supported_filters(
41 __out_ecount(buffer_length) uint32_t *buffer,
42 __in size_t buffer_length,
43 __out size_t *list_lengthp);
45 #endif /* EFSYS_OPT_SIENA */
48 static const efx_filter_ops_t __efx_filter_siena_ops = {
49 siena_filter_init, /* efo_init */
50 siena_filter_fini, /* efo_fini */
51 siena_filter_restore, /* efo_restore */
52 siena_filter_add, /* efo_add */
53 siena_filter_delete, /* efo_delete */
54 siena_filter_supported_filters, /* efo_supported_filters */
55 NULL, /* efo_reconfigure */
57 #endif /* EFSYS_OPT_SIENA */
60 static const efx_filter_ops_t __efx_filter_ef10_ops = {
61 ef10_filter_init, /* efo_init */
62 ef10_filter_fini, /* efo_fini */
63 ef10_filter_restore, /* efo_restore */
64 ef10_filter_add, /* efo_add */
65 ef10_filter_delete, /* efo_delete */
66 ef10_filter_supported_filters, /* efo_supported_filters */
67 ef10_filter_reconfigure, /* efo_reconfigure */
69 #endif /* EFX_OPTS_EF10() */
71 #if EFSYS_OPT_RIVERHEAD
72 static const efx_filter_ops_t __efx_filter_rhead_ops = {
73 ef10_filter_init, /* efo_init */
74 ef10_filter_fini, /* efo_fini */
75 ef10_filter_restore, /* efo_restore */
76 ef10_filter_add, /* efo_add */
77 ef10_filter_delete, /* efo_delete */
78 ef10_filter_supported_filters, /* efo_supported_filters */
79 ef10_filter_reconfigure, /* efo_reconfigure */
81 #endif /* EFSYS_OPT_RIVERHEAD */
83 __checkReturn efx_rc_t
86 __inout efx_filter_spec_t *spec)
88 const efx_filter_ops_t *efop = enp->en_efop;
89 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
92 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
93 EFSYS_ASSERT3P(spec, !=, NULL);
94 EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
96 if ((spec->efs_flags & EFX_FILTER_FLAG_ACTION_MARK) &&
97 !encp->enc_filter_action_mark_supported) {
102 if ((spec->efs_flags & EFX_FILTER_FLAG_ACTION_FLAG) &&
103 !encp->enc_filter_action_flag_supported) {
108 if (spec->efs_priority == EFX_FILTER_PRI_AUTO) {
113 return (efop->efo_add(enp, spec,
114 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY));
121 EFSYS_PROBE1(fail1, efx_rc_t, rc);
126 __checkReturn efx_rc_t
129 __inout efx_filter_spec_t *spec)
131 const efx_filter_ops_t *efop = enp->en_efop;
133 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
134 EFSYS_ASSERT3P(spec, !=, NULL);
135 EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
137 return (efop->efo_delete(enp, spec));
140 __checkReturn efx_rc_t
146 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
148 if ((rc = enp->en_efop->efo_restore(enp)) != 0)
154 EFSYS_PROBE1(fail1, efx_rc_t, rc);
159 __checkReturn efx_rc_t
163 const efx_filter_ops_t *efop;
166 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
167 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
168 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_FILTER));
170 switch (enp->en_family) {
172 case EFX_FAMILY_SIENA:
173 efop = &__efx_filter_siena_ops;
175 #endif /* EFSYS_OPT_SIENA */
177 #if EFSYS_OPT_HUNTINGTON
178 case EFX_FAMILY_HUNTINGTON:
179 efop = &__efx_filter_ef10_ops;
181 #endif /* EFSYS_OPT_HUNTINGTON */
183 #if EFSYS_OPT_MEDFORD
184 case EFX_FAMILY_MEDFORD:
185 efop = &__efx_filter_ef10_ops;
187 #endif /* EFSYS_OPT_MEDFORD */
189 #if EFSYS_OPT_MEDFORD2
190 case EFX_FAMILY_MEDFORD2:
191 efop = &__efx_filter_ef10_ops;
193 #endif /* EFSYS_OPT_MEDFORD2 */
195 #if EFSYS_OPT_RIVERHEAD
196 case EFX_FAMILY_RIVERHEAD:
197 efop = &__efx_filter_rhead_ops;
199 #endif /* EFSYS_OPT_RIVERHEAD */
207 if ((rc = efop->efo_init(enp)) != 0)
211 enp->en_mod_flags |= EFX_MOD_FILTER;
217 EFSYS_PROBE1(fail1, efx_rc_t, rc);
220 enp->en_mod_flags &= ~EFX_MOD_FILTER;
228 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
229 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
230 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
232 enp->en_efop->efo_fini(enp);
235 enp->en_mod_flags &= ~EFX_MOD_FILTER;
239 * Query the possible combinations of match flags which can be filtered on.
240 * These are returned as a list, of which each 32 bit element is a bitmask
241 * formed of EFX_FILTER_MATCH flags.
243 * The combinations are ordered in priority from highest to lowest.
245 * If the provided buffer is too short to hold the list, the call with fail with
246 * ENOSPC and *list_lengthp will be set to the buffer length required.
248 __checkReturn efx_rc_t
249 efx_filter_supported_filters(
251 __out_ecount(buffer_length) uint32_t *buffer,
252 __in size_t buffer_length,
253 __out size_t *list_lengthp)
257 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
258 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
259 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
260 EFSYS_ASSERT(enp->en_efop->efo_supported_filters != NULL);
262 if (buffer == NULL) {
267 rc = enp->en_efop->efo_supported_filters(enp, buffer, buffer_length,
277 EFSYS_PROBE1(fail1, efx_rc_t, rc);
282 __checkReturn efx_rc_t
283 efx_filter_reconfigure(
285 __in_ecount(6) uint8_t const *mac_addr,
286 __in boolean_t all_unicst,
287 __in boolean_t mulcst,
288 __in boolean_t all_mulcst,
289 __in boolean_t brdcst,
290 __in_ecount(6*count) uint8_t const *addrs,
295 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
296 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
297 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
299 if (enp->en_efop->efo_reconfigure != NULL) {
300 if ((rc = enp->en_efop->efo_reconfigure(enp, mac_addr,
310 EFSYS_PROBE1(fail1, efx_rc_t, rc);
316 efx_filter_spec_init_rx(
317 __out efx_filter_spec_t *spec,
318 __in efx_filter_priority_t priority,
319 __in efx_filter_flags_t flags,
322 EFSYS_ASSERT3P(spec, !=, NULL);
323 EFSYS_ASSERT3P(erp, !=, NULL);
324 EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
325 EFX_FILTER_FLAG_RX_SCATTER)) == 0);
327 memset(spec, 0, sizeof (*spec));
328 spec->efs_priority = priority;
329 spec->efs_flags = EFX_FILTER_FLAG_RX | flags;
330 spec->efs_rss_context = EFX_RSS_CONTEXT_DEFAULT;
331 spec->efs_dmaq_id = (uint16_t)erp->er_index;
335 efx_filter_spec_init_tx(
336 __out efx_filter_spec_t *spec,
339 EFSYS_ASSERT3P(spec, !=, NULL);
340 EFSYS_ASSERT3P(etp, !=, NULL);
342 memset(spec, 0, sizeof (*spec));
343 spec->efs_priority = EFX_FILTER_PRI_MANUAL;
344 spec->efs_flags = EFX_FILTER_FLAG_TX;
345 spec->efs_dmaq_id = (uint16_t)etp->et_index;
350 * Specify IPv4 host, transport protocol and port in a filter specification
352 __checkReturn efx_rc_t
353 efx_filter_spec_set_ipv4_local(
354 __inout efx_filter_spec_t *spec,
359 EFSYS_ASSERT3P(spec, !=, NULL);
361 spec->efs_match_flags |=
362 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
363 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
364 spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
365 spec->efs_ip_proto = proto;
366 spec->efs_loc_host.eo_u32[0] = host;
367 spec->efs_loc_port = port;
372 * Specify IPv4 hosts, transport protocol and ports in a filter specification
374 __checkReturn efx_rc_t
375 efx_filter_spec_set_ipv4_full(
376 __inout efx_filter_spec_t *spec,
383 EFSYS_ASSERT3P(spec, !=, NULL);
385 spec->efs_match_flags |=
386 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
387 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
388 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
389 spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
390 spec->efs_ip_proto = proto;
391 spec->efs_loc_host.eo_u32[0] = lhost;
392 spec->efs_loc_port = lport;
393 spec->efs_rem_host.eo_u32[0] = rhost;
394 spec->efs_rem_port = rport;
399 * Specify local Ethernet address and/or VID in filter specification
401 __checkReturn efx_rc_t
402 efx_filter_spec_set_eth_local(
403 __inout efx_filter_spec_t *spec,
405 __in const uint8_t *addr)
407 EFSYS_ASSERT3P(spec, !=, NULL);
408 EFSYS_ASSERT3P(addr, !=, NULL);
410 if (vid == EFX_FILTER_SPEC_VID_UNSPEC && addr == NULL)
413 if (vid != EFX_FILTER_SPEC_VID_UNSPEC) {
414 spec->efs_match_flags |= EFX_FILTER_MATCH_OUTER_VID;
415 spec->efs_outer_vid = vid;
418 spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC;
419 memcpy(spec->efs_loc_mac, addr, EFX_MAC_ADDR_LEN);
425 efx_filter_spec_set_ether_type(
426 __inout efx_filter_spec_t *spec,
427 __in uint16_t ether_type)
429 EFSYS_ASSERT3P(spec, !=, NULL);
431 spec->efs_ether_type = ether_type;
432 spec->efs_match_flags |= EFX_FILTER_MATCH_ETHER_TYPE;
436 * Specify matching otherwise-unmatched unicast in a filter specification
438 __checkReturn efx_rc_t
439 efx_filter_spec_set_uc_def(
440 __inout efx_filter_spec_t *spec)
442 EFSYS_ASSERT3P(spec, !=, NULL);
444 spec->efs_match_flags |= EFX_FILTER_MATCH_UNKNOWN_UCAST_DST;
449 * Specify matching otherwise-unmatched multicast in a filter specification
451 __checkReturn efx_rc_t
452 efx_filter_spec_set_mc_def(
453 __inout efx_filter_spec_t *spec)
455 EFSYS_ASSERT3P(spec, !=, NULL);
457 spec->efs_match_flags |= EFX_FILTER_MATCH_UNKNOWN_MCAST_DST;
462 __checkReturn efx_rc_t
463 efx_filter_spec_set_encap_type(
464 __inout efx_filter_spec_t *spec,
465 __in efx_tunnel_protocol_t encap_type,
466 __in efx_filter_inner_frame_match_t inner_frame_match)
468 uint32_t match_flags = EFX_FILTER_MATCH_ENCAP_TYPE;
472 EFSYS_ASSERT3P(spec, !=, NULL);
474 switch (encap_type) {
475 case EFX_TUNNEL_PROTOCOL_VXLAN:
476 case EFX_TUNNEL_PROTOCOL_GENEVE:
477 ip_proto = EFX_IPPROTO_UDP;
479 case EFX_TUNNEL_PROTOCOL_NVGRE:
480 ip_proto = EFX_IPPROTO_GRE;
488 switch (inner_frame_match) {
489 case EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST:
490 match_flags |= EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST;
492 case EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST:
493 match_flags |= EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST;
495 case EFX_FILTER_INNER_FRAME_MATCH_OTHER:
496 /* This is for when specific inner frames are to be matched. */
504 spec->efs_encap_type = encap_type;
505 spec->efs_ip_proto = ip_proto;
506 spec->efs_match_flags |= (match_flags | EFX_FILTER_MATCH_IP_PROTO);
513 EFSYS_PROBE1(fail1, efx_rc_t, rc);
519 * Specify inner and outer Ethernet address and VNI or VSID in tunnel filter
522 static __checkReturn efx_rc_t
523 efx_filter_spec_set_tunnel(
524 __inout efx_filter_spec_t *spec,
525 __in efx_tunnel_protocol_t encap_type,
526 __in const uint8_t *vni_or_vsid,
527 __in const uint8_t *inner_addr,
528 __in const uint8_t *outer_addr)
532 EFSYS_ASSERT3P(spec, !=, NULL);
533 EFSYS_ASSERT3P(vni_or_vsid, !=, NULL);
534 EFSYS_ASSERT3P(inner_addr, !=, NULL);
535 EFSYS_ASSERT3P(outer_addr, !=, NULL);
537 switch (encap_type) {
538 case EFX_TUNNEL_PROTOCOL_VXLAN:
539 case EFX_TUNNEL_PROTOCOL_GENEVE:
540 case EFX_TUNNEL_PROTOCOL_NVGRE:
547 if ((inner_addr == NULL) && (outer_addr == NULL)) {
552 if (vni_or_vsid != NULL) {
553 spec->efs_match_flags |= EFX_FILTER_MATCH_VNI_OR_VSID;
554 memcpy(spec->efs_vni_or_vsid, vni_or_vsid, EFX_VNI_OR_VSID_LEN);
556 if (outer_addr != NULL) {
557 spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC;
558 memcpy(spec->efs_loc_mac, outer_addr, EFX_MAC_ADDR_LEN);
560 if (inner_addr != NULL) {
561 spec->efs_match_flags |= EFX_FILTER_MATCH_IFRM_LOC_MAC;
562 memcpy(spec->efs_ifrm_loc_mac, inner_addr, EFX_MAC_ADDR_LEN);
565 spec->efs_match_flags |= EFX_FILTER_MATCH_ENCAP_TYPE;
566 spec->efs_encap_type = encap_type;
573 EFSYS_PROBE1(fail1, efx_rc_t, rc);
579 * Specify inner and outer Ethernet address and VNI in VXLAN filter
582 __checkReturn efx_rc_t
583 efx_filter_spec_set_vxlan(
584 __inout efx_filter_spec_t *spec,
585 __in const uint8_t *vni,
586 __in const uint8_t *inner_addr,
587 __in const uint8_t *outer_addr)
589 return efx_filter_spec_set_tunnel(spec, EFX_TUNNEL_PROTOCOL_VXLAN,
590 vni, inner_addr, outer_addr);
594 * Specify inner and outer Ethernet address and VNI in Geneve filter
597 __checkReturn efx_rc_t
598 efx_filter_spec_set_geneve(
599 __inout efx_filter_spec_t *spec,
600 __in const uint8_t *vni,
601 __in const uint8_t *inner_addr,
602 __in const uint8_t *outer_addr)
604 return efx_filter_spec_set_tunnel(spec, EFX_TUNNEL_PROTOCOL_GENEVE,
605 vni, inner_addr, outer_addr);
609 * Specify inner and outer Ethernet address and vsid in NVGRE filter
612 __checkReturn efx_rc_t
613 efx_filter_spec_set_nvgre(
614 __inout efx_filter_spec_t *spec,
615 __in const uint8_t *vsid,
616 __in const uint8_t *inner_addr,
617 __in const uint8_t *outer_addr)
619 return efx_filter_spec_set_tunnel(spec, EFX_TUNNEL_PROTOCOL_NVGRE,
620 vsid, inner_addr, outer_addr);
623 #if EFSYS_OPT_RX_SCALE
624 __checkReturn efx_rc_t
625 efx_filter_spec_set_rss_context(
626 __inout efx_filter_spec_t *spec,
627 __in uint32_t rss_context)
631 EFSYS_ASSERT3P(spec, !=, NULL);
633 /* The filter must have been created with EFX_FILTER_FLAG_RX_RSS. */
634 if ((spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) == 0) {
639 spec->efs_rss_context = rss_context;
644 EFSYS_PROBE1(fail1, efx_rc_t, rc);
653 * "Fudge factors" - difference between programmed value and actual depth.
654 * Due to pipelined implementation we need to program H/W with a value that
655 * is larger than the hop limit we want.
657 #define FILTER_CTL_SRCH_FUDGE_WILD 3
658 #define FILTER_CTL_SRCH_FUDGE_FULL 1
661 * Hard maximum hop limit. Hardware will time-out beyond 200-something.
662 * We also need to avoid infinite loops in efx_filter_search() when the
665 #define FILTER_CTL_SRCH_MAX 200
667 static __checkReturn efx_rc_t
668 siena_filter_spec_from_gen_spec(
669 __out siena_filter_spec_t *sf_spec,
670 __in efx_filter_spec_t *gen_spec)
673 boolean_t is_full = B_FALSE;
675 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX)
676 EFSYS_ASSERT3U(gen_spec->efs_flags, ==, EFX_FILTER_FLAG_TX);
678 EFSYS_ASSERT3U(gen_spec->efs_flags, &, EFX_FILTER_FLAG_RX);
680 /* Siena only has one RSS context */
681 if ((gen_spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) &&
682 gen_spec->efs_rss_context != EFX_RSS_CONTEXT_DEFAULT) {
687 sf_spec->sfs_flags = gen_spec->efs_flags;
688 sf_spec->sfs_dmaq_id = gen_spec->efs_dmaq_id;
690 switch (gen_spec->efs_match_flags) {
691 case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
692 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
693 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT:
696 case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
697 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT: {
698 uint32_t rhost, host1, host2;
699 uint16_t rport, port1, port2;
701 if (gen_spec->efs_ether_type != EFX_ETHER_TYPE_IPV4) {
705 if (gen_spec->efs_loc_port == 0 ||
706 (is_full && gen_spec->efs_rem_port == 0)) {
710 switch (gen_spec->efs_ip_proto) {
711 case EFX_IPPROTO_TCP:
712 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
713 sf_spec->sfs_type = (is_full ?
714 EFX_SIENA_FILTER_TX_TCP_FULL :
715 EFX_SIENA_FILTER_TX_TCP_WILD);
717 sf_spec->sfs_type = (is_full ?
718 EFX_SIENA_FILTER_RX_TCP_FULL :
719 EFX_SIENA_FILTER_RX_TCP_WILD);
722 case EFX_IPPROTO_UDP:
723 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
724 sf_spec->sfs_type = (is_full ?
725 EFX_SIENA_FILTER_TX_UDP_FULL :
726 EFX_SIENA_FILTER_TX_UDP_WILD);
728 sf_spec->sfs_type = (is_full ?
729 EFX_SIENA_FILTER_RX_UDP_FULL :
730 EFX_SIENA_FILTER_RX_UDP_WILD);
738 * The filter is constructed in terms of source and destination,
739 * with the odd wrinkle that the ports are swapped in a UDP
740 * wildcard filter. We need to convert from local and remote
741 * addresses (zero for a wildcard).
743 rhost = is_full ? gen_spec->efs_rem_host.eo_u32[0] : 0;
744 rport = is_full ? gen_spec->efs_rem_port : 0;
745 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
746 host1 = gen_spec->efs_loc_host.eo_u32[0];
750 host2 = gen_spec->efs_loc_host.eo_u32[0];
752 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
753 if (sf_spec->sfs_type ==
754 EFX_SIENA_FILTER_TX_UDP_WILD) {
756 port2 = gen_spec->efs_loc_port;
758 port1 = gen_spec->efs_loc_port;
762 if (sf_spec->sfs_type ==
763 EFX_SIENA_FILTER_RX_UDP_WILD) {
764 port1 = gen_spec->efs_loc_port;
768 port2 = gen_spec->efs_loc_port;
771 sf_spec->sfs_dword[0] = (host1 << 16) | port1;
772 sf_spec->sfs_dword[1] = (port2 << 16) | (host1 >> 16);
773 sf_spec->sfs_dword[2] = host2;
777 case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
780 case EFX_FILTER_MATCH_LOC_MAC:
781 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
782 sf_spec->sfs_type = (is_full ?
783 EFX_SIENA_FILTER_TX_MAC_FULL :
784 EFX_SIENA_FILTER_TX_MAC_WILD);
786 sf_spec->sfs_type = (is_full ?
787 EFX_SIENA_FILTER_RX_MAC_FULL :
788 EFX_SIENA_FILTER_RX_MAC_WILD);
790 sf_spec->sfs_dword[0] = is_full ? gen_spec->efs_outer_vid : 0;
791 sf_spec->sfs_dword[1] =
792 gen_spec->efs_loc_mac[2] << 24 |
793 gen_spec->efs_loc_mac[3] << 16 |
794 gen_spec->efs_loc_mac[4] << 8 |
795 gen_spec->efs_loc_mac[5];
796 sf_spec->sfs_dword[2] =
797 gen_spec->efs_loc_mac[0] << 8 |
798 gen_spec->efs_loc_mac[1];
802 EFSYS_ASSERT(B_FALSE);
818 EFSYS_PROBE1(fail1, efx_rc_t, rc);
824 * The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
825 * key derived from the n-tuple.
828 siena_filter_tbl_hash(
833 /* First 16 rounds */
834 tmp = 0x1fff ^ (uint16_t)(key >> 16);
835 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
836 tmp = tmp ^ tmp >> 9;
839 tmp = tmp ^ tmp << 13 ^ (uint16_t)(key & 0xffff);
840 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
841 tmp = tmp ^ tmp >> 9;
847 * To allow for hash collisions, filter search continues at these
848 * increments from the first possible entry selected by the hash.
851 siena_filter_tbl_increment(
854 return ((uint16_t)(key * 2 - 1));
857 static __checkReturn boolean_t
858 siena_filter_test_used(
859 __in siena_filter_tbl_t *sftp,
860 __in unsigned int index)
862 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
863 return ((sftp->sft_bitmap[index / 32] & (1 << (index % 32))) != 0);
867 siena_filter_set_used(
868 __in siena_filter_tbl_t *sftp,
869 __in unsigned int index)
871 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
872 sftp->sft_bitmap[index / 32] |= (1 << (index % 32));
877 siena_filter_clear_used(
878 __in siena_filter_tbl_t *sftp,
879 __in unsigned int index)
881 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
882 sftp->sft_bitmap[index / 32] &= ~(1 << (index % 32));
885 EFSYS_ASSERT3U(sftp->sft_used, >=, 0);
889 static siena_filter_tbl_id_t
891 __in siena_filter_type_t type)
893 siena_filter_tbl_id_t tbl_id;
896 case EFX_SIENA_FILTER_RX_TCP_FULL:
897 case EFX_SIENA_FILTER_RX_TCP_WILD:
898 case EFX_SIENA_FILTER_RX_UDP_FULL:
899 case EFX_SIENA_FILTER_RX_UDP_WILD:
900 tbl_id = EFX_SIENA_FILTER_TBL_RX_IP;
903 case EFX_SIENA_FILTER_RX_MAC_FULL:
904 case EFX_SIENA_FILTER_RX_MAC_WILD:
905 tbl_id = EFX_SIENA_FILTER_TBL_RX_MAC;
908 case EFX_SIENA_FILTER_TX_TCP_FULL:
909 case EFX_SIENA_FILTER_TX_TCP_WILD:
910 case EFX_SIENA_FILTER_TX_UDP_FULL:
911 case EFX_SIENA_FILTER_TX_UDP_WILD:
912 tbl_id = EFX_SIENA_FILTER_TBL_TX_IP;
915 case EFX_SIENA_FILTER_TX_MAC_FULL:
916 case EFX_SIENA_FILTER_TX_MAC_WILD:
917 tbl_id = EFX_SIENA_FILTER_TBL_TX_MAC;
921 EFSYS_ASSERT(B_FALSE);
922 tbl_id = EFX_SIENA_FILTER_NTBLS;
929 siena_filter_reset_search_depth(
930 __inout siena_filter_t *sfp,
931 __in siena_filter_tbl_id_t tbl_id)
934 case EFX_SIENA_FILTER_TBL_RX_IP:
935 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_FULL] = 0;
936 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_WILD] = 0;
937 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_FULL] = 0;
938 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_WILD] = 0;
941 case EFX_SIENA_FILTER_TBL_RX_MAC:
942 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_FULL] = 0;
943 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_WILD] = 0;
946 case EFX_SIENA_FILTER_TBL_TX_IP:
947 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_FULL] = 0;
948 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_WILD] = 0;
949 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_FULL] = 0;
950 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_WILD] = 0;
953 case EFX_SIENA_FILTER_TBL_TX_MAC:
954 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_FULL] = 0;
955 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_WILD] = 0;
959 EFSYS_ASSERT(B_FALSE);
965 siena_filter_push_rx_limits(
968 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
971 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
973 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_FULL_SRCH_LIMIT,
974 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_FULL] +
975 FILTER_CTL_SRCH_FUDGE_FULL);
976 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_WILD_SRCH_LIMIT,
977 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_WILD] +
978 FILTER_CTL_SRCH_FUDGE_WILD);
979 EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_FULL_SRCH_LIMIT,
980 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_FULL] +
981 FILTER_CTL_SRCH_FUDGE_FULL);
982 EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_WILD_SRCH_LIMIT,
983 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_WILD] +
984 FILTER_CTL_SRCH_FUDGE_WILD);
986 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_MAC].sft_size) {
987 EFX_SET_OWORD_FIELD(oword,
988 FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
989 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_FULL] +
990 FILTER_CTL_SRCH_FUDGE_FULL);
991 EFX_SET_OWORD_FIELD(oword,
992 FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
993 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_WILD] +
994 FILTER_CTL_SRCH_FUDGE_WILD);
997 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1001 siena_filter_push_tx_limits(
1002 __in efx_nic_t *enp)
1004 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1007 EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword);
1009 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_IP].sft_size != 0) {
1010 EFX_SET_OWORD_FIELD(oword,
1011 FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE,
1012 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_FULL] +
1013 FILTER_CTL_SRCH_FUDGE_FULL);
1014 EFX_SET_OWORD_FIELD(oword,
1015 FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE,
1016 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_WILD] +
1017 FILTER_CTL_SRCH_FUDGE_WILD);
1018 EFX_SET_OWORD_FIELD(oword,
1019 FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE,
1020 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_FULL] +
1021 FILTER_CTL_SRCH_FUDGE_FULL);
1022 EFX_SET_OWORD_FIELD(oword,
1023 FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE,
1024 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_WILD] +
1025 FILTER_CTL_SRCH_FUDGE_WILD);
1028 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_MAC].sft_size != 0) {
1029 EFX_SET_OWORD_FIELD(
1030 oword, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
1031 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_FULL] +
1032 FILTER_CTL_SRCH_FUDGE_FULL);
1033 EFX_SET_OWORD_FIELD(
1034 oword, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
1035 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_WILD] +
1036 FILTER_CTL_SRCH_FUDGE_WILD);
1039 EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword);
1042 /* Build a filter entry and return its n-tuple key. */
1043 static __checkReturn uint32_t
1045 __out efx_oword_t *filter,
1046 __in siena_filter_spec_t *spec)
1050 uint8_t type = spec->sfs_type;
1051 uint32_t flags = spec->sfs_flags;
1053 switch (siena_filter_tbl_id(type)) {
1054 case EFX_SIENA_FILTER_TBL_RX_IP: {
1055 boolean_t is_udp = (type == EFX_SIENA_FILTER_RX_UDP_FULL ||
1056 type == EFX_SIENA_FILTER_RX_UDP_WILD);
1057 EFX_POPULATE_OWORD_7(*filter,
1059 (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
1061 (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
1062 FRF_AZ_TCP_UDP, is_udp,
1063 FRF_AZ_RXQ_ID, spec->sfs_dmaq_id,
1064 EFX_DWORD_2, spec->sfs_dword[2],
1065 EFX_DWORD_1, spec->sfs_dword[1],
1066 EFX_DWORD_0, spec->sfs_dword[0]);
1071 case EFX_SIENA_FILTER_TBL_RX_MAC: {
1072 boolean_t is_wild = (type == EFX_SIENA_FILTER_RX_MAC_WILD);
1073 EFX_POPULATE_OWORD_7(*filter,
1075 (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
1076 FRF_CZ_RMFT_SCATTER_EN,
1077 (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
1078 FRF_CZ_RMFT_RXQ_ID, spec->sfs_dmaq_id,
1079 FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
1080 FRF_CZ_RMFT_DEST_MAC_DW1, spec->sfs_dword[2],
1081 FRF_CZ_RMFT_DEST_MAC_DW0, spec->sfs_dword[1],
1082 FRF_CZ_RMFT_VLAN_ID, spec->sfs_dword[0]);
1087 case EFX_SIENA_FILTER_TBL_TX_IP: {
1088 boolean_t is_udp = (type == EFX_SIENA_FILTER_TX_UDP_FULL ||
1089 type == EFX_SIENA_FILTER_TX_UDP_WILD);
1090 EFX_POPULATE_OWORD_5(*filter,
1091 FRF_CZ_TIFT_TCP_UDP, is_udp,
1092 FRF_CZ_TIFT_TXQ_ID, spec->sfs_dmaq_id,
1093 EFX_DWORD_2, spec->sfs_dword[2],
1094 EFX_DWORD_1, spec->sfs_dword[1],
1095 EFX_DWORD_0, spec->sfs_dword[0]);
1096 dword3 = is_udp | spec->sfs_dmaq_id << 1;
1100 case EFX_SIENA_FILTER_TBL_TX_MAC: {
1101 boolean_t is_wild = (type == EFX_SIENA_FILTER_TX_MAC_WILD);
1102 EFX_POPULATE_OWORD_5(*filter,
1103 FRF_CZ_TMFT_TXQ_ID, spec->sfs_dmaq_id,
1104 FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
1105 FRF_CZ_TMFT_SRC_MAC_DW1, spec->sfs_dword[2],
1106 FRF_CZ_TMFT_SRC_MAC_DW0, spec->sfs_dword[1],
1107 FRF_CZ_TMFT_VLAN_ID, spec->sfs_dword[0]);
1108 dword3 = is_wild | spec->sfs_dmaq_id << 1;
1113 EFSYS_ASSERT(B_FALSE);
1114 EFX_ZERO_OWORD(*filter);
1119 spec->sfs_dword[0] ^
1120 spec->sfs_dword[1] ^
1121 spec->sfs_dword[2] ^
1127 static __checkReturn efx_rc_t
1128 siena_filter_push_entry(
1129 __inout efx_nic_t *enp,
1130 __in siena_filter_type_t type,
1132 __in efx_oword_t *eop)
1137 case EFX_SIENA_FILTER_RX_TCP_FULL:
1138 case EFX_SIENA_FILTER_RX_TCP_WILD:
1139 case EFX_SIENA_FILTER_RX_UDP_FULL:
1140 case EFX_SIENA_FILTER_RX_UDP_WILD:
1141 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_FILTER_TBL0, index,
1145 case EFX_SIENA_FILTER_RX_MAC_FULL:
1146 case EFX_SIENA_FILTER_RX_MAC_WILD:
1147 EFX_BAR_TBL_WRITEO(enp, FR_CZ_RX_MAC_FILTER_TBL0, index,
1151 case EFX_SIENA_FILTER_TX_TCP_FULL:
1152 case EFX_SIENA_FILTER_TX_TCP_WILD:
1153 case EFX_SIENA_FILTER_TX_UDP_FULL:
1154 case EFX_SIENA_FILTER_TX_UDP_WILD:
1155 EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_FILTER_TBL0, index,
1159 case EFX_SIENA_FILTER_TX_MAC_FULL:
1160 case EFX_SIENA_FILTER_TX_MAC_WILD:
1161 EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_MAC_FILTER_TBL0, index,
1166 EFSYS_ASSERT(B_FALSE);
1177 static __checkReturn boolean_t
1179 __in const siena_filter_spec_t *left,
1180 __in const siena_filter_spec_t *right)
1182 siena_filter_tbl_id_t tbl_id;
1184 tbl_id = siena_filter_tbl_id(left->sfs_type);
1187 if (left->sfs_type != right->sfs_type)
1190 if (memcmp(left->sfs_dword, right->sfs_dword,
1191 sizeof (left->sfs_dword)))
1194 if ((tbl_id == EFX_SIENA_FILTER_TBL_TX_IP ||
1195 tbl_id == EFX_SIENA_FILTER_TBL_TX_MAC) &&
1196 left->sfs_dmaq_id != right->sfs_dmaq_id)
1202 static __checkReturn efx_rc_t
1203 siena_filter_search(
1204 __in siena_filter_tbl_t *sftp,
1205 __in siena_filter_spec_t *spec,
1207 __in boolean_t for_insert,
1208 __out int *filter_index,
1209 __out unsigned int *depth_required)
1211 unsigned int hash, incr, filter_idx, depth;
1213 hash = siena_filter_tbl_hash(key);
1214 incr = siena_filter_tbl_increment(key);
1216 filter_idx = hash & (sftp->sft_size - 1);
1221 * Return success if entry is used and matches this spec
1222 * or entry is unused and we are trying to insert.
1224 if (siena_filter_test_used(sftp, filter_idx) ?
1225 siena_filter_equal(spec,
1226 &sftp->sft_spec[filter_idx]) :
1228 *filter_index = filter_idx;
1229 *depth_required = depth;
1233 /* Return failure if we reached the maximum search depth */
1234 if (depth == FILTER_CTL_SRCH_MAX)
1235 return (for_insert ? EBUSY : ENOENT);
1237 filter_idx = (filter_idx + incr) & (sftp->sft_size - 1);
1243 siena_filter_clear_entry(
1244 __in efx_nic_t *enp,
1245 __in siena_filter_tbl_t *sftp,
1250 if (siena_filter_test_used(sftp, index)) {
1251 siena_filter_clear_used(sftp, index);
1253 EFX_ZERO_OWORD(filter);
1254 siena_filter_push_entry(enp,
1255 sftp->sft_spec[index].sfs_type,
1258 memset(&sftp->sft_spec[index],
1259 0, sizeof (sftp->sft_spec[0]));
1264 siena_filter_tbl_clear(
1265 __in efx_nic_t *enp,
1266 __in siena_filter_tbl_id_t tbl_id)
1268 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1269 siena_filter_tbl_t *sftp = &sfp->sf_tbl[tbl_id];
1271 efsys_lock_state_t state;
1273 EFSYS_LOCK(enp->en_eslp, state);
1275 for (index = 0; index < sftp->sft_size; ++index) {
1276 siena_filter_clear_entry(enp, sftp, index);
1279 if (sftp->sft_used == 0)
1280 siena_filter_reset_search_depth(sfp, tbl_id);
1282 EFSYS_UNLOCK(enp->en_eslp, state);
1285 static __checkReturn efx_rc_t
1287 __in efx_nic_t *enp)
1289 siena_filter_t *sfp;
1290 siena_filter_tbl_t *sftp;
1294 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (siena_filter_t), sfp);
1301 enp->en_filter.ef_siena_filter = sfp;
1303 switch (enp->en_family) {
1304 case EFX_FAMILY_SIENA:
1305 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_IP];
1306 sftp->sft_size = FR_AZ_RX_FILTER_TBL0_ROWS;
1308 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_MAC];
1309 sftp->sft_size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
1311 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_IP];
1312 sftp->sft_size = FR_CZ_TX_FILTER_TBL0_ROWS;
1314 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_MAC];
1315 sftp->sft_size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
1323 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1324 unsigned int bitmap_size;
1326 sftp = &sfp->sf_tbl[tbl_id];
1327 if (sftp->sft_size == 0)
1330 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1333 (sftp->sft_size + (sizeof (uint32_t) * 8) - 1) / 8;
1335 EFSYS_KMEM_ALLOC(enp->en_esip, bitmap_size, sftp->sft_bitmap);
1336 if (!sftp->sft_bitmap) {
1341 EFSYS_KMEM_ALLOC(enp->en_esip,
1342 sftp->sft_size * sizeof (*sftp->sft_spec),
1344 if (!sftp->sft_spec) {
1348 memset(sftp->sft_spec, 0,
1349 sftp->sft_size * sizeof (*sftp->sft_spec));
1362 siena_filter_fini(enp);
1365 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1371 __in efx_nic_t *enp)
1373 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1374 siena_filter_tbl_id_t tbl_id;
1376 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1377 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
1382 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1383 siena_filter_tbl_t *sftp = &sfp->sf_tbl[tbl_id];
1384 unsigned int bitmap_size;
1386 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1389 (sftp->sft_size + (sizeof (uint32_t) * 8) - 1) / 8;
1391 if (sftp->sft_bitmap != NULL) {
1392 EFSYS_KMEM_FREE(enp->en_esip, bitmap_size,
1394 sftp->sft_bitmap = NULL;
1397 if (sftp->sft_spec != NULL) {
1398 EFSYS_KMEM_FREE(enp->en_esip, sftp->sft_size *
1399 sizeof (*sftp->sft_spec), sftp->sft_spec);
1400 sftp->sft_spec = NULL;
1404 EFSYS_KMEM_FREE(enp->en_esip, sizeof (siena_filter_t),
1405 enp->en_filter.ef_siena_filter);
1408 /* Restore filter state after a reset */
1409 static __checkReturn efx_rc_t
1410 siena_filter_restore(
1411 __in efx_nic_t *enp)
1413 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1414 siena_filter_tbl_id_t tbl_id;
1415 siena_filter_tbl_t *sftp;
1416 siena_filter_spec_t *spec;
1419 efsys_lock_state_t state;
1423 EFSYS_LOCK(enp->en_eslp, state);
1425 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1426 sftp = &sfp->sf_tbl[tbl_id];
1427 for (filter_idx = 0;
1428 filter_idx < sftp->sft_size;
1430 if (!siena_filter_test_used(sftp, filter_idx))
1433 spec = &sftp->sft_spec[filter_idx];
1434 if ((key = siena_filter_build(&filter, spec)) == 0) {
1438 if ((rc = siena_filter_push_entry(enp,
1439 spec->sfs_type, filter_idx, &filter)) != 0)
1444 siena_filter_push_rx_limits(enp);
1445 siena_filter_push_tx_limits(enp);
1447 EFSYS_UNLOCK(enp->en_eslp, state);
1455 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1457 EFSYS_UNLOCK(enp->en_eslp, state);
1462 static __checkReturn efx_rc_t
1464 __in efx_nic_t *enp,
1465 __inout efx_filter_spec_t *spec,
1466 __in efx_filter_replacement_policy_t policy)
1469 siena_filter_spec_t sf_spec;
1470 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1471 siena_filter_tbl_id_t tbl_id;
1472 siena_filter_tbl_t *sftp;
1473 siena_filter_spec_t *saved_sf_spec;
1477 efsys_lock_state_t state;
1481 EFSYS_ASSERT3P(spec, !=, NULL);
1483 if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)
1486 tbl_id = siena_filter_tbl_id(sf_spec.sfs_type);
1487 sftp = &sfp->sf_tbl[tbl_id];
1489 if (sftp->sft_size == 0) {
1494 key = siena_filter_build(&filter, &sf_spec);
1496 EFSYS_LOCK(enp->en_eslp, state);
1498 rc = siena_filter_search(sftp, &sf_spec, key, B_TRUE,
1499 &filter_idx, &depth);
1503 EFSYS_ASSERT3U(filter_idx, <, sftp->sft_size);
1504 saved_sf_spec = &sftp->sft_spec[filter_idx];
1506 if (siena_filter_test_used(sftp, filter_idx)) {
1507 /* All Siena filter are considered the same priority */
1509 case EFX_FILTER_REPLACEMENT_NEVER:
1510 case EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY:
1513 case EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY:
1520 siena_filter_set_used(sftp, filter_idx);
1521 *saved_sf_spec = sf_spec;
1523 if (sfp->sf_depth[sf_spec.sfs_type] < depth) {
1524 sfp->sf_depth[sf_spec.sfs_type] = depth;
1525 if (tbl_id == EFX_SIENA_FILTER_TBL_TX_IP ||
1526 tbl_id == EFX_SIENA_FILTER_TBL_TX_MAC)
1527 siena_filter_push_tx_limits(enp);
1529 siena_filter_push_rx_limits(enp);
1532 siena_filter_push_entry(enp, sf_spec.sfs_type,
1533 filter_idx, &filter);
1535 EFSYS_UNLOCK(enp->en_eslp, state);
1542 EFSYS_UNLOCK(enp->en_eslp, state);
1549 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1553 static __checkReturn efx_rc_t
1554 siena_filter_delete(
1555 __in efx_nic_t *enp,
1556 __inout efx_filter_spec_t *spec)
1559 siena_filter_spec_t sf_spec;
1560 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1561 siena_filter_tbl_id_t tbl_id;
1562 siena_filter_tbl_t *sftp;
1566 efsys_lock_state_t state;
1569 EFSYS_ASSERT3P(spec, !=, NULL);
1571 if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)
1574 tbl_id = siena_filter_tbl_id(sf_spec.sfs_type);
1575 sftp = &sfp->sf_tbl[tbl_id];
1577 key = siena_filter_build(&filter, &sf_spec);
1579 EFSYS_LOCK(enp->en_eslp, state);
1581 rc = siena_filter_search(sftp, &sf_spec, key, B_FALSE,
1582 &filter_idx, &depth);
1586 siena_filter_clear_entry(enp, sftp, filter_idx);
1587 if (sftp->sft_used == 0)
1588 siena_filter_reset_search_depth(sfp, tbl_id);
1590 EFSYS_UNLOCK(enp->en_eslp, state);
1594 EFSYS_UNLOCK(enp->en_eslp, state);
1598 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1602 #define SIENA_MAX_SUPPORTED_MATCHES 4
1604 static __checkReturn efx_rc_t
1605 siena_filter_supported_filters(
1606 __in efx_nic_t *enp,
1607 __out_ecount(buffer_length) uint32_t *buffer,
1608 __in size_t buffer_length,
1609 __out size_t *list_lengthp)
1612 uint32_t rx_matches[SIENA_MAX_SUPPORTED_MATCHES];
1616 rx_matches[index++] =
1617 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
1618 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
1619 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
1621 rx_matches[index++] =
1622 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
1623 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
1625 if (enp->en_features & EFX_FEATURE_MAC_HEADER_FILTERS) {
1626 rx_matches[index++] =
1627 EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC;
1629 rx_matches[index++] = EFX_FILTER_MATCH_LOC_MAC;
1632 EFSYS_ASSERT3U(index, <=, SIENA_MAX_SUPPORTED_MATCHES);
1633 list_length = index;
1635 *list_lengthp = list_length;
1637 if (buffer_length < list_length) {
1642 memcpy(buffer, rx_matches, list_length * sizeof (rx_matches[0]));
1647 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1652 #undef MAX_SUPPORTED
1654 #endif /* EFSYS_OPT_SIENA */
1656 #endif /* EFSYS_OPT_FILTER */