1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
7 #ifndef _SYS_EFX_IMPL_H
8 #define _SYS_EFX_IMPL_H
12 #include "efx_regs_ef10.h"
13 #include "efx_regs_ef100.h"
16 #endif /* EFSYS_OPT_MCDI */
18 /* FIXME: Add definition for driver generated software events */
19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
25 #include "siena_impl.h"
26 #endif /* EFSYS_OPT_SIENA */
28 #if EFSYS_OPT_HUNTINGTON
29 #include "hunt_impl.h"
30 #endif /* EFSYS_OPT_HUNTINGTON */
33 #include "medford_impl.h"
34 #endif /* EFSYS_OPT_MEDFORD */
36 #if EFSYS_OPT_MEDFORD2
37 #include "medford2_impl.h"
38 #endif /* EFSYS_OPT_MEDFORD2 */
41 #include "ef10_impl.h"
42 #endif /* EFX_OPTS_EF10() */
48 #define EFX_MOD_MCDI 0x00000001
49 #define EFX_MOD_PROBE 0x00000002
50 #define EFX_MOD_NVRAM 0x00000004
51 #define EFX_MOD_VPD 0x00000008
52 #define EFX_MOD_NIC 0x00000010
53 #define EFX_MOD_INTR 0x00000020
54 #define EFX_MOD_EV 0x00000040
55 #define EFX_MOD_RX 0x00000080
56 #define EFX_MOD_TX 0x00000100
57 #define EFX_MOD_PORT 0x00000200
58 #define EFX_MOD_MON 0x00000400
59 #define EFX_MOD_FILTER 0x00001000
60 #define EFX_MOD_LIC 0x00002000
61 #define EFX_MOD_TUNNEL 0x00004000
62 #define EFX_MOD_EVB 0x00008000
63 #define EFX_MOD_PROXY 0x00010000
65 #define EFX_RESET_PHY 0x00000001
66 #define EFX_RESET_RXQ_ERR 0x00000002
67 #define EFX_RESET_TXQ_ERR 0x00000004
68 #define EFX_RESET_HW_UNAVAIL 0x00000008
70 typedef enum efx_mac_type_e {
79 typedef struct efx_ev_ops_s {
80 efx_rc_t (*eevo_init)(efx_nic_t *);
81 void (*eevo_fini)(efx_nic_t *);
82 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
83 efsys_mem_t *, size_t, uint32_t,
84 uint32_t, uint32_t, efx_evq_t *);
85 void (*eevo_qdestroy)(efx_evq_t *);
86 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
87 void (*eevo_qpost)(efx_evq_t *, uint16_t);
88 void (*eevo_qpoll)(efx_evq_t *, unsigned int *,
89 const efx_ev_callbacks_t *, void *);
90 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
92 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
96 typedef struct efx_tx_ops_s {
97 efx_rc_t (*etxo_init)(efx_nic_t *);
98 void (*etxo_fini)(efx_nic_t *);
99 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
100 unsigned int, unsigned int,
101 efsys_mem_t *, size_t,
103 efx_evq_t *, efx_txq_t *,
105 void (*etxo_qdestroy)(efx_txq_t *);
106 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
107 unsigned int, unsigned int,
109 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
110 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
111 efx_rc_t (*etxo_qflush)(efx_txq_t *);
112 void (*etxo_qenable)(efx_txq_t *);
113 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
114 void (*etxo_qpio_disable)(efx_txq_t *);
115 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
117 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
119 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
120 unsigned int, unsigned int,
122 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
125 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
128 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
129 uint16_t, uint32_t, uint16_t,
131 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
133 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
136 void (*etxo_qstats_update)(efx_txq_t *,
141 typedef union efx_rxq_type_data_u {
145 #if EFSYS_OPT_RX_PACKED_STREAM
147 uint32_t eps_buf_size;
148 } ertd_packed_stream;
150 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
152 uint32_t eessb_bufs_per_desc;
153 uint32_t eessb_max_dma_len;
154 uint32_t eessb_buf_stride;
155 uint32_t eessb_hol_block_timeout;
156 } ertd_es_super_buffer;
158 } efx_rxq_type_data_t;
160 typedef struct efx_rx_ops_s {
161 efx_rc_t (*erxo_init)(efx_nic_t *);
162 void (*erxo_fini)(efx_nic_t *);
163 #if EFSYS_OPT_RX_SCATTER
164 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
166 #if EFSYS_OPT_RX_SCALE
167 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *,
168 efx_rx_scale_context_type_t,
169 uint32_t, uint32_t *);
170 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
171 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
173 efx_rx_hash_type_t, boolean_t);
174 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
176 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
177 unsigned int *, size_t);
178 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
180 #endif /* EFSYS_OPT_RX_SCALE */
181 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
183 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
184 unsigned int, unsigned int,
186 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
187 #if EFSYS_OPT_RX_PACKED_STREAM
188 void (*erxo_qpush_ps_credits)(efx_rxq_t *);
189 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
191 uint16_t *, uint32_t *, uint32_t *);
193 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
194 void (*erxo_qenable)(efx_rxq_t *);
195 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
196 unsigned int, efx_rxq_type_t,
197 const efx_rxq_type_data_t *,
198 efsys_mem_t *, size_t, uint32_t,
200 efx_evq_t *, efx_rxq_t *);
201 void (*erxo_qdestroy)(efx_rxq_t *);
204 typedef struct efx_mac_ops_s {
205 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
206 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
207 efx_rc_t (*emo_addr_set)(efx_nic_t *);
208 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
209 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
210 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
211 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
212 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
213 efx_rxq_t *, boolean_t);
214 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
215 #if EFSYS_OPT_LOOPBACK
216 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
217 efx_loopback_type_t);
218 #endif /* EFSYS_OPT_LOOPBACK */
219 #if EFSYS_OPT_MAC_STATS
220 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
221 efx_rc_t (*emo_stats_clear)(efx_nic_t *);
222 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
223 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
224 uint16_t, boolean_t);
225 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
226 efsys_stat_t *, uint32_t *);
227 #endif /* EFSYS_OPT_MAC_STATS */
230 typedef struct efx_phy_ops_s {
231 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
232 efx_rc_t (*epo_reset)(efx_nic_t *);
233 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
234 efx_rc_t (*epo_verify)(efx_nic_t *);
235 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
236 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
237 #if EFSYS_OPT_PHY_STATS
238 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
240 #endif /* EFSYS_OPT_PHY_STATS */
242 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
243 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
244 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
245 efx_bist_result_t *, uint32_t *,
246 unsigned long *, size_t);
247 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
248 #endif /* EFSYS_OPT_BIST */
254 * Policy for replacing existing filter when inserting a new one.
255 * Note that all policies allow for storing the new lower priority
256 * filters as overridden by existing higher priority ones. It is needed
257 * to restore the lower priority filters on higher priority ones removal.
259 typedef enum efx_filter_replacement_policy_e {
260 /* Cannot replace existing filter */
261 EFX_FILTER_REPLACEMENT_NEVER,
262 /* Higher priority filters can replace lower priotiry ones */
263 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY,
265 * Higher priority filters can replace lower priority ones and
266 * equal priority filters can replace each other.
268 EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY,
269 } efx_filter_replacement_policy_t;
271 typedef struct efx_filter_ops_s {
272 efx_rc_t (*efo_init)(efx_nic_t *);
273 void (*efo_fini)(efx_nic_t *);
274 efx_rc_t (*efo_restore)(efx_nic_t *);
275 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
276 efx_filter_replacement_policy_t policy);
277 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
278 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *,
280 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
281 boolean_t, boolean_t, boolean_t,
282 uint8_t const *, uint32_t);
286 extern __checkReturn efx_rc_t
287 efx_filter_reconfigure(
289 __in_ecount(6) uint8_t const *mac_addr,
290 __in boolean_t all_unicst,
291 __in boolean_t mulcst,
292 __in boolean_t all_mulcst,
293 __in boolean_t brdcst,
294 __in_ecount(6*count) uint8_t const *addrs,
295 __in uint32_t count);
297 #endif /* EFSYS_OPT_FILTER */
300 typedef struct efx_tunnel_ops_s {
301 boolean_t (*eto_udp_encap_supported)(efx_nic_t *);
302 efx_rc_t (*eto_reconfigure)(efx_nic_t *);
304 #endif /* EFSYS_OPT_TUNNEL */
306 typedef struct efx_port_s {
307 efx_mac_type_t ep_mac_type;
308 uint32_t ep_phy_type;
311 uint8_t ep_mac_addr[6];
312 efx_link_mode_t ep_link_mode;
313 boolean_t ep_all_unicst;
314 boolean_t ep_all_unicst_inserted;
316 boolean_t ep_all_mulcst;
317 boolean_t ep_all_mulcst_inserted;
319 unsigned int ep_fcntl;
320 boolean_t ep_fcntl_autoneg;
321 efx_oword_t ep_multicst_hash[2];
322 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
323 EFX_MAC_MULTICAST_LIST_MAX];
324 uint32_t ep_mulcst_addr_count;
325 #if EFSYS_OPT_LOOPBACK
326 efx_loopback_type_t ep_loopback_type;
327 efx_link_mode_t ep_loopback_link_mode;
328 #endif /* EFSYS_OPT_LOOPBACK */
329 #if EFSYS_OPT_PHY_FLAGS
330 uint32_t ep_phy_flags;
331 #endif /* EFSYS_OPT_PHY_FLAGS */
332 #if EFSYS_OPT_PHY_LED_CONTROL
333 efx_phy_led_mode_t ep_phy_led_mode;
334 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
335 efx_phy_media_type_t ep_fixed_port_type;
336 efx_phy_media_type_t ep_module_type;
337 uint32_t ep_adv_cap_mask;
338 uint32_t ep_lp_cap_mask;
339 uint32_t ep_default_adv_cap_mask;
340 uint32_t ep_phy_cap_mask;
341 boolean_t ep_mac_drain;
343 efx_bist_type_t ep_current_bist;
345 const efx_mac_ops_t *ep_emop;
346 const efx_phy_ops_t *ep_epop;
349 typedef struct efx_mon_ops_s {
350 #if EFSYS_OPT_MON_STATS
351 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
352 efx_mon_stat_value_t *);
353 efx_rc_t (*emo_limits_update)(efx_nic_t *,
354 efx_mon_stat_limits_t *);
355 #endif /* EFSYS_OPT_MON_STATS */
358 typedef struct efx_mon_s {
359 efx_mon_type_t em_type;
360 const efx_mon_ops_t *em_emop;
363 typedef struct efx_intr_ops_s {
364 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
365 void (*eio_enable)(efx_nic_t *);
366 void (*eio_disable)(efx_nic_t *);
367 void (*eio_disable_unlocked)(efx_nic_t *);
368 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
369 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
370 void (*eio_status_message)(efx_nic_t *, unsigned int,
372 void (*eio_fatal)(efx_nic_t *);
373 void (*eio_fini)(efx_nic_t *);
376 typedef struct efx_intr_s {
377 const efx_intr_ops_t *ei_eiop;
378 efsys_mem_t *ei_esmp;
379 efx_intr_type_t ei_type;
380 unsigned int ei_level;
383 typedef struct efx_nic_ops_s {
384 efx_rc_t (*eno_probe)(efx_nic_t *);
385 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
386 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
387 efx_rc_t (*eno_reset)(efx_nic_t *);
388 efx_rc_t (*eno_init)(efx_nic_t *);
389 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
390 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
391 uint32_t *, size_t *);
392 boolean_t (*eno_hw_unavailable)(efx_nic_t *);
393 void (*eno_set_hw_unavailable)(efx_nic_t *);
395 efx_rc_t (*eno_register_test)(efx_nic_t *);
396 #endif /* EFSYS_OPT_DIAG */
397 void (*eno_fini)(efx_nic_t *);
398 void (*eno_unprobe)(efx_nic_t *);
401 #ifndef EFX_TXQ_LIMIT_TARGET
402 #define EFX_TXQ_LIMIT_TARGET 259
404 #ifndef EFX_RXQ_LIMIT_TARGET
405 #define EFX_RXQ_LIMIT_TARGET 512
413 typedef struct siena_filter_spec_s {
416 uint32_t sfs_dmaq_id;
417 uint32_t sfs_dword[3];
418 } siena_filter_spec_t;
420 typedef enum siena_filter_type_e {
421 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
422 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */
423 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
424 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */
425 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
426 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
428 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
429 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
430 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
431 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */
432 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */
433 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */
435 EFX_SIENA_FILTER_NTYPES
436 } siena_filter_type_t;
438 typedef enum siena_filter_tbl_id_e {
439 EFX_SIENA_FILTER_TBL_RX_IP = 0,
440 EFX_SIENA_FILTER_TBL_RX_MAC,
441 EFX_SIENA_FILTER_TBL_TX_IP,
442 EFX_SIENA_FILTER_TBL_TX_MAC,
443 EFX_SIENA_FILTER_NTBLS
444 } siena_filter_tbl_id_t;
446 typedef struct siena_filter_tbl_s {
447 int sft_size; /* number of entries */
448 int sft_used; /* active count */
449 uint32_t *sft_bitmap; /* active bitmap */
450 siena_filter_spec_t *sft_spec; /* array of saved specs */
451 } siena_filter_tbl_t;
453 typedef struct siena_filter_s {
454 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS];
455 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES];
458 #endif /* EFSYS_OPT_SIENA */
460 typedef struct efx_filter_s {
462 siena_filter_t *ef_siena_filter;
463 #endif /* EFSYS_OPT_SIENA */
465 ef10_filter_table_t *ef_ef10_filter_table;
466 #endif /* EFX_OPTS_EF10() */
473 siena_filter_tbl_clear(
475 __in siena_filter_tbl_id_t tbl);
477 #endif /* EFSYS_OPT_SIENA */
479 #endif /* EFSYS_OPT_FILTER */
483 #define EFX_TUNNEL_MAXNENTRIES (16)
487 typedef struct efx_tunnel_udp_entry_s {
488 uint16_t etue_port; /* host/cpu-endian */
489 uint16_t etue_protocol;
490 } efx_tunnel_udp_entry_t;
492 typedef struct efx_tunnel_cfg_s {
493 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
494 unsigned int etc_udp_entries_num;
497 #endif /* EFSYS_OPT_TUNNEL */
499 typedef struct efx_mcdi_ops_s {
500 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
501 void (*emco_send_request)(efx_nic_t *, void *, size_t,
503 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
504 boolean_t (*emco_poll_response)(efx_nic_t *);
505 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
506 void (*emco_fini)(efx_nic_t *);
507 efx_rc_t (*emco_feature_supported)(efx_nic_t *,
508 efx_mcdi_feature_id_t, boolean_t *);
509 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
513 typedef struct efx_mcdi_s {
514 const efx_mcdi_ops_t *em_emcop;
515 const efx_mcdi_transport_t *em_emtp;
516 efx_mcdi_iface_t em_emip;
519 #endif /* EFSYS_OPT_MCDI */
523 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
524 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu)
526 typedef struct efx_nvram_ops_s {
528 efx_rc_t (*envo_test)(efx_nic_t *);
529 #endif /* EFSYS_OPT_DIAG */
530 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
532 efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t,
534 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
535 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t,
536 unsigned int, caddr_t, size_t);
537 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
538 unsigned int, caddr_t, size_t);
539 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t,
540 unsigned int, size_t);
541 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t,
542 unsigned int, caddr_t, size_t);
543 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
545 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t,
546 uint32_t *, uint16_t *);
547 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t,
549 efx_rc_t (*envo_buffer_validate)(uint32_t,
552 #endif /* EFSYS_OPT_NVRAM */
555 typedef struct efx_vpd_ops_s {
556 efx_rc_t (*evpdo_init)(efx_nic_t *);
557 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
558 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
559 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
560 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
561 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
563 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
565 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
566 efx_vpd_value_t *, unsigned int *);
567 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
568 void (*evpdo_fini)(efx_nic_t *);
570 #endif /* EFSYS_OPT_VPD */
572 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
575 extern __checkReturn efx_rc_t
576 efx_mcdi_nvram_partitions(
578 __out_bcount(size) caddr_t data,
580 __out unsigned int *npartnp);
583 extern __checkReturn efx_rc_t
584 efx_mcdi_nvram_metadata(
587 __out uint32_t *subtypep,
588 __out_ecount(4) uint16_t version[4],
589 __out_bcount_opt(size) char *descp,
593 extern __checkReturn efx_rc_t
597 __out efx_nvram_info_t *eni);
600 extern __checkReturn efx_rc_t
601 efx_mcdi_nvram_update_start(
603 __in uint32_t partn);
606 extern __checkReturn efx_rc_t
610 __in uint32_t offset,
611 __out_bcount(size) caddr_t data,
616 extern __checkReturn efx_rc_t
617 efx_mcdi_nvram_erase(
620 __in uint32_t offset,
624 extern __checkReturn efx_rc_t
625 efx_mcdi_nvram_write(
628 __in uint32_t offset,
629 __in_bcount(size) caddr_t data,
632 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001
633 #define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002
636 extern __checkReturn efx_rc_t
637 efx_mcdi_nvram_update_finish(
640 __in boolean_t reboot,
642 __out_opt uint32_t *verify_resultp);
647 extern __checkReturn efx_rc_t
650 __in uint32_t partn);
652 #endif /* EFSYS_OPT_DIAG */
654 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
656 #if EFSYS_OPT_LICENSING
658 typedef struct efx_lic_ops_s {
659 efx_rc_t (*elo_update_licenses)(efx_nic_t *);
660 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
661 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
662 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
663 size_t *, uint8_t *);
664 efx_rc_t (*elo_find_start)
665 (efx_nic_t *, caddr_t, size_t, uint32_t *);
666 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
667 uint32_t, uint32_t *);
668 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
669 uint32_t, uint32_t *, uint32_t *);
670 boolean_t (*elo_validate_key)(efx_nic_t *,
672 efx_rc_t (*elo_read_key)(efx_nic_t *,
673 caddr_t, size_t, uint32_t, uint32_t,
674 caddr_t, size_t, uint32_t *);
675 efx_rc_t (*elo_write_key)(efx_nic_t *,
676 caddr_t, size_t, uint32_t,
677 caddr_t, uint32_t, uint32_t *);
678 efx_rc_t (*elo_delete_key)(efx_nic_t *,
679 caddr_t, size_t, uint32_t,
680 uint32_t, uint32_t, uint32_t *);
681 efx_rc_t (*elo_create_partition)(efx_nic_t *,
683 efx_rc_t (*elo_finish_partition)(efx_nic_t *,
691 struct efx_vswitch_s {
693 efx_vswitch_id_t ev_vswitch_id;
694 uint32_t ev_num_vports;
696 * Vport configuration array: index 0 to store PF configuration
697 * and next ev_num_vports-1 entries hold VFs configuration.
699 efx_vport_config_t *ev_evcp;
702 typedef struct efx_evb_ops_s {
703 efx_rc_t (*eeo_init)(efx_nic_t *);
704 void (*eeo_fini)(efx_nic_t *);
705 efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
706 efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
707 efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
708 efx_vport_type_t, uint16_t,
709 boolean_t, efx_vport_id_t *);
710 efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
712 efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
713 efx_vport_id_t, uint8_t *);
714 efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
715 efx_vport_id_t, uint8_t *);
716 efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
718 efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
720 efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
721 efx_vport_id_t, uint32_t);
722 efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
724 uint16_t *, uint8_t *,
726 efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
727 efx_vport_id_t, efsys_mem_t *);
731 extern __checkReturn boolean_t
732 efx_is_zero_eth_addr(
733 __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp);
735 #endif /* EFSYS_OPT_EVB */
737 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
739 #define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF
742 typedef struct efx_proxy_ops_s {
743 efx_rc_t (*epo_init)(efx_nic_t *);
744 void (*epo_fini)(efx_nic_t *);
745 efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
746 efsys_mem_t *, efsys_mem_t *,
747 uint32_t, uint32_t *, size_t);
748 efx_rc_t (*epo_disable)(efx_nic_t *);
749 efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
750 uint32_t, uint32_t, uint32_t);
751 efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
753 efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t,
755 efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
756 efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
757 uint32_t, uint32_t *);
760 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
762 #define EFX_DRV_VER_MAX 20
764 typedef struct efx_drv_cfg_s {
765 uint32_t edc_min_vi_count;
766 uint32_t edc_max_vi_count;
768 uint32_t edc_max_piobuf_count;
769 uint32_t edc_pio_alloc_size;
774 efx_family_t en_family;
775 uint32_t en_features;
776 efsys_identifier_t *en_esip;
777 efsys_lock_t *en_eslp;
778 efsys_bar_t *en_esbp;
779 unsigned int en_mod_flags;
780 unsigned int en_reset_flags;
781 efx_nic_cfg_t en_nic_cfg;
782 efx_drv_cfg_t en_drv_cfg;
786 uint32_t en_ev_qcount;
787 uint32_t en_rx_qcount;
788 uint32_t en_tx_qcount;
789 const efx_nic_ops_t *en_enop;
790 const efx_ev_ops_t *en_eevop;
791 const efx_tx_ops_t *en_etxop;
792 const efx_rx_ops_t *en_erxop;
793 efx_fw_variant_t efv;
794 char en_drv_version[EFX_DRV_VER_MAX];
796 efx_filter_t en_filter;
797 const efx_filter_ops_t *en_efop;
798 #endif /* EFSYS_OPT_FILTER */
800 efx_tunnel_cfg_t en_tunnel_cfg;
801 const efx_tunnel_ops_t *en_etop;
802 #endif /* EFSYS_OPT_TUNNEL */
805 #endif /* EFSYS_OPT_MCDI */
807 uint32_t en_nvram_partn_locked;
808 const efx_nvram_ops_t *en_envop;
809 #endif /* EFSYS_OPT_NVRAM */
811 const efx_vpd_ops_t *en_evpdop;
812 #endif /* EFSYS_OPT_VPD */
813 #if EFSYS_OPT_RX_SCALE
814 efx_rx_hash_support_t en_hash_support;
815 efx_rx_scale_context_type_t en_rss_context_type;
816 uint32_t en_rss_context;
817 #endif /* EFSYS_OPT_RX_SCALE */
818 uint32_t en_vport_id;
819 #if EFSYS_OPT_LICENSING
820 const efx_lic_ops_t *en_elop;
821 boolean_t en_licensing_supported;
826 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
827 unsigned int enu_partn_mask;
828 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
831 size_t enu_svpd_length;
832 #endif /* EFSYS_OPT_VPD */
835 #endif /* EFSYS_OPT_SIENA */
846 size_t ena_svpd_length;
847 #endif /* EFSYS_OPT_VPD */
848 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
849 uint32_t ena_piobuf_count;
850 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
851 uint32_t ena_pio_write_vi_base;
852 /* Memory BAR mapping regions */
853 uint32_t ena_uc_mem_map_offset;
854 size_t ena_uc_mem_map_size;
855 uint32_t ena_wc_mem_map_offset;
856 size_t ena_wc_mem_map_size;
859 #endif /* EFX_OPTS_EF10() */
861 const efx_evb_ops_t *en_eeop;
862 struct efx_vswitch_s *en_vswitchp;
863 #endif /* EFSYS_OPT_EVB */
864 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
865 const efx_proxy_ops_t *en_epop;
866 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
869 #define EFX_FAMILY_IS_EF10(_enp) \
870 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
871 (_enp)->en_family == EFX_FAMILY_MEDFORD || \
872 (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
875 #define EFX_NIC_MAGIC 0x02121996
877 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
878 const efx_ev_callbacks_t *, void *);
880 typedef struct efx_evq_rxq_state_s {
881 unsigned int eers_rx_read_ptr;
882 unsigned int eers_rx_mask;
883 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
884 unsigned int eers_rx_stream_npackets;
885 boolean_t eers_rx_packed_stream;
887 #if EFSYS_OPT_RX_PACKED_STREAM
888 unsigned int eers_rx_packed_stream_credits;
890 } efx_evq_rxq_state_t;
896 unsigned int ee_index;
897 unsigned int ee_mask;
898 efsys_mem_t *ee_esmp;
900 uint32_t ee_stat[EV_NQSTATS];
901 #endif /* EFSYS_OPT_QSTATS */
903 efx_ev_handler_t ee_rx;
904 efx_ev_handler_t ee_tx;
905 efx_ev_handler_t ee_driver;
906 efx_ev_handler_t ee_global;
907 efx_ev_handler_t ee_drv_gen;
909 efx_ev_handler_t ee_mcdi;
910 #endif /* EFSYS_OPT_MCDI */
912 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
915 #define EFX_EVQ_MAGIC 0x08081997
917 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
920 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
922 (_eep)->ee_stat[_stat]++; \
923 _NOTE(CONSTANTCONDITION) \
926 #define EFX_EV_QSTAT_INCR(_eep, _stat)
933 unsigned int er_index;
934 unsigned int er_label;
935 unsigned int er_mask;
937 efsys_mem_t *er_esmp;
938 efx_evq_rxq_state_t *er_ev_qstate;
941 #define EFX_RXQ_MAGIC 0x15022005
946 unsigned int et_index;
947 unsigned int et_mask;
948 efsys_mem_t *et_esmp;
949 #if EFSYS_OPT_HUNTINGTON
950 uint32_t et_pio_bufnum;
951 uint32_t et_pio_blknum;
952 uint32_t et_pio_write_offset;
953 uint32_t et_pio_offset;
957 uint32_t et_stat[TX_NQSTATS];
958 #endif /* EFSYS_OPT_QSTATS */
961 #define EFX_TXQ_MAGIC 0x05092005
963 #define EFX_MAC_ADDR_COPY(_dst, _src) \
965 (_dst)[0] = (_src)[0]; \
966 (_dst)[1] = (_src)[1]; \
967 (_dst)[2] = (_src)[2]; \
968 (_dst)[3] = (_src)[3]; \
969 (_dst)[4] = (_src)[4]; \
970 (_dst)[5] = (_src)[5]; \
971 _NOTE(CONSTANTCONDITION) \
974 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
976 uint16_t *_d = (uint16_t *)(_dst); \
980 _NOTE(CONSTANTCONDITION) \
983 #if EFSYS_OPT_CHECK_REG
984 #define EFX_CHECK_REG(_enp, _reg) \
986 const char *name = #_reg; \
987 char min = name[4]; \
988 char max = name[5]; \
991 switch ((_enp)->en_family) { \
992 case EFX_FAMILY_SIENA: \
996 case EFX_FAMILY_HUNTINGTON: \
1000 case EFX_FAMILY_MEDFORD: \
1004 case EFX_FAMILY_MEDFORD2: \
1013 EFSYS_ASSERT3S(rev, >=, min); \
1014 EFSYS_ASSERT3S(rev, <=, max); \
1016 _NOTE(CONSTANTCONDITION) \
1019 #define EFX_CHECK_REG(_enp, _reg) do { \
1020 _NOTE(CONSTANTCONDITION) \
1024 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
1026 EFX_CHECK_REG((_enp), (_reg)); \
1027 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
1029 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
1030 uint32_t, _reg ## _OFST, \
1031 uint32_t, (_edp)->ed_u32[0]); \
1032 _NOTE(CONSTANTCONDITION) \
1035 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
1037 EFX_CHECK_REG((_enp), (_reg)); \
1038 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
1039 uint32_t, _reg ## _OFST, \
1040 uint32_t, (_edp)->ed_u32[0]); \
1041 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
1043 _NOTE(CONSTANTCONDITION) \
1046 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
1048 EFX_CHECK_REG((_enp), (_reg)); \
1049 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
1051 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
1052 uint32_t, _reg ## _OFST, \
1053 uint32_t, (_eqp)->eq_u32[1], \
1054 uint32_t, (_eqp)->eq_u32[0]); \
1055 _NOTE(CONSTANTCONDITION) \
1058 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
1060 EFX_CHECK_REG((_enp), (_reg)); \
1061 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
1062 uint32_t, _reg ## _OFST, \
1063 uint32_t, (_eqp)->eq_u32[1], \
1064 uint32_t, (_eqp)->eq_u32[0]); \
1065 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
1067 _NOTE(CONSTANTCONDITION) \
1070 #define EFX_BAR_READO(_enp, _reg, _eop) \
1072 EFX_CHECK_REG((_enp), (_reg)); \
1073 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
1075 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
1076 uint32_t, _reg ## _OFST, \
1077 uint32_t, (_eop)->eo_u32[3], \
1078 uint32_t, (_eop)->eo_u32[2], \
1079 uint32_t, (_eop)->eo_u32[1], \
1080 uint32_t, (_eop)->eo_u32[0]); \
1081 _NOTE(CONSTANTCONDITION) \
1084 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
1086 EFX_CHECK_REG((_enp), (_reg)); \
1087 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
1088 uint32_t, _reg ## _OFST, \
1089 uint32_t, (_eop)->eo_u32[3], \
1090 uint32_t, (_eop)->eo_u32[2], \
1091 uint32_t, (_eop)->eo_u32[1], \
1092 uint32_t, (_eop)->eo_u32[0]); \
1093 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
1095 _NOTE(CONSTANTCONDITION) \
1099 * Accessors for memory BAR non-VI tables.
1101 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1102 * to ensure the correct runtime VI window size is used on Medford2.
1104 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1107 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
1109 EFX_CHECK_REG((_enp), (_reg)); \
1110 EFSYS_BAR_READD((_enp)->en_esbp, \
1111 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1113 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
1114 uint32_t, (_index), \
1115 uint32_t, _reg ## _OFST, \
1116 uint32_t, (_edp)->ed_u32[0]); \
1117 _NOTE(CONSTANTCONDITION) \
1120 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
1122 EFX_CHECK_REG((_enp), (_reg)); \
1123 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
1124 uint32_t, (_index), \
1125 uint32_t, _reg ## _OFST, \
1126 uint32_t, (_edp)->ed_u32[0]); \
1127 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1128 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1130 _NOTE(CONSTANTCONDITION) \
1133 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
1135 EFX_CHECK_REG((_enp), (_reg)); \
1136 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
1137 uint32_t, (_index), \
1138 uint32_t, _reg ## _OFST, \
1139 uint32_t, (_edp)->ed_u32[0]); \
1140 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1142 (3 * sizeof (efx_dword_t)) + \
1143 ((_index) * _reg ## _STEP)), \
1145 _NOTE(CONSTANTCONDITION) \
1148 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
1150 EFX_CHECK_REG((_enp), (_reg)); \
1151 EFSYS_BAR_READQ((_enp)->en_esbp, \
1152 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1154 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
1155 uint32_t, (_index), \
1156 uint32_t, _reg ## _OFST, \
1157 uint32_t, (_eqp)->eq_u32[1], \
1158 uint32_t, (_eqp)->eq_u32[0]); \
1159 _NOTE(CONSTANTCONDITION) \
1162 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
1164 EFX_CHECK_REG((_enp), (_reg)); \
1165 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
1166 uint32_t, (_index), \
1167 uint32_t, _reg ## _OFST, \
1168 uint32_t, (_eqp)->eq_u32[1], \
1169 uint32_t, (_eqp)->eq_u32[0]); \
1170 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
1171 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1173 _NOTE(CONSTANTCONDITION) \
1176 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
1178 EFX_CHECK_REG((_enp), (_reg)); \
1179 EFSYS_BAR_READO((_enp)->en_esbp, \
1180 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1182 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
1183 uint32_t, (_index), \
1184 uint32_t, _reg ## _OFST, \
1185 uint32_t, (_eop)->eo_u32[3], \
1186 uint32_t, (_eop)->eo_u32[2], \
1187 uint32_t, (_eop)->eo_u32[1], \
1188 uint32_t, (_eop)->eo_u32[0]); \
1189 _NOTE(CONSTANTCONDITION) \
1192 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1194 EFX_CHECK_REG((_enp), (_reg)); \
1195 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1196 uint32_t, (_index), \
1197 uint32_t, _reg ## _OFST, \
1198 uint32_t, (_eop)->eo_u32[3], \
1199 uint32_t, (_eop)->eo_u32[2], \
1200 uint32_t, (_eop)->eo_u32[1], \
1201 uint32_t, (_eop)->eo_u32[0]); \
1202 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1203 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1205 _NOTE(CONSTANTCONDITION) \
1209 * Accessors for memory BAR per-VI registers.
1211 * The VI window size is 8KB for Medford and all earlier controllers.
1212 * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1215 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \
1217 EFX_CHECK_REG((_enp), (_reg)); \
1218 EFSYS_BAR_READD((_enp)->en_esbp, \
1219 ((_reg ## _OFST) + \
1220 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1222 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \
1223 uint32_t, (_index), \
1224 uint32_t, _reg ## _OFST, \
1225 uint32_t, (_edp)->ed_u32[0]); \
1226 _NOTE(CONSTANTCONDITION) \
1229 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \
1231 EFX_CHECK_REG((_enp), (_reg)); \
1232 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1233 uint32_t, (_index), \
1234 uint32_t, _reg ## _OFST, \
1235 uint32_t, (_edp)->ed_u32[0]); \
1236 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1237 ((_reg ## _OFST) + \
1238 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1240 _NOTE(CONSTANTCONDITION) \
1243 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \
1245 EFX_CHECK_REG((_enp), (_reg)); \
1246 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \
1247 uint32_t, (_index), \
1248 uint32_t, _reg ## _OFST, \
1249 uint32_t, (_edp)->ed_u32[0]); \
1250 EFSYS_BAR_WRITED((_enp)->en_esbp, \
1251 ((_reg ## _OFST) + \
1252 (2 * sizeof (efx_dword_t)) + \
1253 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1255 _NOTE(CONSTANTCONDITION) \
1259 * Allow drivers to perform optimised 128-bit VI doorbell writes.
1260 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1261 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1262 * the need for locking in the host, and are the only ones known to be safe to
1263 * use 128-bites write with.
1265 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1267 EFX_CHECK_REG((_enp), (_reg)); \
1268 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \
1269 const char *, #_reg, \
1270 uint32_t, (_index), \
1271 uint32_t, _reg ## _OFST, \
1272 uint32_t, (_eop)->eo_u32[3], \
1273 uint32_t, (_eop)->eo_u32[2], \
1274 uint32_t, (_eop)->eo_u32[1], \
1275 uint32_t, (_eop)->eo_u32[0]); \
1276 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1278 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1280 _NOTE(CONSTANTCONDITION) \
1283 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1285 unsigned int _new = (_wptr); \
1286 unsigned int _old = (_owptr); \
1288 if ((_new) >= (_old)) \
1289 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1290 (_old) * sizeof (efx_desc_t), \
1291 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1294 * It is cheaper to sync entire map than sync \
1295 * two parts especially when offset/size are \
1296 * ignored and entire map is synced in any case.\
1298 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1300 (_entries) * sizeof (efx_desc_t)); \
1301 _NOTE(CONSTANTCONDITION) \
1305 extern __checkReturn efx_rc_t
1307 __in efx_nic_t *enp);
1311 efx_mac_multicast_hash_compute(
1312 __in_ecount(6*count) uint8_t const *addrs,
1314 __out efx_oword_t *hash_low,
1315 __out efx_oword_t *hash_high);
1318 extern __checkReturn efx_rc_t
1320 __in efx_nic_t *enp);
1325 __in efx_nic_t *enp);
1329 /* VPD utility functions */
1332 extern __checkReturn efx_rc_t
1333 efx_vpd_hunk_length(
1334 __in_bcount(size) caddr_t data,
1336 __out size_t *lengthp);
1339 extern __checkReturn efx_rc_t
1340 efx_vpd_hunk_verify(
1341 __in_bcount(size) caddr_t data,
1343 __out_opt boolean_t *cksummedp);
1346 extern __checkReturn efx_rc_t
1347 efx_vpd_hunk_reinit(
1348 __in_bcount(size) caddr_t data,
1350 __in boolean_t wantpid);
1353 extern __checkReturn efx_rc_t
1355 __in_bcount(size) caddr_t data,
1357 __in efx_vpd_tag_t tag,
1358 __in efx_vpd_keyword_t keyword,
1359 __out unsigned int *payloadp,
1360 __out uint8_t *paylenp);
1363 extern __checkReturn efx_rc_t
1365 __in_bcount(size) caddr_t data,
1367 __out efx_vpd_tag_t *tagp,
1368 __out efx_vpd_keyword_t *keyword,
1369 __out_opt unsigned int *payloadp,
1370 __out_opt uint8_t *paylenp,
1371 __inout unsigned int *contp);
1374 extern __checkReturn efx_rc_t
1376 __in_bcount(size) caddr_t data,
1378 __in efx_vpd_value_t *evvp);
1380 #endif /* EFSYS_OPT_VPD */
1385 extern __checkReturn efx_rc_t
1386 efx_mcdi_set_workaround(
1387 __in efx_nic_t *enp,
1389 __in boolean_t enabled,
1390 __out_opt uint32_t *flagsp);
1393 extern __checkReturn efx_rc_t
1394 efx_mcdi_get_workarounds(
1395 __in efx_nic_t *enp,
1396 __out_opt uint32_t *implementedp,
1397 __out_opt uint32_t *enabledp);
1399 #endif /* EFSYS_OPT_MCDI */
1401 #if EFSYS_OPT_MAC_STATS
1404 * Closed range of stats (i.e. the first and the last are included).
1405 * The last must be greater or equal (if the range is one item only) to
1408 struct efx_mac_stats_range {
1409 efx_mac_stat_t first;
1410 efx_mac_stat_t last;
1413 typedef enum efx_stats_action_e {
1416 EFX_STATS_ENABLE_NOEVENTS,
1417 EFX_STATS_ENABLE_EVENTS,
1419 } efx_stats_action_t;
1423 efx_mac_stats_mask_add_ranges(
1424 __inout_bcount(mask_size) uint32_t *maskp,
1425 __in size_t mask_size,
1426 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp,
1427 __in unsigned int rng_count);
1430 extern __checkReturn efx_rc_t
1432 __in efx_nic_t *enp,
1433 __in uint32_t vport_id,
1434 __in_opt efsys_mem_t *esmp,
1435 __in efx_stats_action_t action,
1436 __in uint16_t period_ms);
1438 #endif /* EFSYS_OPT_MAC_STATS */
1444 #endif /* _SYS_EFX_IMPL_H */