drivers/common/sfc_efx/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2021 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #include "efx_regs_ef100.h"
  14 #if EFSYS_OPT_MCDI
  15 #include "efx_mcdi.h"
  16 #endif  /* EFSYS_OPT_MCDI */
  17
  18 /* FIXME: Add definition for driver generated software events */
  19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  21 #endif
  22
  23
  24 #if EFSYS_OPT_SIENA
  25 #include "siena_impl.h"
  26 #endif  /* EFSYS_OPT_SIENA */
  27
  28 #if EFSYS_OPT_HUNTINGTON
  29 #include "hunt_impl.h"
  30 #endif  /* EFSYS_OPT_HUNTINGTON */
  31
  32 #if EFSYS_OPT_MEDFORD
  33 #include "medford_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD */
  35
  36 #if EFSYS_OPT_MEDFORD2
  37 #include "medford2_impl.h"
  38 #endif  /* EFSYS_OPT_MEDFORD2 */
  39
  40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
  41 #include "ef10_impl.h"
  42 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
  43
  44 #if EFSYS_OPT_RIVERHEAD
  45 #include "rhead_impl.h"
  46 #endif  /* EFSYS_OPT_RIVERHEAD */
  47
  48 #ifdef  __cplusplus
  49 extern "C" {
  50 #endif
  51
  52 #define EFX_MOD_MCDI            0x00000001
  53 #define EFX_MOD_PROBE           0x00000002
  54 #define EFX_MOD_NVRAM           0x00000004
  55 #define EFX_MOD_VPD             0x00000008
  56 #define EFX_MOD_NIC             0x00000010
  57 #define EFX_MOD_INTR            0x00000020
  58 #define EFX_MOD_EV              0x00000040
  59 #define EFX_MOD_RX              0x00000080
  60 #define EFX_MOD_TX              0x00000100
  61 #define EFX_MOD_PORT            0x00000200
  62 #define EFX_MOD_MON             0x00000400
  63 #define EFX_MOD_FILTER          0x00001000
  64 #define EFX_MOD_LIC             0x00002000
  65 #define EFX_MOD_TUNNEL          0x00004000
  66 #define EFX_MOD_EVB             0x00008000
  67 #define EFX_MOD_PROXY           0x00010000
  68 #define EFX_MOD_VIRTIO          0x00020000
  69
  70 #define EFX_RESET_PHY           0x00000001
  71 #define EFX_RESET_RXQ_ERR       0x00000002
  72 #define EFX_RESET_TXQ_ERR       0x00000004
  73 #define EFX_RESET_HW_UNAVAIL    0x00000008
  74
  75 typedef enum efx_mac_type_e {
  76         EFX_MAC_INVALID = 0,
  77         EFX_MAC_SIENA,
  78         EFX_MAC_HUNTINGTON,
  79         EFX_MAC_MEDFORD,
  80         EFX_MAC_MEDFORD2,
  81         EFX_MAC_RIVERHEAD,
  82         EFX_MAC_NTYPES
  83 } efx_mac_type_t;
  84
  85 typedef struct efx_ev_ops_s {
  86         efx_rc_t        (*eevo_init)(efx_nic_t *);
  87         void            (*eevo_fini)(efx_nic_t *);
  88         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  89                                           efsys_mem_t *, size_t, uint32_t,
  90                                           uint32_t, uint32_t, efx_evq_t *);
  91         void            (*eevo_qdestroy)(efx_evq_t *);
  92         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  93         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  94         void            (*eevo_qpoll)(efx_evq_t *, unsigned int *,
  95                                         const efx_ev_callbacks_t *, void *);
  96         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  97 #if EFSYS_OPT_QSTATS
  98         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  99 #endif
 100 } efx_ev_ops_t;
 101
 102 typedef struct efx_tx_ops_s {
 103         efx_rc_t        (*etxo_init)(efx_nic_t *);
 104         void            (*etxo_fini)(efx_nic_t *);
 105         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 106                                         unsigned int, unsigned int,
 107                                         efsys_mem_t *, size_t,
 108                                         uint32_t, uint16_t,
 109                                         efx_evq_t *, efx_txq_t *,
 110                                         unsigned int *);
 111         void            (*etxo_qdestroy)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 113                                       unsigned int, unsigned int,
 114                                       unsigned int *);
 115         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 116         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 117         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 118         void            (*etxo_qenable)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 120         void            (*etxo_qpio_disable)(efx_txq_t *);
 121         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 122                                            size_t);
 123         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 124                                            unsigned int *);
 125         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 126                                       unsigned int, unsigned int,
 127                                       unsigned int *);
 128         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 129                                                 size_t, boolean_t,
 130                                                 efx_desc_t *);
 131         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 132                                                 uint32_t, uint8_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 135                                                 uint16_t, uint32_t, uint16_t,
 136                                                 efx_desc_t *, int);
 137         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 138                                                 efx_desc_t *);
 139         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 140                                                 efx_desc_t *);
 141 #if EFSYS_OPT_QSTATS
 142         void            (*etxo_qstats_update)(efx_txq_t *,
 143                                               efsys_stat_t *);
 144 #endif
 145 } efx_tx_ops_t;
 146
 147 typedef union efx_rxq_type_data_u {
 148         struct {
 149                 size_t          ed_buf_size;
 150         } ertd_default;
 151 #if EFSYS_OPT_RX_PACKED_STREAM
 152         struct {
 153                 uint32_t        eps_buf_size;
 154         } ertd_packed_stream;
 155 #endif
 156 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 157         struct {
 158                 uint32_t        eessb_bufs_per_desc;
 159                 uint32_t        eessb_max_dma_len;
 160                 uint32_t        eessb_buf_stride;
 161                 uint32_t        eessb_hol_block_timeout;
 162         } ertd_es_super_buffer;
 163 #endif
 164 } efx_rxq_type_data_t;
 165
 166 typedef struct efx_rx_ops_s {
 167         efx_rc_t        (*erxo_init)(efx_nic_t *);
 168         void            (*erxo_fini)(efx_nic_t *);
 169 #if EFSYS_OPT_RX_SCATTER
 170         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 171 #endif
 172 #if EFSYS_OPT_RX_SCALE
 173         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 174                                                     efx_rx_scale_context_type_t,
 175                                                     uint32_t, uint32_t *);
 176         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 177         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 178                                                efx_rx_hash_alg_t,
 179                                                efx_rx_hash_type_t, boolean_t);
 180         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 181                                               uint8_t *, size_t);
 182         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 183                                               unsigned int *, size_t);
 184         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 185                                             uint8_t *);
 186 #endif /* EFSYS_OPT_RX_SCALE */
 187         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 188                                               uint16_t *);
 189         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 190                                       unsigned int, unsigned int,
 191                                       unsigned int);
 192         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 193 #if EFSYS_OPT_RX_PACKED_STREAM
 194         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 195         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 196                                                 uint32_t, uint32_t,
 197                                                 uint16_t *, uint32_t *, uint32_t *);
 198 #endif
 199         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 200         void            (*erxo_qenable)(efx_rxq_t *);
 201         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 202                                         unsigned int, efx_rxq_type_t,
 203                                         const efx_rxq_type_data_t *,
 204                                         efsys_mem_t *, size_t, uint32_t,
 205                                         unsigned int,
 206                                         efx_evq_t *, efx_rxq_t *);
 207         void            (*erxo_qdestroy)(efx_rxq_t *);
 208 } efx_rx_ops_t;
 209
 210 typedef struct efx_mac_ops_s {
 211         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 212         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 213         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 214         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 215         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 216         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 217         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 218         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 219                                                       efx_rxq_t *, boolean_t);
 220         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 221 #if EFSYS_OPT_LOOPBACK
 222         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 223                                             efx_loopback_type_t);
 224 #endif  /* EFSYS_OPT_LOOPBACK */
 225 #if EFSYS_OPT_MAC_STATS
 226         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 227         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 228         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 229         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 230                                               uint16_t, boolean_t);
 231         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 232                                             efsys_stat_t *, uint32_t *);
 233 #endif  /* EFSYS_OPT_MAC_STATS */
 234 } efx_mac_ops_t;
 235
 236 typedef struct efx_phy_ops_s {
 237         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 238         efx_rc_t        (*epo_reset)(efx_nic_t *);
 239         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 240         efx_rc_t        (*epo_verify)(efx_nic_t *);
 241         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 242         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 243 #if EFSYS_OPT_PHY_STATS
 244         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 245                                             uint32_t *);
 246 #endif  /* EFSYS_OPT_PHY_STATS */
 247 #if EFSYS_OPT_BIST
 248         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 249         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 250         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 251                                          efx_bist_result_t *, uint32_t *,
 252                                          unsigned long *, size_t);
 253         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 254 #endif  /* EFSYS_OPT_BIST */
 255 } efx_phy_ops_t;
 256
 257 #if EFSYS_OPT_FILTER
 258
 259 /*
 260  * Policy for replacing existing filter when inserting a new one.
 261  * Note that all policies allow for storing the new lower priority
 262  * filters as overridden by existing higher priority ones. It is needed
 263  * to restore the lower priority filters on higher priority ones removal.
 264  */
 265 typedef enum efx_filter_replacement_policy_e {
 266         /* Cannot replace existing filter */
 267         EFX_FILTER_REPLACEMENT_NEVER,
 268         /* Higher priority filters can replace lower priotiry ones */
 269         EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY,
 270         /*
 271          * Higher priority filters can replace lower priority ones and
 272          * equal priority filters can replace each other.
 273          */
 274         EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY,
 275 } efx_filter_replacement_policy_t;
 276
 277 typedef struct efx_filter_ops_s {
 278         efx_rc_t        (*efo_init)(efx_nic_t *);
 279         void            (*efo_fini)(efx_nic_t *);
 280         efx_rc_t        (*efo_restore)(efx_nic_t *);
 281         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 282                                    efx_filter_replacement_policy_t policy);
 283         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 284         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 285                                    size_t, size_t *);
 286         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 287                                    boolean_t, boolean_t, boolean_t,
 288                                    uint8_t const *, uint32_t);
 289 } efx_filter_ops_t;
 290
 291 LIBEFX_INTERNAL
 292 extern  __checkReturn   efx_rc_t
 293 efx_filter_reconfigure(
 294         __in                            efx_nic_t *enp,
 295         __in_ecount(6)                  uint8_t const *mac_addr,
 296         __in                            boolean_t all_unicst,
 297         __in                            boolean_t mulcst,
 298         __in                            boolean_t all_mulcst,
 299         __in                            boolean_t brdcst,
 300         __in_ecount(6*count)            uint8_t const *addrs,
 301         __in                            uint32_t count);
 302
 303 #endif /* EFSYS_OPT_FILTER */
 304
 305 #if EFSYS_OPT_TUNNEL
 306 typedef struct efx_tunnel_ops_s {
 307         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 308         void            (*eto_fini)(efx_nic_t *);
 309 } efx_tunnel_ops_t;
 310 #endif /* EFSYS_OPT_TUNNEL */
 311
 312 #if EFSYS_OPT_VIRTIO
 313 typedef struct efx_virtio_ops_s {
 314         efx_rc_t        (*evo_virtio_qstart)(efx_virtio_vq_t *,
 315                                 efx_virtio_vq_cfg_t *,
 316                                 efx_virtio_vq_dyncfg_t *);
 317         efx_rc_t        (*evo_virtio_qstop)(efx_virtio_vq_t *,
 318                                 efx_virtio_vq_dyncfg_t *);
 319         efx_rc_t        (*evo_get_doorbell_offset)(efx_virtio_vq_t *,
 320                                 uint32_t *);
 321         efx_rc_t        (*evo_get_features)(efx_nic_t *,
 322                                 efx_virtio_device_type_t, uint64_t *);
 323 } efx_virtio_ops_t;
 324 #endif /* EFSYS_OPT_VIRTIO */
 325
 326 typedef struct efx_port_s {
 327         efx_mac_type_t          ep_mac_type;
 328         uint32_t                ep_phy_type;
 329         uint8_t                 ep_port;
 330         uint32_t                ep_mac_pdu;
 331         uint8_t                 ep_mac_addr[6];
 332         efx_link_mode_t         ep_link_mode;
 333         boolean_t               ep_all_unicst;
 334         boolean_t               ep_all_unicst_inserted;
 335         boolean_t               ep_mulcst;
 336         boolean_t               ep_all_mulcst;
 337         boolean_t               ep_all_mulcst_inserted;
 338         boolean_t               ep_brdcst;
 339         unsigned int            ep_fcntl;
 340         boolean_t               ep_fcntl_autoneg;
 341         efx_oword_t             ep_multicst_hash[2];
 342         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 343                                                     EFX_MAC_MULTICAST_LIST_MAX];
 344         uint32_t                ep_mulcst_addr_count;
 345 #if EFSYS_OPT_LOOPBACK
 346         efx_loopback_type_t     ep_loopback_type;
 347         efx_link_mode_t         ep_loopback_link_mode;
 348 #endif  /* EFSYS_OPT_LOOPBACK */
 349 #if EFSYS_OPT_PHY_FLAGS
 350         uint32_t                ep_phy_flags;
 351 #endif  /* EFSYS_OPT_PHY_FLAGS */
 352 #if EFSYS_OPT_PHY_LED_CONTROL
 353         efx_phy_led_mode_t      ep_phy_led_mode;
 354 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 355         efx_phy_media_type_t    ep_fixed_port_type;
 356         efx_phy_media_type_t    ep_module_type;
 357         uint32_t                ep_adv_cap_mask;
 358         uint32_t                ep_lp_cap_mask;
 359         uint32_t                ep_default_adv_cap_mask;
 360         uint32_t                ep_phy_cap_mask;
 361         boolean_t               ep_mac_drain;
 362 #if EFSYS_OPT_BIST
 363         efx_bist_type_t         ep_current_bist;
 364 #endif
 365         const efx_mac_ops_t     *ep_emop;
 366         const efx_phy_ops_t     *ep_epop;
 367 } efx_port_t;
 368
 369 typedef struct efx_mon_ops_s {
 370 #if EFSYS_OPT_MON_STATS
 371         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 372                                             efx_mon_stat_value_t *);
 373         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 374                                              efx_mon_stat_limits_t *);
 375 #endif  /* EFSYS_OPT_MON_STATS */
 376 } efx_mon_ops_t;
 377
 378 typedef struct efx_mon_s {
 379         efx_mon_type_t          em_type;
 380         const efx_mon_ops_t     *em_emop;
 381 } efx_mon_t;
 382
 383 typedef struct efx_intr_ops_s {
 384         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 385         void            (*eio_enable)(efx_nic_t *);
 386         void            (*eio_disable)(efx_nic_t *);
 387         void            (*eio_disable_unlocked)(efx_nic_t *);
 388         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 389         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 390         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 391                                  boolean_t *);
 392         void            (*eio_fatal)(efx_nic_t *);
 393         void            (*eio_fini)(efx_nic_t *);
 394 } efx_intr_ops_t;
 395
 396 typedef struct efx_intr_s {
 397         const efx_intr_ops_t    *ei_eiop;
 398         efsys_mem_t             *ei_esmp;
 399         efx_intr_type_t         ei_type;
 400         unsigned int            ei_level;
 401 } efx_intr_t;
 402
 403 typedef struct efx_nic_ops_s {
 404         efx_rc_t        (*eno_probe)(efx_nic_t *);
 405         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 406         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 407         efx_rc_t        (*eno_reset)(efx_nic_t *);
 408         efx_rc_t        (*eno_init)(efx_nic_t *);
 409         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 410         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 411                                         uint32_t *, size_t *);
 412         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 413         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 414 #if EFSYS_OPT_DIAG
 415         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 416 #endif  /* EFSYS_OPT_DIAG */
 417         void            (*eno_fini)(efx_nic_t *);
 418         void            (*eno_unprobe)(efx_nic_t *);
 419 } efx_nic_ops_t;
 420
 421 #ifndef EFX_TXQ_LIMIT_TARGET
 422 #define EFX_TXQ_LIMIT_TARGET 259
 423 #endif
 424 #ifndef EFX_RXQ_LIMIT_TARGET
 425 #define EFX_RXQ_LIMIT_TARGET 512
 426 #endif
 427
 428
 429 #if EFSYS_OPT_FILTER
 430
 431 #if EFSYS_OPT_SIENA
 432
 433 typedef struct siena_filter_spec_s {
 434         uint8_t         sfs_type;
 435         uint32_t        sfs_flags;
 436         uint32_t        sfs_dmaq_id;
 437         uint32_t        sfs_dword[3];
 438 } siena_filter_spec_t;
 439
 440 typedef enum siena_filter_type_e {
 441         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 442         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 443         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 444         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 445         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 446         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 447
 448         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 449         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 450         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 451         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 452         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 453         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 454
 455         EFX_SIENA_FILTER_NTYPES
 456 } siena_filter_type_t;
 457
 458 typedef enum siena_filter_tbl_id_e {
 459         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 460         EFX_SIENA_FILTER_TBL_RX_MAC,
 461         EFX_SIENA_FILTER_TBL_TX_IP,
 462         EFX_SIENA_FILTER_TBL_TX_MAC,
 463         EFX_SIENA_FILTER_NTBLS
 464 } siena_filter_tbl_id_t;
 465
 466 typedef struct siena_filter_tbl_s {
 467         int                     sft_size;       /* number of entries */
 468         int                     sft_used;       /* active count */
 469         uint32_t                *sft_bitmap;    /* active bitmap */
 470         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 471 } siena_filter_tbl_t;
 472
 473 typedef struct siena_filter_s {
 474         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 475         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 476 } siena_filter_t;
 477
 478 #endif  /* EFSYS_OPT_SIENA */
 479
 480 typedef struct efx_filter_s {
 481 #if EFSYS_OPT_SIENA
 482         siena_filter_t          *ef_siena_filter;
 483 #endif /* EFSYS_OPT_SIENA */
 484 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 485         ef10_filter_table_t     *ef_ef10_filter_table;
 486 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 487 } efx_filter_t;
 488
 489 #if EFSYS_OPT_SIENA
 490
 491 LIBEFX_INTERNAL
 492 extern                  void
 493 siena_filter_tbl_clear(
 494         __in            efx_nic_t *enp,
 495         __in            siena_filter_tbl_id_t tbl);
 496
 497 #endif  /* EFSYS_OPT_SIENA */
 498
 499 #endif  /* EFSYS_OPT_FILTER */
 500
 501 #if EFSYS_OPT_MCDI
 502
 503 #define EFX_TUNNEL_MAXNENTRIES  (16)
 504
 505 #if EFSYS_OPT_TUNNEL
 506
 507 /* State of a UDP tunnel table entry */
 508 typedef enum efx_tunnel_udp_entry_state_e {
 509         EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */
 510         EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */
 511         EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */
 512 } efx_tunnel_udp_entry_state_t;
 513
 514 #if EFSYS_OPT_RIVERHEAD
 515 typedef uint32_t        efx_vnic_encap_rule_handle_t;
 516 #endif /* EFSYS_OPT_RIVERHEAD */
 517
 518 typedef struct efx_tunnel_udp_entry_s {
 519         uint16_t                        etue_port; /* host/cpu-endian */
 520         uint16_t                        etue_protocol;
 521         boolean_t                       etue_busy;
 522         efx_tunnel_udp_entry_state_t    etue_state;
 523 #if EFSYS_OPT_RIVERHEAD
 524         efx_vnic_encap_rule_handle_t    etue_handle;
 525 #endif /* EFSYS_OPT_RIVERHEAD */
 526 } efx_tunnel_udp_entry_t;
 527
 528 typedef struct efx_tunnel_cfg_s {
 529         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 530         unsigned int            etc_udp_entries_num;
 531 } efx_tunnel_cfg_t;
 532
 533 #endif /* EFSYS_OPT_TUNNEL */
 534
 535 typedef struct efx_mcdi_ops_s {
 536         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 537         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 538                                         void *, size_t);
 539         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 540         boolean_t       (*emco_poll_response)(efx_nic_t *);
 541         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 542         void            (*emco_fini)(efx_nic_t *);
 543         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 544                                             efx_mcdi_feature_id_t, boolean_t *);
 545         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 546                                             uint32_t *);
 547 } efx_mcdi_ops_t;
 548
 549 typedef struct efx_mcdi_s {
 550         const efx_mcdi_ops_t            *em_emcop;
 551         const efx_mcdi_transport_t      *em_emtp;
 552         efx_mcdi_iface_t                em_emip;
 553 } efx_mcdi_t;
 554
 555 #endif /* EFSYS_OPT_MCDI */
 556
 557 #if EFSYS_OPT_NVRAM
 558
 559 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 560 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 561
 562 typedef struct efx_nvram_ops_s {
 563 #if EFSYS_OPT_DIAG
 564         efx_rc_t        (*envo_test)(efx_nic_t *);
 565 #endif  /* EFSYS_OPT_DIAG */
 566         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 567                                             uint32_t *);
 568         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 569                                             efx_nvram_info_t *);
 570         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 571         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 572                                             unsigned int, caddr_t, size_t);
 573         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 574                                             unsigned int, caddr_t, size_t);
 575         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 576                                             unsigned int, size_t);
 577         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 578                                             unsigned int, caddr_t, size_t);
 579         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 580                                             uint32_t *);
 581         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 582                                             uint32_t *, uint16_t *);
 583         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 584                                             uint16_t *);
 585         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 586                                             caddr_t, size_t);
 587 } efx_nvram_ops_t;
 588 #endif /* EFSYS_OPT_NVRAM */
 589
 590 #if EFSYS_OPT_VPD
 591 typedef struct efx_vpd_ops_s {
 592         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 593         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 594         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 595         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 596         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 597         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 598                                         efx_vpd_value_t *);
 599         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 600                                         efx_vpd_value_t *);
 601         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 602                                         efx_vpd_value_t *, unsigned int *);
 603         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 604         void            (*evpdo_fini)(efx_nic_t *);
 605 } efx_vpd_ops_t;
 606 #endif  /* EFSYS_OPT_VPD */
 607
 608 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 609
 610 LIBEFX_INTERNAL
 611 extern  __checkReturn           efx_rc_t
 612 efx_mcdi_nvram_partitions(
 613         __in                    efx_nic_t *enp,
 614         __out_bcount(size)      caddr_t data,
 615         __in                    size_t size,
 616         __out                   unsigned int *npartnp);
 617
 618 LIBEFX_INTERNAL
 619 extern  __checkReturn           efx_rc_t
 620 efx_mcdi_nvram_metadata(
 621         __in                    efx_nic_t *enp,
 622         __in                    uint32_t partn,
 623         __out                   uint32_t *subtypep,
 624         __out_ecount(4)         uint16_t version[4],
 625         __out_bcount_opt(size)  char *descp,
 626         __in                    size_t size);
 627
 628 LIBEFX_INTERNAL
 629 extern  __checkReturn           efx_rc_t
 630 efx_mcdi_nvram_info(
 631         __in                    efx_nic_t *enp,
 632         __in                    uint32_t partn,
 633         __out                   efx_nvram_info_t *eni);
 634
 635 LIBEFX_INTERNAL
 636 extern  __checkReturn           efx_rc_t
 637 efx_mcdi_nvram_update_start(
 638         __in                    efx_nic_t *enp,
 639         __in                    uint32_t partn);
 640
 641 LIBEFX_INTERNAL
 642 extern  __checkReturn           efx_rc_t
 643 efx_mcdi_nvram_read(
 644         __in                    efx_nic_t *enp,
 645         __in                    uint32_t partn,
 646         __in                    uint32_t offset,
 647         __out_bcount(size)      caddr_t data,
 648         __in                    size_t size,
 649         __in                    uint32_t mode);
 650
 651 LIBEFX_INTERNAL
 652 extern  __checkReturn           efx_rc_t
 653 efx_mcdi_nvram_erase(
 654         __in                    efx_nic_t *enp,
 655         __in                    uint32_t partn,
 656         __in                    uint32_t offset,
 657         __in                    size_t size);
 658
 659 LIBEFX_INTERNAL
 660 extern  __checkReturn           efx_rc_t
 661 efx_mcdi_nvram_write(
 662         __in                    efx_nic_t *enp,
 663         __in                    uint32_t partn,
 664         __in                    uint32_t offset,
 665         __in_bcount(size)       caddr_t data,
 666         __in                    size_t size);
 667
 668 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 669 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 670
 671 LIBEFX_INTERNAL
 672 extern  __checkReturn           efx_rc_t
 673 efx_mcdi_nvram_update_finish(
 674         __in                    efx_nic_t *enp,
 675         __in                    uint32_t partn,
 676         __in                    boolean_t reboot,
 677         __in                    uint32_t flags,
 678         __out_opt               uint32_t *verify_resultp);
 679
 680 #if EFSYS_OPT_DIAG
 681
 682 LIBEFX_INTERNAL
 683 extern  __checkReturn           efx_rc_t
 684 efx_mcdi_nvram_test(
 685         __in                    efx_nic_t *enp,
 686         __in                    uint32_t partn);
 687
 688 #endif  /* EFSYS_OPT_DIAG */
 689
 690 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 691
 692 #if EFSYS_OPT_LICENSING
 693
 694 typedef struct efx_lic_ops_s {
 695         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 696         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 697         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 698         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 699                                       size_t *, uint8_t *);
 700         efx_rc_t        (*elo_find_start)
 701                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 702         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 703                                 uint32_t, uint32_t *);
 704         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 705                                 uint32_t, uint32_t *, uint32_t *);
 706         boolean_t       (*elo_validate_key)(efx_nic_t *,
 707                                 caddr_t, uint32_t);
 708         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 709                                 caddr_t, size_t, uint32_t, uint32_t,
 710                                 caddr_t, size_t, uint32_t *);
 711         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 712                                 caddr_t, size_t, uint32_t,
 713                                 caddr_t, uint32_t, uint32_t *);
 714         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 715                                 caddr_t, size_t, uint32_t,
 716                                 uint32_t, uint32_t, uint32_t *);
 717         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 718                                 caddr_t, size_t);
 719         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 720                                 caddr_t, size_t);
 721 } efx_lic_ops_t;
 722
 723 #endif
 724
 725 #if EFSYS_OPT_EVB
 726
 727 struct efx_vswitch_s {
 728         efx_nic_t               *ev_enp;
 729         efx_vswitch_id_t        ev_vswitch_id;
 730         uint32_t                ev_num_vports;
 731         /*
 732          * Vport configuration array: index 0 to store PF configuration
 733          * and next ev_num_vports-1 entries hold VFs configuration.
 734          */
 735         efx_vport_config_t      *ev_evcp;
 736 };
 737
 738 typedef struct efx_evb_ops_s {
 739         efx_rc_t        (*eeo_init)(efx_nic_t *);
 740         void            (*eeo_fini)(efx_nic_t *);
 741         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 742         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 743         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 744                                                 efx_vport_type_t, uint16_t,
 745                                                 boolean_t, efx_vport_id_t *);
 746         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 747                                                 efx_vport_id_t);
 748         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 749                                                 efx_vport_id_t, uint8_t *);
 750         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 751                                                 efx_vport_id_t, uint8_t *);
 752         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 753                                                 efx_vport_id_t);
 754         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 755                                                 efx_vport_id_t);
 756         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 757                                                 efx_vport_id_t, uint32_t);
 758         efx_rc_t        (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
 759                                                         efx_vport_id_t,
 760                                                         uint16_t *, uint8_t *,
 761                                                         boolean_t *);
 762         efx_rc_t        (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
 763                                                 efx_vport_id_t, efsys_mem_t *);
 764 } efx_evb_ops_t;
 765
 766 LIBEFX_INTERNAL
 767 extern __checkReturn    boolean_t
 768 efx_is_zero_eth_addr(
 769         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 770
 771 #endif /* EFSYS_OPT_EVB */
 772
 773 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 774
 775 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 776
 777
 778 typedef struct efx_proxy_ops_s {
 779         efx_rc_t        (*epo_init)(efx_nic_t *);
 780         void            (*epo_fini)(efx_nic_t *);
 781         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 782                                         efsys_mem_t *, efsys_mem_t *,
 783                                         uint32_t, uint32_t *, size_t);
 784         efx_rc_t        (*epo_disable)(efx_nic_t *);
 785         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 786                                         uint32_t, uint32_t, uint32_t);
 787         efx_rc_t        (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
 788                                         uint32_t, uint32_t);
 789         efx_rc_t        (*epo_complete_request)(efx_nic_t *, uint32_t,
 790                                         uint32_t, uint32_t);
 791         efx_rc_t        (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
 792         efx_rc_t        (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
 793                                         uint32_t, uint32_t *);
 794 } efx_proxy_ops_t;
 795
 796 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 797
 798 #if EFSYS_OPT_MAE
 799
 800 typedef struct efx_mae_field_cap_s {
 801         uint32_t                        emfc_support;
 802         boolean_t                       emfc_mask_affects_class;
 803         boolean_t                       emfc_match_affects_class;
 804 } efx_mae_field_cap_t;
 805
 806 typedef struct efx_mae_s {
 807         uint32_t                        em_max_n_action_prios;
 808         /*
 809          * The number of MAE field IDs recognised by the FW implementation.
 810          * Any field ID greater than or equal to this value is unsupported.
 811          */
 812         uint32_t                        em_max_nfields;
 813         /** Action rule match field capabilities. */
 814         efx_mae_field_cap_t             *em_action_rule_field_caps;
 815         size_t                          em_action_rule_field_caps_size;
 816         uint32_t                        em_max_n_outer_prios;
 817         uint32_t                        em_encap_types_supported;
 818         /** Outer rule match field capabilities. */
 819         efx_mae_field_cap_t             *em_outer_rule_field_caps;
 820         size_t                          em_outer_rule_field_caps_size;
 821 } efx_mae_t;
 822
 823 #endif /* EFSYS_OPT_MAE */
 824
 825 #define EFX_DRV_VER_MAX         20
 826
 827 typedef struct efx_drv_cfg_s {
 828         uint32_t                edc_min_vi_count;
 829         uint32_t                edc_max_vi_count;
 830
 831         uint32_t                edc_max_piobuf_count;
 832         uint32_t                edc_pio_alloc_size;
 833 } efx_drv_cfg_t;
 834
 835 struct efx_nic_s {
 836         uint32_t                en_magic;
 837         efx_family_t            en_family;
 838         uint32_t                en_features;
 839         efsys_identifier_t      *en_esip;
 840         efsys_lock_t            *en_eslp;
 841         efsys_bar_t             *en_esbp;
 842         unsigned int            en_mod_flags;
 843         unsigned int            en_reset_flags;
 844         efx_nic_cfg_t           en_nic_cfg;
 845         efx_drv_cfg_t           en_drv_cfg;
 846         efx_port_t              en_port;
 847         efx_mon_t               en_mon;
 848         efx_intr_t              en_intr;
 849         uint32_t                en_ev_qcount;
 850         uint32_t                en_rx_qcount;
 851         uint32_t                en_tx_qcount;
 852         const efx_nic_ops_t     *en_enop;
 853         const efx_ev_ops_t      *en_eevop;
 854         const efx_tx_ops_t      *en_etxop;
 855         const efx_rx_ops_t      *en_erxop;
 856         efx_fw_variant_t        efv;
 857         char                    en_drv_version[EFX_DRV_VER_MAX];
 858 #if EFSYS_OPT_FILTER
 859         efx_filter_t            en_filter;
 860         const efx_filter_ops_t  *en_efop;
 861 #endif  /* EFSYS_OPT_FILTER */
 862 #if EFSYS_OPT_TUNNEL
 863         efx_tunnel_cfg_t        en_tunnel_cfg;
 864         const efx_tunnel_ops_t  *en_etop;
 865 #endif /* EFSYS_OPT_TUNNEL */
 866 #if EFSYS_OPT_MCDI
 867         efx_mcdi_t              en_mcdi;
 868 #endif  /* EFSYS_OPT_MCDI */
 869 #if EFSYS_OPT_NVRAM
 870         uint32_t                en_nvram_partn_locked;
 871         const efx_nvram_ops_t   *en_envop;
 872 #endif  /* EFSYS_OPT_NVRAM */
 873 #if EFSYS_OPT_VPD
 874         const efx_vpd_ops_t     *en_evpdop;
 875 #endif  /* EFSYS_OPT_VPD */
 876 #if EFSYS_OPT_VIRTIO
 877         const efx_virtio_ops_t  *en_evop;
 878 #endif  /* EFSYS_OPT_VPD */
 879 #if EFSYS_OPT_RX_SCALE
 880         efx_rx_hash_support_t           en_hash_support;
 881         efx_rx_scale_context_type_t     en_rss_context_type;
 882         uint32_t                        en_rss_context;
 883 #endif  /* EFSYS_OPT_RX_SCALE */
 884         uint32_t                en_vport_id;
 885 #if EFSYS_OPT_LICENSING
 886         const efx_lic_ops_t     *en_elop;
 887         boolean_t               en_licensing_supported;
 888 #endif
 889         union {
 890 #if EFSYS_OPT_SIENA
 891                 struct {
 892 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 893                         unsigned int            enu_partn_mask;
 894 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 895 #if EFSYS_OPT_VPD
 896                         caddr_t                 enu_svpd;
 897                         size_t                  enu_svpd_length;
 898 #endif  /* EFSYS_OPT_VPD */
 899                         int                     enu_unused;
 900                 } siena;
 901 #endif  /* EFSYS_OPT_SIENA */
 902                 int     enu_unused;
 903         } en_u;
 904 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 905         union en_arch {
 906                 struct {
 907                         int                     ena_vi_base;
 908                         int                     ena_vi_count;
 909                         int                     ena_vi_shift;
 910                         uint32_t                ena_fcw_base;
 911 #if EFSYS_OPT_VPD
 912                         caddr_t                 ena_svpd;
 913                         size_t                  ena_svpd_length;
 914 #endif  /* EFSYS_OPT_VPD */
 915                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 916                         uint32_t                ena_piobuf_count;
 917                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 918                         uint32_t                ena_pio_write_vi_base;
 919                         /* Memory BAR mapping regions */
 920                         uint32_t                ena_uc_mem_map_offset;
 921                         size_t                  ena_uc_mem_map_size;
 922                         uint32_t                ena_wc_mem_map_offset;
 923                         size_t                  ena_wc_mem_map_size;
 924                 } ef10;
 925         } en_arch;
 926 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 927 #if EFSYS_OPT_EVB
 928         const efx_evb_ops_t     *en_eeop;
 929         struct efx_vswitch_s    *en_vswitchp;
 930 #endif  /* EFSYS_OPT_EVB */
 931 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 932         const efx_proxy_ops_t   *en_epop;
 933 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 934 #if EFSYS_OPT_MAE
 935         efx_mae_t               *en_maep;
 936 #endif  /* EFSYS_OPT_MAE */
 937 };
 938
 939 #define EFX_FAMILY_IS_EF10(_enp) \
 940         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 941          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 942          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 943
 944 #define EFX_FAMILY_IS_EF100(_enp) \
 945         ((_enp)->en_family == EFX_FAMILY_RIVERHEAD)
 946
 947
 948 #define EFX_NIC_MAGIC   0x02121996
 949
 950 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 951     const efx_ev_callbacks_t *, void *);
 952
 953 #if EFSYS_OPT_EV_EXTENDED_WIDTH
 954 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *,
 955     const efx_ev_callbacks_t *, void *);
 956 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */
 957
 958 typedef struct efx_evq_rxq_state_s {
 959         unsigned int                    eers_rx_read_ptr;
 960         unsigned int                    eers_rx_mask;
 961 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 962         unsigned int                    eers_rx_stream_npackets;
 963         boolean_t                       eers_rx_packed_stream;
 964 #endif
 965 #if EFSYS_OPT_RX_PACKED_STREAM
 966         unsigned int                    eers_rx_packed_stream_credits;
 967 #endif
 968 } efx_evq_rxq_state_t;
 969
 970 struct efx_evq_s {
 971         uint32_t                        ee_magic;
 972         uint32_t                        ee_flags;
 973         efx_nic_t                       *ee_enp;
 974         unsigned int                    ee_index;
 975         unsigned int                    ee_mask;
 976         efsys_mem_t                     *ee_esmp;
 977 #if EFSYS_OPT_QSTATS
 978         uint32_t                        ee_stat[EV_NQSTATS];
 979 #endif  /* EFSYS_OPT_QSTATS */
 980
 981         efx_ev_handler_t                ee_rx;
 982         efx_ev_handler_t                ee_tx;
 983         efx_ev_handler_t                ee_driver;
 984         efx_ev_handler_t                ee_global;
 985         efx_ev_handler_t                ee_drv_gen;
 986 #if EFSYS_OPT_MCDI
 987         efx_ev_handler_t                ee_mcdi;
 988 #endif  /* EFSYS_OPT_MCDI */
 989
 990 #if EFSYS_OPT_DESC_PROXY
 991         efx_ev_ew_handler_t             ee_ew_txq_desc;
 992         efx_ev_ew_handler_t             ee_ew_virtq_desc;
 993 #endif /* EFSYS_OPT_DESC_PROXY */
 994
 995         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 996 };
 997
 998 #define EFX_EVQ_MAGIC   0x08081997
 999
1000 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
1001
1002 #if EFSYS_OPT_QSTATS
1003 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
1004         do {                                                            \
1005                 (_eep)->ee_stat[_stat]++;                               \
1006         _NOTE(CONSTANTCONDITION)                                        \
1007         } while (B_FALSE)
1008 #else
1009 #define EFX_EV_QSTAT_INCR(_eep, _stat)
1010 #endif
1011
1012 struct efx_rxq_s {
1013         uint32_t                        er_magic;
1014         efx_nic_t                       *er_enp;
1015         efx_evq_t                       *er_eep;
1016         unsigned int                    er_index;
1017         unsigned int                    er_label;
1018         unsigned int                    er_mask;
1019         size_t                          er_buf_size;
1020         efsys_mem_t                     *er_esmp;
1021         efx_evq_rxq_state_t             *er_ev_qstate;
1022         efx_rx_prefix_layout_t          er_prefix_layout;
1023 };
1024
1025 #define EFX_RXQ_MAGIC   0x15022005
1026
1027 struct efx_txq_s {
1028         uint32_t                        et_magic;
1029         efx_nic_t                       *et_enp;
1030         unsigned int                    et_index;
1031         unsigned int                    et_mask;
1032         efsys_mem_t                     *et_esmp;
1033 #if EFSYS_OPT_HUNTINGTON
1034         uint32_t                        et_pio_bufnum;
1035         uint32_t                        et_pio_blknum;
1036         uint32_t                        et_pio_write_offset;
1037         uint32_t                        et_pio_offset;
1038         size_t                          et_pio_size;
1039 #endif
1040 #if EFSYS_OPT_QSTATS
1041         uint32_t                        et_stat[TX_NQSTATS];
1042 #endif  /* EFSYS_OPT_QSTATS */
1043 };
1044
1045 #define EFX_TXQ_MAGIC   0x05092005
1046
1047 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
1048         do {                                                            \
1049                 (_dst)[0] = (_src)[0];                                  \
1050                 (_dst)[1] = (_src)[1];                                  \
1051                 (_dst)[2] = (_src)[2];                                  \
1052                 (_dst)[3] = (_src)[3];                                  \
1053                 (_dst)[4] = (_src)[4];                                  \
1054                 (_dst)[5] = (_src)[5];                                  \
1055         _NOTE(CONSTANTCONDITION)                                        \
1056         } while (B_FALSE)
1057
1058 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
1059         do {                                                            \
1060                 uint16_t *_d = (uint16_t *)(_dst);                      \
1061                 _d[0] = 0xffff;                                         \
1062                 _d[1] = 0xffff;                                         \
1063                 _d[2] = 0xffff;                                         \
1064         _NOTE(CONSTANTCONDITION)                                        \
1065         } while (B_FALSE)
1066
1067 #if EFSYS_OPT_CHECK_REG
1068 #define EFX_CHECK_REG(_enp, _reg)                                       \
1069         do {                                                            \
1070                 const char *name = #_reg;                               \
1071                 char min = name[4];                                     \
1072                 char max = name[5];                                     \
1073                 char rev;                                               \
1074                                                                         \
1075                 switch ((_enp)->en_family) {                            \
1076                 case EFX_FAMILY_SIENA:                                  \
1077                         rev = 'C';                                      \
1078                         break;                                          \
1079                                                                         \
1080                 case EFX_FAMILY_HUNTINGTON:                             \
1081                         rev = 'D';                                      \
1082                         break;                                          \
1083                                                                         \
1084                 case EFX_FAMILY_MEDFORD:                                \
1085                         rev = 'E';                                      \
1086                         break;                                          \
1087                                                                         \
1088                 case EFX_FAMILY_MEDFORD2:                               \
1089                         rev = 'F';                                      \
1090                         break;                                          \
1091                                                                         \
1092                 case EFX_FAMILY_RIVERHEAD:                              \
1093                         rev = 'G';                                      \
1094                         break;                                          \
1095                                                                         \
1096                 default:                                                \
1097                         rev = '?';                                      \
1098                         break;                                          \
1099                 }                                                       \
1100                                                                         \
1101                 EFSYS_ASSERT3S(rev, >=, min);                           \
1102                 EFSYS_ASSERT3S(rev, <=, max);                           \
1103                                                                         \
1104         _NOTE(CONSTANTCONDITION)                                        \
1105         } while (B_FALSE)
1106 #else
1107 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
1108         _NOTE(CONSTANTCONDITION)                                        \
1109         } while (B_FALSE)
1110 #endif
1111
1112 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
1113         do {                                                            \
1114                 EFX_CHECK_REG((_enp), (_reg));                          \
1115                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
1116                     (_edp), (_lock));                                   \
1117                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
1118                     uint32_t, _reg ## _OFST,                            \
1119                     uint32_t, (_edp)->ed_u32[0]);                       \
1120         _NOTE(CONSTANTCONDITION)                                        \
1121         } while (B_FALSE)
1122
1123 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
1124         do {                                                            \
1125                 EFX_CHECK_REG((_enp), (_reg));                          \
1126                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
1127                     uint32_t, _reg ## _OFST,                            \
1128                     uint32_t, (_edp)->ed_u32[0]);                       \
1129                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
1130                     (_edp), (_lock));                                   \
1131         _NOTE(CONSTANTCONDITION)                                        \
1132         } while (B_FALSE)
1133
1134 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
1135         do {                                                            \
1136                 EFX_CHECK_REG((_enp), (_reg));                          \
1137                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1138                     (_eqp));                                            \
1139                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1140                     uint32_t, _reg ## _OFST,                            \
1141                     uint32_t, (_eqp)->eq_u32[1],                        \
1142                     uint32_t, (_eqp)->eq_u32[0]);                       \
1143         _NOTE(CONSTANTCONDITION)                                        \
1144         } while (B_FALSE)
1145
1146 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1147         do {                                                            \
1148                 EFX_CHECK_REG((_enp), (_reg));                          \
1149                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1150                     uint32_t, _reg ## _OFST,                            \
1151                     uint32_t, (_eqp)->eq_u32[1],                        \
1152                     uint32_t, (_eqp)->eq_u32[0]);                       \
1153                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1154                     (_eqp));                                            \
1155         _NOTE(CONSTANTCONDITION)                                        \
1156         } while (B_FALSE)
1157
1158 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1159         do {                                                            \
1160                 EFX_CHECK_REG((_enp), (_reg));                          \
1161                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1162                     (_eop), B_TRUE);                                    \
1163                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1164                     uint32_t, _reg ## _OFST,                            \
1165                     uint32_t, (_eop)->eo_u32[3],                        \
1166                     uint32_t, (_eop)->eo_u32[2],                        \
1167                     uint32_t, (_eop)->eo_u32[1],                        \
1168                     uint32_t, (_eop)->eo_u32[0]);                       \
1169         _NOTE(CONSTANTCONDITION)                                        \
1170         } while (B_FALSE)
1171
1172 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1173         do {                                                            \
1174                 EFX_CHECK_REG((_enp), (_reg));                          \
1175                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1176                     uint32_t, _reg ## _OFST,                            \
1177                     uint32_t, (_eop)->eo_u32[3],                        \
1178                     uint32_t, (_eop)->eo_u32[2],                        \
1179                     uint32_t, (_eop)->eo_u32[1],                        \
1180                     uint32_t, (_eop)->eo_u32[0]);                       \
1181                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1182                     (_eop), B_TRUE);                                    \
1183         _NOTE(CONSTANTCONDITION)                                        \
1184         } while (B_FALSE)
1185
1186 /*
1187  * Accessors for memory BAR non-VI tables.
1188  *
1189  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1190  * to ensure the correct runtime VI window size is used on Medford2.
1191  *
1192  * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control
1193  * window registers, to ensure the correct starting offset is used.
1194  *
1195  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1196  */
1197
1198 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1199         do {                                                            \
1200                 EFX_CHECK_REG((_enp), (_reg));                          \
1201                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1202                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1203                     (_edp), (_lock));                                   \
1204                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1205                     uint32_t, (_index),                                 \
1206                     uint32_t, _reg ## _OFST,                            \
1207                     uint32_t, (_edp)->ed_u32[0]);                       \
1208         _NOTE(CONSTANTCONDITION)                                        \
1209         } while (B_FALSE)
1210
1211 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1212         do {                                                            \
1213                 EFX_CHECK_REG((_enp), (_reg));                          \
1214                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1215                     uint32_t, (_index),                                 \
1216                     uint32_t, _reg ## _OFST,                            \
1217                     uint32_t, (_edp)->ed_u32[0]);                       \
1218                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1219                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1220                     (_edp), (_lock));                                   \
1221         _NOTE(CONSTANTCONDITION)                                        \
1222         } while (B_FALSE)
1223
1224 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1225         do {                                                            \
1226                 EFX_CHECK_REG((_enp), (_reg));                          \
1227                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1228                     uint32_t, (_index),                                 \
1229                     uint32_t, _reg ## _OFST,                            \
1230                     uint32_t, (_edp)->ed_u32[0]);                       \
1231                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1232                     (_reg ## _OFST +                                    \
1233                     (3 * sizeof (efx_dword_t)) +                        \
1234                     ((_index) * _reg ## _STEP)),                        \
1235                     (_edp), (_lock));                                   \
1236         _NOTE(CONSTANTCONDITION)                                        \
1237         } while (B_FALSE)
1238
1239 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1240         do {                                                            \
1241                 EFX_CHECK_REG((_enp), (_reg));                          \
1242                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1243                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1244                     (_eqp));                                            \
1245                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1246                     uint32_t, (_index),                                 \
1247                     uint32_t, _reg ## _OFST,                            \
1248                     uint32_t, (_eqp)->eq_u32[1],                        \
1249                     uint32_t, (_eqp)->eq_u32[0]);                       \
1250         _NOTE(CONSTANTCONDITION)                                        \
1251         } while (B_FALSE)
1252
1253 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1254         do {                                                            \
1255                 EFX_CHECK_REG((_enp), (_reg));                          \
1256                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1257                     uint32_t, (_index),                                 \
1258                     uint32_t, _reg ## _OFST,                            \
1259                     uint32_t, (_eqp)->eq_u32[1],                        \
1260                     uint32_t, (_eqp)->eq_u32[0]);                       \
1261                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1262                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1263                     (_eqp));                                            \
1264         _NOTE(CONSTANTCONDITION)                                        \
1265         } while (B_FALSE)
1266
1267 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1268         do {                                                            \
1269                 EFX_CHECK_REG((_enp), (_reg));                          \
1270                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1271                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1272                     (_eop), (_lock));                                   \
1273                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1274                     uint32_t, (_index),                                 \
1275                     uint32_t, _reg ## _OFST,                            \
1276                     uint32_t, (_eop)->eo_u32[3],                        \
1277                     uint32_t, (_eop)->eo_u32[2],                        \
1278                     uint32_t, (_eop)->eo_u32[1],                        \
1279                     uint32_t, (_eop)->eo_u32[0]);                       \
1280         _NOTE(CONSTANTCONDITION)                                        \
1281         } while (B_FALSE)
1282
1283 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1284         do {                                                            \
1285                 EFX_CHECK_REG((_enp), (_reg));                          \
1286                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1287                     uint32_t, (_index),                                 \
1288                     uint32_t, _reg ## _OFST,                            \
1289                     uint32_t, (_eop)->eo_u32[3],                        \
1290                     uint32_t, (_eop)->eo_u32[2],                        \
1291                     uint32_t, (_eop)->eo_u32[1],                        \
1292                     uint32_t, (_eop)->eo_u32[0]);                       \
1293                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1294                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1295                     (_eop), (_lock));                                   \
1296         _NOTE(CONSTANTCONDITION)                                        \
1297         } while (B_FALSE)
1298
1299 /*
1300  * Accessors for memory BAR function control window registers.
1301  *
1302  * The function control window is located at an offset which can be
1303  * non-zero in case of Riverhead.
1304  */
1305
1306 #if EFSYS_OPT_RIVERHEAD
1307
1308 #define EFX_BAR_FCW_READD(_enp, _reg, _edp)                             \
1309         do {                                                            \
1310                 EFX_CHECK_REG((_enp), (_reg));                          \
1311                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST +        \
1312                     (_enp)->en_arch.ef10.ena_fcw_base,                  \
1313                     (_edp), B_FALSE);                                   \
1314                 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg,    \
1315                     uint32_t, _reg ## _OFST,                            \
1316                     uint32_t, (_edp)->ed_u32[0]);                       \
1317         _NOTE(CONSTANTCONDITION)                                        \
1318         } while (B_FALSE)
1319
1320 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp)                            \
1321         do {                                                            \
1322                 EFX_CHECK_REG((_enp), (_reg));                          \
1323                 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg,   \
1324                     uint32_t, _reg ## _OFST,                            \
1325                     uint32_t, (_edp)->ed_u32[0]);                       \
1326                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST +       \
1327                     (_enp)->en_arch.ef10.ena_fcw_base,                  \
1328                     (_edp), B_FALSE);                                   \
1329         _NOTE(CONSTANTCONDITION)                                        \
1330         } while (B_FALSE)
1331
1332 #endif  /* EFSYS_OPT_RIVERHEAD */
1333
1334 /*
1335  * Accessors for memory BAR per-VI registers.
1336  *
1337  * The VI window size is 8KB for Medford and all earlier controllers.
1338  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1339  */
1340
1341 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1342         do {                                                            \
1343                 EFX_CHECK_REG((_enp), (_reg));                          \
1344                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1345                     ((_reg ## _OFST) +                                  \
1346                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1347                     (_edp), (_lock));                                   \
1348                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1349                     uint32_t, (_index),                                 \
1350                     uint32_t, _reg ## _OFST,                            \
1351                     uint32_t, (_edp)->ed_u32[0]);                       \
1352         _NOTE(CONSTANTCONDITION)                                        \
1353         } while (B_FALSE)
1354
1355 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1356         do {                                                            \
1357                 EFX_CHECK_REG((_enp), (_reg));                          \
1358                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1359                     uint32_t, (_index),                                 \
1360                     uint32_t, _reg ## _OFST,                            \
1361                     uint32_t, (_edp)->ed_u32[0]);                       \
1362                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1363                     ((_reg ## _OFST) +                                  \
1364                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1365                     (_edp), (_lock));                                   \
1366         _NOTE(CONSTANTCONDITION)                                        \
1367         } while (B_FALSE)
1368
1369 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1370         do {                                                            \
1371                 EFX_CHECK_REG((_enp), (_reg));                          \
1372                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1373                     uint32_t, (_index),                                 \
1374                     uint32_t, _reg ## _OFST,                            \
1375                     uint32_t, (_edp)->ed_u32[0]);                       \
1376                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1377                     ((_reg ## _OFST) +                                  \
1378                     (2 * sizeof (efx_dword_t)) +                        \
1379                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1380                     (_edp), (_lock));                                   \
1381         _NOTE(CONSTANTCONDITION)                                        \
1382         } while (B_FALSE)
1383
1384 /*
1385  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1386  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1387  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1388  * the need for locking in the host, and are the only ones known to be safe to
1389  * use 128-bites write with.
1390  */
1391 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1392         do {                                                            \
1393                 EFX_CHECK_REG((_enp), (_reg));                          \
1394                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1395                     const char *, #_reg,                                \
1396                     uint32_t, (_index),                                 \
1397                     uint32_t, _reg ## _OFST,                            \
1398                     uint32_t, (_eop)->eo_u32[3],                        \
1399                     uint32_t, (_eop)->eo_u32[2],                        \
1400                     uint32_t, (_eop)->eo_u32[1],                        \
1401                     uint32_t, (_eop)->eo_u32[0]);                       \
1402                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1403                     (_reg ## _OFST +                                    \
1404                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1405                     (_eop));                                            \
1406         _NOTE(CONSTANTCONDITION)                                        \
1407         } while (B_FALSE)
1408
1409 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size,      \
1410                                       _wptr, _owptr)                    \
1411         do {                                                            \
1412                 unsigned int _new = (_wptr);                            \
1413                 unsigned int _old = (_owptr);                           \
1414                                                                         \
1415                 if ((_new) >= (_old))                                   \
1416                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1417                             (_old) * (_desc_size),                      \
1418                             ((_new) - (_old)) * (_desc_size));          \
1419                 else                                                    \
1420                         /*                                              \
1421                          * It is cheaper to sync entire map than sync   \
1422                          * two parts especially when offset/size are    \
1423                          * ignored and entire map is synced in any case.\
1424                          */                                             \
1425                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1426                             0,                                          \
1427                             (_entries) * (_desc_size));                 \
1428         _NOTE(CONSTANTCONDITION)                                        \
1429         } while (B_FALSE)
1430
1431 LIBEFX_INTERNAL
1432 extern  __checkReturn   efx_rc_t
1433 efx_mac_select(
1434         __in            efx_nic_t *enp);
1435
1436 LIBEFX_INTERNAL
1437 extern  void
1438 efx_mac_multicast_hash_compute(
1439         __in_ecount(6*count)            uint8_t const *addrs,
1440         __in                            int count,
1441         __out                           efx_oword_t *hash_low,
1442         __out                           efx_oword_t *hash_high);
1443
1444 LIBEFX_INTERNAL
1445 extern  __checkReturn   efx_rc_t
1446 efx_phy_probe(
1447         __in            efx_nic_t *enp);
1448
1449 LIBEFX_INTERNAL
1450 extern                  void
1451 efx_phy_unprobe(
1452         __in            efx_nic_t *enp);
1453
1454 #if EFSYS_OPT_VPD
1455
1456 /* VPD utility functions */
1457
1458 LIBEFX_INTERNAL
1459 extern  __checkReturn           efx_rc_t
1460 efx_vpd_hunk_length(
1461         __in_bcount(size)       caddr_t data,
1462         __in                    size_t size,
1463         __out                   size_t *lengthp);
1464
1465 LIBEFX_INTERNAL
1466 extern  __checkReturn           efx_rc_t
1467 efx_vpd_hunk_verify(
1468         __in_bcount(size)       caddr_t data,
1469         __in                    size_t size,
1470         __out_opt               boolean_t *cksummedp);
1471
1472 LIBEFX_INTERNAL
1473 extern  __checkReturn           efx_rc_t
1474 efx_vpd_hunk_reinit(
1475         __in_bcount(size)       caddr_t data,
1476         __in                    size_t size,
1477         __in                    boolean_t wantpid);
1478
1479 LIBEFX_INTERNAL
1480 extern  __checkReturn           efx_rc_t
1481 efx_vpd_hunk_get(
1482         __in_bcount(size)       caddr_t data,
1483         __in                    size_t size,
1484         __in                    efx_vpd_tag_t tag,
1485         __in                    efx_vpd_keyword_t keyword,
1486         __out                   unsigned int *payloadp,
1487         __out                   uint8_t *paylenp);
1488
1489 LIBEFX_INTERNAL
1490 extern  __checkReturn                   efx_rc_t
1491 efx_vpd_hunk_next(
1492         __in_bcount(size)               caddr_t data,
1493         __in                            size_t size,
1494         __out                           efx_vpd_tag_t *tagp,
1495         __out                           efx_vpd_keyword_t *keyword,
1496         __out_opt                       unsigned int *payloadp,
1497         __out_opt                       uint8_t *paylenp,
1498         __inout                         unsigned int *contp);
1499
1500 LIBEFX_INTERNAL
1501 extern  __checkReturn           efx_rc_t
1502 efx_vpd_hunk_set(
1503         __in_bcount(size)       caddr_t data,
1504         __in                    size_t size,
1505         __in                    efx_vpd_value_t *evvp);
1506
1507 #endif  /* EFSYS_OPT_VPD */
1508
1509 #if EFSYS_OPT_MCDI
1510
1511 LIBEFX_INTERNAL
1512 extern  __checkReturn           efx_rc_t
1513 efx_mcdi_set_workaround(
1514         __in                    efx_nic_t *enp,
1515         __in                    uint32_t type,
1516         __in                    boolean_t enabled,
1517         __out_opt               uint32_t *flagsp);
1518
1519 LIBEFX_INTERNAL
1520 extern  __checkReturn           efx_rc_t
1521 efx_mcdi_get_workarounds(
1522         __in                    efx_nic_t *enp,
1523         __out_opt               uint32_t *implementedp,
1524         __out_opt               uint32_t *enabledp);
1525
1526 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1527
1528 LIBEFX_INTERNAL
1529 extern  __checkReturn   efx_rc_t
1530 efx_mcdi_init_evq(
1531         __in            efx_nic_t *enp,
1532         __in            unsigned int instance,
1533         __in            efsys_mem_t *esmp,
1534         __in            size_t nevs,
1535         __in            uint32_t irq,
1536         __in            uint32_t us,
1537         __in            uint32_t flags,
1538         __in            boolean_t low_latency);
1539
1540 LIBEFX_INTERNAL
1541 extern  __checkReturn   efx_rc_t
1542 efx_mcdi_fini_evq(
1543         __in            efx_nic_t *enp,
1544         __in            uint32_t instance);
1545
1546 typedef struct efx_mcdi_init_rxq_params_s {
1547         boolean_t       disable_scatter;
1548         boolean_t       want_inner_classes;
1549         uint32_t        buf_size;
1550         uint32_t        ps_buf_size;
1551         uint32_t        es_bufs_per_desc;
1552         uint32_t        es_max_dma_len;
1553         uint32_t        es_buf_stride;
1554         uint32_t        hol_block_timeout;
1555         uint32_t        prefix_id;
1556 } efx_mcdi_init_rxq_params_t;
1557
1558 LIBEFX_INTERNAL
1559 extern  __checkReturn   efx_rc_t
1560 efx_mcdi_init_rxq(
1561         __in            efx_nic_t *enp,
1562         __in            uint32_t ndescs,
1563         __in            efx_evq_t *eep,
1564         __in            uint32_t label,
1565         __in            uint32_t instance,
1566         __in            efsys_mem_t *esmp,
1567         __in            const efx_mcdi_init_rxq_params_t *params);
1568
1569 LIBEFX_INTERNAL
1570 extern  __checkReturn   efx_rc_t
1571 efx_mcdi_fini_rxq(
1572         __in            efx_nic_t *enp,
1573         __in            uint32_t instance);
1574
1575 LIBEFX_INTERNAL
1576 extern  __checkReturn   efx_rc_t
1577 efx_mcdi_init_txq(
1578         __in            efx_nic_t *enp,
1579         __in            uint32_t ndescs,
1580         __in            uint32_t target_evq,
1581         __in            uint32_t label,
1582         __in            uint32_t instance,
1583         __in            uint16_t flags,
1584         __in            efsys_mem_t *esmp);
1585
1586 LIBEFX_INTERNAL
1587 extern  __checkReturn   efx_rc_t
1588 efx_mcdi_fini_txq(
1589         __in            efx_nic_t *enp,
1590         __in            uint32_t instance);
1591
1592 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1593
1594 #endif /* EFSYS_OPT_MCDI */
1595
1596 #if EFSYS_OPT_MAC_STATS
1597
1598 /*
1599  * Closed range of stats (i.e. the first and the last are included).
1600  * The last must be greater or equal (if the range is one item only) to
1601  * the first.
1602  */
1603 struct efx_mac_stats_range {
1604         efx_mac_stat_t          first;
1605         efx_mac_stat_t          last;
1606 };
1607
1608 typedef enum efx_stats_action_e {
1609         EFX_STATS_CLEAR,
1610         EFX_STATS_UPLOAD,
1611         EFX_STATS_ENABLE_NOEVENTS,
1612         EFX_STATS_ENABLE_EVENTS,
1613         EFX_STATS_DISABLE,
1614 } efx_stats_action_t;
1615
1616 LIBEFX_INTERNAL
1617 extern                                  efx_rc_t
1618 efx_mac_stats_mask_add_ranges(
1619         __inout_bcount(mask_size)       uint32_t *maskp,
1620         __in                            size_t mask_size,
1621         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1622         __in                            unsigned int rng_count);
1623
1624 LIBEFX_INTERNAL
1625 extern  __checkReturn   efx_rc_t
1626 efx_mcdi_mac_stats(
1627         __in            efx_nic_t *enp,
1628         __in            uint32_t vport_id,
1629         __in_opt        efsys_mem_t *esmp,
1630         __in            efx_stats_action_t action,
1631         __in            uint16_t period_ms);
1632
1633 #endif  /* EFSYS_OPT_MAC_STATS */
1634
1635 #if EFSYS_OPT_PCI
1636
1637 /*
1638  * Find the next extended capability in a PCI device's config space
1639  * with specified capability id.
1640  * Passing 0 offset makes the function search from the start.
1641  * If search succeeds, found capability is in modified offset.
1642  *
1643  * Returns ENOENT if a capability is not found.
1644  */
1645 LIBEFX_INTERNAL
1646 extern  __checkReturn                   efx_rc_t
1647 efx_pci_config_find_next_ext_cap(
1648         __in                            efsys_pci_config_t *espcp,
1649         __in                            const efx_pci_ops_t *epop,
1650         __in                            uint16_t cap_id,
1651         __inout                         size_t *offsetp);
1652
1653 /*
1654  * Get the next extended capability in a PCI device's config space.
1655  * Passing 0 offset makes the function get the first capability.
1656  * If search succeeds, the capability is in modified offset.
1657  *
1658  * Returns ENOENT if there is no next capability.
1659  */
1660 LIBEFX_INTERNAL
1661 extern  __checkReturn                   efx_rc_t
1662 efx_pci_config_next_ext_cap(
1663         __in                            efsys_pci_config_t *espcp,
1664         __in                            const efx_pci_ops_t *epop,
1665         __inout                         size_t *offsetp);
1666
1667 /*
1668  * Find the next Xilinx capabilities table location by searching
1669  * PCI extended capabilities.
1670  *
1671  * Returns ENOENT if a table location is not found.
1672  */
1673 LIBEFX_INTERNAL
1674 extern  __checkReturn                   efx_rc_t
1675 efx_pci_find_next_xilinx_cap_table(
1676         __in                            efsys_pci_config_t *espcp,
1677         __in                            const efx_pci_ops_t *epop,
1678         __inout                         size_t *pci_cap_offsetp,
1679         __out                           unsigned int *xilinx_tbl_barp,
1680         __out                           efsys_dma_addr_t *xilinx_tbl_offsetp);
1681
1682 /*
1683  * Read a Xilinx extended PCI capability that gives the location
1684  * of a Xilinx capabilities table.
1685  *
1686  * Returns ENOENT if the extended PCI capability does not contain
1687  * Xilinx capabilities table locator.
1688  */
1689 LIBEFX_INTERNAL
1690 extern  __checkReturn                   efx_rc_t
1691 efx_pci_read_ext_cap_xilinx_table(
1692         __in                            efsys_pci_config_t *espcp,
1693         __in                            const efx_pci_ops_t *epop,
1694         __in                            size_t cap_offset,
1695         __out                           unsigned int *barp,
1696         __out                           efsys_dma_addr_t *offsetp);
1697
1698 /*
1699  * Find a capability with specified format_id in a Xilinx capabilities table.
1700  * Searching is started from provided offset, taking skip_first into account.
1701  * If search succeeds, found capability is in modified offset.
1702  *
1703  * Returns ENOENT if an entry with specified format id is not found.
1704  */
1705 LIBEFX_INTERNAL
1706 extern  __checkReturn                   efx_rc_t
1707 efx_pci_xilinx_cap_tbl_find(
1708         __in                            efsys_bar_t *esbp,
1709         __in                            uint32_t format_id,
1710         __in                            boolean_t skip_first,
1711         __inout                         efsys_dma_addr_t *entry_offsetp);
1712
1713 #endif /* EFSYS_OPT_PCI */
1714
1715 #if EFSYS_OPT_MAE
1716
1717 struct efx_mae_match_spec_s {
1718         efx_mae_rule_type_t             emms_type;
1719         uint32_t                        emms_prio;
1720         union emms_mask_value_pairs {
1721                 uint8_t                 action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
1722                 uint8_t                 outer[MAE_ENC_FIELD_PAIRS_LEN];
1723         } emms_mask_value_pairs;
1724 };
1725
1726 typedef enum efx_mae_action_e {
1727         /* These actions are strictly ordered. */
1728         EFX_MAE_ACTION_VLAN_POP,
1729         EFX_MAE_ACTION_VLAN_PUSH,
1730
1731         /*
1732          * These actions are not strictly ordered and can
1733          * be passed by a client in any order (before DELIVER).
1734          * However, these enumerants must be kept compactly
1735          * in the end of the enumeration (before DELIVER).
1736          */
1737         EFX_MAE_ACTION_FLAG,
1738         EFX_MAE_ACTION_MARK,
1739
1740         /* DELIVER is always the last action. */
1741         EFX_MAE_ACTION_DELIVER,
1742
1743         EFX_MAE_NACTIONS
1744 } efx_mae_action_t;
1745
1746 /* MAE VLAN_POP action can handle 1 or 2 tags. */
1747 #define EFX_MAE_VLAN_POP_MAX_NTAGS      (2)
1748
1749 /* MAE VLAN_PUSH action can handle 1 or 2 tags. */
1750 #define EFX_MAE_VLAN_PUSH_MAX_NTAGS     (2)
1751
1752 typedef struct efx_mae_action_vlan_push_s {
1753         uint16_t                        emavp_tpid_be;
1754         uint16_t                        emavp_tci_be;
1755 } efx_mae_action_vlan_push_t;
1756
1757 struct efx_mae_actions_s {
1758         /* Bitmap of actions in spec, indexed by action type */
1759         uint32_t                        ema_actions;
1760
1761         unsigned int                    ema_n_vlan_tags_to_pop;
1762         unsigned int                    ema_n_vlan_tags_to_push;
1763         efx_mae_action_vlan_push_t      ema_vlan_push_descs[
1764             EFX_MAE_VLAN_PUSH_MAX_NTAGS];
1765         uint32_t                        ema_mark_value;
1766         efx_mport_sel_t                 ema_deliver_mport;
1767 };
1768
1769 #endif /* EFSYS_OPT_MAE */
1770
1771 #if EFSYS_OPT_VIRTIO
1772
1773 #define EFX_VQ_MAGIC    0x026011950
1774
1775 typedef enum efx_virtio_vq_state_e {
1776         EFX_VIRTIO_VQ_STATE_UNKNOWN = 0,
1777         EFX_VIRTIO_VQ_STATE_INITIALIZED,
1778         EFX_VIRTIO_VQ_STATE_STARTED,
1779         EFX_VIRTIO_VQ_NSTATES
1780 } efx_virtio_vq_state_t;
1781
1782 struct efx_virtio_vq_s {
1783         uint32_t                evv_magic;
1784         efx_nic_t               *evv_enp;
1785         efx_virtio_vq_state_t   evv_state;
1786         uint32_t                evv_vi_index;
1787         efx_virtio_vq_type_t    evv_type;
1788         uint16_t                evv_target_vf;
1789 };
1790
1791 #endif /* EFSYS_OPT_VIRTIO */
1792
1793 #ifdef  __cplusplus
1794 }
1795 #endif
1796
1797 #endif  /* _SYS_EFX_IMPL_H */