drivers/common/sfc_efx/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #include "efx_regs_ef100.h"
  14 #if EFSYS_OPT_MCDI
  15 #include "efx_mcdi.h"
  16 #endif  /* EFSYS_OPT_MCDI */
  17
  18 /* FIXME: Add definition for driver generated software events */
  19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  21 #endif
  22
  23
  24 #if EFSYS_OPT_SIENA
  25 #include "siena_impl.h"
  26 #endif  /* EFSYS_OPT_SIENA */
  27
  28 #if EFSYS_OPT_HUNTINGTON
  29 #include "hunt_impl.h"
  30 #endif  /* EFSYS_OPT_HUNTINGTON */
  31
  32 #if EFSYS_OPT_MEDFORD
  33 #include "medford_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD */
  35
  36 #if EFSYS_OPT_MEDFORD2
  37 #include "medford2_impl.h"
  38 #endif  /* EFSYS_OPT_MEDFORD2 */
  39
  40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
  41 #include "ef10_impl.h"
  42 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
  43
  44 #if EFSYS_OPT_RIVERHEAD
  45 #include "rhead_impl.h"
  46 #endif  /* EFSYS_OPT_RIVERHEAD */
  47
  48 #ifdef  __cplusplus
  49 extern "C" {
  50 #endif
  51
  52 #define EFX_MOD_MCDI            0x00000001
  53 #define EFX_MOD_PROBE           0x00000002
  54 #define EFX_MOD_NVRAM           0x00000004
  55 #define EFX_MOD_VPD             0x00000008
  56 #define EFX_MOD_NIC             0x00000010
  57 #define EFX_MOD_INTR            0x00000020
  58 #define EFX_MOD_EV              0x00000040
  59 #define EFX_MOD_RX              0x00000080
  60 #define EFX_MOD_TX              0x00000100
  61 #define EFX_MOD_PORT            0x00000200
  62 #define EFX_MOD_MON             0x00000400
  63 #define EFX_MOD_FILTER          0x00001000
  64 #define EFX_MOD_LIC             0x00002000
  65 #define EFX_MOD_TUNNEL          0x00004000
  66 #define EFX_MOD_EVB             0x00008000
  67 #define EFX_MOD_PROXY           0x00010000
  68
  69 #define EFX_RESET_PHY           0x00000001
  70 #define EFX_RESET_RXQ_ERR       0x00000002
  71 #define EFX_RESET_TXQ_ERR       0x00000004
  72 #define EFX_RESET_HW_UNAVAIL    0x00000008
  73
  74 typedef enum efx_mac_type_e {
  75         EFX_MAC_INVALID = 0,
  76         EFX_MAC_SIENA,
  77         EFX_MAC_HUNTINGTON,
  78         EFX_MAC_MEDFORD,
  79         EFX_MAC_MEDFORD2,
  80         EFX_MAC_NTYPES
  81 } efx_mac_type_t;
  82
  83 typedef struct efx_ev_ops_s {
  84         efx_rc_t        (*eevo_init)(efx_nic_t *);
  85         void            (*eevo_fini)(efx_nic_t *);
  86         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  87                                           efsys_mem_t *, size_t, uint32_t,
  88                                           uint32_t, uint32_t, efx_evq_t *);
  89         void            (*eevo_qdestroy)(efx_evq_t *);
  90         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  91         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  92         void            (*eevo_qpoll)(efx_evq_t *, unsigned int *,
  93                                         const efx_ev_callbacks_t *, void *);
  94         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  95 #if EFSYS_OPT_QSTATS
  96         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  97 #endif
  98 } efx_ev_ops_t;
  99
 100 typedef struct efx_tx_ops_s {
 101         efx_rc_t        (*etxo_init)(efx_nic_t *);
 102         void            (*etxo_fini)(efx_nic_t *);
 103         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 104                                         unsigned int, unsigned int,
 105                                         efsys_mem_t *, size_t,
 106                                         uint32_t, uint16_t,
 107                                         efx_evq_t *, efx_txq_t *,
 108                                         unsigned int *);
 109         void            (*etxo_qdestroy)(efx_txq_t *);
 110         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 111                                       unsigned int, unsigned int,
 112                                       unsigned int *);
 113         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 114         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 115         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 116         void            (*etxo_qenable)(efx_txq_t *);
 117         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 118         void            (*etxo_qpio_disable)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 120                                            size_t);
 121         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 122                                            unsigned int *);
 123         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 124                                       unsigned int, unsigned int,
 125                                       unsigned int *);
 126         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 127                                                 size_t, boolean_t,
 128                                                 efx_desc_t *);
 129         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 130                                                 uint32_t, uint8_t,
 131                                                 efx_desc_t *);
 132         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 133                                                 uint16_t, uint32_t, uint16_t,
 134                                                 efx_desc_t *, int);
 135         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 138                                                 efx_desc_t *);
 139 #if EFSYS_OPT_QSTATS
 140         void            (*etxo_qstats_update)(efx_txq_t *,
 141                                               efsys_stat_t *);
 142 #endif
 143 } efx_tx_ops_t;
 144
 145 typedef union efx_rxq_type_data_u {
 146         struct {
 147                 size_t          ed_buf_size;
 148         } ertd_default;
 149 #if EFSYS_OPT_RX_PACKED_STREAM
 150         struct {
 151                 uint32_t        eps_buf_size;
 152         } ertd_packed_stream;
 153 #endif
 154 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 155         struct {
 156                 uint32_t        eessb_bufs_per_desc;
 157                 uint32_t        eessb_max_dma_len;
 158                 uint32_t        eessb_buf_stride;
 159                 uint32_t        eessb_hol_block_timeout;
 160         } ertd_es_super_buffer;
 161 #endif
 162 } efx_rxq_type_data_t;
 163
 164 typedef struct efx_rx_ops_s {
 165         efx_rc_t        (*erxo_init)(efx_nic_t *);
 166         void            (*erxo_fini)(efx_nic_t *);
 167 #if EFSYS_OPT_RX_SCATTER
 168         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 169 #endif
 170 #if EFSYS_OPT_RX_SCALE
 171         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 172                                                     efx_rx_scale_context_type_t,
 173                                                     uint32_t, uint32_t *);
 174         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 175         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 176                                                efx_rx_hash_alg_t,
 177                                                efx_rx_hash_type_t, boolean_t);
 178         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 179                                               uint8_t *, size_t);
 180         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 181                                               unsigned int *, size_t);
 182         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 183                                             uint8_t *);
 184 #endif /* EFSYS_OPT_RX_SCALE */
 185         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 186                                               uint16_t *);
 187         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 188                                       unsigned int, unsigned int,
 189                                       unsigned int);
 190         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 191 #if EFSYS_OPT_RX_PACKED_STREAM
 192         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 193         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 194                                                 uint32_t, uint32_t,
 195                                                 uint16_t *, uint32_t *, uint32_t *);
 196 #endif
 197         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 198         void            (*erxo_qenable)(efx_rxq_t *);
 199         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 200                                         unsigned int, efx_rxq_type_t,
 201                                         const efx_rxq_type_data_t *,
 202                                         efsys_mem_t *, size_t, uint32_t,
 203                                         unsigned int,
 204                                         efx_evq_t *, efx_rxq_t *);
 205         void            (*erxo_qdestroy)(efx_rxq_t *);
 206 } efx_rx_ops_t;
 207
 208 typedef struct efx_mac_ops_s {
 209         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 210         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 211         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 212         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 213         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 214         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 215         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 216         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 217                                                       efx_rxq_t *, boolean_t);
 218         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 219 #if EFSYS_OPT_LOOPBACK
 220         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 221                                             efx_loopback_type_t);
 222 #endif  /* EFSYS_OPT_LOOPBACK */
 223 #if EFSYS_OPT_MAC_STATS
 224         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 225         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 226         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 227         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 228                                               uint16_t, boolean_t);
 229         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 230                                             efsys_stat_t *, uint32_t *);
 231 #endif  /* EFSYS_OPT_MAC_STATS */
 232 } efx_mac_ops_t;
 233
 234 typedef struct efx_phy_ops_s {
 235         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 236         efx_rc_t        (*epo_reset)(efx_nic_t *);
 237         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 238         efx_rc_t        (*epo_verify)(efx_nic_t *);
 239         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 240         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 241 #if EFSYS_OPT_PHY_STATS
 242         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 243                                             uint32_t *);
 244 #endif  /* EFSYS_OPT_PHY_STATS */
 245 #if EFSYS_OPT_BIST
 246         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 247         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 248         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 249                                          efx_bist_result_t *, uint32_t *,
 250                                          unsigned long *, size_t);
 251         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 252 #endif  /* EFSYS_OPT_BIST */
 253 } efx_phy_ops_t;
 254
 255 #if EFSYS_OPT_FILTER
 256
 257 /*
 258  * Policy for replacing existing filter when inserting a new one.
 259  * Note that all policies allow for storing the new lower priority
 260  * filters as overridden by existing higher priority ones. It is needed
 261  * to restore the lower priority filters on higher priority ones removal.
 262  */
 263 typedef enum efx_filter_replacement_policy_e {
 264         /* Cannot replace existing filter */
 265         EFX_FILTER_REPLACEMENT_NEVER,
 266         /* Higher priority filters can replace lower priotiry ones */
 267         EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY,
 268         /*
 269          * Higher priority filters can replace lower priority ones and
 270          * equal priority filters can replace each other.
 271          */
 272         EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY,
 273 } efx_filter_replacement_policy_t;
 274
 275 typedef struct efx_filter_ops_s {
 276         efx_rc_t        (*efo_init)(efx_nic_t *);
 277         void            (*efo_fini)(efx_nic_t *);
 278         efx_rc_t        (*efo_restore)(efx_nic_t *);
 279         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 280                                    efx_filter_replacement_policy_t policy);
 281         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 282         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 283                                    size_t, size_t *);
 284         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 285                                    boolean_t, boolean_t, boolean_t,
 286                                    uint8_t const *, uint32_t);
 287 } efx_filter_ops_t;
 288
 289 LIBEFX_INTERNAL
 290 extern  __checkReturn   efx_rc_t
 291 efx_filter_reconfigure(
 292         __in                            efx_nic_t *enp,
 293         __in_ecount(6)                  uint8_t const *mac_addr,
 294         __in                            boolean_t all_unicst,
 295         __in                            boolean_t mulcst,
 296         __in                            boolean_t all_mulcst,
 297         __in                            boolean_t brdcst,
 298         __in_ecount(6*count)            uint8_t const *addrs,
 299         __in                            uint32_t count);
 300
 301 #endif /* EFSYS_OPT_FILTER */
 302
 303 #if EFSYS_OPT_TUNNEL
 304 typedef struct efx_tunnel_ops_s {
 305         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 306         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 307 } efx_tunnel_ops_t;
 308 #endif /* EFSYS_OPT_TUNNEL */
 309
 310 typedef struct efx_port_s {
 311         efx_mac_type_t          ep_mac_type;
 312         uint32_t                ep_phy_type;
 313         uint8_t                 ep_port;
 314         uint32_t                ep_mac_pdu;
 315         uint8_t                 ep_mac_addr[6];
 316         efx_link_mode_t         ep_link_mode;
 317         boolean_t               ep_all_unicst;
 318         boolean_t               ep_all_unicst_inserted;
 319         boolean_t               ep_mulcst;
 320         boolean_t               ep_all_mulcst;
 321         boolean_t               ep_all_mulcst_inserted;
 322         boolean_t               ep_brdcst;
 323         unsigned int            ep_fcntl;
 324         boolean_t               ep_fcntl_autoneg;
 325         efx_oword_t             ep_multicst_hash[2];
 326         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 327                                                     EFX_MAC_MULTICAST_LIST_MAX];
 328         uint32_t                ep_mulcst_addr_count;
 329 #if EFSYS_OPT_LOOPBACK
 330         efx_loopback_type_t     ep_loopback_type;
 331         efx_link_mode_t         ep_loopback_link_mode;
 332 #endif  /* EFSYS_OPT_LOOPBACK */
 333 #if EFSYS_OPT_PHY_FLAGS
 334         uint32_t                ep_phy_flags;
 335 #endif  /* EFSYS_OPT_PHY_FLAGS */
 336 #if EFSYS_OPT_PHY_LED_CONTROL
 337         efx_phy_led_mode_t      ep_phy_led_mode;
 338 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 339         efx_phy_media_type_t    ep_fixed_port_type;
 340         efx_phy_media_type_t    ep_module_type;
 341         uint32_t                ep_adv_cap_mask;
 342         uint32_t                ep_lp_cap_mask;
 343         uint32_t                ep_default_adv_cap_mask;
 344         uint32_t                ep_phy_cap_mask;
 345         boolean_t               ep_mac_drain;
 346 #if EFSYS_OPT_BIST
 347         efx_bist_type_t         ep_current_bist;
 348 #endif
 349         const efx_mac_ops_t     *ep_emop;
 350         const efx_phy_ops_t     *ep_epop;
 351 } efx_port_t;
 352
 353 typedef struct efx_mon_ops_s {
 354 #if EFSYS_OPT_MON_STATS
 355         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 356                                             efx_mon_stat_value_t *);
 357         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 358                                              efx_mon_stat_limits_t *);
 359 #endif  /* EFSYS_OPT_MON_STATS */
 360 } efx_mon_ops_t;
 361
 362 typedef struct efx_mon_s {
 363         efx_mon_type_t          em_type;
 364         const efx_mon_ops_t     *em_emop;
 365 } efx_mon_t;
 366
 367 typedef struct efx_intr_ops_s {
 368         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 369         void            (*eio_enable)(efx_nic_t *);
 370         void            (*eio_disable)(efx_nic_t *);
 371         void            (*eio_disable_unlocked)(efx_nic_t *);
 372         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 373         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 374         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 375                                  boolean_t *);
 376         void            (*eio_fatal)(efx_nic_t *);
 377         void            (*eio_fini)(efx_nic_t *);
 378 } efx_intr_ops_t;
 379
 380 typedef struct efx_intr_s {
 381         const efx_intr_ops_t    *ei_eiop;
 382         efsys_mem_t             *ei_esmp;
 383         efx_intr_type_t         ei_type;
 384         unsigned int            ei_level;
 385 } efx_intr_t;
 386
 387 typedef struct efx_nic_ops_s {
 388         efx_rc_t        (*eno_probe)(efx_nic_t *);
 389         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 390         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 391         efx_rc_t        (*eno_reset)(efx_nic_t *);
 392         efx_rc_t        (*eno_init)(efx_nic_t *);
 393         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 394         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 395                                         uint32_t *, size_t *);
 396         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 397         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 398 #if EFSYS_OPT_DIAG
 399         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 400 #endif  /* EFSYS_OPT_DIAG */
 401         void            (*eno_fini)(efx_nic_t *);
 402         void            (*eno_unprobe)(efx_nic_t *);
 403 } efx_nic_ops_t;
 404
 405 #ifndef EFX_TXQ_LIMIT_TARGET
 406 #define EFX_TXQ_LIMIT_TARGET 259
 407 #endif
 408 #ifndef EFX_RXQ_LIMIT_TARGET
 409 #define EFX_RXQ_LIMIT_TARGET 512
 410 #endif
 411
 412
 413 #if EFSYS_OPT_FILTER
 414
 415 #if EFSYS_OPT_SIENA
 416
 417 typedef struct siena_filter_spec_s {
 418         uint8_t         sfs_type;
 419         uint32_t        sfs_flags;
 420         uint32_t        sfs_dmaq_id;
 421         uint32_t        sfs_dword[3];
 422 } siena_filter_spec_t;
 423
 424 typedef enum siena_filter_type_e {
 425         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 426         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 427         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 428         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 429         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 430         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 431
 432         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 433         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 434         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 435         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 436         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 437         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 438
 439         EFX_SIENA_FILTER_NTYPES
 440 } siena_filter_type_t;
 441
 442 typedef enum siena_filter_tbl_id_e {
 443         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 444         EFX_SIENA_FILTER_TBL_RX_MAC,
 445         EFX_SIENA_FILTER_TBL_TX_IP,
 446         EFX_SIENA_FILTER_TBL_TX_MAC,
 447         EFX_SIENA_FILTER_NTBLS
 448 } siena_filter_tbl_id_t;
 449
 450 typedef struct siena_filter_tbl_s {
 451         int                     sft_size;       /* number of entries */
 452         int                     sft_used;       /* active count */
 453         uint32_t                *sft_bitmap;    /* active bitmap */
 454         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 455 } siena_filter_tbl_t;
 456
 457 typedef struct siena_filter_s {
 458         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 459         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 460 } siena_filter_t;
 461
 462 #endif  /* EFSYS_OPT_SIENA */
 463
 464 typedef struct efx_filter_s {
 465 #if EFSYS_OPT_SIENA
 466         siena_filter_t          *ef_siena_filter;
 467 #endif /* EFSYS_OPT_SIENA */
 468 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 469         ef10_filter_table_t     *ef_ef10_filter_table;
 470 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 471 } efx_filter_t;
 472
 473 #if EFSYS_OPT_SIENA
 474
 475 LIBEFX_INTERNAL
 476 extern                  void
 477 siena_filter_tbl_clear(
 478         __in            efx_nic_t *enp,
 479         __in            siena_filter_tbl_id_t tbl);
 480
 481 #endif  /* EFSYS_OPT_SIENA */
 482
 483 #endif  /* EFSYS_OPT_FILTER */
 484
 485 #if EFSYS_OPT_MCDI
 486
 487 #define EFX_TUNNEL_MAXNENTRIES  (16)
 488
 489 #if EFSYS_OPT_TUNNEL
 490
 491 typedef struct efx_tunnel_udp_entry_s {
 492         uint16_t                        etue_port; /* host/cpu-endian */
 493         uint16_t                        etue_protocol;
 494 } efx_tunnel_udp_entry_t;
 495
 496 typedef struct efx_tunnel_cfg_s {
 497         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 498         unsigned int            etc_udp_entries_num;
 499 } efx_tunnel_cfg_t;
 500
 501 #endif /* EFSYS_OPT_TUNNEL */
 502
 503 typedef struct efx_mcdi_ops_s {
 504         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 505         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 506                                         void *, size_t);
 507         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 508         boolean_t       (*emco_poll_response)(efx_nic_t *);
 509         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 510         void            (*emco_fini)(efx_nic_t *);
 511         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 512                                             efx_mcdi_feature_id_t, boolean_t *);
 513         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 514                                             uint32_t *);
 515 } efx_mcdi_ops_t;
 516
 517 typedef struct efx_mcdi_s {
 518         const efx_mcdi_ops_t            *em_emcop;
 519         const efx_mcdi_transport_t      *em_emtp;
 520         efx_mcdi_iface_t                em_emip;
 521 } efx_mcdi_t;
 522
 523 #endif /* EFSYS_OPT_MCDI */
 524
 525 #if EFSYS_OPT_NVRAM
 526
 527 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 528 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 529
 530 typedef struct efx_nvram_ops_s {
 531 #if EFSYS_OPT_DIAG
 532         efx_rc_t        (*envo_test)(efx_nic_t *);
 533 #endif  /* EFSYS_OPT_DIAG */
 534         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 535                                             uint32_t *);
 536         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 537                                             efx_nvram_info_t *);
 538         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 539         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 540                                             unsigned int, caddr_t, size_t);
 541         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 542                                             unsigned int, caddr_t, size_t);
 543         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 544                                             unsigned int, size_t);
 545         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 546                                             unsigned int, caddr_t, size_t);
 547         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 548                                             uint32_t *);
 549         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 550                                             uint32_t *, uint16_t *);
 551         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 552                                             uint16_t *);
 553         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 554                                             caddr_t, size_t);
 555 } efx_nvram_ops_t;
 556 #endif /* EFSYS_OPT_NVRAM */
 557
 558 #if EFSYS_OPT_VPD
 559 typedef struct efx_vpd_ops_s {
 560         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 561         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 562         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 563         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 564         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 565         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 566                                         efx_vpd_value_t *);
 567         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 568                                         efx_vpd_value_t *);
 569         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 570                                         efx_vpd_value_t *, unsigned int *);
 571         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 572         void            (*evpdo_fini)(efx_nic_t *);
 573 } efx_vpd_ops_t;
 574 #endif  /* EFSYS_OPT_VPD */
 575
 576 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 577
 578 LIBEFX_INTERNAL
 579 extern  __checkReturn           efx_rc_t
 580 efx_mcdi_nvram_partitions(
 581         __in                    efx_nic_t *enp,
 582         __out_bcount(size)      caddr_t data,
 583         __in                    size_t size,
 584         __out                   unsigned int *npartnp);
 585
 586 LIBEFX_INTERNAL
 587 extern  __checkReturn           efx_rc_t
 588 efx_mcdi_nvram_metadata(
 589         __in                    efx_nic_t *enp,
 590         __in                    uint32_t partn,
 591         __out                   uint32_t *subtypep,
 592         __out_ecount(4)         uint16_t version[4],
 593         __out_bcount_opt(size)  char *descp,
 594         __in                    size_t size);
 595
 596 LIBEFX_INTERNAL
 597 extern  __checkReturn           efx_rc_t
 598 efx_mcdi_nvram_info(
 599         __in                    efx_nic_t *enp,
 600         __in                    uint32_t partn,
 601         __out                   efx_nvram_info_t *eni);
 602
 603 LIBEFX_INTERNAL
 604 extern  __checkReturn           efx_rc_t
 605 efx_mcdi_nvram_update_start(
 606         __in                    efx_nic_t *enp,
 607         __in                    uint32_t partn);
 608
 609 LIBEFX_INTERNAL
 610 extern  __checkReturn           efx_rc_t
 611 efx_mcdi_nvram_read(
 612         __in                    efx_nic_t *enp,
 613         __in                    uint32_t partn,
 614         __in                    uint32_t offset,
 615         __out_bcount(size)      caddr_t data,
 616         __in                    size_t size,
 617         __in                    uint32_t mode);
 618
 619 LIBEFX_INTERNAL
 620 extern  __checkReturn           efx_rc_t
 621 efx_mcdi_nvram_erase(
 622         __in                    efx_nic_t *enp,
 623         __in                    uint32_t partn,
 624         __in                    uint32_t offset,
 625         __in                    size_t size);
 626
 627 LIBEFX_INTERNAL
 628 extern  __checkReturn           efx_rc_t
 629 efx_mcdi_nvram_write(
 630         __in                    efx_nic_t *enp,
 631         __in                    uint32_t partn,
 632         __in                    uint32_t offset,
 633         __in_bcount(size)       caddr_t data,
 634         __in                    size_t size);
 635
 636 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 637 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 638
 639 LIBEFX_INTERNAL
 640 extern  __checkReturn           efx_rc_t
 641 efx_mcdi_nvram_update_finish(
 642         __in                    efx_nic_t *enp,
 643         __in                    uint32_t partn,
 644         __in                    boolean_t reboot,
 645         __in                    uint32_t flags,
 646         __out_opt               uint32_t *verify_resultp);
 647
 648 #if EFSYS_OPT_DIAG
 649
 650 LIBEFX_INTERNAL
 651 extern  __checkReturn           efx_rc_t
 652 efx_mcdi_nvram_test(
 653         __in                    efx_nic_t *enp,
 654         __in                    uint32_t partn);
 655
 656 #endif  /* EFSYS_OPT_DIAG */
 657
 658 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 659
 660 #if EFSYS_OPT_LICENSING
 661
 662 typedef struct efx_lic_ops_s {
 663         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 664         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 665         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 666         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 667                                       size_t *, uint8_t *);
 668         efx_rc_t        (*elo_find_start)
 669                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 670         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 671                                 uint32_t, uint32_t *);
 672         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 673                                 uint32_t, uint32_t *, uint32_t *);
 674         boolean_t       (*elo_validate_key)(efx_nic_t *,
 675                                 caddr_t, uint32_t);
 676         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 677                                 caddr_t, size_t, uint32_t, uint32_t,
 678                                 caddr_t, size_t, uint32_t *);
 679         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 680                                 caddr_t, size_t, uint32_t,
 681                                 caddr_t, uint32_t, uint32_t *);
 682         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 683                                 caddr_t, size_t, uint32_t,
 684                                 uint32_t, uint32_t, uint32_t *);
 685         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 686                                 caddr_t, size_t);
 687         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 688                                 caddr_t, size_t);
 689 } efx_lic_ops_t;
 690
 691 #endif
 692
 693 #if EFSYS_OPT_EVB
 694
 695 struct efx_vswitch_s {
 696         efx_nic_t               *ev_enp;
 697         efx_vswitch_id_t        ev_vswitch_id;
 698         uint32_t                ev_num_vports;
 699         /*
 700          * Vport configuration array: index 0 to store PF configuration
 701          * and next ev_num_vports-1 entries hold VFs configuration.
 702          */
 703         efx_vport_config_t      *ev_evcp;
 704 };
 705
 706 typedef struct efx_evb_ops_s {
 707         efx_rc_t        (*eeo_init)(efx_nic_t *);
 708         void            (*eeo_fini)(efx_nic_t *);
 709         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 710         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 711         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 712                                                 efx_vport_type_t, uint16_t,
 713                                                 boolean_t, efx_vport_id_t *);
 714         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 715                                                 efx_vport_id_t);
 716         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 717                                                 efx_vport_id_t, uint8_t *);
 718         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 719                                                 efx_vport_id_t, uint8_t *);
 720         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 721                                                 efx_vport_id_t);
 722         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 723                                                 efx_vport_id_t);
 724         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 725                                                 efx_vport_id_t, uint32_t);
 726         efx_rc_t        (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
 727                                                         efx_vport_id_t,
 728                                                         uint16_t *, uint8_t *,
 729                                                         boolean_t *);
 730         efx_rc_t        (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
 731                                                 efx_vport_id_t, efsys_mem_t *);
 732 } efx_evb_ops_t;
 733
 734 LIBEFX_INTERNAL
 735 extern __checkReturn    boolean_t
 736 efx_is_zero_eth_addr(
 737         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 738
 739 #endif /* EFSYS_OPT_EVB */
 740
 741 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 742
 743 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 744
 745
 746 typedef struct efx_proxy_ops_s {
 747         efx_rc_t        (*epo_init)(efx_nic_t *);
 748         void            (*epo_fini)(efx_nic_t *);
 749         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 750                                         efsys_mem_t *, efsys_mem_t *,
 751                                         uint32_t, uint32_t *, size_t);
 752         efx_rc_t        (*epo_disable)(efx_nic_t *);
 753         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 754                                         uint32_t, uint32_t, uint32_t);
 755         efx_rc_t        (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
 756                                         uint32_t, uint32_t);
 757         efx_rc_t        (*epo_complete_request)(efx_nic_t *, uint32_t,
 758                                         uint32_t, uint32_t);
 759         efx_rc_t        (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
 760         efx_rc_t        (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
 761                                         uint32_t, uint32_t *);
 762 } efx_proxy_ops_t;
 763
 764 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 765
 766 #define EFX_DRV_VER_MAX         20
 767
 768 typedef struct efx_drv_cfg_s {
 769         uint32_t                edc_min_vi_count;
 770         uint32_t                edc_max_vi_count;
 771
 772         uint32_t                edc_max_piobuf_count;
 773         uint32_t                edc_pio_alloc_size;
 774 } efx_drv_cfg_t;
 775
 776 struct efx_nic_s {
 777         uint32_t                en_magic;
 778         efx_family_t            en_family;
 779         uint32_t                en_features;
 780         efsys_identifier_t      *en_esip;
 781         efsys_lock_t            *en_eslp;
 782         efsys_bar_t             *en_esbp;
 783         unsigned int            en_mod_flags;
 784         unsigned int            en_reset_flags;
 785         efx_nic_cfg_t           en_nic_cfg;
 786         efx_drv_cfg_t           en_drv_cfg;
 787         efx_port_t              en_port;
 788         efx_mon_t               en_mon;
 789         efx_intr_t              en_intr;
 790         uint32_t                en_ev_qcount;
 791         uint32_t                en_rx_qcount;
 792         uint32_t                en_tx_qcount;
 793         const efx_nic_ops_t     *en_enop;
 794         const efx_ev_ops_t      *en_eevop;
 795         const efx_tx_ops_t      *en_etxop;
 796         const efx_rx_ops_t      *en_erxop;
 797         efx_fw_variant_t        efv;
 798         char                    en_drv_version[EFX_DRV_VER_MAX];
 799 #if EFSYS_OPT_FILTER
 800         efx_filter_t            en_filter;
 801         const efx_filter_ops_t  *en_efop;
 802 #endif  /* EFSYS_OPT_FILTER */
 803 #if EFSYS_OPT_TUNNEL
 804         efx_tunnel_cfg_t        en_tunnel_cfg;
 805         const efx_tunnel_ops_t  *en_etop;
 806 #endif /* EFSYS_OPT_TUNNEL */
 807 #if EFSYS_OPT_MCDI
 808         efx_mcdi_t              en_mcdi;
 809 #endif  /* EFSYS_OPT_MCDI */
 810 #if EFSYS_OPT_NVRAM
 811         uint32_t                en_nvram_partn_locked;
 812         const efx_nvram_ops_t   *en_envop;
 813 #endif  /* EFSYS_OPT_NVRAM */
 814 #if EFSYS_OPT_VPD
 815         const efx_vpd_ops_t     *en_evpdop;
 816 #endif  /* EFSYS_OPT_VPD */
 817 #if EFSYS_OPT_RX_SCALE
 818         efx_rx_hash_support_t           en_hash_support;
 819         efx_rx_scale_context_type_t     en_rss_context_type;
 820         uint32_t                        en_rss_context;
 821 #endif  /* EFSYS_OPT_RX_SCALE */
 822         uint32_t                en_vport_id;
 823 #if EFSYS_OPT_LICENSING
 824         const efx_lic_ops_t     *en_elop;
 825         boolean_t               en_licensing_supported;
 826 #endif
 827         union {
 828 #if EFSYS_OPT_SIENA
 829                 struct {
 830 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 831                         unsigned int            enu_partn_mask;
 832 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 833 #if EFSYS_OPT_VPD
 834                         caddr_t                 enu_svpd;
 835                         size_t                  enu_svpd_length;
 836 #endif  /* EFSYS_OPT_VPD */
 837                         int                     enu_unused;
 838                 } siena;
 839 #endif  /* EFSYS_OPT_SIENA */
 840                 int     enu_unused;
 841         } en_u;
 842 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 843         union en_arch {
 844                 struct {
 845                         int                     ena_vi_base;
 846                         int                     ena_vi_count;
 847                         int                     ena_vi_shift;
 848 #if EFSYS_OPT_VPD
 849                         caddr_t                 ena_svpd;
 850                         size_t                  ena_svpd_length;
 851 #endif  /* EFSYS_OPT_VPD */
 852                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 853                         uint32_t                ena_piobuf_count;
 854                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 855                         uint32_t                ena_pio_write_vi_base;
 856                         /* Memory BAR mapping regions */
 857                         uint32_t                ena_uc_mem_map_offset;
 858                         size_t                  ena_uc_mem_map_size;
 859                         uint32_t                ena_wc_mem_map_offset;
 860                         size_t                  ena_wc_mem_map_size;
 861                 } ef10;
 862         } en_arch;
 863 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 864 #if EFSYS_OPT_EVB
 865         const efx_evb_ops_t     *en_eeop;
 866         struct efx_vswitch_s    *en_vswitchp;
 867 #endif  /* EFSYS_OPT_EVB */
 868 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 869         const efx_proxy_ops_t   *en_epop;
 870 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 871 };
 872
 873 #define EFX_FAMILY_IS_EF10(_enp) \
 874         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 875          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 876          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 877
 878 #define EFX_FAMILY_IS_EF100(_enp) \
 879         ((_enp)->en_family == EFX_FAMILY_RIVERHEAD)
 880
 881
 882 #define EFX_NIC_MAGIC   0x02121996
 883
 884 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 885     const efx_ev_callbacks_t *, void *);
 886
 887 typedef struct efx_evq_rxq_state_s {
 888         unsigned int                    eers_rx_read_ptr;
 889         unsigned int                    eers_rx_mask;
 890 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 891         unsigned int                    eers_rx_stream_npackets;
 892         boolean_t                       eers_rx_packed_stream;
 893 #endif
 894 #if EFSYS_OPT_RX_PACKED_STREAM
 895         unsigned int                    eers_rx_packed_stream_credits;
 896 #endif
 897 } efx_evq_rxq_state_t;
 898
 899 struct efx_evq_s {
 900         uint32_t                        ee_magic;
 901         uint32_t                        ee_flags;
 902         efx_nic_t                       *ee_enp;
 903         unsigned int                    ee_index;
 904         unsigned int                    ee_mask;
 905         efsys_mem_t                     *ee_esmp;
 906 #if EFSYS_OPT_QSTATS
 907         uint32_t                        ee_stat[EV_NQSTATS];
 908 #endif  /* EFSYS_OPT_QSTATS */
 909
 910         efx_ev_handler_t                ee_rx;
 911         efx_ev_handler_t                ee_tx;
 912         efx_ev_handler_t                ee_driver;
 913         efx_ev_handler_t                ee_global;
 914         efx_ev_handler_t                ee_drv_gen;
 915 #if EFSYS_OPT_MCDI
 916         efx_ev_handler_t                ee_mcdi;
 917 #endif  /* EFSYS_OPT_MCDI */
 918
 919         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 920 };
 921
 922 #define EFX_EVQ_MAGIC   0x08081997
 923
 924 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 925
 926 #if EFSYS_OPT_QSTATS
 927 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
 928         do {                                                            \
 929                 (_eep)->ee_stat[_stat]++;                               \
 930         _NOTE(CONSTANTCONDITION)                                        \
 931         } while (B_FALSE)
 932 #else
 933 #define EFX_EV_QSTAT_INCR(_eep, _stat)
 934 #endif
 935
 936 struct efx_rxq_s {
 937         uint32_t                        er_magic;
 938         efx_nic_t                       *er_enp;
 939         efx_evq_t                       *er_eep;
 940         unsigned int                    er_index;
 941         unsigned int                    er_label;
 942         unsigned int                    er_mask;
 943         size_t                          er_buf_size;
 944         efsys_mem_t                     *er_esmp;
 945         efx_evq_rxq_state_t             *er_ev_qstate;
 946 };
 947
 948 #define EFX_RXQ_MAGIC   0x15022005
 949
 950 struct efx_txq_s {
 951         uint32_t                        et_magic;
 952         efx_nic_t                       *et_enp;
 953         unsigned int                    et_index;
 954         unsigned int                    et_mask;
 955         efsys_mem_t                     *et_esmp;
 956 #if EFSYS_OPT_HUNTINGTON
 957         uint32_t                        et_pio_bufnum;
 958         uint32_t                        et_pio_blknum;
 959         uint32_t                        et_pio_write_offset;
 960         uint32_t                        et_pio_offset;
 961         size_t                          et_pio_size;
 962 #endif
 963 #if EFSYS_OPT_QSTATS
 964         uint32_t                        et_stat[TX_NQSTATS];
 965 #endif  /* EFSYS_OPT_QSTATS */
 966 };
 967
 968 #define EFX_TXQ_MAGIC   0x05092005
 969
 970 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 971         do {                                                            \
 972                 (_dst)[0] = (_src)[0];                                  \
 973                 (_dst)[1] = (_src)[1];                                  \
 974                 (_dst)[2] = (_src)[2];                                  \
 975                 (_dst)[3] = (_src)[3];                                  \
 976                 (_dst)[4] = (_src)[4];                                  \
 977                 (_dst)[5] = (_src)[5];                                  \
 978         _NOTE(CONSTANTCONDITION)                                        \
 979         } while (B_FALSE)
 980
 981 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 982         do {                                                            \
 983                 uint16_t *_d = (uint16_t *)(_dst);                      \
 984                 _d[0] = 0xffff;                                         \
 985                 _d[1] = 0xffff;                                         \
 986                 _d[2] = 0xffff;                                         \
 987         _NOTE(CONSTANTCONDITION)                                        \
 988         } while (B_FALSE)
 989
 990 #if EFSYS_OPT_CHECK_REG
 991 #define EFX_CHECK_REG(_enp, _reg)                                       \
 992         do {                                                            \
 993                 const char *name = #_reg;                               \
 994                 char min = name[4];                                     \
 995                 char max = name[5];                                     \
 996                 char rev;                                               \
 997                                                                         \
 998                 switch ((_enp)->en_family) {                            \
 999                 case EFX_FAMILY_SIENA:                                  \
1000                         rev = 'C';                                      \
1001                         break;                                          \
1002                                                                         \
1003                 case EFX_FAMILY_HUNTINGTON:                             \
1004                         rev = 'D';                                      \
1005                         break;                                          \
1006                                                                         \
1007                 case EFX_FAMILY_MEDFORD:                                \
1008                         rev = 'E';                                      \
1009                         break;                                          \
1010                                                                         \
1011                 case EFX_FAMILY_MEDFORD2:                               \
1012                         rev = 'F';                                      \
1013                         break;                                          \
1014                                                                         \
1015                 case EFX_FAMILY_RIVERHEAD:                              \
1016                         rev = 'G';                                      \
1017                         break;                                          \
1018                                                                         \
1019                 default:                                                \
1020                         rev = '?';                                      \
1021                         break;                                          \
1022                 }                                                       \
1023                                                                         \
1024                 EFSYS_ASSERT3S(rev, >=, min);                           \
1025                 EFSYS_ASSERT3S(rev, <=, max);                           \
1026                                                                         \
1027         _NOTE(CONSTANTCONDITION)                                        \
1028         } while (B_FALSE)
1029 #else
1030 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
1031         _NOTE(CONSTANTCONDITION)                                        \
1032         } while (B_FALSE)
1033 #endif
1034
1035 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
1036         do {                                                            \
1037                 EFX_CHECK_REG((_enp), (_reg));                          \
1038                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
1039                     (_edp), (_lock));                                   \
1040                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
1041                     uint32_t, _reg ## _OFST,                            \
1042                     uint32_t, (_edp)->ed_u32[0]);                       \
1043         _NOTE(CONSTANTCONDITION)                                        \
1044         } while (B_FALSE)
1045
1046 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
1047         do {                                                            \
1048                 EFX_CHECK_REG((_enp), (_reg));                          \
1049                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
1050                     uint32_t, _reg ## _OFST,                            \
1051                     uint32_t, (_edp)->ed_u32[0]);                       \
1052                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
1053                     (_edp), (_lock));                                   \
1054         _NOTE(CONSTANTCONDITION)                                        \
1055         } while (B_FALSE)
1056
1057 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
1058         do {                                                            \
1059                 EFX_CHECK_REG((_enp), (_reg));                          \
1060                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1061                     (_eqp));                                            \
1062                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1063                     uint32_t, _reg ## _OFST,                            \
1064                     uint32_t, (_eqp)->eq_u32[1],                        \
1065                     uint32_t, (_eqp)->eq_u32[0]);                       \
1066         _NOTE(CONSTANTCONDITION)                                        \
1067         } while (B_FALSE)
1068
1069 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1070         do {                                                            \
1071                 EFX_CHECK_REG((_enp), (_reg));                          \
1072                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1073                     uint32_t, _reg ## _OFST,                            \
1074                     uint32_t, (_eqp)->eq_u32[1],                        \
1075                     uint32_t, (_eqp)->eq_u32[0]);                       \
1076                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1077                     (_eqp));                                            \
1078         _NOTE(CONSTANTCONDITION)                                        \
1079         } while (B_FALSE)
1080
1081 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1082         do {                                                            \
1083                 EFX_CHECK_REG((_enp), (_reg));                          \
1084                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1085                     (_eop), B_TRUE);                                    \
1086                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1087                     uint32_t, _reg ## _OFST,                            \
1088                     uint32_t, (_eop)->eo_u32[3],                        \
1089                     uint32_t, (_eop)->eo_u32[2],                        \
1090                     uint32_t, (_eop)->eo_u32[1],                        \
1091                     uint32_t, (_eop)->eo_u32[0]);                       \
1092         _NOTE(CONSTANTCONDITION)                                        \
1093         } while (B_FALSE)
1094
1095 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1096         do {                                                            \
1097                 EFX_CHECK_REG((_enp), (_reg));                          \
1098                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1099                     uint32_t, _reg ## _OFST,                            \
1100                     uint32_t, (_eop)->eo_u32[3],                        \
1101                     uint32_t, (_eop)->eo_u32[2],                        \
1102                     uint32_t, (_eop)->eo_u32[1],                        \
1103                     uint32_t, (_eop)->eo_u32[0]);                       \
1104                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1105                     (_eop), B_TRUE);                                    \
1106         _NOTE(CONSTANTCONDITION)                                        \
1107         } while (B_FALSE)
1108
1109 /*
1110  * Accessors for memory BAR non-VI tables.
1111  *
1112  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1113  * to ensure the correct runtime VI window size is used on Medford2.
1114  *
1115  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1116  */
1117
1118 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1119         do {                                                            \
1120                 EFX_CHECK_REG((_enp), (_reg));                          \
1121                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1122                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1123                     (_edp), (_lock));                                   \
1124                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1125                     uint32_t, (_index),                                 \
1126                     uint32_t, _reg ## _OFST,                            \
1127                     uint32_t, (_edp)->ed_u32[0]);                       \
1128         _NOTE(CONSTANTCONDITION)                                        \
1129         } while (B_FALSE)
1130
1131 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1132         do {                                                            \
1133                 EFX_CHECK_REG((_enp), (_reg));                          \
1134                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1135                     uint32_t, (_index),                                 \
1136                     uint32_t, _reg ## _OFST,                            \
1137                     uint32_t, (_edp)->ed_u32[0]);                       \
1138                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1139                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1140                     (_edp), (_lock));                                   \
1141         _NOTE(CONSTANTCONDITION)                                        \
1142         } while (B_FALSE)
1143
1144 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1145         do {                                                            \
1146                 EFX_CHECK_REG((_enp), (_reg));                          \
1147                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1148                     uint32_t, (_index),                                 \
1149                     uint32_t, _reg ## _OFST,                            \
1150                     uint32_t, (_edp)->ed_u32[0]);                       \
1151                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1152                     (_reg ## _OFST +                                    \
1153                     (3 * sizeof (efx_dword_t)) +                        \
1154                     ((_index) * _reg ## _STEP)),                        \
1155                     (_edp), (_lock));                                   \
1156         _NOTE(CONSTANTCONDITION)                                        \
1157         } while (B_FALSE)
1158
1159 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1160         do {                                                            \
1161                 EFX_CHECK_REG((_enp), (_reg));                          \
1162                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1163                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1164                     (_eqp));                                            \
1165                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1166                     uint32_t, (_index),                                 \
1167                     uint32_t, _reg ## _OFST,                            \
1168                     uint32_t, (_eqp)->eq_u32[1],                        \
1169                     uint32_t, (_eqp)->eq_u32[0]);                       \
1170         _NOTE(CONSTANTCONDITION)                                        \
1171         } while (B_FALSE)
1172
1173 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1174         do {                                                            \
1175                 EFX_CHECK_REG((_enp), (_reg));                          \
1176                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1177                     uint32_t, (_index),                                 \
1178                     uint32_t, _reg ## _OFST,                            \
1179                     uint32_t, (_eqp)->eq_u32[1],                        \
1180                     uint32_t, (_eqp)->eq_u32[0]);                       \
1181                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1182                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1183                     (_eqp));                                            \
1184         _NOTE(CONSTANTCONDITION)                                        \
1185         } while (B_FALSE)
1186
1187 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1188         do {                                                            \
1189                 EFX_CHECK_REG((_enp), (_reg));                          \
1190                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1191                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1192                     (_eop), (_lock));                                   \
1193                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1194                     uint32_t, (_index),                                 \
1195                     uint32_t, _reg ## _OFST,                            \
1196                     uint32_t, (_eop)->eo_u32[3],                        \
1197                     uint32_t, (_eop)->eo_u32[2],                        \
1198                     uint32_t, (_eop)->eo_u32[1],                        \
1199                     uint32_t, (_eop)->eo_u32[0]);                       \
1200         _NOTE(CONSTANTCONDITION)                                        \
1201         } while (B_FALSE)
1202
1203 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1204         do {                                                            \
1205                 EFX_CHECK_REG((_enp), (_reg));                          \
1206                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1207                     uint32_t, (_index),                                 \
1208                     uint32_t, _reg ## _OFST,                            \
1209                     uint32_t, (_eop)->eo_u32[3],                        \
1210                     uint32_t, (_eop)->eo_u32[2],                        \
1211                     uint32_t, (_eop)->eo_u32[1],                        \
1212                     uint32_t, (_eop)->eo_u32[0]);                       \
1213                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1214                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1215                     (_eop), (_lock));                                   \
1216         _NOTE(CONSTANTCONDITION)                                        \
1217         } while (B_FALSE)
1218
1219 /*
1220  * Accessors for memory BAR per-VI registers.
1221  *
1222  * The VI window size is 8KB for Medford and all earlier controllers.
1223  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1224  */
1225
1226 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1227         do {                                                            \
1228                 EFX_CHECK_REG((_enp), (_reg));                          \
1229                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1230                     ((_reg ## _OFST) +                                  \
1231                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1232                     (_edp), (_lock));                                   \
1233                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1234                     uint32_t, (_index),                                 \
1235                     uint32_t, _reg ## _OFST,                            \
1236                     uint32_t, (_edp)->ed_u32[0]);                       \
1237         _NOTE(CONSTANTCONDITION)                                        \
1238         } while (B_FALSE)
1239
1240 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1241         do {                                                            \
1242                 EFX_CHECK_REG((_enp), (_reg));                          \
1243                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1244                     uint32_t, (_index),                                 \
1245                     uint32_t, _reg ## _OFST,                            \
1246                     uint32_t, (_edp)->ed_u32[0]);                       \
1247                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1248                     ((_reg ## _OFST) +                                  \
1249                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1250                     (_edp), (_lock));                                   \
1251         _NOTE(CONSTANTCONDITION)                                        \
1252         } while (B_FALSE)
1253
1254 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1255         do {                                                            \
1256                 EFX_CHECK_REG((_enp), (_reg));                          \
1257                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1258                     uint32_t, (_index),                                 \
1259                     uint32_t, _reg ## _OFST,                            \
1260                     uint32_t, (_edp)->ed_u32[0]);                       \
1261                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1262                     ((_reg ## _OFST) +                                  \
1263                     (2 * sizeof (efx_dword_t)) +                        \
1264                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1265                     (_edp), (_lock));                                   \
1266         _NOTE(CONSTANTCONDITION)                                        \
1267         } while (B_FALSE)
1268
1269 /*
1270  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1271  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1272  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1273  * the need for locking in the host, and are the only ones known to be safe to
1274  * use 128-bites write with.
1275  */
1276 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1277         do {                                                            \
1278                 EFX_CHECK_REG((_enp), (_reg));                          \
1279                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1280                     const char *, #_reg,                                \
1281                     uint32_t, (_index),                                 \
1282                     uint32_t, _reg ## _OFST,                            \
1283                     uint32_t, (_eop)->eo_u32[3],                        \
1284                     uint32_t, (_eop)->eo_u32[2],                        \
1285                     uint32_t, (_eop)->eo_u32[1],                        \
1286                     uint32_t, (_eop)->eo_u32[0]);                       \
1287                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1288                     (_reg ## _OFST +                                    \
1289                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1290                     (_eop));                                            \
1291         _NOTE(CONSTANTCONDITION)                                        \
1292         } while (B_FALSE)
1293
1294 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1295         do {                                                            \
1296                 unsigned int _new = (_wptr);                            \
1297                 unsigned int _old = (_owptr);                           \
1298                                                                         \
1299                 if ((_new) >= (_old))                                   \
1300                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1301                             (_old) * sizeof (efx_desc_t),               \
1302                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1303                 else                                                    \
1304                         /*                                              \
1305                          * It is cheaper to sync entire map than sync   \
1306                          * two parts especially when offset/size are    \
1307                          * ignored and entire map is synced in any case.\
1308                          */                                             \
1309                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1310                             0,                                          \
1311                             (_entries) * sizeof (efx_desc_t));          \
1312         _NOTE(CONSTANTCONDITION)                                        \
1313         } while (B_FALSE)
1314
1315 LIBEFX_INTERNAL
1316 extern  __checkReturn   efx_rc_t
1317 efx_mac_select(
1318         __in            efx_nic_t *enp);
1319
1320 LIBEFX_INTERNAL
1321 extern  void
1322 efx_mac_multicast_hash_compute(
1323         __in_ecount(6*count)            uint8_t const *addrs,
1324         __in                            int count,
1325         __out                           efx_oword_t *hash_low,
1326         __out                           efx_oword_t *hash_high);
1327
1328 LIBEFX_INTERNAL
1329 extern  __checkReturn   efx_rc_t
1330 efx_phy_probe(
1331         __in            efx_nic_t *enp);
1332
1333 LIBEFX_INTERNAL
1334 extern                  void
1335 efx_phy_unprobe(
1336         __in            efx_nic_t *enp);
1337
1338 #if EFSYS_OPT_VPD
1339
1340 /* VPD utility functions */
1341
1342 LIBEFX_INTERNAL
1343 extern  __checkReturn           efx_rc_t
1344 efx_vpd_hunk_length(
1345         __in_bcount(size)       caddr_t data,
1346         __in                    size_t size,
1347         __out                   size_t *lengthp);
1348
1349 LIBEFX_INTERNAL
1350 extern  __checkReturn           efx_rc_t
1351 efx_vpd_hunk_verify(
1352         __in_bcount(size)       caddr_t data,
1353         __in                    size_t size,
1354         __out_opt               boolean_t *cksummedp);
1355
1356 LIBEFX_INTERNAL
1357 extern  __checkReturn           efx_rc_t
1358 efx_vpd_hunk_reinit(
1359         __in_bcount(size)       caddr_t data,
1360         __in                    size_t size,
1361         __in                    boolean_t wantpid);
1362
1363 LIBEFX_INTERNAL
1364 extern  __checkReturn           efx_rc_t
1365 efx_vpd_hunk_get(
1366         __in_bcount(size)       caddr_t data,
1367         __in                    size_t size,
1368         __in                    efx_vpd_tag_t tag,
1369         __in                    efx_vpd_keyword_t keyword,
1370         __out                   unsigned int *payloadp,
1371         __out                   uint8_t *paylenp);
1372
1373 LIBEFX_INTERNAL
1374 extern  __checkReturn                   efx_rc_t
1375 efx_vpd_hunk_next(
1376         __in_bcount(size)               caddr_t data,
1377         __in                            size_t size,
1378         __out                           efx_vpd_tag_t *tagp,
1379         __out                           efx_vpd_keyword_t *keyword,
1380         __out_opt                       unsigned int *payloadp,
1381         __out_opt                       uint8_t *paylenp,
1382         __inout                         unsigned int *contp);
1383
1384 LIBEFX_INTERNAL
1385 extern  __checkReturn           efx_rc_t
1386 efx_vpd_hunk_set(
1387         __in_bcount(size)       caddr_t data,
1388         __in                    size_t size,
1389         __in                    efx_vpd_value_t *evvp);
1390
1391 #endif  /* EFSYS_OPT_VPD */
1392
1393 #if EFSYS_OPT_MCDI
1394
1395 LIBEFX_INTERNAL
1396 extern  __checkReturn           efx_rc_t
1397 efx_mcdi_set_workaround(
1398         __in                    efx_nic_t *enp,
1399         __in                    uint32_t type,
1400         __in                    boolean_t enabled,
1401         __out_opt               uint32_t *flagsp);
1402
1403 LIBEFX_INTERNAL
1404 extern  __checkReturn           efx_rc_t
1405 efx_mcdi_get_workarounds(
1406         __in                    efx_nic_t *enp,
1407         __out_opt               uint32_t *implementedp,
1408         __out_opt               uint32_t *enabledp);
1409
1410 #endif /* EFSYS_OPT_MCDI */
1411
1412 #if EFSYS_OPT_MAC_STATS
1413
1414 /*
1415  * Closed range of stats (i.e. the first and the last are included).
1416  * The last must be greater or equal (if the range is one item only) to
1417  * the first.
1418  */
1419 struct efx_mac_stats_range {
1420         efx_mac_stat_t          first;
1421         efx_mac_stat_t          last;
1422 };
1423
1424 typedef enum efx_stats_action_e {
1425         EFX_STATS_CLEAR,
1426         EFX_STATS_UPLOAD,
1427         EFX_STATS_ENABLE_NOEVENTS,
1428         EFX_STATS_ENABLE_EVENTS,
1429         EFX_STATS_DISABLE,
1430 } efx_stats_action_t;
1431
1432 LIBEFX_INTERNAL
1433 extern                                  efx_rc_t
1434 efx_mac_stats_mask_add_ranges(
1435         __inout_bcount(mask_size)       uint32_t *maskp,
1436         __in                            size_t mask_size,
1437         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1438         __in                            unsigned int rng_count);
1439
1440 LIBEFX_INTERNAL
1441 extern  __checkReturn   efx_rc_t
1442 efx_mcdi_mac_stats(
1443         __in            efx_nic_t *enp,
1444         __in            uint32_t vport_id,
1445         __in_opt        efsys_mem_t *esmp,
1446         __in            efx_stats_action_t action,
1447         __in            uint16_t period_ms);
1448
1449 #endif  /* EFSYS_OPT_MAC_STATS */
1450
1451 #ifdef  __cplusplus
1452 }
1453 #endif
1454
1455 #endif  /* _SYS_EFX_IMPL_H */