drivers/common/sfc_efx/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2021 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #include "efx_regs_ef100.h"
  14 #if EFSYS_OPT_MCDI
  15 #include "efx_mcdi.h"
  16 #endif  /* EFSYS_OPT_MCDI */
  17
  18 /* FIXME: Add definition for driver generated software events */
  19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  21 #endif
  22
  23
  24 #if EFSYS_OPT_SIENA
  25 #include "siena_impl.h"
  26 #endif  /* EFSYS_OPT_SIENA */
  27
  28 #if EFSYS_OPT_HUNTINGTON
  29 #include "hunt_impl.h"
  30 #endif  /* EFSYS_OPT_HUNTINGTON */
  31
  32 #if EFSYS_OPT_MEDFORD
  33 #include "medford_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD */
  35
  36 #if EFSYS_OPT_MEDFORD2
  37 #include "medford2_impl.h"
  38 #endif  /* EFSYS_OPT_MEDFORD2 */
  39
  40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
  41 #include "ef10_impl.h"
  42 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
  43
  44 #if EFSYS_OPT_RIVERHEAD
  45 #include "rhead_impl.h"
  46 #endif  /* EFSYS_OPT_RIVERHEAD */
  47
  48 #ifdef  __cplusplus
  49 extern "C" {
  50 #endif
  51
  52 #define EFX_MOD_MCDI            0x00000001
  53 #define EFX_MOD_PROBE           0x00000002
  54 #define EFX_MOD_NVRAM           0x00000004
  55 #define EFX_MOD_VPD             0x00000008
  56 #define EFX_MOD_NIC             0x00000010
  57 #define EFX_MOD_INTR            0x00000020
  58 #define EFX_MOD_EV              0x00000040
  59 #define EFX_MOD_RX              0x00000080
  60 #define EFX_MOD_TX              0x00000100
  61 #define EFX_MOD_PORT            0x00000200
  62 #define EFX_MOD_MON             0x00000400
  63 #define EFX_MOD_FILTER          0x00001000
  64 #define EFX_MOD_LIC             0x00002000
  65 #define EFX_MOD_TUNNEL          0x00004000
  66 #define EFX_MOD_EVB             0x00008000
  67 #define EFX_MOD_PROXY           0x00010000
  68 #define EFX_MOD_VIRTIO          0x00020000
  69
  70 #define EFX_RESET_PHY           0x00000001
  71 #define EFX_RESET_RXQ_ERR       0x00000002
  72 #define EFX_RESET_TXQ_ERR       0x00000004
  73 #define EFX_RESET_HW_UNAVAIL    0x00000008
  74
  75 typedef enum efx_mac_type_e {
  76         EFX_MAC_INVALID = 0,
  77         EFX_MAC_SIENA,
  78         EFX_MAC_HUNTINGTON,
  79         EFX_MAC_MEDFORD,
  80         EFX_MAC_MEDFORD2,
  81         EFX_MAC_RIVERHEAD,
  82         EFX_MAC_NTYPES
  83 } efx_mac_type_t;
  84
  85 typedef struct efx_ev_ops_s {
  86         efx_rc_t        (*eevo_init)(efx_nic_t *);
  87         void            (*eevo_fini)(efx_nic_t *);
  88         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  89                                           efsys_mem_t *, size_t, uint32_t,
  90                                           uint32_t, uint32_t, efx_evq_t *);
  91         void            (*eevo_qdestroy)(efx_evq_t *);
  92         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  93         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  94         void            (*eevo_qpoll)(efx_evq_t *, unsigned int *,
  95                                         const efx_ev_callbacks_t *, void *);
  96         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  97 #if EFSYS_OPT_QSTATS
  98         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  99 #endif
 100 } efx_ev_ops_t;
 101
 102 typedef struct efx_tx_ops_s {
 103         efx_rc_t        (*etxo_init)(efx_nic_t *);
 104         void            (*etxo_fini)(efx_nic_t *);
 105         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 106                                         unsigned int, unsigned int,
 107                                         efsys_mem_t *, size_t,
 108                                         uint32_t, uint16_t,
 109                                         efx_evq_t *, efx_txq_t *,
 110                                         unsigned int *);
 111         void            (*etxo_qdestroy)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 113                                       unsigned int, unsigned int,
 114                                       unsigned int *);
 115         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 116         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 117         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 118         void            (*etxo_qenable)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 120         void            (*etxo_qpio_disable)(efx_txq_t *);
 121         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 122                                            size_t);
 123         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 124                                            unsigned int *);
 125         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 126                                       unsigned int, unsigned int,
 127                                       unsigned int *);
 128         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 129                                                 size_t, boolean_t,
 130                                                 efx_desc_t *);
 131         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 132                                                 uint32_t, uint8_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 135                                                 uint16_t, uint32_t, uint16_t,
 136                                                 efx_desc_t *, int);
 137         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 138                                                 efx_desc_t *);
 139         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 140                                                 efx_desc_t *);
 141 #if EFSYS_OPT_QSTATS
 142         void            (*etxo_qstats_update)(efx_txq_t *,
 143                                               efsys_stat_t *);
 144 #endif
 145 } efx_tx_ops_t;
 146
 147 typedef union efx_rxq_type_data_u {
 148         struct {
 149                 size_t          ed_buf_size;
 150         } ertd_default;
 151 #if EFSYS_OPT_RX_PACKED_STREAM
 152         struct {
 153                 uint32_t        eps_buf_size;
 154         } ertd_packed_stream;
 155 #endif
 156 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 157         struct {
 158                 uint32_t        eessb_bufs_per_desc;
 159                 uint32_t        eessb_max_dma_len;
 160                 uint32_t        eessb_buf_stride;
 161                 uint32_t        eessb_hol_block_timeout;
 162         } ertd_es_super_buffer;
 163 #endif
 164 } efx_rxq_type_data_t;
 165
 166 typedef struct efx_rx_ops_s {
 167         efx_rc_t        (*erxo_init)(efx_nic_t *);
 168         void            (*erxo_fini)(efx_nic_t *);
 169 #if EFSYS_OPT_RX_SCATTER
 170         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 171 #endif
 172 #if EFSYS_OPT_RX_SCALE
 173         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 174                                                     efx_rx_scale_context_type_t,
 175                                                     uint32_t, uint32_t *);
 176         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 177         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 178                                                efx_rx_hash_alg_t,
 179                                                efx_rx_hash_type_t, boolean_t);
 180         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 181                                               uint8_t *, size_t);
 182         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 183                                               unsigned int *, size_t);
 184         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 185                                             uint8_t *);
 186 #endif /* EFSYS_OPT_RX_SCALE */
 187         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 188                                               uint16_t *);
 189         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 190                                       unsigned int, unsigned int,
 191                                       unsigned int);
 192         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 193 #if EFSYS_OPT_RX_PACKED_STREAM
 194         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 195         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 196                                                 uint32_t, uint32_t,
 197                                                 uint16_t *, uint32_t *, uint32_t *);
 198 #endif
 199         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 200         void            (*erxo_qenable)(efx_rxq_t *);
 201         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 202                                         unsigned int, efx_rxq_type_t,
 203                                         const efx_rxq_type_data_t *,
 204                                         efsys_mem_t *, size_t, uint32_t,
 205                                         unsigned int,
 206                                         efx_evq_t *, efx_rxq_t *);
 207         void            (*erxo_qdestroy)(efx_rxq_t *);
 208 } efx_rx_ops_t;
 209
 210 typedef struct efx_mac_ops_s {
 211         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 212         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 213         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 214         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 215         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 216         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 217         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 218         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 219                                                       efx_rxq_t *, boolean_t);
 220         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 221 #if EFSYS_OPT_LOOPBACK
 222         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 223                                             efx_loopback_type_t);
 224 #endif  /* EFSYS_OPT_LOOPBACK */
 225 #if EFSYS_OPT_MAC_STATS
 226         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 227         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 228         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 229         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 230                                               uint16_t, boolean_t);
 231         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 232                                             efsys_stat_t *, uint32_t *);
 233 #endif  /* EFSYS_OPT_MAC_STATS */
 234 } efx_mac_ops_t;
 235
 236 typedef struct efx_phy_ops_s {
 237         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 238         efx_rc_t        (*epo_reset)(efx_nic_t *);
 239         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 240         efx_rc_t        (*epo_verify)(efx_nic_t *);
 241         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 242         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 243 #if EFSYS_OPT_PHY_STATS
 244         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 245                                             uint32_t *);
 246 #endif  /* EFSYS_OPT_PHY_STATS */
 247 #if EFSYS_OPT_BIST
 248         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 249         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 250         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 251                                          efx_bist_result_t *, uint32_t *,
 252                                          unsigned long *, size_t);
 253         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 254 #endif  /* EFSYS_OPT_BIST */
 255 } efx_phy_ops_t;
 256
 257 #if EFSYS_OPT_FILTER
 258
 259 /*
 260  * Policy for replacing existing filter when inserting a new one.
 261  * Note that all policies allow for storing the new lower priority
 262  * filters as overridden by existing higher priority ones. It is needed
 263  * to restore the lower priority filters on higher priority ones removal.
 264  */
 265 typedef enum efx_filter_replacement_policy_e {
 266         /* Cannot replace existing filter */
 267         EFX_FILTER_REPLACEMENT_NEVER,
 268         /* Higher priority filters can replace lower priotiry ones */
 269         EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY,
 270         /*
 271          * Higher priority filters can replace lower priority ones and
 272          * equal priority filters can replace each other.
 273          */
 274         EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY,
 275 } efx_filter_replacement_policy_t;
 276
 277 typedef struct efx_filter_ops_s {
 278         efx_rc_t        (*efo_init)(efx_nic_t *);
 279         void            (*efo_fini)(efx_nic_t *);
 280         efx_rc_t        (*efo_restore)(efx_nic_t *);
 281         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 282                                    efx_filter_replacement_policy_t policy);
 283         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 284         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 285                                    size_t, size_t *);
 286         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 287                                    boolean_t, boolean_t, boolean_t,
 288                                    uint8_t const *, uint32_t);
 289 } efx_filter_ops_t;
 290
 291 LIBEFX_INTERNAL
 292 extern  __checkReturn   efx_rc_t
 293 efx_filter_reconfigure(
 294         __in                            efx_nic_t *enp,
 295         __in_ecount(6)                  uint8_t const *mac_addr,
 296         __in                            boolean_t all_unicst,
 297         __in                            boolean_t mulcst,
 298         __in                            boolean_t all_mulcst,
 299         __in                            boolean_t brdcst,
 300         __in_ecount(6*count)            uint8_t const *addrs,
 301         __in                            uint32_t count);
 302
 303 #endif /* EFSYS_OPT_FILTER */
 304
 305 #if EFSYS_OPT_TUNNEL
 306 typedef struct efx_tunnel_ops_s {
 307         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 308         void            (*eto_fini)(efx_nic_t *);
 309 } efx_tunnel_ops_t;
 310 #endif /* EFSYS_OPT_TUNNEL */
 311
 312 #if EFSYS_OPT_VIRTIO
 313 typedef struct efx_virtio_ops_s {
 314         efx_rc_t        (*evo_virtio_qstart)(efx_virtio_vq_t *,
 315                                 efx_virtio_vq_cfg_t *,
 316                                 efx_virtio_vq_dyncfg_t *);
 317         efx_rc_t        (*evo_virtio_qstop)(efx_virtio_vq_t *,
 318                                 efx_virtio_vq_dyncfg_t *);
 319 } efx_virtio_ops_t;
 320 #endif /* EFSYS_OPT_VIRTIO */
 321
 322 typedef struct efx_port_s {
 323         efx_mac_type_t          ep_mac_type;
 324         uint32_t                ep_phy_type;
 325         uint8_t                 ep_port;
 326         uint32_t                ep_mac_pdu;
 327         uint8_t                 ep_mac_addr[6];
 328         efx_link_mode_t         ep_link_mode;
 329         boolean_t               ep_all_unicst;
 330         boolean_t               ep_all_unicst_inserted;
 331         boolean_t               ep_mulcst;
 332         boolean_t               ep_all_mulcst;
 333         boolean_t               ep_all_mulcst_inserted;
 334         boolean_t               ep_brdcst;
 335         unsigned int            ep_fcntl;
 336         boolean_t               ep_fcntl_autoneg;
 337         efx_oword_t             ep_multicst_hash[2];
 338         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 339                                                     EFX_MAC_MULTICAST_LIST_MAX];
 340         uint32_t                ep_mulcst_addr_count;
 341 #if EFSYS_OPT_LOOPBACK
 342         efx_loopback_type_t     ep_loopback_type;
 343         efx_link_mode_t         ep_loopback_link_mode;
 344 #endif  /* EFSYS_OPT_LOOPBACK */
 345 #if EFSYS_OPT_PHY_FLAGS
 346         uint32_t                ep_phy_flags;
 347 #endif  /* EFSYS_OPT_PHY_FLAGS */
 348 #if EFSYS_OPT_PHY_LED_CONTROL
 349         efx_phy_led_mode_t      ep_phy_led_mode;
 350 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 351         efx_phy_media_type_t    ep_fixed_port_type;
 352         efx_phy_media_type_t    ep_module_type;
 353         uint32_t                ep_adv_cap_mask;
 354         uint32_t                ep_lp_cap_mask;
 355         uint32_t                ep_default_adv_cap_mask;
 356         uint32_t                ep_phy_cap_mask;
 357         boolean_t               ep_mac_drain;
 358 #if EFSYS_OPT_BIST
 359         efx_bist_type_t         ep_current_bist;
 360 #endif
 361         const efx_mac_ops_t     *ep_emop;
 362         const efx_phy_ops_t     *ep_epop;
 363 } efx_port_t;
 364
 365 typedef struct efx_mon_ops_s {
 366 #if EFSYS_OPT_MON_STATS
 367         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 368                                             efx_mon_stat_value_t *);
 369         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 370                                              efx_mon_stat_limits_t *);
 371 #endif  /* EFSYS_OPT_MON_STATS */
 372 } efx_mon_ops_t;
 373
 374 typedef struct efx_mon_s {
 375         efx_mon_type_t          em_type;
 376         const efx_mon_ops_t     *em_emop;
 377 } efx_mon_t;
 378
 379 typedef struct efx_intr_ops_s {
 380         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 381         void            (*eio_enable)(efx_nic_t *);
 382         void            (*eio_disable)(efx_nic_t *);
 383         void            (*eio_disable_unlocked)(efx_nic_t *);
 384         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 385         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 386         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 387                                  boolean_t *);
 388         void            (*eio_fatal)(efx_nic_t *);
 389         void            (*eio_fini)(efx_nic_t *);
 390 } efx_intr_ops_t;
 391
 392 typedef struct efx_intr_s {
 393         const efx_intr_ops_t    *ei_eiop;
 394         efsys_mem_t             *ei_esmp;
 395         efx_intr_type_t         ei_type;
 396         unsigned int            ei_level;
 397 } efx_intr_t;
 398
 399 typedef struct efx_nic_ops_s {
 400         efx_rc_t        (*eno_probe)(efx_nic_t *);
 401         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 402         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 403         efx_rc_t        (*eno_reset)(efx_nic_t *);
 404         efx_rc_t        (*eno_init)(efx_nic_t *);
 405         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 406         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 407                                         uint32_t *, size_t *);
 408         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 409         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 410 #if EFSYS_OPT_DIAG
 411         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 412 #endif  /* EFSYS_OPT_DIAG */
 413         void            (*eno_fini)(efx_nic_t *);
 414         void            (*eno_unprobe)(efx_nic_t *);
 415 } efx_nic_ops_t;
 416
 417 #ifndef EFX_TXQ_LIMIT_TARGET
 418 #define EFX_TXQ_LIMIT_TARGET 259
 419 #endif
 420 #ifndef EFX_RXQ_LIMIT_TARGET
 421 #define EFX_RXQ_LIMIT_TARGET 512
 422 #endif
 423
 424
 425 #if EFSYS_OPT_FILTER
 426
 427 #if EFSYS_OPT_SIENA
 428
 429 typedef struct siena_filter_spec_s {
 430         uint8_t         sfs_type;
 431         uint32_t        sfs_flags;
 432         uint32_t        sfs_dmaq_id;
 433         uint32_t        sfs_dword[3];
 434 } siena_filter_spec_t;
 435
 436 typedef enum siena_filter_type_e {
 437         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 438         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 439         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 440         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 441         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 442         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 443
 444         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 445         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 446         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 447         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 448         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 449         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 450
 451         EFX_SIENA_FILTER_NTYPES
 452 } siena_filter_type_t;
 453
 454 typedef enum siena_filter_tbl_id_e {
 455         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 456         EFX_SIENA_FILTER_TBL_RX_MAC,
 457         EFX_SIENA_FILTER_TBL_TX_IP,
 458         EFX_SIENA_FILTER_TBL_TX_MAC,
 459         EFX_SIENA_FILTER_NTBLS
 460 } siena_filter_tbl_id_t;
 461
 462 typedef struct siena_filter_tbl_s {
 463         int                     sft_size;       /* number of entries */
 464         int                     sft_used;       /* active count */
 465         uint32_t                *sft_bitmap;    /* active bitmap */
 466         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 467 } siena_filter_tbl_t;
 468
 469 typedef struct siena_filter_s {
 470         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 471         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 472 } siena_filter_t;
 473
 474 #endif  /* EFSYS_OPT_SIENA */
 475
 476 typedef struct efx_filter_s {
 477 #if EFSYS_OPT_SIENA
 478         siena_filter_t          *ef_siena_filter;
 479 #endif /* EFSYS_OPT_SIENA */
 480 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 481         ef10_filter_table_t     *ef_ef10_filter_table;
 482 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 483 } efx_filter_t;
 484
 485 #if EFSYS_OPT_SIENA
 486
 487 LIBEFX_INTERNAL
 488 extern                  void
 489 siena_filter_tbl_clear(
 490         __in            efx_nic_t *enp,
 491         __in            siena_filter_tbl_id_t tbl);
 492
 493 #endif  /* EFSYS_OPT_SIENA */
 494
 495 #endif  /* EFSYS_OPT_FILTER */
 496
 497 #if EFSYS_OPT_MCDI
 498
 499 #define EFX_TUNNEL_MAXNENTRIES  (16)
 500
 501 #if EFSYS_OPT_TUNNEL
 502
 503 /* State of a UDP tunnel table entry */
 504 typedef enum efx_tunnel_udp_entry_state_e {
 505         EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */
 506         EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */
 507         EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */
 508 } efx_tunnel_udp_entry_state_t;
 509
 510 #if EFSYS_OPT_RIVERHEAD
 511 typedef uint32_t        efx_vnic_encap_rule_handle_t;
 512 #endif /* EFSYS_OPT_RIVERHEAD */
 513
 514 typedef struct efx_tunnel_udp_entry_s {
 515         uint16_t                        etue_port; /* host/cpu-endian */
 516         uint16_t                        etue_protocol;
 517         boolean_t                       etue_busy;
 518         efx_tunnel_udp_entry_state_t    etue_state;
 519 #if EFSYS_OPT_RIVERHEAD
 520         efx_vnic_encap_rule_handle_t    etue_handle;
 521 #endif /* EFSYS_OPT_RIVERHEAD */
 522 } efx_tunnel_udp_entry_t;
 523
 524 typedef struct efx_tunnel_cfg_s {
 525         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 526         unsigned int            etc_udp_entries_num;
 527 } efx_tunnel_cfg_t;
 528
 529 #endif /* EFSYS_OPT_TUNNEL */
 530
 531 typedef struct efx_mcdi_ops_s {
 532         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 533         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 534                                         void *, size_t);
 535         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 536         boolean_t       (*emco_poll_response)(efx_nic_t *);
 537         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 538         void            (*emco_fini)(efx_nic_t *);
 539         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 540                                             efx_mcdi_feature_id_t, boolean_t *);
 541         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 542                                             uint32_t *);
 543 } efx_mcdi_ops_t;
 544
 545 typedef struct efx_mcdi_s {
 546         const efx_mcdi_ops_t            *em_emcop;
 547         const efx_mcdi_transport_t      *em_emtp;
 548         efx_mcdi_iface_t                em_emip;
 549 } efx_mcdi_t;
 550
 551 #endif /* EFSYS_OPT_MCDI */
 552
 553 #if EFSYS_OPT_NVRAM
 554
 555 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 556 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 557
 558 typedef struct efx_nvram_ops_s {
 559 #if EFSYS_OPT_DIAG
 560         efx_rc_t        (*envo_test)(efx_nic_t *);
 561 #endif  /* EFSYS_OPT_DIAG */
 562         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 563                                             uint32_t *);
 564         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 565                                             efx_nvram_info_t *);
 566         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 567         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 568                                             unsigned int, caddr_t, size_t);
 569         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 570                                             unsigned int, caddr_t, size_t);
 571         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 572                                             unsigned int, size_t);
 573         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 574                                             unsigned int, caddr_t, size_t);
 575         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 576                                             uint32_t *);
 577         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 578                                             uint32_t *, uint16_t *);
 579         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 580                                             uint16_t *);
 581         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 582                                             caddr_t, size_t);
 583 } efx_nvram_ops_t;
 584 #endif /* EFSYS_OPT_NVRAM */
 585
 586 #if EFSYS_OPT_VPD
 587 typedef struct efx_vpd_ops_s {
 588         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 589         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 590         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 591         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 592         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 593         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 594                                         efx_vpd_value_t *);
 595         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 596                                         efx_vpd_value_t *);
 597         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 598                                         efx_vpd_value_t *, unsigned int *);
 599         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 600         void            (*evpdo_fini)(efx_nic_t *);
 601 } efx_vpd_ops_t;
 602 #endif  /* EFSYS_OPT_VPD */
 603
 604 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 605
 606 LIBEFX_INTERNAL
 607 extern  __checkReturn           efx_rc_t
 608 efx_mcdi_nvram_partitions(
 609         __in                    efx_nic_t *enp,
 610         __out_bcount(size)      caddr_t data,
 611         __in                    size_t size,
 612         __out                   unsigned int *npartnp);
 613
 614 LIBEFX_INTERNAL
 615 extern  __checkReturn           efx_rc_t
 616 efx_mcdi_nvram_metadata(
 617         __in                    efx_nic_t *enp,
 618         __in                    uint32_t partn,
 619         __out                   uint32_t *subtypep,
 620         __out_ecount(4)         uint16_t version[4],
 621         __out_bcount_opt(size)  char *descp,
 622         __in                    size_t size);
 623
 624 LIBEFX_INTERNAL
 625 extern  __checkReturn           efx_rc_t
 626 efx_mcdi_nvram_info(
 627         __in                    efx_nic_t *enp,
 628         __in                    uint32_t partn,
 629         __out                   efx_nvram_info_t *eni);
 630
 631 LIBEFX_INTERNAL
 632 extern  __checkReturn           efx_rc_t
 633 efx_mcdi_nvram_update_start(
 634         __in                    efx_nic_t *enp,
 635         __in                    uint32_t partn);
 636
 637 LIBEFX_INTERNAL
 638 extern  __checkReturn           efx_rc_t
 639 efx_mcdi_nvram_read(
 640         __in                    efx_nic_t *enp,
 641         __in                    uint32_t partn,
 642         __in                    uint32_t offset,
 643         __out_bcount(size)      caddr_t data,
 644         __in                    size_t size,
 645         __in                    uint32_t mode);
 646
 647 LIBEFX_INTERNAL
 648 extern  __checkReturn           efx_rc_t
 649 efx_mcdi_nvram_erase(
 650         __in                    efx_nic_t *enp,
 651         __in                    uint32_t partn,
 652         __in                    uint32_t offset,
 653         __in                    size_t size);
 654
 655 LIBEFX_INTERNAL
 656 extern  __checkReturn           efx_rc_t
 657 efx_mcdi_nvram_write(
 658         __in                    efx_nic_t *enp,
 659         __in                    uint32_t partn,
 660         __in                    uint32_t offset,
 661         __in_bcount(size)       caddr_t data,
 662         __in                    size_t size);
 663
 664 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 665 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 666
 667 LIBEFX_INTERNAL
 668 extern  __checkReturn           efx_rc_t
 669 efx_mcdi_nvram_update_finish(
 670         __in                    efx_nic_t *enp,
 671         __in                    uint32_t partn,
 672         __in                    boolean_t reboot,
 673         __in                    uint32_t flags,
 674         __out_opt               uint32_t *verify_resultp);
 675
 676 #if EFSYS_OPT_DIAG
 677
 678 LIBEFX_INTERNAL
 679 extern  __checkReturn           efx_rc_t
 680 efx_mcdi_nvram_test(
 681         __in                    efx_nic_t *enp,
 682         __in                    uint32_t partn);
 683
 684 #endif  /* EFSYS_OPT_DIAG */
 685
 686 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 687
 688 #if EFSYS_OPT_LICENSING
 689
 690 typedef struct efx_lic_ops_s {
 691         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 692         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 693         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 694         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 695                                       size_t *, uint8_t *);
 696         efx_rc_t        (*elo_find_start)
 697                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 698         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 699                                 uint32_t, uint32_t *);
 700         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 701                                 uint32_t, uint32_t *, uint32_t *);
 702         boolean_t       (*elo_validate_key)(efx_nic_t *,
 703                                 caddr_t, uint32_t);
 704         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 705                                 caddr_t, size_t, uint32_t, uint32_t,
 706                                 caddr_t, size_t, uint32_t *);
 707         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 708                                 caddr_t, size_t, uint32_t,
 709                                 caddr_t, uint32_t, uint32_t *);
 710         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 711                                 caddr_t, size_t, uint32_t,
 712                                 uint32_t, uint32_t, uint32_t *);
 713         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 714                                 caddr_t, size_t);
 715         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 716                                 caddr_t, size_t);
 717 } efx_lic_ops_t;
 718
 719 #endif
 720
 721 #if EFSYS_OPT_EVB
 722
 723 struct efx_vswitch_s {
 724         efx_nic_t               *ev_enp;
 725         efx_vswitch_id_t        ev_vswitch_id;
 726         uint32_t                ev_num_vports;
 727         /*
 728          * Vport configuration array: index 0 to store PF configuration
 729          * and next ev_num_vports-1 entries hold VFs configuration.
 730          */
 731         efx_vport_config_t      *ev_evcp;
 732 };
 733
 734 typedef struct efx_evb_ops_s {
 735         efx_rc_t        (*eeo_init)(efx_nic_t *);
 736         void            (*eeo_fini)(efx_nic_t *);
 737         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 738         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 739         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 740                                                 efx_vport_type_t, uint16_t,
 741                                                 boolean_t, efx_vport_id_t *);
 742         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 743                                                 efx_vport_id_t);
 744         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 745                                                 efx_vport_id_t, uint8_t *);
 746         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 747                                                 efx_vport_id_t, uint8_t *);
 748         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 749                                                 efx_vport_id_t);
 750         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 751                                                 efx_vport_id_t);
 752         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 753                                                 efx_vport_id_t, uint32_t);
 754         efx_rc_t        (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
 755                                                         efx_vport_id_t,
 756                                                         uint16_t *, uint8_t *,
 757                                                         boolean_t *);
 758         efx_rc_t        (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
 759                                                 efx_vport_id_t, efsys_mem_t *);
 760 } efx_evb_ops_t;
 761
 762 LIBEFX_INTERNAL
 763 extern __checkReturn    boolean_t
 764 efx_is_zero_eth_addr(
 765         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 766
 767 #endif /* EFSYS_OPT_EVB */
 768
 769 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 770
 771 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 772
 773
 774 typedef struct efx_proxy_ops_s {
 775         efx_rc_t        (*epo_init)(efx_nic_t *);
 776         void            (*epo_fini)(efx_nic_t *);
 777         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 778                                         efsys_mem_t *, efsys_mem_t *,
 779                                         uint32_t, uint32_t *, size_t);
 780         efx_rc_t        (*epo_disable)(efx_nic_t *);
 781         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 782                                         uint32_t, uint32_t, uint32_t);
 783         efx_rc_t        (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
 784                                         uint32_t, uint32_t);
 785         efx_rc_t        (*epo_complete_request)(efx_nic_t *, uint32_t,
 786                                         uint32_t, uint32_t);
 787         efx_rc_t        (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
 788         efx_rc_t        (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
 789                                         uint32_t, uint32_t *);
 790 } efx_proxy_ops_t;
 791
 792 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 793
 794 #if EFSYS_OPT_MAE
 795
 796 typedef struct efx_mae_field_cap_s {
 797         uint32_t                        emfc_support;
 798         boolean_t                       emfc_mask_affects_class;
 799         boolean_t                       emfc_match_affects_class;
 800 } efx_mae_field_cap_t;
 801
 802 typedef struct efx_mae_s {
 803         uint32_t                        em_max_n_action_prios;
 804         /*
 805          * The number of MAE field IDs recognised by the FW implementation.
 806          * Any field ID greater than or equal to this value is unsupported.
 807          */
 808         uint32_t                        em_max_nfields;
 809         /** Action rule match field capabilities. */
 810         efx_mae_field_cap_t             *em_action_rule_field_caps;
 811         size_t                          em_action_rule_field_caps_size;
 812         uint32_t                        em_max_n_outer_prios;
 813         uint32_t                        em_encap_types_supported;
 814         /** Outer rule match field capabilities. */
 815         efx_mae_field_cap_t             *em_outer_rule_field_caps;
 816         size_t                          em_outer_rule_field_caps_size;
 817 } efx_mae_t;
 818
 819 #endif /* EFSYS_OPT_MAE */
 820
 821 #define EFX_DRV_VER_MAX         20
 822
 823 typedef struct efx_drv_cfg_s {
 824         uint32_t                edc_min_vi_count;
 825         uint32_t                edc_max_vi_count;
 826
 827         uint32_t                edc_max_piobuf_count;
 828         uint32_t                edc_pio_alloc_size;
 829 } efx_drv_cfg_t;
 830
 831 struct efx_nic_s {
 832         uint32_t                en_magic;
 833         efx_family_t            en_family;
 834         uint32_t                en_features;
 835         efsys_identifier_t      *en_esip;
 836         efsys_lock_t            *en_eslp;
 837         efsys_bar_t             *en_esbp;
 838         unsigned int            en_mod_flags;
 839         unsigned int            en_reset_flags;
 840         efx_nic_cfg_t           en_nic_cfg;
 841         efx_drv_cfg_t           en_drv_cfg;
 842         efx_port_t              en_port;
 843         efx_mon_t               en_mon;
 844         efx_intr_t              en_intr;
 845         uint32_t                en_ev_qcount;
 846         uint32_t                en_rx_qcount;
 847         uint32_t                en_tx_qcount;
 848         const efx_nic_ops_t     *en_enop;
 849         const efx_ev_ops_t      *en_eevop;
 850         const efx_tx_ops_t      *en_etxop;
 851         const efx_rx_ops_t      *en_erxop;
 852         efx_fw_variant_t        efv;
 853         char                    en_drv_version[EFX_DRV_VER_MAX];
 854 #if EFSYS_OPT_FILTER
 855         efx_filter_t            en_filter;
 856         const efx_filter_ops_t  *en_efop;
 857 #endif  /* EFSYS_OPT_FILTER */
 858 #if EFSYS_OPT_TUNNEL
 859         efx_tunnel_cfg_t        en_tunnel_cfg;
 860         const efx_tunnel_ops_t  *en_etop;
 861 #endif /* EFSYS_OPT_TUNNEL */
 862 #if EFSYS_OPT_MCDI
 863         efx_mcdi_t              en_mcdi;
 864 #endif  /* EFSYS_OPT_MCDI */
 865 #if EFSYS_OPT_NVRAM
 866         uint32_t                en_nvram_partn_locked;
 867         const efx_nvram_ops_t   *en_envop;
 868 #endif  /* EFSYS_OPT_NVRAM */
 869 #if EFSYS_OPT_VPD
 870         const efx_vpd_ops_t     *en_evpdop;
 871 #endif  /* EFSYS_OPT_VPD */
 872 #if EFSYS_OPT_VIRTIO
 873         const efx_virtio_ops_t  *en_evop;
 874 #endif  /* EFSYS_OPT_VPD */
 875 #if EFSYS_OPT_RX_SCALE
 876         efx_rx_hash_support_t           en_hash_support;
 877         efx_rx_scale_context_type_t     en_rss_context_type;
 878         uint32_t                        en_rss_context;
 879 #endif  /* EFSYS_OPT_RX_SCALE */
 880         uint32_t                en_vport_id;
 881 #if EFSYS_OPT_LICENSING
 882         const efx_lic_ops_t     *en_elop;
 883         boolean_t               en_licensing_supported;
 884 #endif
 885         union {
 886 #if EFSYS_OPT_SIENA
 887                 struct {
 888 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 889                         unsigned int            enu_partn_mask;
 890 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 891 #if EFSYS_OPT_VPD
 892                         caddr_t                 enu_svpd;
 893                         size_t                  enu_svpd_length;
 894 #endif  /* EFSYS_OPT_VPD */
 895                         int                     enu_unused;
 896                 } siena;
 897 #endif  /* EFSYS_OPT_SIENA */
 898                 int     enu_unused;
 899         } en_u;
 900 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 901         union en_arch {
 902                 struct {
 903                         int                     ena_vi_base;
 904                         int                     ena_vi_count;
 905                         int                     ena_vi_shift;
 906                         uint32_t                ena_fcw_base;
 907 #if EFSYS_OPT_VPD
 908                         caddr_t                 ena_svpd;
 909                         size_t                  ena_svpd_length;
 910 #endif  /* EFSYS_OPT_VPD */
 911                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 912                         uint32_t                ena_piobuf_count;
 913                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 914                         uint32_t                ena_pio_write_vi_base;
 915                         /* Memory BAR mapping regions */
 916                         uint32_t                ena_uc_mem_map_offset;
 917                         size_t                  ena_uc_mem_map_size;
 918                         uint32_t                ena_wc_mem_map_offset;
 919                         size_t                  ena_wc_mem_map_size;
 920                 } ef10;
 921         } en_arch;
 922 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 923 #if EFSYS_OPT_EVB
 924         const efx_evb_ops_t     *en_eeop;
 925         struct efx_vswitch_s    *en_vswitchp;
 926 #endif  /* EFSYS_OPT_EVB */
 927 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 928         const efx_proxy_ops_t   *en_epop;
 929 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 930 #if EFSYS_OPT_MAE
 931         efx_mae_t               *en_maep;
 932 #endif  /* EFSYS_OPT_MAE */
 933 };
 934
 935 #define EFX_FAMILY_IS_EF10(_enp) \
 936         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 937          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 938          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 939
 940 #define EFX_FAMILY_IS_EF100(_enp) \
 941         ((_enp)->en_family == EFX_FAMILY_RIVERHEAD)
 942
 943
 944 #define EFX_NIC_MAGIC   0x02121996
 945
 946 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 947     const efx_ev_callbacks_t *, void *);
 948
 949 #if EFSYS_OPT_EV_EXTENDED_WIDTH
 950 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *,
 951     const efx_ev_callbacks_t *, void *);
 952 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */
 953
 954 typedef struct efx_evq_rxq_state_s {
 955         unsigned int                    eers_rx_read_ptr;
 956         unsigned int                    eers_rx_mask;
 957 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 958         unsigned int                    eers_rx_stream_npackets;
 959         boolean_t                       eers_rx_packed_stream;
 960 #endif
 961 #if EFSYS_OPT_RX_PACKED_STREAM
 962         unsigned int                    eers_rx_packed_stream_credits;
 963 #endif
 964 } efx_evq_rxq_state_t;
 965
 966 struct efx_evq_s {
 967         uint32_t                        ee_magic;
 968         uint32_t                        ee_flags;
 969         efx_nic_t                       *ee_enp;
 970         unsigned int                    ee_index;
 971         unsigned int                    ee_mask;
 972         efsys_mem_t                     *ee_esmp;
 973 #if EFSYS_OPT_QSTATS
 974         uint32_t                        ee_stat[EV_NQSTATS];
 975 #endif  /* EFSYS_OPT_QSTATS */
 976
 977         efx_ev_handler_t                ee_rx;
 978         efx_ev_handler_t                ee_tx;
 979         efx_ev_handler_t                ee_driver;
 980         efx_ev_handler_t                ee_global;
 981         efx_ev_handler_t                ee_drv_gen;
 982 #if EFSYS_OPT_MCDI
 983         efx_ev_handler_t                ee_mcdi;
 984 #endif  /* EFSYS_OPT_MCDI */
 985
 986 #if EFSYS_OPT_DESC_PROXY
 987         efx_ev_ew_handler_t             ee_ew_txq_desc;
 988         efx_ev_ew_handler_t             ee_ew_virtq_desc;
 989 #endif /* EFSYS_OPT_DESC_PROXY */
 990
 991         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 992 };
 993
 994 #define EFX_EVQ_MAGIC   0x08081997
 995
 996 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 997
 998 #if EFSYS_OPT_QSTATS
 999 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
1000         do {                                                            \
1001                 (_eep)->ee_stat[_stat]++;                               \
1002         _NOTE(CONSTANTCONDITION)                                        \
1003         } while (B_FALSE)
1004 #else
1005 #define EFX_EV_QSTAT_INCR(_eep, _stat)
1006 #endif
1007
1008 struct efx_rxq_s {
1009         uint32_t                        er_magic;
1010         efx_nic_t                       *er_enp;
1011         efx_evq_t                       *er_eep;
1012         unsigned int                    er_index;
1013         unsigned int                    er_label;
1014         unsigned int                    er_mask;
1015         size_t                          er_buf_size;
1016         efsys_mem_t                     *er_esmp;
1017         efx_evq_rxq_state_t             *er_ev_qstate;
1018         efx_rx_prefix_layout_t          er_prefix_layout;
1019 };
1020
1021 #define EFX_RXQ_MAGIC   0x15022005
1022
1023 struct efx_txq_s {
1024         uint32_t                        et_magic;
1025         efx_nic_t                       *et_enp;
1026         unsigned int                    et_index;
1027         unsigned int                    et_mask;
1028         efsys_mem_t                     *et_esmp;
1029 #if EFSYS_OPT_HUNTINGTON
1030         uint32_t                        et_pio_bufnum;
1031         uint32_t                        et_pio_blknum;
1032         uint32_t                        et_pio_write_offset;
1033         uint32_t                        et_pio_offset;
1034         size_t                          et_pio_size;
1035 #endif
1036 #if EFSYS_OPT_QSTATS
1037         uint32_t                        et_stat[TX_NQSTATS];
1038 #endif  /* EFSYS_OPT_QSTATS */
1039 };
1040
1041 #define EFX_TXQ_MAGIC   0x05092005
1042
1043 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
1044         do {                                                            \
1045                 (_dst)[0] = (_src)[0];                                  \
1046                 (_dst)[1] = (_src)[1];                                  \
1047                 (_dst)[2] = (_src)[2];                                  \
1048                 (_dst)[3] = (_src)[3];                                  \
1049                 (_dst)[4] = (_src)[4];                                  \
1050                 (_dst)[5] = (_src)[5];                                  \
1051         _NOTE(CONSTANTCONDITION)                                        \
1052         } while (B_FALSE)
1053
1054 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
1055         do {                                                            \
1056                 uint16_t *_d = (uint16_t *)(_dst);                      \
1057                 _d[0] = 0xffff;                                         \
1058                 _d[1] = 0xffff;                                         \
1059                 _d[2] = 0xffff;                                         \
1060         _NOTE(CONSTANTCONDITION)                                        \
1061         } while (B_FALSE)
1062
1063 #if EFSYS_OPT_CHECK_REG
1064 #define EFX_CHECK_REG(_enp, _reg)                                       \
1065         do {                                                            \
1066                 const char *name = #_reg;                               \
1067                 char min = name[4];                                     \
1068                 char max = name[5];                                     \
1069                 char rev;                                               \
1070                                                                         \
1071                 switch ((_enp)->en_family) {                            \
1072                 case EFX_FAMILY_SIENA:                                  \
1073                         rev = 'C';                                      \
1074                         break;                                          \
1075                                                                         \
1076                 case EFX_FAMILY_HUNTINGTON:                             \
1077                         rev = 'D';                                      \
1078                         break;                                          \
1079                                                                         \
1080                 case EFX_FAMILY_MEDFORD:                                \
1081                         rev = 'E';                                      \
1082                         break;                                          \
1083                                                                         \
1084                 case EFX_FAMILY_MEDFORD2:                               \
1085                         rev = 'F';                                      \
1086                         break;                                          \
1087                                                                         \
1088                 case EFX_FAMILY_RIVERHEAD:                              \
1089                         rev = 'G';                                      \
1090                         break;                                          \
1091                                                                         \
1092                 default:                                                \
1093                         rev = '?';                                      \
1094                         break;                                          \
1095                 }                                                       \
1096                                                                         \
1097                 EFSYS_ASSERT3S(rev, >=, min);                           \
1098                 EFSYS_ASSERT3S(rev, <=, max);                           \
1099                                                                         \
1100         _NOTE(CONSTANTCONDITION)                                        \
1101         } while (B_FALSE)
1102 #else
1103 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
1104         _NOTE(CONSTANTCONDITION)                                        \
1105         } while (B_FALSE)
1106 #endif
1107
1108 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
1109         do {                                                            \
1110                 EFX_CHECK_REG((_enp), (_reg));                          \
1111                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
1112                     (_edp), (_lock));                                   \
1113                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
1114                     uint32_t, _reg ## _OFST,                            \
1115                     uint32_t, (_edp)->ed_u32[0]);                       \
1116         _NOTE(CONSTANTCONDITION)                                        \
1117         } while (B_FALSE)
1118
1119 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
1120         do {                                                            \
1121                 EFX_CHECK_REG((_enp), (_reg));                          \
1122                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
1123                     uint32_t, _reg ## _OFST,                            \
1124                     uint32_t, (_edp)->ed_u32[0]);                       \
1125                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
1126                     (_edp), (_lock));                                   \
1127         _NOTE(CONSTANTCONDITION)                                        \
1128         } while (B_FALSE)
1129
1130 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
1131         do {                                                            \
1132                 EFX_CHECK_REG((_enp), (_reg));                          \
1133                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1134                     (_eqp));                                            \
1135                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1136                     uint32_t, _reg ## _OFST,                            \
1137                     uint32_t, (_eqp)->eq_u32[1],                        \
1138                     uint32_t, (_eqp)->eq_u32[0]);                       \
1139         _NOTE(CONSTANTCONDITION)                                        \
1140         } while (B_FALSE)
1141
1142 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1143         do {                                                            \
1144                 EFX_CHECK_REG((_enp), (_reg));                          \
1145                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1146                     uint32_t, _reg ## _OFST,                            \
1147                     uint32_t, (_eqp)->eq_u32[1],                        \
1148                     uint32_t, (_eqp)->eq_u32[0]);                       \
1149                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1150                     (_eqp));                                            \
1151         _NOTE(CONSTANTCONDITION)                                        \
1152         } while (B_FALSE)
1153
1154 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1155         do {                                                            \
1156                 EFX_CHECK_REG((_enp), (_reg));                          \
1157                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1158                     (_eop), B_TRUE);                                    \
1159                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1160                     uint32_t, _reg ## _OFST,                            \
1161                     uint32_t, (_eop)->eo_u32[3],                        \
1162                     uint32_t, (_eop)->eo_u32[2],                        \
1163                     uint32_t, (_eop)->eo_u32[1],                        \
1164                     uint32_t, (_eop)->eo_u32[0]);                       \
1165         _NOTE(CONSTANTCONDITION)                                        \
1166         } while (B_FALSE)
1167
1168 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1169         do {                                                            \
1170                 EFX_CHECK_REG((_enp), (_reg));                          \
1171                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1172                     uint32_t, _reg ## _OFST,                            \
1173                     uint32_t, (_eop)->eo_u32[3],                        \
1174                     uint32_t, (_eop)->eo_u32[2],                        \
1175                     uint32_t, (_eop)->eo_u32[1],                        \
1176                     uint32_t, (_eop)->eo_u32[0]);                       \
1177                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1178                     (_eop), B_TRUE);                                    \
1179         _NOTE(CONSTANTCONDITION)                                        \
1180         } while (B_FALSE)
1181
1182 /*
1183  * Accessors for memory BAR non-VI tables.
1184  *
1185  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1186  * to ensure the correct runtime VI window size is used on Medford2.
1187  *
1188  * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control
1189  * window registers, to ensure the correct starting offset is used.
1190  *
1191  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1192  */
1193
1194 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1195         do {                                                            \
1196                 EFX_CHECK_REG((_enp), (_reg));                          \
1197                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1198                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1199                     (_edp), (_lock));                                   \
1200                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1201                     uint32_t, (_index),                                 \
1202                     uint32_t, _reg ## _OFST,                            \
1203                     uint32_t, (_edp)->ed_u32[0]);                       \
1204         _NOTE(CONSTANTCONDITION)                                        \
1205         } while (B_FALSE)
1206
1207 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1208         do {                                                            \
1209                 EFX_CHECK_REG((_enp), (_reg));                          \
1210                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1211                     uint32_t, (_index),                                 \
1212                     uint32_t, _reg ## _OFST,                            \
1213                     uint32_t, (_edp)->ed_u32[0]);                       \
1214                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1215                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1216                     (_edp), (_lock));                                   \
1217         _NOTE(CONSTANTCONDITION)                                        \
1218         } while (B_FALSE)
1219
1220 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1221         do {                                                            \
1222                 EFX_CHECK_REG((_enp), (_reg));                          \
1223                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1224                     uint32_t, (_index),                                 \
1225                     uint32_t, _reg ## _OFST,                            \
1226                     uint32_t, (_edp)->ed_u32[0]);                       \
1227                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1228                     (_reg ## _OFST +                                    \
1229                     (3 * sizeof (efx_dword_t)) +                        \
1230                     ((_index) * _reg ## _STEP)),                        \
1231                     (_edp), (_lock));                                   \
1232         _NOTE(CONSTANTCONDITION)                                        \
1233         } while (B_FALSE)
1234
1235 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1236         do {                                                            \
1237                 EFX_CHECK_REG((_enp), (_reg));                          \
1238                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1239                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1240                     (_eqp));                                            \
1241                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1242                     uint32_t, (_index),                                 \
1243                     uint32_t, _reg ## _OFST,                            \
1244                     uint32_t, (_eqp)->eq_u32[1],                        \
1245                     uint32_t, (_eqp)->eq_u32[0]);                       \
1246         _NOTE(CONSTANTCONDITION)                                        \
1247         } while (B_FALSE)
1248
1249 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1250         do {                                                            \
1251                 EFX_CHECK_REG((_enp), (_reg));                          \
1252                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1253                     uint32_t, (_index),                                 \
1254                     uint32_t, _reg ## _OFST,                            \
1255                     uint32_t, (_eqp)->eq_u32[1],                        \
1256                     uint32_t, (_eqp)->eq_u32[0]);                       \
1257                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1258                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1259                     (_eqp));                                            \
1260         _NOTE(CONSTANTCONDITION)                                        \
1261         } while (B_FALSE)
1262
1263 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1264         do {                                                            \
1265                 EFX_CHECK_REG((_enp), (_reg));                          \
1266                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1267                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1268                     (_eop), (_lock));                                   \
1269                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1270                     uint32_t, (_index),                                 \
1271                     uint32_t, _reg ## _OFST,                            \
1272                     uint32_t, (_eop)->eo_u32[3],                        \
1273                     uint32_t, (_eop)->eo_u32[2],                        \
1274                     uint32_t, (_eop)->eo_u32[1],                        \
1275                     uint32_t, (_eop)->eo_u32[0]);                       \
1276         _NOTE(CONSTANTCONDITION)                                        \
1277         } while (B_FALSE)
1278
1279 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1280         do {                                                            \
1281                 EFX_CHECK_REG((_enp), (_reg));                          \
1282                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1283                     uint32_t, (_index),                                 \
1284                     uint32_t, _reg ## _OFST,                            \
1285                     uint32_t, (_eop)->eo_u32[3],                        \
1286                     uint32_t, (_eop)->eo_u32[2],                        \
1287                     uint32_t, (_eop)->eo_u32[1],                        \
1288                     uint32_t, (_eop)->eo_u32[0]);                       \
1289                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1290                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1291                     (_eop), (_lock));                                   \
1292         _NOTE(CONSTANTCONDITION)                                        \
1293         } while (B_FALSE)
1294
1295 /*
1296  * Accessors for memory BAR function control window registers.
1297  *
1298  * The function control window is located at an offset which can be
1299  * non-zero in case of Riverhead.
1300  */
1301
1302 #if EFSYS_OPT_RIVERHEAD
1303
1304 #define EFX_BAR_FCW_READD(_enp, _reg, _edp)                             \
1305         do {                                                            \
1306                 EFX_CHECK_REG((_enp), (_reg));                          \
1307                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST +        \
1308                     (_enp)->en_arch.ef10.ena_fcw_base,                  \
1309                     (_edp), B_FALSE);                                   \
1310                 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg,    \
1311                     uint32_t, _reg ## _OFST,                            \
1312                     uint32_t, (_edp)->ed_u32[0]);                       \
1313         _NOTE(CONSTANTCONDITION)                                        \
1314         } while (B_FALSE)
1315
1316 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp)                            \
1317         do {                                                            \
1318                 EFX_CHECK_REG((_enp), (_reg));                          \
1319                 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg,   \
1320                     uint32_t, _reg ## _OFST,                            \
1321                     uint32_t, (_edp)->ed_u32[0]);                       \
1322                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST +       \
1323                     (_enp)->en_arch.ef10.ena_fcw_base,                  \
1324                     (_edp), B_FALSE);                                   \
1325         _NOTE(CONSTANTCONDITION)                                        \
1326         } while (B_FALSE)
1327
1328 #endif  /* EFSYS_OPT_RIVERHEAD */
1329
1330 /*
1331  * Accessors for memory BAR per-VI registers.
1332  *
1333  * The VI window size is 8KB for Medford and all earlier controllers.
1334  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1335  */
1336
1337 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1338         do {                                                            \
1339                 EFX_CHECK_REG((_enp), (_reg));                          \
1340                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1341                     ((_reg ## _OFST) +                                  \
1342                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1343                     (_edp), (_lock));                                   \
1344                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1345                     uint32_t, (_index),                                 \
1346                     uint32_t, _reg ## _OFST,                            \
1347                     uint32_t, (_edp)->ed_u32[0]);                       \
1348         _NOTE(CONSTANTCONDITION)                                        \
1349         } while (B_FALSE)
1350
1351 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1352         do {                                                            \
1353                 EFX_CHECK_REG((_enp), (_reg));                          \
1354                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1355                     uint32_t, (_index),                                 \
1356                     uint32_t, _reg ## _OFST,                            \
1357                     uint32_t, (_edp)->ed_u32[0]);                       \
1358                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1359                     ((_reg ## _OFST) +                                  \
1360                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1361                     (_edp), (_lock));                                   \
1362         _NOTE(CONSTANTCONDITION)                                        \
1363         } while (B_FALSE)
1364
1365 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1366         do {                                                            \
1367                 EFX_CHECK_REG((_enp), (_reg));                          \
1368                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1369                     uint32_t, (_index),                                 \
1370                     uint32_t, _reg ## _OFST,                            \
1371                     uint32_t, (_edp)->ed_u32[0]);                       \
1372                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1373                     ((_reg ## _OFST) +                                  \
1374                     (2 * sizeof (efx_dword_t)) +                        \
1375                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1376                     (_edp), (_lock));                                   \
1377         _NOTE(CONSTANTCONDITION)                                        \
1378         } while (B_FALSE)
1379
1380 /*
1381  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1382  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1383  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1384  * the need for locking in the host, and are the only ones known to be safe to
1385  * use 128-bites write with.
1386  */
1387 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1388         do {                                                            \
1389                 EFX_CHECK_REG((_enp), (_reg));                          \
1390                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1391                     const char *, #_reg,                                \
1392                     uint32_t, (_index),                                 \
1393                     uint32_t, _reg ## _OFST,                            \
1394                     uint32_t, (_eop)->eo_u32[3],                        \
1395                     uint32_t, (_eop)->eo_u32[2],                        \
1396                     uint32_t, (_eop)->eo_u32[1],                        \
1397                     uint32_t, (_eop)->eo_u32[0]);                       \
1398                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1399                     (_reg ## _OFST +                                    \
1400                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1401                     (_eop));                                            \
1402         _NOTE(CONSTANTCONDITION)                                        \
1403         } while (B_FALSE)
1404
1405 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size,      \
1406                                       _wptr, _owptr)                    \
1407         do {                                                            \
1408                 unsigned int _new = (_wptr);                            \
1409                 unsigned int _old = (_owptr);                           \
1410                                                                         \
1411                 if ((_new) >= (_old))                                   \
1412                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1413                             (_old) * (_desc_size),                      \
1414                             ((_new) - (_old)) * (_desc_size));          \
1415                 else                                                    \
1416                         /*                                              \
1417                          * It is cheaper to sync entire map than sync   \
1418                          * two parts especially when offset/size are    \
1419                          * ignored and entire map is synced in any case.\
1420                          */                                             \
1421                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1422                             0,                                          \
1423                             (_entries) * (_desc_size));                 \
1424         _NOTE(CONSTANTCONDITION)                                        \
1425         } while (B_FALSE)
1426
1427 LIBEFX_INTERNAL
1428 extern  __checkReturn   efx_rc_t
1429 efx_mac_select(
1430         __in            efx_nic_t *enp);
1431
1432 LIBEFX_INTERNAL
1433 extern  void
1434 efx_mac_multicast_hash_compute(
1435         __in_ecount(6*count)            uint8_t const *addrs,
1436         __in                            int count,
1437         __out                           efx_oword_t *hash_low,
1438         __out                           efx_oword_t *hash_high);
1439
1440 LIBEFX_INTERNAL
1441 extern  __checkReturn   efx_rc_t
1442 efx_phy_probe(
1443         __in            efx_nic_t *enp);
1444
1445 LIBEFX_INTERNAL
1446 extern                  void
1447 efx_phy_unprobe(
1448         __in            efx_nic_t *enp);
1449
1450 #if EFSYS_OPT_VPD
1451
1452 /* VPD utility functions */
1453
1454 LIBEFX_INTERNAL
1455 extern  __checkReturn           efx_rc_t
1456 efx_vpd_hunk_length(
1457         __in_bcount(size)       caddr_t data,
1458         __in                    size_t size,
1459         __out                   size_t *lengthp);
1460
1461 LIBEFX_INTERNAL
1462 extern  __checkReturn           efx_rc_t
1463 efx_vpd_hunk_verify(
1464         __in_bcount(size)       caddr_t data,
1465         __in                    size_t size,
1466         __out_opt               boolean_t *cksummedp);
1467
1468 LIBEFX_INTERNAL
1469 extern  __checkReturn           efx_rc_t
1470 efx_vpd_hunk_reinit(
1471         __in_bcount(size)       caddr_t data,
1472         __in                    size_t size,
1473         __in                    boolean_t wantpid);
1474
1475 LIBEFX_INTERNAL
1476 extern  __checkReturn           efx_rc_t
1477 efx_vpd_hunk_get(
1478         __in_bcount(size)       caddr_t data,
1479         __in                    size_t size,
1480         __in                    efx_vpd_tag_t tag,
1481         __in                    efx_vpd_keyword_t keyword,
1482         __out                   unsigned int *payloadp,
1483         __out                   uint8_t *paylenp);
1484
1485 LIBEFX_INTERNAL
1486 extern  __checkReturn                   efx_rc_t
1487 efx_vpd_hunk_next(
1488         __in_bcount(size)               caddr_t data,
1489         __in                            size_t size,
1490         __out                           efx_vpd_tag_t *tagp,
1491         __out                           efx_vpd_keyword_t *keyword,
1492         __out_opt                       unsigned int *payloadp,
1493         __out_opt                       uint8_t *paylenp,
1494         __inout                         unsigned int *contp);
1495
1496 LIBEFX_INTERNAL
1497 extern  __checkReturn           efx_rc_t
1498 efx_vpd_hunk_set(
1499         __in_bcount(size)       caddr_t data,
1500         __in                    size_t size,
1501         __in                    efx_vpd_value_t *evvp);
1502
1503 #endif  /* EFSYS_OPT_VPD */
1504
1505 #if EFSYS_OPT_MCDI
1506
1507 LIBEFX_INTERNAL
1508 extern  __checkReturn           efx_rc_t
1509 efx_mcdi_set_workaround(
1510         __in                    efx_nic_t *enp,
1511         __in                    uint32_t type,
1512         __in                    boolean_t enabled,
1513         __out_opt               uint32_t *flagsp);
1514
1515 LIBEFX_INTERNAL
1516 extern  __checkReturn           efx_rc_t
1517 efx_mcdi_get_workarounds(
1518         __in                    efx_nic_t *enp,
1519         __out_opt               uint32_t *implementedp,
1520         __out_opt               uint32_t *enabledp);
1521
1522 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1523
1524 LIBEFX_INTERNAL
1525 extern  __checkReturn   efx_rc_t
1526 efx_mcdi_init_evq(
1527         __in            efx_nic_t *enp,
1528         __in            unsigned int instance,
1529         __in            efsys_mem_t *esmp,
1530         __in            size_t nevs,
1531         __in            uint32_t irq,
1532         __in            uint32_t us,
1533         __in            uint32_t flags,
1534         __in            boolean_t low_latency);
1535
1536 LIBEFX_INTERNAL
1537 extern  __checkReturn   efx_rc_t
1538 efx_mcdi_fini_evq(
1539         __in            efx_nic_t *enp,
1540         __in            uint32_t instance);
1541
1542 typedef struct efx_mcdi_init_rxq_params_s {
1543         boolean_t       disable_scatter;
1544         boolean_t       want_inner_classes;
1545         uint32_t        buf_size;
1546         uint32_t        ps_buf_size;
1547         uint32_t        es_bufs_per_desc;
1548         uint32_t        es_max_dma_len;
1549         uint32_t        es_buf_stride;
1550         uint32_t        hol_block_timeout;
1551         uint32_t        prefix_id;
1552 } efx_mcdi_init_rxq_params_t;
1553
1554 LIBEFX_INTERNAL
1555 extern  __checkReturn   efx_rc_t
1556 efx_mcdi_init_rxq(
1557         __in            efx_nic_t *enp,
1558         __in            uint32_t ndescs,
1559         __in            efx_evq_t *eep,
1560         __in            uint32_t label,
1561         __in            uint32_t instance,
1562         __in            efsys_mem_t *esmp,
1563         __in            const efx_mcdi_init_rxq_params_t *params);
1564
1565 LIBEFX_INTERNAL
1566 extern  __checkReturn   efx_rc_t
1567 efx_mcdi_fini_rxq(
1568         __in            efx_nic_t *enp,
1569         __in            uint32_t instance);
1570
1571 LIBEFX_INTERNAL
1572 extern  __checkReturn   efx_rc_t
1573 efx_mcdi_init_txq(
1574         __in            efx_nic_t *enp,
1575         __in            uint32_t ndescs,
1576         __in            uint32_t target_evq,
1577         __in            uint32_t label,
1578         __in            uint32_t instance,
1579         __in            uint16_t flags,
1580         __in            efsys_mem_t *esmp);
1581
1582 LIBEFX_INTERNAL
1583 extern  __checkReturn   efx_rc_t
1584 efx_mcdi_fini_txq(
1585         __in            efx_nic_t *enp,
1586         __in            uint32_t instance);
1587
1588 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1589
1590 #endif /* EFSYS_OPT_MCDI */
1591
1592 #if EFSYS_OPT_MAC_STATS
1593
1594 /*
1595  * Closed range of stats (i.e. the first and the last are included).
1596  * The last must be greater or equal (if the range is one item only) to
1597  * the first.
1598  */
1599 struct efx_mac_stats_range {
1600         efx_mac_stat_t          first;
1601         efx_mac_stat_t          last;
1602 };
1603
1604 typedef enum efx_stats_action_e {
1605         EFX_STATS_CLEAR,
1606         EFX_STATS_UPLOAD,
1607         EFX_STATS_ENABLE_NOEVENTS,
1608         EFX_STATS_ENABLE_EVENTS,
1609         EFX_STATS_DISABLE,
1610 } efx_stats_action_t;
1611
1612 LIBEFX_INTERNAL
1613 extern                                  efx_rc_t
1614 efx_mac_stats_mask_add_ranges(
1615         __inout_bcount(mask_size)       uint32_t *maskp,
1616         __in                            size_t mask_size,
1617         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1618         __in                            unsigned int rng_count);
1619
1620 LIBEFX_INTERNAL
1621 extern  __checkReturn   efx_rc_t
1622 efx_mcdi_mac_stats(
1623         __in            efx_nic_t *enp,
1624         __in            uint32_t vport_id,
1625         __in_opt        efsys_mem_t *esmp,
1626         __in            efx_stats_action_t action,
1627         __in            uint16_t period_ms);
1628
1629 #endif  /* EFSYS_OPT_MAC_STATS */
1630
1631 #if EFSYS_OPT_PCI
1632
1633 /*
1634  * Find the next extended capability in a PCI device's config space
1635  * with specified capability id.
1636  * Passing 0 offset makes the function search from the start.
1637  * If search succeeds, found capability is in modified offset.
1638  *
1639  * Returns ENOENT if a capability is not found.
1640  */
1641 LIBEFX_INTERNAL
1642 extern  __checkReturn                   efx_rc_t
1643 efx_pci_config_find_next_ext_cap(
1644         __in                            efsys_pci_config_t *espcp,
1645         __in                            const efx_pci_ops_t *epop,
1646         __in                            uint16_t cap_id,
1647         __inout                         size_t *offsetp);
1648
1649 /*
1650  * Get the next extended capability in a PCI device's config space.
1651  * Passing 0 offset makes the function get the first capability.
1652  * If search succeeds, the capability is in modified offset.
1653  *
1654  * Returns ENOENT if there is no next capability.
1655  */
1656 LIBEFX_INTERNAL
1657 extern  __checkReturn                   efx_rc_t
1658 efx_pci_config_next_ext_cap(
1659         __in                            efsys_pci_config_t *espcp,
1660         __in                            const efx_pci_ops_t *epop,
1661         __inout                         size_t *offsetp);
1662
1663 /*
1664  * Find the next Xilinx capabilities table location by searching
1665  * PCI extended capabilities.
1666  *
1667  * Returns ENOENT if a table location is not found.
1668  */
1669 LIBEFX_INTERNAL
1670 extern  __checkReturn                   efx_rc_t
1671 efx_pci_find_next_xilinx_cap_table(
1672         __in                            efsys_pci_config_t *espcp,
1673         __in                            const efx_pci_ops_t *epop,
1674         __inout                         size_t *pci_cap_offsetp,
1675         __out                           unsigned int *xilinx_tbl_barp,
1676         __out                           efsys_dma_addr_t *xilinx_tbl_offsetp);
1677
1678 /*
1679  * Read a Xilinx extended PCI capability that gives the location
1680  * of a Xilinx capabilities table.
1681  *
1682  * Returns ENOENT if the extended PCI capability does not contain
1683  * Xilinx capabilities table locator.
1684  */
1685 LIBEFX_INTERNAL
1686 extern  __checkReturn                   efx_rc_t
1687 efx_pci_read_ext_cap_xilinx_table(
1688         __in                            efsys_pci_config_t *espcp,
1689         __in                            const efx_pci_ops_t *epop,
1690         __in                            size_t cap_offset,
1691         __out                           unsigned int *barp,
1692         __out                           efsys_dma_addr_t *offsetp);
1693
1694 /*
1695  * Find a capability with specified format_id in a Xilinx capabilities table.
1696  * Searching is started from provided offset, taking skip_first into account.
1697  * If search succeeds, found capability is in modified offset.
1698  *
1699  * Returns ENOENT if an entry with specified format id is not found.
1700  */
1701 LIBEFX_INTERNAL
1702 extern  __checkReturn                   efx_rc_t
1703 efx_pci_xilinx_cap_tbl_find(
1704         __in                            efsys_bar_t *esbp,
1705         __in                            uint32_t format_id,
1706         __in                            boolean_t skip_first,
1707         __inout                         efsys_dma_addr_t *entry_offsetp);
1708
1709 #endif /* EFSYS_OPT_PCI */
1710
1711 #if EFSYS_OPT_MAE
1712
1713 struct efx_mae_match_spec_s {
1714         efx_mae_rule_type_t             emms_type;
1715         uint32_t                        emms_prio;
1716         union emms_mask_value_pairs {
1717                 uint8_t                 action[MAE_FIELD_MASK_VALUE_PAIRS_LEN];
1718                 uint8_t                 outer[MAE_ENC_FIELD_PAIRS_LEN];
1719         } emms_mask_value_pairs;
1720 };
1721
1722 typedef enum efx_mae_action_e {
1723         /* These actions are strictly ordered. */
1724         EFX_MAE_ACTION_VLAN_POP,
1725         EFX_MAE_ACTION_VLAN_PUSH,
1726
1727         /*
1728          * These actions are not strictly ordered and can
1729          * be passed by a client in any order (before DELIVER).
1730          * However, these enumerants must be kept compactly
1731          * in the end of the enumeration (before DELIVER).
1732          */
1733         EFX_MAE_ACTION_FLAG,
1734         EFX_MAE_ACTION_MARK,
1735
1736         /* DELIVER is always the last action. */
1737         EFX_MAE_ACTION_DELIVER,
1738
1739         EFX_MAE_NACTIONS
1740 } efx_mae_action_t;
1741
1742 /* MAE VLAN_POP action can handle 1 or 2 tags. */
1743 #define EFX_MAE_VLAN_POP_MAX_NTAGS      (2)
1744
1745 /* MAE VLAN_PUSH action can handle 1 or 2 tags. */
1746 #define EFX_MAE_VLAN_PUSH_MAX_NTAGS     (2)
1747
1748 typedef struct efx_mae_action_vlan_push_s {
1749         uint16_t                        emavp_tpid_be;
1750         uint16_t                        emavp_tci_be;
1751 } efx_mae_action_vlan_push_t;
1752
1753 struct efx_mae_actions_s {
1754         /* Bitmap of actions in spec, indexed by action type */
1755         uint32_t                        ema_actions;
1756
1757         unsigned int                    ema_n_vlan_tags_to_pop;
1758         unsigned int                    ema_n_vlan_tags_to_push;
1759         efx_mae_action_vlan_push_t      ema_vlan_push_descs[
1760             EFX_MAE_VLAN_PUSH_MAX_NTAGS];
1761         uint32_t                        ema_mark_value;
1762         efx_mport_sel_t                 ema_deliver_mport;
1763 };
1764
1765 #endif /* EFSYS_OPT_MAE */
1766
1767 #if EFSYS_OPT_VIRTIO
1768
1769 #define EFX_VQ_MAGIC    0x026011950
1770
1771 typedef enum efx_virtio_vq_state_e {
1772         EFX_VIRTIO_VQ_STATE_UNKNOWN = 0,
1773         EFX_VIRTIO_VQ_STATE_INITIALIZED,
1774         EFX_VIRTIO_VQ_STATE_STARTED,
1775         EFX_VIRTIO_VQ_NSTATES
1776 } efx_virtio_vq_state_t;
1777
1778 struct efx_virtio_vq_s {
1779         uint32_t                evv_magic;
1780         efx_nic_t               *evv_enp;
1781         efx_virtio_vq_state_t   evv_state;
1782         uint32_t                evv_vi_index;
1783         efx_virtio_vq_type_t    evv_type;
1784         uint16_t                evv_target_vf;
1785 };
1786
1787 #endif /* EFSYS_OPT_VIRTIO */
1788
1789 #ifdef  __cplusplus
1790 }
1791 #endif
1792
1793 #endif  /* _SYS_EFX_IMPL_H */