drivers/common/sfc_efx/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #include "efx_regs_ef100.h"
  14 #if EFSYS_OPT_MCDI
  15 #include "efx_mcdi.h"
  16 #endif  /* EFSYS_OPT_MCDI */
  17
  18 /* FIXME: Add definition for driver generated software events */
  19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  21 #endif
  22
  23
  24 #if EFSYS_OPT_SIENA
  25 #include "siena_impl.h"
  26 #endif  /* EFSYS_OPT_SIENA */
  27
  28 #if EFSYS_OPT_HUNTINGTON
  29 #include "hunt_impl.h"
  30 #endif  /* EFSYS_OPT_HUNTINGTON */
  31
  32 #if EFSYS_OPT_MEDFORD
  33 #include "medford_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD */
  35
  36 #if EFSYS_OPT_MEDFORD2
  37 #include "medford2_impl.h"
  38 #endif  /* EFSYS_OPT_MEDFORD2 */
  39
  40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
  41 #include "ef10_impl.h"
  42 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
  43
  44 #if EFSYS_OPT_RIVERHEAD
  45 #include "rhead_impl.h"
  46 #endif  /* EFSYS_OPT_RIVERHEAD */
  47
  48 #ifdef  __cplusplus
  49 extern "C" {
  50 #endif
  51
  52 #define EFX_MOD_MCDI            0x00000001
  53 #define EFX_MOD_PROBE           0x00000002
  54 #define EFX_MOD_NVRAM           0x00000004
  55 #define EFX_MOD_VPD             0x00000008
  56 #define EFX_MOD_NIC             0x00000010
  57 #define EFX_MOD_INTR            0x00000020
  58 #define EFX_MOD_EV              0x00000040
  59 #define EFX_MOD_RX              0x00000080
  60 #define EFX_MOD_TX              0x00000100
  61 #define EFX_MOD_PORT            0x00000200
  62 #define EFX_MOD_MON             0x00000400
  63 #define EFX_MOD_FILTER          0x00001000
  64 #define EFX_MOD_LIC             0x00002000
  65 #define EFX_MOD_TUNNEL          0x00004000
  66 #define EFX_MOD_EVB             0x00008000
  67 #define EFX_MOD_PROXY           0x00010000
  68
  69 #define EFX_RESET_PHY           0x00000001
  70 #define EFX_RESET_RXQ_ERR       0x00000002
  71 #define EFX_RESET_TXQ_ERR       0x00000004
  72 #define EFX_RESET_HW_UNAVAIL    0x00000008
  73
  74 typedef enum efx_mac_type_e {
  75         EFX_MAC_INVALID = 0,
  76         EFX_MAC_SIENA,
  77         EFX_MAC_HUNTINGTON,
  78         EFX_MAC_MEDFORD,
  79         EFX_MAC_MEDFORD2,
  80         EFX_MAC_RIVERHEAD,
  81         EFX_MAC_NTYPES
  82 } efx_mac_type_t;
  83
  84 typedef struct efx_ev_ops_s {
  85         efx_rc_t        (*eevo_init)(efx_nic_t *);
  86         void            (*eevo_fini)(efx_nic_t *);
  87         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  88                                           efsys_mem_t *, size_t, uint32_t,
  89                                           uint32_t, uint32_t, efx_evq_t *);
  90         void            (*eevo_qdestroy)(efx_evq_t *);
  91         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  92         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  93         void            (*eevo_qpoll)(efx_evq_t *, unsigned int *,
  94                                         const efx_ev_callbacks_t *, void *);
  95         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  96 #if EFSYS_OPT_QSTATS
  97         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  98 #endif
  99 } efx_ev_ops_t;
 100
 101 typedef struct efx_tx_ops_s {
 102         efx_rc_t        (*etxo_init)(efx_nic_t *);
 103         void            (*etxo_fini)(efx_nic_t *);
 104         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 105                                         unsigned int, unsigned int,
 106                                         efsys_mem_t *, size_t,
 107                                         uint32_t, uint16_t,
 108                                         efx_evq_t *, efx_txq_t *,
 109                                         unsigned int *);
 110         void            (*etxo_qdestroy)(efx_txq_t *);
 111         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 112                                       unsigned int, unsigned int,
 113                                       unsigned int *);
 114         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 115         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 116         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 117         void            (*etxo_qenable)(efx_txq_t *);
 118         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 119         void            (*etxo_qpio_disable)(efx_txq_t *);
 120         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 121                                            size_t);
 122         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 123                                            unsigned int *);
 124         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 125                                       unsigned int, unsigned int,
 126                                       unsigned int *);
 127         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 128                                                 size_t, boolean_t,
 129                                                 efx_desc_t *);
 130         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 131                                                 uint32_t, uint8_t,
 132                                                 efx_desc_t *);
 133         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 134                                                 uint16_t, uint32_t, uint16_t,
 135                                                 efx_desc_t *, int);
 136         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 137                                                 efx_desc_t *);
 138         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 139                                                 efx_desc_t *);
 140 #if EFSYS_OPT_QSTATS
 141         void            (*etxo_qstats_update)(efx_txq_t *,
 142                                               efsys_stat_t *);
 143 #endif
 144 } efx_tx_ops_t;
 145
 146 typedef union efx_rxq_type_data_u {
 147         struct {
 148                 size_t          ed_buf_size;
 149         } ertd_default;
 150 #if EFSYS_OPT_RX_PACKED_STREAM
 151         struct {
 152                 uint32_t        eps_buf_size;
 153         } ertd_packed_stream;
 154 #endif
 155 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 156         struct {
 157                 uint32_t        eessb_bufs_per_desc;
 158                 uint32_t        eessb_max_dma_len;
 159                 uint32_t        eessb_buf_stride;
 160                 uint32_t        eessb_hol_block_timeout;
 161         } ertd_es_super_buffer;
 162 #endif
 163 } efx_rxq_type_data_t;
 164
 165 typedef struct efx_rx_ops_s {
 166         efx_rc_t        (*erxo_init)(efx_nic_t *);
 167         void            (*erxo_fini)(efx_nic_t *);
 168 #if EFSYS_OPT_RX_SCATTER
 169         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 170 #endif
 171 #if EFSYS_OPT_RX_SCALE
 172         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 173                                                     efx_rx_scale_context_type_t,
 174                                                     uint32_t, uint32_t *);
 175         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 176         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 177                                                efx_rx_hash_alg_t,
 178                                                efx_rx_hash_type_t, boolean_t);
 179         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 180                                               uint8_t *, size_t);
 181         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 182                                               unsigned int *, size_t);
 183         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 184                                             uint8_t *);
 185 #endif /* EFSYS_OPT_RX_SCALE */
 186         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 187                                               uint16_t *);
 188         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 189                                       unsigned int, unsigned int,
 190                                       unsigned int);
 191         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 192 #if EFSYS_OPT_RX_PACKED_STREAM
 193         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 194         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 195                                                 uint32_t, uint32_t,
 196                                                 uint16_t *, uint32_t *, uint32_t *);
 197 #endif
 198         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 199         void            (*erxo_qenable)(efx_rxq_t *);
 200         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 201                                         unsigned int, efx_rxq_type_t,
 202                                         const efx_rxq_type_data_t *,
 203                                         efsys_mem_t *, size_t, uint32_t,
 204                                         unsigned int,
 205                                         efx_evq_t *, efx_rxq_t *);
 206         void            (*erxo_qdestroy)(efx_rxq_t *);
 207 } efx_rx_ops_t;
 208
 209 typedef struct efx_mac_ops_s {
 210         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 211         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 212         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 213         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 214         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 215         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 216         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 217         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 218                                                       efx_rxq_t *, boolean_t);
 219         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 220 #if EFSYS_OPT_LOOPBACK
 221         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 222                                             efx_loopback_type_t);
 223 #endif  /* EFSYS_OPT_LOOPBACK */
 224 #if EFSYS_OPT_MAC_STATS
 225         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 226         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 227         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 228         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 229                                               uint16_t, boolean_t);
 230         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 231                                             efsys_stat_t *, uint32_t *);
 232 #endif  /* EFSYS_OPT_MAC_STATS */
 233 } efx_mac_ops_t;
 234
 235 typedef struct efx_phy_ops_s {
 236         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 237         efx_rc_t        (*epo_reset)(efx_nic_t *);
 238         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 239         efx_rc_t        (*epo_verify)(efx_nic_t *);
 240         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 241         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 242 #if EFSYS_OPT_PHY_STATS
 243         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 244                                             uint32_t *);
 245 #endif  /* EFSYS_OPT_PHY_STATS */
 246 #if EFSYS_OPT_BIST
 247         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 248         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 249         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 250                                          efx_bist_result_t *, uint32_t *,
 251                                          unsigned long *, size_t);
 252         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 253 #endif  /* EFSYS_OPT_BIST */
 254 } efx_phy_ops_t;
 255
 256 #if EFSYS_OPT_FILTER
 257
 258 /*
 259  * Policy for replacing existing filter when inserting a new one.
 260  * Note that all policies allow for storing the new lower priority
 261  * filters as overridden by existing higher priority ones. It is needed
 262  * to restore the lower priority filters on higher priority ones removal.
 263  */
 264 typedef enum efx_filter_replacement_policy_e {
 265         /* Cannot replace existing filter */
 266         EFX_FILTER_REPLACEMENT_NEVER,
 267         /* Higher priority filters can replace lower priotiry ones */
 268         EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY,
 269         /*
 270          * Higher priority filters can replace lower priority ones and
 271          * equal priority filters can replace each other.
 272          */
 273         EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY,
 274 } efx_filter_replacement_policy_t;
 275
 276 typedef struct efx_filter_ops_s {
 277         efx_rc_t        (*efo_init)(efx_nic_t *);
 278         void            (*efo_fini)(efx_nic_t *);
 279         efx_rc_t        (*efo_restore)(efx_nic_t *);
 280         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 281                                    efx_filter_replacement_policy_t policy);
 282         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 283         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 284                                    size_t, size_t *);
 285         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 286                                    boolean_t, boolean_t, boolean_t,
 287                                    uint8_t const *, uint32_t);
 288 } efx_filter_ops_t;
 289
 290 LIBEFX_INTERNAL
 291 extern  __checkReturn   efx_rc_t
 292 efx_filter_reconfigure(
 293         __in                            efx_nic_t *enp,
 294         __in_ecount(6)                  uint8_t const *mac_addr,
 295         __in                            boolean_t all_unicst,
 296         __in                            boolean_t mulcst,
 297         __in                            boolean_t all_mulcst,
 298         __in                            boolean_t brdcst,
 299         __in_ecount(6*count)            uint8_t const *addrs,
 300         __in                            uint32_t count);
 301
 302 #endif /* EFSYS_OPT_FILTER */
 303
 304 #if EFSYS_OPT_TUNNEL
 305 typedef struct efx_tunnel_ops_s {
 306         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 307         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 308 } efx_tunnel_ops_t;
 309 #endif /* EFSYS_OPT_TUNNEL */
 310
 311 typedef struct efx_port_s {
 312         efx_mac_type_t          ep_mac_type;
 313         uint32_t                ep_phy_type;
 314         uint8_t                 ep_port;
 315         uint32_t                ep_mac_pdu;
 316         uint8_t                 ep_mac_addr[6];
 317         efx_link_mode_t         ep_link_mode;
 318         boolean_t               ep_all_unicst;
 319         boolean_t               ep_all_unicst_inserted;
 320         boolean_t               ep_mulcst;
 321         boolean_t               ep_all_mulcst;
 322         boolean_t               ep_all_mulcst_inserted;
 323         boolean_t               ep_brdcst;
 324         unsigned int            ep_fcntl;
 325         boolean_t               ep_fcntl_autoneg;
 326         efx_oword_t             ep_multicst_hash[2];
 327         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 328                                                     EFX_MAC_MULTICAST_LIST_MAX];
 329         uint32_t                ep_mulcst_addr_count;
 330 #if EFSYS_OPT_LOOPBACK
 331         efx_loopback_type_t     ep_loopback_type;
 332         efx_link_mode_t         ep_loopback_link_mode;
 333 #endif  /* EFSYS_OPT_LOOPBACK */
 334 #if EFSYS_OPT_PHY_FLAGS
 335         uint32_t                ep_phy_flags;
 336 #endif  /* EFSYS_OPT_PHY_FLAGS */
 337 #if EFSYS_OPT_PHY_LED_CONTROL
 338         efx_phy_led_mode_t      ep_phy_led_mode;
 339 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 340         efx_phy_media_type_t    ep_fixed_port_type;
 341         efx_phy_media_type_t    ep_module_type;
 342         uint32_t                ep_adv_cap_mask;
 343         uint32_t                ep_lp_cap_mask;
 344         uint32_t                ep_default_adv_cap_mask;
 345         uint32_t                ep_phy_cap_mask;
 346         boolean_t               ep_mac_drain;
 347 #if EFSYS_OPT_BIST
 348         efx_bist_type_t         ep_current_bist;
 349 #endif
 350         const efx_mac_ops_t     *ep_emop;
 351         const efx_phy_ops_t     *ep_epop;
 352 } efx_port_t;
 353
 354 typedef struct efx_mon_ops_s {
 355 #if EFSYS_OPT_MON_STATS
 356         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 357                                             efx_mon_stat_value_t *);
 358         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 359                                              efx_mon_stat_limits_t *);
 360 #endif  /* EFSYS_OPT_MON_STATS */
 361 } efx_mon_ops_t;
 362
 363 typedef struct efx_mon_s {
 364         efx_mon_type_t          em_type;
 365         const efx_mon_ops_t     *em_emop;
 366 } efx_mon_t;
 367
 368 typedef struct efx_intr_ops_s {
 369         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 370         void            (*eio_enable)(efx_nic_t *);
 371         void            (*eio_disable)(efx_nic_t *);
 372         void            (*eio_disable_unlocked)(efx_nic_t *);
 373         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 374         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 375         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 376                                  boolean_t *);
 377         void            (*eio_fatal)(efx_nic_t *);
 378         void            (*eio_fini)(efx_nic_t *);
 379 } efx_intr_ops_t;
 380
 381 typedef struct efx_intr_s {
 382         const efx_intr_ops_t    *ei_eiop;
 383         efsys_mem_t             *ei_esmp;
 384         efx_intr_type_t         ei_type;
 385         unsigned int            ei_level;
 386 } efx_intr_t;
 387
 388 typedef struct efx_nic_ops_s {
 389         efx_rc_t        (*eno_probe)(efx_nic_t *);
 390         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 391         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 392         efx_rc_t        (*eno_reset)(efx_nic_t *);
 393         efx_rc_t        (*eno_init)(efx_nic_t *);
 394         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 395         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 396                                         uint32_t *, size_t *);
 397         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 398         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 399 #if EFSYS_OPT_DIAG
 400         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 401 #endif  /* EFSYS_OPT_DIAG */
 402         void            (*eno_fini)(efx_nic_t *);
 403         void            (*eno_unprobe)(efx_nic_t *);
 404 } efx_nic_ops_t;
 405
 406 #ifndef EFX_TXQ_LIMIT_TARGET
 407 #define EFX_TXQ_LIMIT_TARGET 259
 408 #endif
 409 #ifndef EFX_RXQ_LIMIT_TARGET
 410 #define EFX_RXQ_LIMIT_TARGET 512
 411 #endif
 412
 413
 414 #if EFSYS_OPT_FILTER
 415
 416 #if EFSYS_OPT_SIENA
 417
 418 typedef struct siena_filter_spec_s {
 419         uint8_t         sfs_type;
 420         uint32_t        sfs_flags;
 421         uint32_t        sfs_dmaq_id;
 422         uint32_t        sfs_dword[3];
 423 } siena_filter_spec_t;
 424
 425 typedef enum siena_filter_type_e {
 426         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 427         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 428         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 429         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 430         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 431         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 432
 433         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 434         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 435         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 436         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 437         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 438         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 439
 440         EFX_SIENA_FILTER_NTYPES
 441 } siena_filter_type_t;
 442
 443 typedef enum siena_filter_tbl_id_e {
 444         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 445         EFX_SIENA_FILTER_TBL_RX_MAC,
 446         EFX_SIENA_FILTER_TBL_TX_IP,
 447         EFX_SIENA_FILTER_TBL_TX_MAC,
 448         EFX_SIENA_FILTER_NTBLS
 449 } siena_filter_tbl_id_t;
 450
 451 typedef struct siena_filter_tbl_s {
 452         int                     sft_size;       /* number of entries */
 453         int                     sft_used;       /* active count */
 454         uint32_t                *sft_bitmap;    /* active bitmap */
 455         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 456 } siena_filter_tbl_t;
 457
 458 typedef struct siena_filter_s {
 459         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 460         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 461 } siena_filter_t;
 462
 463 #endif  /* EFSYS_OPT_SIENA */
 464
 465 typedef struct efx_filter_s {
 466 #if EFSYS_OPT_SIENA
 467         siena_filter_t          *ef_siena_filter;
 468 #endif /* EFSYS_OPT_SIENA */
 469 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 470         ef10_filter_table_t     *ef_ef10_filter_table;
 471 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 472 } efx_filter_t;
 473
 474 #if EFSYS_OPT_SIENA
 475
 476 LIBEFX_INTERNAL
 477 extern                  void
 478 siena_filter_tbl_clear(
 479         __in            efx_nic_t *enp,
 480         __in            siena_filter_tbl_id_t tbl);
 481
 482 #endif  /* EFSYS_OPT_SIENA */
 483
 484 #endif  /* EFSYS_OPT_FILTER */
 485
 486 #if EFSYS_OPT_MCDI
 487
 488 #define EFX_TUNNEL_MAXNENTRIES  (16)
 489
 490 #if EFSYS_OPT_TUNNEL
 491
 492 typedef struct efx_tunnel_udp_entry_s {
 493         uint16_t                        etue_port; /* host/cpu-endian */
 494         uint16_t                        etue_protocol;
 495 } efx_tunnel_udp_entry_t;
 496
 497 typedef struct efx_tunnel_cfg_s {
 498         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 499         unsigned int            etc_udp_entries_num;
 500 } efx_tunnel_cfg_t;
 501
 502 #endif /* EFSYS_OPT_TUNNEL */
 503
 504 typedef struct efx_mcdi_ops_s {
 505         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 506         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 507                                         void *, size_t);
 508         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 509         boolean_t       (*emco_poll_response)(efx_nic_t *);
 510         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 511         void            (*emco_fini)(efx_nic_t *);
 512         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 513                                             efx_mcdi_feature_id_t, boolean_t *);
 514         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 515                                             uint32_t *);
 516 } efx_mcdi_ops_t;
 517
 518 typedef struct efx_mcdi_s {
 519         const efx_mcdi_ops_t            *em_emcop;
 520         const efx_mcdi_transport_t      *em_emtp;
 521         efx_mcdi_iface_t                em_emip;
 522 } efx_mcdi_t;
 523
 524 #endif /* EFSYS_OPT_MCDI */
 525
 526 #if EFSYS_OPT_NVRAM
 527
 528 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 529 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 530
 531 typedef struct efx_nvram_ops_s {
 532 #if EFSYS_OPT_DIAG
 533         efx_rc_t        (*envo_test)(efx_nic_t *);
 534 #endif  /* EFSYS_OPT_DIAG */
 535         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 536                                             uint32_t *);
 537         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 538                                             efx_nvram_info_t *);
 539         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 540         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 541                                             unsigned int, caddr_t, size_t);
 542         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 543                                             unsigned int, caddr_t, size_t);
 544         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 545                                             unsigned int, size_t);
 546         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 547                                             unsigned int, caddr_t, size_t);
 548         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 549                                             uint32_t *);
 550         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 551                                             uint32_t *, uint16_t *);
 552         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 553                                             uint16_t *);
 554         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 555                                             caddr_t, size_t);
 556 } efx_nvram_ops_t;
 557 #endif /* EFSYS_OPT_NVRAM */
 558
 559 #if EFSYS_OPT_VPD
 560 typedef struct efx_vpd_ops_s {
 561         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 562         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 563         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 564         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 565         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 566         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 567                                         efx_vpd_value_t *);
 568         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 569                                         efx_vpd_value_t *);
 570         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 571                                         efx_vpd_value_t *, unsigned int *);
 572         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 573         void            (*evpdo_fini)(efx_nic_t *);
 574 } efx_vpd_ops_t;
 575 #endif  /* EFSYS_OPT_VPD */
 576
 577 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 578
 579 LIBEFX_INTERNAL
 580 extern  __checkReturn           efx_rc_t
 581 efx_mcdi_nvram_partitions(
 582         __in                    efx_nic_t *enp,
 583         __out_bcount(size)      caddr_t data,
 584         __in                    size_t size,
 585         __out                   unsigned int *npartnp);
 586
 587 LIBEFX_INTERNAL
 588 extern  __checkReturn           efx_rc_t
 589 efx_mcdi_nvram_metadata(
 590         __in                    efx_nic_t *enp,
 591         __in                    uint32_t partn,
 592         __out                   uint32_t *subtypep,
 593         __out_ecount(4)         uint16_t version[4],
 594         __out_bcount_opt(size)  char *descp,
 595         __in                    size_t size);
 596
 597 LIBEFX_INTERNAL
 598 extern  __checkReturn           efx_rc_t
 599 efx_mcdi_nvram_info(
 600         __in                    efx_nic_t *enp,
 601         __in                    uint32_t partn,
 602         __out                   efx_nvram_info_t *eni);
 603
 604 LIBEFX_INTERNAL
 605 extern  __checkReturn           efx_rc_t
 606 efx_mcdi_nvram_update_start(
 607         __in                    efx_nic_t *enp,
 608         __in                    uint32_t partn);
 609
 610 LIBEFX_INTERNAL
 611 extern  __checkReturn           efx_rc_t
 612 efx_mcdi_nvram_read(
 613         __in                    efx_nic_t *enp,
 614         __in                    uint32_t partn,
 615         __in                    uint32_t offset,
 616         __out_bcount(size)      caddr_t data,
 617         __in                    size_t size,
 618         __in                    uint32_t mode);
 619
 620 LIBEFX_INTERNAL
 621 extern  __checkReturn           efx_rc_t
 622 efx_mcdi_nvram_erase(
 623         __in                    efx_nic_t *enp,
 624         __in                    uint32_t partn,
 625         __in                    uint32_t offset,
 626         __in                    size_t size);
 627
 628 LIBEFX_INTERNAL
 629 extern  __checkReturn           efx_rc_t
 630 efx_mcdi_nvram_write(
 631         __in                    efx_nic_t *enp,
 632         __in                    uint32_t partn,
 633         __in                    uint32_t offset,
 634         __in_bcount(size)       caddr_t data,
 635         __in                    size_t size);
 636
 637 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 638 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 639
 640 LIBEFX_INTERNAL
 641 extern  __checkReturn           efx_rc_t
 642 efx_mcdi_nvram_update_finish(
 643         __in                    efx_nic_t *enp,
 644         __in                    uint32_t partn,
 645         __in                    boolean_t reboot,
 646         __in                    uint32_t flags,
 647         __out_opt               uint32_t *verify_resultp);
 648
 649 #if EFSYS_OPT_DIAG
 650
 651 LIBEFX_INTERNAL
 652 extern  __checkReturn           efx_rc_t
 653 efx_mcdi_nvram_test(
 654         __in                    efx_nic_t *enp,
 655         __in                    uint32_t partn);
 656
 657 #endif  /* EFSYS_OPT_DIAG */
 658
 659 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 660
 661 #if EFSYS_OPT_LICENSING
 662
 663 typedef struct efx_lic_ops_s {
 664         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 665         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 666         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 667         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 668                                       size_t *, uint8_t *);
 669         efx_rc_t        (*elo_find_start)
 670                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 671         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 672                                 uint32_t, uint32_t *);
 673         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 674                                 uint32_t, uint32_t *, uint32_t *);
 675         boolean_t       (*elo_validate_key)(efx_nic_t *,
 676                                 caddr_t, uint32_t);
 677         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 678                                 caddr_t, size_t, uint32_t, uint32_t,
 679                                 caddr_t, size_t, uint32_t *);
 680         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 681                                 caddr_t, size_t, uint32_t,
 682                                 caddr_t, uint32_t, uint32_t *);
 683         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 684                                 caddr_t, size_t, uint32_t,
 685                                 uint32_t, uint32_t, uint32_t *);
 686         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 687                                 caddr_t, size_t);
 688         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 689                                 caddr_t, size_t);
 690 } efx_lic_ops_t;
 691
 692 #endif
 693
 694 #if EFSYS_OPT_EVB
 695
 696 struct efx_vswitch_s {
 697         efx_nic_t               *ev_enp;
 698         efx_vswitch_id_t        ev_vswitch_id;
 699         uint32_t                ev_num_vports;
 700         /*
 701          * Vport configuration array: index 0 to store PF configuration
 702          * and next ev_num_vports-1 entries hold VFs configuration.
 703          */
 704         efx_vport_config_t      *ev_evcp;
 705 };
 706
 707 typedef struct efx_evb_ops_s {
 708         efx_rc_t        (*eeo_init)(efx_nic_t *);
 709         void            (*eeo_fini)(efx_nic_t *);
 710         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 711         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 712         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 713                                                 efx_vport_type_t, uint16_t,
 714                                                 boolean_t, efx_vport_id_t *);
 715         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 716                                                 efx_vport_id_t);
 717         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 718                                                 efx_vport_id_t, uint8_t *);
 719         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 720                                                 efx_vport_id_t, uint8_t *);
 721         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 722                                                 efx_vport_id_t);
 723         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 724                                                 efx_vport_id_t);
 725         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 726                                                 efx_vport_id_t, uint32_t);
 727         efx_rc_t        (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
 728                                                         efx_vport_id_t,
 729                                                         uint16_t *, uint8_t *,
 730                                                         boolean_t *);
 731         efx_rc_t        (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
 732                                                 efx_vport_id_t, efsys_mem_t *);
 733 } efx_evb_ops_t;
 734
 735 LIBEFX_INTERNAL
 736 extern __checkReturn    boolean_t
 737 efx_is_zero_eth_addr(
 738         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 739
 740 #endif /* EFSYS_OPT_EVB */
 741
 742 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 743
 744 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 745
 746
 747 typedef struct efx_proxy_ops_s {
 748         efx_rc_t        (*epo_init)(efx_nic_t *);
 749         void            (*epo_fini)(efx_nic_t *);
 750         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 751                                         efsys_mem_t *, efsys_mem_t *,
 752                                         uint32_t, uint32_t *, size_t);
 753         efx_rc_t        (*epo_disable)(efx_nic_t *);
 754         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 755                                         uint32_t, uint32_t, uint32_t);
 756         efx_rc_t        (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
 757                                         uint32_t, uint32_t);
 758         efx_rc_t        (*epo_complete_request)(efx_nic_t *, uint32_t,
 759                                         uint32_t, uint32_t);
 760         efx_rc_t        (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
 761         efx_rc_t        (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
 762                                         uint32_t, uint32_t *);
 763 } efx_proxy_ops_t;
 764
 765 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 766
 767 #define EFX_DRV_VER_MAX         20
 768
 769 typedef struct efx_drv_cfg_s {
 770         uint32_t                edc_min_vi_count;
 771         uint32_t                edc_max_vi_count;
 772
 773         uint32_t                edc_max_piobuf_count;
 774         uint32_t                edc_pio_alloc_size;
 775 } efx_drv_cfg_t;
 776
 777 struct efx_nic_s {
 778         uint32_t                en_magic;
 779         efx_family_t            en_family;
 780         uint32_t                en_features;
 781         efsys_identifier_t      *en_esip;
 782         efsys_lock_t            *en_eslp;
 783         efsys_bar_t             *en_esbp;
 784         unsigned int            en_mod_flags;
 785         unsigned int            en_reset_flags;
 786         efx_nic_cfg_t           en_nic_cfg;
 787         efx_drv_cfg_t           en_drv_cfg;
 788         efx_port_t              en_port;
 789         efx_mon_t               en_mon;
 790         efx_intr_t              en_intr;
 791         uint32_t                en_ev_qcount;
 792         uint32_t                en_rx_qcount;
 793         uint32_t                en_tx_qcount;
 794         const efx_nic_ops_t     *en_enop;
 795         const efx_ev_ops_t      *en_eevop;
 796         const efx_tx_ops_t      *en_etxop;
 797         const efx_rx_ops_t      *en_erxop;
 798         efx_fw_variant_t        efv;
 799         char                    en_drv_version[EFX_DRV_VER_MAX];
 800 #if EFSYS_OPT_FILTER
 801         efx_filter_t            en_filter;
 802         const efx_filter_ops_t  *en_efop;
 803 #endif  /* EFSYS_OPT_FILTER */
 804 #if EFSYS_OPT_TUNNEL
 805         efx_tunnel_cfg_t        en_tunnel_cfg;
 806         const efx_tunnel_ops_t  *en_etop;
 807 #endif /* EFSYS_OPT_TUNNEL */
 808 #if EFSYS_OPT_MCDI
 809         efx_mcdi_t              en_mcdi;
 810 #endif  /* EFSYS_OPT_MCDI */
 811 #if EFSYS_OPT_NVRAM
 812         uint32_t                en_nvram_partn_locked;
 813         const efx_nvram_ops_t   *en_envop;
 814 #endif  /* EFSYS_OPT_NVRAM */
 815 #if EFSYS_OPT_VPD
 816         const efx_vpd_ops_t     *en_evpdop;
 817 #endif  /* EFSYS_OPT_VPD */
 818 #if EFSYS_OPT_RX_SCALE
 819         efx_rx_hash_support_t           en_hash_support;
 820         efx_rx_scale_context_type_t     en_rss_context_type;
 821         uint32_t                        en_rss_context;
 822 #endif  /* EFSYS_OPT_RX_SCALE */
 823         uint32_t                en_vport_id;
 824 #if EFSYS_OPT_LICENSING
 825         const efx_lic_ops_t     *en_elop;
 826         boolean_t               en_licensing_supported;
 827 #endif
 828         union {
 829 #if EFSYS_OPT_SIENA
 830                 struct {
 831 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 832                         unsigned int            enu_partn_mask;
 833 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 834 #if EFSYS_OPT_VPD
 835                         caddr_t                 enu_svpd;
 836                         size_t                  enu_svpd_length;
 837 #endif  /* EFSYS_OPT_VPD */
 838                         int                     enu_unused;
 839                 } siena;
 840 #endif  /* EFSYS_OPT_SIENA */
 841                 int     enu_unused;
 842         } en_u;
 843 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 844         union en_arch {
 845                 struct {
 846                         int                     ena_vi_base;
 847                         int                     ena_vi_count;
 848                         int                     ena_vi_shift;
 849                         uint32_t                ena_fcw_base;
 850 #if EFSYS_OPT_VPD
 851                         caddr_t                 ena_svpd;
 852                         size_t                  ena_svpd_length;
 853 #endif  /* EFSYS_OPT_VPD */
 854                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 855                         uint32_t                ena_piobuf_count;
 856                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 857                         uint32_t                ena_pio_write_vi_base;
 858                         /* Memory BAR mapping regions */
 859                         uint32_t                ena_uc_mem_map_offset;
 860                         size_t                  ena_uc_mem_map_size;
 861                         uint32_t                ena_wc_mem_map_offset;
 862                         size_t                  ena_wc_mem_map_size;
 863                 } ef10;
 864         } en_arch;
 865 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 866 #if EFSYS_OPT_EVB
 867         const efx_evb_ops_t     *en_eeop;
 868         struct efx_vswitch_s    *en_vswitchp;
 869 #endif  /* EFSYS_OPT_EVB */
 870 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 871         const efx_proxy_ops_t   *en_epop;
 872 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 873 };
 874
 875 #define EFX_FAMILY_IS_EF10(_enp) \
 876         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 877          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 878          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 879
 880 #define EFX_FAMILY_IS_EF100(_enp) \
 881         ((_enp)->en_family == EFX_FAMILY_RIVERHEAD)
 882
 883
 884 #define EFX_NIC_MAGIC   0x02121996
 885
 886 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 887     const efx_ev_callbacks_t *, void *);
 888
 889 typedef struct efx_evq_rxq_state_s {
 890         unsigned int                    eers_rx_read_ptr;
 891         unsigned int                    eers_rx_mask;
 892 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 893         unsigned int                    eers_rx_stream_npackets;
 894         boolean_t                       eers_rx_packed_stream;
 895 #endif
 896 #if EFSYS_OPT_RX_PACKED_STREAM
 897         unsigned int                    eers_rx_packed_stream_credits;
 898 #endif
 899 } efx_evq_rxq_state_t;
 900
 901 struct efx_evq_s {
 902         uint32_t                        ee_magic;
 903         uint32_t                        ee_flags;
 904         efx_nic_t                       *ee_enp;
 905         unsigned int                    ee_index;
 906         unsigned int                    ee_mask;
 907         efsys_mem_t                     *ee_esmp;
 908 #if EFSYS_OPT_QSTATS
 909         uint32_t                        ee_stat[EV_NQSTATS];
 910 #endif  /* EFSYS_OPT_QSTATS */
 911
 912         efx_ev_handler_t                ee_rx;
 913         efx_ev_handler_t                ee_tx;
 914         efx_ev_handler_t                ee_driver;
 915         efx_ev_handler_t                ee_global;
 916         efx_ev_handler_t                ee_drv_gen;
 917 #if EFSYS_OPT_MCDI
 918         efx_ev_handler_t                ee_mcdi;
 919 #endif  /* EFSYS_OPT_MCDI */
 920
 921         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 922 };
 923
 924 #define EFX_EVQ_MAGIC   0x08081997
 925
 926 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 927
 928 #if EFSYS_OPT_QSTATS
 929 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
 930         do {                                                            \
 931                 (_eep)->ee_stat[_stat]++;                               \
 932         _NOTE(CONSTANTCONDITION)                                        \
 933         } while (B_FALSE)
 934 #else
 935 #define EFX_EV_QSTAT_INCR(_eep, _stat)
 936 #endif
 937
 938 struct efx_rxq_s {
 939         uint32_t                        er_magic;
 940         efx_nic_t                       *er_enp;
 941         efx_evq_t                       *er_eep;
 942         unsigned int                    er_index;
 943         unsigned int                    er_label;
 944         unsigned int                    er_mask;
 945         size_t                          er_buf_size;
 946         efsys_mem_t                     *er_esmp;
 947         efx_evq_rxq_state_t             *er_ev_qstate;
 948         efx_rx_prefix_layout_t          er_prefix_layout;
 949 };
 950
 951 #define EFX_RXQ_MAGIC   0x15022005
 952
 953 struct efx_txq_s {
 954         uint32_t                        et_magic;
 955         efx_nic_t                       *et_enp;
 956         unsigned int                    et_index;
 957         unsigned int                    et_mask;
 958         efsys_mem_t                     *et_esmp;
 959 #if EFSYS_OPT_HUNTINGTON
 960         uint32_t                        et_pio_bufnum;
 961         uint32_t                        et_pio_blknum;
 962         uint32_t                        et_pio_write_offset;
 963         uint32_t                        et_pio_offset;
 964         size_t                          et_pio_size;
 965 #endif
 966 #if EFSYS_OPT_QSTATS
 967         uint32_t                        et_stat[TX_NQSTATS];
 968 #endif  /* EFSYS_OPT_QSTATS */
 969 };
 970
 971 #define EFX_TXQ_MAGIC   0x05092005
 972
 973 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 974         do {                                                            \
 975                 (_dst)[0] = (_src)[0];                                  \
 976                 (_dst)[1] = (_src)[1];                                  \
 977                 (_dst)[2] = (_src)[2];                                  \
 978                 (_dst)[3] = (_src)[3];                                  \
 979                 (_dst)[4] = (_src)[4];                                  \
 980                 (_dst)[5] = (_src)[5];                                  \
 981         _NOTE(CONSTANTCONDITION)                                        \
 982         } while (B_FALSE)
 983
 984 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 985         do {                                                            \
 986                 uint16_t *_d = (uint16_t *)(_dst);                      \
 987                 _d[0] = 0xffff;                                         \
 988                 _d[1] = 0xffff;                                         \
 989                 _d[2] = 0xffff;                                         \
 990         _NOTE(CONSTANTCONDITION)                                        \
 991         } while (B_FALSE)
 992
 993 #if EFSYS_OPT_CHECK_REG
 994 #define EFX_CHECK_REG(_enp, _reg)                                       \
 995         do {                                                            \
 996                 const char *name = #_reg;                               \
 997                 char min = name[4];                                     \
 998                 char max = name[5];                                     \
 999                 char rev;                                               \
1000                                                                         \
1001                 switch ((_enp)->en_family) {                            \
1002                 case EFX_FAMILY_SIENA:                                  \
1003                         rev = 'C';                                      \
1004                         break;                                          \
1005                                                                         \
1006                 case EFX_FAMILY_HUNTINGTON:                             \
1007                         rev = 'D';                                      \
1008                         break;                                          \
1009                                                                         \
1010                 case EFX_FAMILY_MEDFORD:                                \
1011                         rev = 'E';                                      \
1012                         break;                                          \
1013                                                                         \
1014                 case EFX_FAMILY_MEDFORD2:                               \
1015                         rev = 'F';                                      \
1016                         break;                                          \
1017                                                                         \
1018                 case EFX_FAMILY_RIVERHEAD:                              \
1019                         rev = 'G';                                      \
1020                         break;                                          \
1021                                                                         \
1022                 default:                                                \
1023                         rev = '?';                                      \
1024                         break;                                          \
1025                 }                                                       \
1026                                                                         \
1027                 EFSYS_ASSERT3S(rev, >=, min);                           \
1028                 EFSYS_ASSERT3S(rev, <=, max);                           \
1029                                                                         \
1030         _NOTE(CONSTANTCONDITION)                                        \
1031         } while (B_FALSE)
1032 #else
1033 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
1034         _NOTE(CONSTANTCONDITION)                                        \
1035         } while (B_FALSE)
1036 #endif
1037
1038 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
1039         do {                                                            \
1040                 EFX_CHECK_REG((_enp), (_reg));                          \
1041                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
1042                     (_edp), (_lock));                                   \
1043                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
1044                     uint32_t, _reg ## _OFST,                            \
1045                     uint32_t, (_edp)->ed_u32[0]);                       \
1046         _NOTE(CONSTANTCONDITION)                                        \
1047         } while (B_FALSE)
1048
1049 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
1050         do {                                                            \
1051                 EFX_CHECK_REG((_enp), (_reg));                          \
1052                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
1053                     uint32_t, _reg ## _OFST,                            \
1054                     uint32_t, (_edp)->ed_u32[0]);                       \
1055                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
1056                     (_edp), (_lock));                                   \
1057         _NOTE(CONSTANTCONDITION)                                        \
1058         } while (B_FALSE)
1059
1060 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
1061         do {                                                            \
1062                 EFX_CHECK_REG((_enp), (_reg));                          \
1063                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1064                     (_eqp));                                            \
1065                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1066                     uint32_t, _reg ## _OFST,                            \
1067                     uint32_t, (_eqp)->eq_u32[1],                        \
1068                     uint32_t, (_eqp)->eq_u32[0]);                       \
1069         _NOTE(CONSTANTCONDITION)                                        \
1070         } while (B_FALSE)
1071
1072 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1073         do {                                                            \
1074                 EFX_CHECK_REG((_enp), (_reg));                          \
1075                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1076                     uint32_t, _reg ## _OFST,                            \
1077                     uint32_t, (_eqp)->eq_u32[1],                        \
1078                     uint32_t, (_eqp)->eq_u32[0]);                       \
1079                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1080                     (_eqp));                                            \
1081         _NOTE(CONSTANTCONDITION)                                        \
1082         } while (B_FALSE)
1083
1084 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1085         do {                                                            \
1086                 EFX_CHECK_REG((_enp), (_reg));                          \
1087                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1088                     (_eop), B_TRUE);                                    \
1089                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1090                     uint32_t, _reg ## _OFST,                            \
1091                     uint32_t, (_eop)->eo_u32[3],                        \
1092                     uint32_t, (_eop)->eo_u32[2],                        \
1093                     uint32_t, (_eop)->eo_u32[1],                        \
1094                     uint32_t, (_eop)->eo_u32[0]);                       \
1095         _NOTE(CONSTANTCONDITION)                                        \
1096         } while (B_FALSE)
1097
1098 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1099         do {                                                            \
1100                 EFX_CHECK_REG((_enp), (_reg));                          \
1101                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1102                     uint32_t, _reg ## _OFST,                            \
1103                     uint32_t, (_eop)->eo_u32[3],                        \
1104                     uint32_t, (_eop)->eo_u32[2],                        \
1105                     uint32_t, (_eop)->eo_u32[1],                        \
1106                     uint32_t, (_eop)->eo_u32[0]);                       \
1107                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1108                     (_eop), B_TRUE);                                    \
1109         _NOTE(CONSTANTCONDITION)                                        \
1110         } while (B_FALSE)
1111
1112 /*
1113  * Accessors for memory BAR non-VI tables.
1114  *
1115  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1116  * to ensure the correct runtime VI window size is used on Medford2.
1117  *
1118  * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control
1119  * window registers, to ensure the correct starting offset is used.
1120  *
1121  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1122  */
1123
1124 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1125         do {                                                            \
1126                 EFX_CHECK_REG((_enp), (_reg));                          \
1127                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1128                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1129                     (_edp), (_lock));                                   \
1130                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1131                     uint32_t, (_index),                                 \
1132                     uint32_t, _reg ## _OFST,                            \
1133                     uint32_t, (_edp)->ed_u32[0]);                       \
1134         _NOTE(CONSTANTCONDITION)                                        \
1135         } while (B_FALSE)
1136
1137 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1138         do {                                                            \
1139                 EFX_CHECK_REG((_enp), (_reg));                          \
1140                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1141                     uint32_t, (_index),                                 \
1142                     uint32_t, _reg ## _OFST,                            \
1143                     uint32_t, (_edp)->ed_u32[0]);                       \
1144                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1145                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1146                     (_edp), (_lock));                                   \
1147         _NOTE(CONSTANTCONDITION)                                        \
1148         } while (B_FALSE)
1149
1150 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1151         do {                                                            \
1152                 EFX_CHECK_REG((_enp), (_reg));                          \
1153                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1154                     uint32_t, (_index),                                 \
1155                     uint32_t, _reg ## _OFST,                            \
1156                     uint32_t, (_edp)->ed_u32[0]);                       \
1157                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1158                     (_reg ## _OFST +                                    \
1159                     (3 * sizeof (efx_dword_t)) +                        \
1160                     ((_index) * _reg ## _STEP)),                        \
1161                     (_edp), (_lock));                                   \
1162         _NOTE(CONSTANTCONDITION)                                        \
1163         } while (B_FALSE)
1164
1165 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1166         do {                                                            \
1167                 EFX_CHECK_REG((_enp), (_reg));                          \
1168                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1169                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1170                     (_eqp));                                            \
1171                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1172                     uint32_t, (_index),                                 \
1173                     uint32_t, _reg ## _OFST,                            \
1174                     uint32_t, (_eqp)->eq_u32[1],                        \
1175                     uint32_t, (_eqp)->eq_u32[0]);                       \
1176         _NOTE(CONSTANTCONDITION)                                        \
1177         } while (B_FALSE)
1178
1179 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1180         do {                                                            \
1181                 EFX_CHECK_REG((_enp), (_reg));                          \
1182                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1183                     uint32_t, (_index),                                 \
1184                     uint32_t, _reg ## _OFST,                            \
1185                     uint32_t, (_eqp)->eq_u32[1],                        \
1186                     uint32_t, (_eqp)->eq_u32[0]);                       \
1187                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1188                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1189                     (_eqp));                                            \
1190         _NOTE(CONSTANTCONDITION)                                        \
1191         } while (B_FALSE)
1192
1193 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1194         do {                                                            \
1195                 EFX_CHECK_REG((_enp), (_reg));                          \
1196                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1197                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1198                     (_eop), (_lock));                                   \
1199                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1200                     uint32_t, (_index),                                 \
1201                     uint32_t, _reg ## _OFST,                            \
1202                     uint32_t, (_eop)->eo_u32[3],                        \
1203                     uint32_t, (_eop)->eo_u32[2],                        \
1204                     uint32_t, (_eop)->eo_u32[1],                        \
1205                     uint32_t, (_eop)->eo_u32[0]);                       \
1206         _NOTE(CONSTANTCONDITION)                                        \
1207         } while (B_FALSE)
1208
1209 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1210         do {                                                            \
1211                 EFX_CHECK_REG((_enp), (_reg));                          \
1212                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1213                     uint32_t, (_index),                                 \
1214                     uint32_t, _reg ## _OFST,                            \
1215                     uint32_t, (_eop)->eo_u32[3],                        \
1216                     uint32_t, (_eop)->eo_u32[2],                        \
1217                     uint32_t, (_eop)->eo_u32[1],                        \
1218                     uint32_t, (_eop)->eo_u32[0]);                       \
1219                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1220                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1221                     (_eop), (_lock));                                   \
1222         _NOTE(CONSTANTCONDITION)                                        \
1223         } while (B_FALSE)
1224
1225 /*
1226  * Accessors for memory BAR function control window registers.
1227  *
1228  * The function control window is located at an offset which can be
1229  * non-zero in case of Riverhead.
1230  */
1231
1232 #if EFSYS_OPT_RIVERHEAD
1233
1234 #define EFX_BAR_FCW_READD(_enp, _reg, _edp)                             \
1235         do {                                                            \
1236                 EFX_CHECK_REG((_enp), (_reg));                          \
1237                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST +        \
1238                     (_enp)->en_arch.ef10.ena_fcw_base,                  \
1239                     (_edp), B_FALSE);                                   \
1240                 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg,    \
1241                     uint32_t, _reg ## _OFST,                            \
1242                     uint32_t, (_edp)->ed_u32[0]);                       \
1243         _NOTE(CONSTANTCONDITION)                                        \
1244         } while (B_FALSE)
1245
1246 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp)                            \
1247         do {                                                            \
1248                 EFX_CHECK_REG((_enp), (_reg));                          \
1249                 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg,   \
1250                     uint32_t, _reg ## _OFST,                            \
1251                     uint32_t, (_edp)->ed_u32[0]);                       \
1252                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST +       \
1253                     (_enp)->en_arch.ef10.ena_fcw_base,                  \
1254                     (_edp), B_FALSE);                                   \
1255         _NOTE(CONSTANTCONDITION)                                        \
1256         } while (B_FALSE)
1257
1258 #endif  /* EFSYS_OPT_RIVERHEAD */
1259
1260 /*
1261  * Accessors for memory BAR per-VI registers.
1262  *
1263  * The VI window size is 8KB for Medford and all earlier controllers.
1264  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1265  */
1266
1267 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1268         do {                                                            \
1269                 EFX_CHECK_REG((_enp), (_reg));                          \
1270                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1271                     ((_reg ## _OFST) +                                  \
1272                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1273                     (_edp), (_lock));                                   \
1274                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1275                     uint32_t, (_index),                                 \
1276                     uint32_t, _reg ## _OFST,                            \
1277                     uint32_t, (_edp)->ed_u32[0]);                       \
1278         _NOTE(CONSTANTCONDITION)                                        \
1279         } while (B_FALSE)
1280
1281 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1282         do {                                                            \
1283                 EFX_CHECK_REG((_enp), (_reg));                          \
1284                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1285                     uint32_t, (_index),                                 \
1286                     uint32_t, _reg ## _OFST,                            \
1287                     uint32_t, (_edp)->ed_u32[0]);                       \
1288                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1289                     ((_reg ## _OFST) +                                  \
1290                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1291                     (_edp), (_lock));                                   \
1292         _NOTE(CONSTANTCONDITION)                                        \
1293         } while (B_FALSE)
1294
1295 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1296         do {                                                            \
1297                 EFX_CHECK_REG((_enp), (_reg));                          \
1298                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1299                     uint32_t, (_index),                                 \
1300                     uint32_t, _reg ## _OFST,                            \
1301                     uint32_t, (_edp)->ed_u32[0]);                       \
1302                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1303                     ((_reg ## _OFST) +                                  \
1304                     (2 * sizeof (efx_dword_t)) +                        \
1305                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1306                     (_edp), (_lock));                                   \
1307         _NOTE(CONSTANTCONDITION)                                        \
1308         } while (B_FALSE)
1309
1310 /*
1311  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1312  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1313  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1314  * the need for locking in the host, and are the only ones known to be safe to
1315  * use 128-bites write with.
1316  */
1317 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1318         do {                                                            \
1319                 EFX_CHECK_REG((_enp), (_reg));                          \
1320                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1321                     const char *, #_reg,                                \
1322                     uint32_t, (_index),                                 \
1323                     uint32_t, _reg ## _OFST,                            \
1324                     uint32_t, (_eop)->eo_u32[3],                        \
1325                     uint32_t, (_eop)->eo_u32[2],                        \
1326                     uint32_t, (_eop)->eo_u32[1],                        \
1327                     uint32_t, (_eop)->eo_u32[0]);                       \
1328                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1329                     (_reg ## _OFST +                                    \
1330                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1331                     (_eop));                                            \
1332         _NOTE(CONSTANTCONDITION)                                        \
1333         } while (B_FALSE)
1334
1335 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size,      \
1336                                       _wptr, _owptr)                    \
1337         do {                                                            \
1338                 unsigned int _new = (_wptr);                            \
1339                 unsigned int _old = (_owptr);                           \
1340                                                                         \
1341                 if ((_new) >= (_old))                                   \
1342                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1343                             (_old) * (_desc_size),                      \
1344                             ((_new) - (_old)) * (_desc_size));          \
1345                 else                                                    \
1346                         /*                                              \
1347                          * It is cheaper to sync entire map than sync   \
1348                          * two parts especially when offset/size are    \
1349                          * ignored and entire map is synced in any case.\
1350                          */                                             \
1351                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1352                             0,                                          \
1353                             (_entries) * (_desc_size));                 \
1354         _NOTE(CONSTANTCONDITION)                                        \
1355         } while (B_FALSE)
1356
1357 LIBEFX_INTERNAL
1358 extern  __checkReturn   efx_rc_t
1359 efx_mac_select(
1360         __in            efx_nic_t *enp);
1361
1362 LIBEFX_INTERNAL
1363 extern  void
1364 efx_mac_multicast_hash_compute(
1365         __in_ecount(6*count)            uint8_t const *addrs,
1366         __in                            int count,
1367         __out                           efx_oword_t *hash_low,
1368         __out                           efx_oword_t *hash_high);
1369
1370 LIBEFX_INTERNAL
1371 extern  __checkReturn   efx_rc_t
1372 efx_phy_probe(
1373         __in            efx_nic_t *enp);
1374
1375 LIBEFX_INTERNAL
1376 extern                  void
1377 efx_phy_unprobe(
1378         __in            efx_nic_t *enp);
1379
1380 #if EFSYS_OPT_VPD
1381
1382 /* VPD utility functions */
1383
1384 LIBEFX_INTERNAL
1385 extern  __checkReturn           efx_rc_t
1386 efx_vpd_hunk_length(
1387         __in_bcount(size)       caddr_t data,
1388         __in                    size_t size,
1389         __out                   size_t *lengthp);
1390
1391 LIBEFX_INTERNAL
1392 extern  __checkReturn           efx_rc_t
1393 efx_vpd_hunk_verify(
1394         __in_bcount(size)       caddr_t data,
1395         __in                    size_t size,
1396         __out_opt               boolean_t *cksummedp);
1397
1398 LIBEFX_INTERNAL
1399 extern  __checkReturn           efx_rc_t
1400 efx_vpd_hunk_reinit(
1401         __in_bcount(size)       caddr_t data,
1402         __in                    size_t size,
1403         __in                    boolean_t wantpid);
1404
1405 LIBEFX_INTERNAL
1406 extern  __checkReturn           efx_rc_t
1407 efx_vpd_hunk_get(
1408         __in_bcount(size)       caddr_t data,
1409         __in                    size_t size,
1410         __in                    efx_vpd_tag_t tag,
1411         __in                    efx_vpd_keyword_t keyword,
1412         __out                   unsigned int *payloadp,
1413         __out                   uint8_t *paylenp);
1414
1415 LIBEFX_INTERNAL
1416 extern  __checkReturn                   efx_rc_t
1417 efx_vpd_hunk_next(
1418         __in_bcount(size)               caddr_t data,
1419         __in                            size_t size,
1420         __out                           efx_vpd_tag_t *tagp,
1421         __out                           efx_vpd_keyword_t *keyword,
1422         __out_opt                       unsigned int *payloadp,
1423         __out_opt                       uint8_t *paylenp,
1424         __inout                         unsigned int *contp);
1425
1426 LIBEFX_INTERNAL
1427 extern  __checkReturn           efx_rc_t
1428 efx_vpd_hunk_set(
1429         __in_bcount(size)       caddr_t data,
1430         __in                    size_t size,
1431         __in                    efx_vpd_value_t *evvp);
1432
1433 #endif  /* EFSYS_OPT_VPD */
1434
1435 #if EFSYS_OPT_MCDI
1436
1437 LIBEFX_INTERNAL
1438 extern  __checkReturn           efx_rc_t
1439 efx_mcdi_set_workaround(
1440         __in                    efx_nic_t *enp,
1441         __in                    uint32_t type,
1442         __in                    boolean_t enabled,
1443         __out_opt               uint32_t *flagsp);
1444
1445 LIBEFX_INTERNAL
1446 extern  __checkReturn           efx_rc_t
1447 efx_mcdi_get_workarounds(
1448         __in                    efx_nic_t *enp,
1449         __out_opt               uint32_t *implementedp,
1450         __out_opt               uint32_t *enabledp);
1451
1452 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1453
1454 LIBEFX_INTERNAL
1455 extern  __checkReturn   efx_rc_t
1456 efx_mcdi_init_evq(
1457         __in            efx_nic_t *enp,
1458         __in            unsigned int instance,
1459         __in            efsys_mem_t *esmp,
1460         __in            size_t nevs,
1461         __in            uint32_t irq,
1462         __in            uint32_t us,
1463         __in            uint32_t flags,
1464         __in            boolean_t low_latency);
1465
1466 LIBEFX_INTERNAL
1467 extern  __checkReturn   efx_rc_t
1468 efx_mcdi_fini_evq(
1469         __in            efx_nic_t *enp,
1470         __in            uint32_t instance);
1471
1472 typedef struct efx_mcdi_init_rxq_params_s {
1473         boolean_t       disable_scatter;
1474         boolean_t       want_inner_classes;
1475         uint32_t        buf_size;
1476         uint32_t        ps_buf_size;
1477         uint32_t        es_bufs_per_desc;
1478         uint32_t        es_max_dma_len;
1479         uint32_t        es_buf_stride;
1480         uint32_t        hol_block_timeout;
1481         uint32_t        prefix_id;
1482 } efx_mcdi_init_rxq_params_t;
1483
1484 LIBEFX_INTERNAL
1485 extern  __checkReturn   efx_rc_t
1486 efx_mcdi_init_rxq(
1487         __in            efx_nic_t *enp,
1488         __in            uint32_t ndescs,
1489         __in            efx_evq_t *eep,
1490         __in            uint32_t label,
1491         __in            uint32_t instance,
1492         __in            efsys_mem_t *esmp,
1493         __in            const efx_mcdi_init_rxq_params_t *params);
1494
1495 LIBEFX_INTERNAL
1496 extern  __checkReturn   efx_rc_t
1497 efx_mcdi_fini_rxq(
1498         __in            efx_nic_t *enp,
1499         __in            uint32_t instance);
1500
1501 LIBEFX_INTERNAL
1502 extern  __checkReturn   efx_rc_t
1503 efx_mcdi_init_txq(
1504         __in            efx_nic_t *enp,
1505         __in            uint32_t ndescs,
1506         __in            uint32_t target_evq,
1507         __in            uint32_t label,
1508         __in            uint32_t instance,
1509         __in            uint16_t flags,
1510         __in            efsys_mem_t *esmp);
1511
1512 LIBEFX_INTERNAL
1513 extern  __checkReturn   efx_rc_t
1514 efx_mcdi_fini_txq(
1515         __in            efx_nic_t *enp,
1516         __in            uint32_t instance);
1517
1518 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1519
1520 #endif /* EFSYS_OPT_MCDI */
1521
1522 #if EFSYS_OPT_MAC_STATS
1523
1524 /*
1525  * Closed range of stats (i.e. the first and the last are included).
1526  * The last must be greater or equal (if the range is one item only) to
1527  * the first.
1528  */
1529 struct efx_mac_stats_range {
1530         efx_mac_stat_t          first;
1531         efx_mac_stat_t          last;
1532 };
1533
1534 typedef enum efx_stats_action_e {
1535         EFX_STATS_CLEAR,
1536         EFX_STATS_UPLOAD,
1537         EFX_STATS_ENABLE_NOEVENTS,
1538         EFX_STATS_ENABLE_EVENTS,
1539         EFX_STATS_DISABLE,
1540 } efx_stats_action_t;
1541
1542 LIBEFX_INTERNAL
1543 extern                                  efx_rc_t
1544 efx_mac_stats_mask_add_ranges(
1545         __inout_bcount(mask_size)       uint32_t *maskp,
1546         __in                            size_t mask_size,
1547         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1548         __in                            unsigned int rng_count);
1549
1550 LIBEFX_INTERNAL
1551 extern  __checkReturn   efx_rc_t
1552 efx_mcdi_mac_stats(
1553         __in            efx_nic_t *enp,
1554         __in            uint32_t vport_id,
1555         __in_opt        efsys_mem_t *esmp,
1556         __in            efx_stats_action_t action,
1557         __in            uint16_t period_ms);
1558
1559 #endif  /* EFSYS_OPT_MAC_STATS */
1560
1561 #ifdef  __cplusplus
1562 }
1563 #endif
1564
1565 #endif  /* _SYS_EFX_IMPL_H */