1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
13 static __checkReturn efx_rc_t
14 efx_mae_get_capabilities(
18 EFX_MCDI_DECLARE_BUF(payload,
19 MC_CMD_MAE_GET_CAPS_IN_LEN,
20 MC_CMD_MAE_GET_CAPS_OUT_LEN);
21 struct efx_mae_s *maep = enp->en_maep;
24 req.emr_cmd = MC_CMD_MAE_GET_CAPS;
25 req.emr_in_buf = payload;
26 req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
27 req.emr_out_buf = payload;
28 req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
30 efx_mcdi_execute(enp, &req);
32 if (req.emr_rc != 0) {
37 if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
42 maep->em_max_n_outer_prios =
43 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
45 maep->em_max_n_action_prios =
46 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
48 maep->em_encap_types_supported = 0;
50 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
51 maep->em_encap_types_supported |=
52 (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
55 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
56 maep->em_encap_types_supported |=
57 (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
60 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
61 maep->em_encap_types_supported |=
62 (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
65 maep->em_max_nfields =
66 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
73 EFSYS_PROBE1(fail1, efx_rc_t, rc);
77 static __checkReturn efx_rc_t
78 efx_mae_get_outer_rule_caps(
80 __in unsigned int field_ncaps,
81 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
84 EFX_MCDI_DECLARE_BUF(payload,
85 MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
86 MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
87 unsigned int mcdi_field_ncaps;
91 if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
92 MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
97 req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
98 req.emr_in_buf = payload;
99 req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
100 req.emr_out_buf = payload;
101 req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
103 efx_mcdi_execute(enp, &req);
105 if (req.emr_rc != 0) {
110 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
112 if (req.emr_out_length_used <
113 MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
118 if (mcdi_field_ncaps > field_ncaps) {
123 for (i = 0; i < mcdi_field_ncaps; ++i) {
127 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
128 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
129 MAE_FIELD_FLAGS_SUPPORT_STATUS);
131 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
132 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
133 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
135 field_caps[i].emfc_match_affects_class =
136 (match_flag != 0) ? B_TRUE : B_FALSE;
138 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
139 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
140 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
142 field_caps[i].emfc_mask_affects_class =
143 (mask_flag != 0) ? B_TRUE : B_FALSE;
155 EFSYS_PROBE1(fail1, efx_rc_t, rc);
159 static __checkReturn efx_rc_t
160 efx_mae_get_action_rule_caps(
162 __in unsigned int field_ncaps,
163 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
166 EFX_MCDI_DECLARE_BUF(payload,
167 MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
168 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
169 unsigned int mcdi_field_ncaps;
173 if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
174 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
179 req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
180 req.emr_in_buf = payload;
181 req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
182 req.emr_out_buf = payload;
183 req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
185 efx_mcdi_execute(enp, &req);
187 if (req.emr_rc != 0) {
192 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
194 if (req.emr_out_length_used <
195 MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
200 if (mcdi_field_ncaps > field_ncaps) {
205 for (i = 0; i < mcdi_field_ncaps; ++i) {
209 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
210 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
211 MAE_FIELD_FLAGS_SUPPORT_STATUS);
213 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
214 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
215 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
217 field_caps[i].emfc_match_affects_class =
218 (match_flag != 0) ? B_TRUE : B_FALSE;
220 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
221 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
222 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
224 field_caps[i].emfc_mask_affects_class =
225 (mask_flag != 0) ? B_TRUE : B_FALSE;
237 EFSYS_PROBE1(fail1, efx_rc_t, rc);
241 __checkReturn efx_rc_t
245 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
246 efx_mae_field_cap_t *or_fcaps;
247 size_t or_fcaps_size;
248 efx_mae_field_cap_t *ar_fcaps;
249 size_t ar_fcaps_size;
253 if (encp->enc_mae_supported == B_FALSE) {
258 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
266 rc = efx_mae_get_capabilities(enp);
270 or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
271 EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
272 if (or_fcaps == NULL) {
277 maep->em_outer_rule_field_caps_size = or_fcaps_size;
278 maep->em_outer_rule_field_caps = or_fcaps;
280 rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
284 ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
285 EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
286 if (ar_fcaps == NULL) {
291 maep->em_action_rule_field_caps_size = ar_fcaps_size;
292 maep->em_action_rule_field_caps = ar_fcaps;
294 rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
302 EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
307 EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
312 EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
317 EFSYS_PROBE1(fail1, efx_rc_t, rc);
325 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
326 efx_mae_t *maep = enp->en_maep;
328 if (encp->enc_mae_supported == B_FALSE)
331 EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
332 maep->em_action_rule_field_caps);
333 EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
334 maep->em_outer_rule_field_caps);
335 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
339 __checkReturn efx_rc_t
342 __out efx_mae_limits_t *emlp)
344 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
345 struct efx_mae_s *maep = enp->en_maep;
348 if (encp->enc_mae_supported == B_FALSE) {
353 emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
354 emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
355 emlp->eml_encap_types_supported = maep->em_encap_types_supported;
360 EFSYS_PROBE1(fail1, efx_rc_t, rc);
364 __checkReturn efx_rc_t
365 efx_mae_match_spec_init(
367 __in efx_mae_rule_type_t type,
369 __out efx_mae_match_spec_t **specp)
371 efx_mae_match_spec_t *spec;
375 case EFX_MAE_RULE_OUTER:
377 case EFX_MAE_RULE_ACTION:
384 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
390 spec->emms_type = type;
391 spec->emms_prio = prio;
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
405 efx_mae_match_spec_fini(
407 __in efx_mae_match_spec_t *spec)
409 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
412 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
413 typedef enum efx_mae_field_cap_id_e {
414 EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
415 EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
416 EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
417 EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
418 EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
419 EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
420 EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
421 EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
422 EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
423 EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
424 EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
425 EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
426 EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
427 EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
428 EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
429 EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
430 EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
431 EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
432 EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
433 EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
434 EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
435 EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
436 EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
437 EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
438 EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
439 EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
440 EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
441 EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
442 EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
443 EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
444 EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
445 EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
446 EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
447 EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
448 EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
449 EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
451 EFX_MAE_FIELD_CAP_NIDS
452 } efx_mae_field_cap_id_t;
454 typedef enum efx_mae_field_endianness_e {
455 EFX_MAE_FIELD_LE = 0,
458 EFX_MAE_FIELD_ENDIANNESS_NTYPES
459 } efx_mae_field_endianness_t;
462 * The following structure is a means to describe an MAE field.
463 * The information in it is meant to be used internally by
464 * APIs for addressing a given field in a mask-value pairs
465 * structure and for validation purposes.
467 typedef struct efx_mae_mv_desc_s {
468 efx_mae_field_cap_id_t emmd_field_cap_id;
470 size_t emmd_value_size;
471 size_t emmd_value_offset;
472 size_t emmd_mask_size;
473 size_t emmd_mask_offset;
475 efx_mae_field_endianness_t emmd_endianness;
478 /* Indices to this array are provided by efx_mae_field_id_t */
479 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
480 #define EFX_MAE_MV_DESC(_name, _endianness) \
481 [EFX_MAE_FIELD_##_name] = \
483 EFX_MAE_FIELD_ID_##_name, \
484 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN, \
485 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST, \
486 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN, \
487 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST, \
491 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
492 EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
493 EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
494 EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
495 EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
496 EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
497 EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
498 EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
499 EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
500 EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
501 EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
502 EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
503 EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
504 EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
505 EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
506 EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
507 EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
508 EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
509 EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
510 EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
512 #undef EFX_MAE_MV_DESC
515 /* Indices to this array are provided by efx_mae_field_id_t */
516 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
517 #define EFX_MAE_MV_DESC(_name, _endianness) \
518 [EFX_MAE_FIELD_##_name] = \
520 EFX_MAE_FIELD_ID_##_name, \
521 MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
522 MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
523 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
524 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
528 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
529 EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
530 EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
531 EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
532 EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
533 EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
534 EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
535 EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
536 EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
537 EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
538 EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
539 EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
540 EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
541 EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
542 EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
543 EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
544 EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
546 #undef EFX_MAE_MV_DESC
549 __checkReturn efx_rc_t
550 efx_mae_mport_by_phy_port(
551 __in uint32_t phy_port,
552 __out efx_mport_sel_t *mportp)
557 if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
562 EFX_POPULATE_DWORD_2(dword,
563 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
564 MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
566 memset(mportp, 0, sizeof (*mportp));
567 mportp->sel = dword.ed_u32[0];
572 EFSYS_PROBE1(fail1, efx_rc_t, rc);
576 __checkReturn efx_rc_t
577 efx_mae_mport_by_pcie_function(
580 __out efx_mport_sel_t *mportp)
585 EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
586 MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
588 if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
593 if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
598 EFX_POPULATE_DWORD_3(dword,
599 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
600 MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
601 MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
603 memset(mportp, 0, sizeof (*mportp));
604 mportp->sel = dword.ed_u32[0];
611 EFSYS_PROBE1(fail1, efx_rc_t, rc);
615 __checkReturn efx_rc_t
616 efx_mae_match_spec_field_set(
617 __in efx_mae_match_spec_t *spec,
618 __in efx_mae_field_id_t field_id,
619 __in size_t value_size,
620 __in_bcount(value_size) const uint8_t *value,
621 __in size_t mask_size,
622 __in_bcount(mask_size) const uint8_t *mask)
624 const efx_mae_mv_desc_t *descp;
625 unsigned int desc_set_nentries;
629 switch (spec->emms_type) {
630 case EFX_MAE_RULE_OUTER:
632 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
633 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
634 mvp = spec->emms_mask_value_pairs.outer;
636 case EFX_MAE_RULE_ACTION:
638 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
639 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
640 mvp = spec->emms_mask_value_pairs.action;
647 if ((unsigned int)field_id >= desc_set_nentries) {
652 if (value_size != descp->emmd_value_size) {
657 if (mask_size != descp->emmd_mask_size) {
662 if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
664 * The mask/value are in network (big endian) order.
665 * The MCDI request field is also big endian.
667 memcpy(mvp + descp->emmd_value_offset, value, value_size);
668 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
673 * The mask/value are in host byte order.
674 * The MCDI request field is little endian.
676 switch (value_size) {
678 EFX_POPULATE_DWORD_1(dword,
679 EFX_DWORD_0, *(const uint32_t *)value);
681 memcpy(mvp + descp->emmd_value_offset,
682 &dword, sizeof (dword));
685 EFSYS_ASSERT(B_FALSE);
690 EFX_POPULATE_DWORD_1(dword,
691 EFX_DWORD_0, *(const uint32_t *)mask);
693 memcpy(mvp + descp->emmd_mask_offset,
694 &dword, sizeof (dword));
697 EFSYS_ASSERT(B_FALSE);
710 EFSYS_PROBE1(fail1, efx_rc_t, rc);
714 __checkReturn efx_rc_t
715 efx_mae_match_spec_mport_set(
716 __in efx_mae_match_spec_t *spec,
717 __in const efx_mport_sel_t *valuep,
718 __in_opt const efx_mport_sel_t *maskp)
720 uint32_t full_mask = UINT32_MAX;
725 if (valuep == NULL) {
730 vp = (const uint8_t *)&valuep->sel;
732 mp = (const uint8_t *)&maskp->sel;
734 mp = (const uint8_t *)&full_mask;
736 rc = efx_mae_match_spec_field_set(spec,
737 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
738 sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
747 EFSYS_PROBE1(fail1, efx_rc_t, rc);
751 __checkReturn boolean_t
752 efx_mae_match_specs_equal(
753 __in const efx_mae_match_spec_t *left,
754 __in const efx_mae_match_spec_t *right)
756 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
759 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit) \
760 ((_mask)[(_bit) / (_mask_page_nbits)] & \
761 (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
765 __in size_t mask_nbytes,
766 __in_bcount(mask_nbytes) const uint8_t *maskp)
768 boolean_t prev_bit_is_set = B_TRUE;
771 for (i = 0; i < 8 * mask_nbytes; ++i) {
772 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
774 if (!prev_bit_is_set && bit_is_set)
777 prev_bit_is_set = bit_is_set;
784 efx_mask_is_all_ones(
785 __in size_t mask_nbytes,
786 __in_bcount(mask_nbytes) const uint8_t *maskp)
791 for (i = 0; i < mask_nbytes; ++i)
794 return (t == (uint8_t)(~0));
798 efx_mask_is_all_zeros(
799 __in size_t mask_nbytes,
800 __in_bcount(mask_nbytes) const uint8_t *maskp)
805 for (i = 0; i < mask_nbytes; ++i)
811 __checkReturn boolean_t
812 efx_mae_match_spec_is_valid(
814 __in const efx_mae_match_spec_t *spec)
816 efx_mae_t *maep = enp->en_maep;
817 unsigned int field_ncaps = maep->em_max_nfields;
818 const efx_mae_field_cap_t *field_caps;
819 const efx_mae_mv_desc_t *desc_setp;
820 unsigned int desc_set_nentries;
821 boolean_t is_valid = B_TRUE;
822 efx_mae_field_id_t field_id;
825 switch (spec->emms_type) {
826 case EFX_MAE_RULE_OUTER:
827 field_caps = maep->em_outer_rule_field_caps;
828 desc_setp = __efx_mae_outer_rule_mv_desc_set;
830 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
831 mvp = spec->emms_mask_value_pairs.outer;
833 case EFX_MAE_RULE_ACTION:
834 field_caps = maep->em_action_rule_field_caps;
835 desc_setp = __efx_mae_action_rule_mv_desc_set;
837 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
838 mvp = spec->emms_mask_value_pairs.action;
844 if (field_caps == NULL)
847 for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
849 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
850 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
851 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
852 size_t m_size = descp->emmd_mask_size;
855 continue; /* Skip array gap */
857 if ((unsigned int)field_cap_id >= field_ncaps)
860 switch (field_caps[field_cap_id].emfc_support) {
861 case MAE_FIELD_SUPPORTED_MATCH_MASK:
864 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
865 is_valid = efx_mask_is_prefix(m_size, m_buf);
867 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
868 is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
869 efx_mask_is_all_zeros(m_size, m_buf));
871 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
872 is_valid = efx_mask_is_all_ones(m_size, m_buf);
874 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
875 case MAE_FIELD_UNSUPPORTED:
877 is_valid = efx_mask_is_all_zeros(m_size, m_buf);
881 if (is_valid == B_FALSE)
888 __checkReturn efx_rc_t
889 efx_mae_action_set_spec_init(
891 __out efx_mae_actions_t **specp)
893 efx_mae_actions_t *spec;
896 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
907 EFSYS_PROBE1(fail1, efx_rc_t, rc);
912 efx_mae_action_set_spec_fini(
914 __in efx_mae_actions_t *spec)
916 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
919 static __checkReturn efx_rc_t
920 efx_mae_action_set_add_vlan_pop(
921 __in efx_mae_actions_t *spec,
922 __in size_t arg_size,
923 __in_bcount(arg_size) const uint8_t *arg)
937 if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
942 ++spec->ema_n_vlan_tags_to_pop;
951 EFSYS_PROBE1(fail1, efx_rc_t, rc);
955 static __checkReturn efx_rc_t
956 efx_mae_action_set_add_vlan_push(
957 __in efx_mae_actions_t *spec,
958 __in size_t arg_size,
959 __in_bcount(arg_size) const uint8_t *arg)
961 unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
964 if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
974 if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
979 memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
980 ++(spec->ema_n_vlan_tags_to_push);
989 EFSYS_PROBE1(fail1, efx_rc_t, rc);
993 static __checkReturn efx_rc_t
994 efx_mae_action_set_add_flag(
995 __in efx_mae_actions_t *spec,
996 __in size_t arg_size,
997 __in_bcount(arg_size) const uint8_t *arg)
1001 _NOTE(ARGUNUSED(spec))
1003 if (arg_size != 0) {
1013 /* This action does not have any arguments, so do nothing here. */
1020 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1024 static __checkReturn efx_rc_t
1025 efx_mae_action_set_add_mark(
1026 __in efx_mae_actions_t *spec,
1027 __in size_t arg_size,
1028 __in_bcount(arg_size) const uint8_t *arg)
1032 if (arg_size != sizeof (spec->ema_mark_value)) {
1042 memcpy(&spec->ema_mark_value, arg, arg_size);
1049 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1053 static __checkReturn efx_rc_t
1054 efx_mae_action_set_add_deliver(
1055 __in efx_mae_actions_t *spec,
1056 __in size_t arg_size,
1057 __in_bcount(arg_size) const uint8_t *arg)
1061 if (arg_size != sizeof (spec->ema_deliver_mport)) {
1071 memcpy(&spec->ema_deliver_mport, arg, arg_size);
1078 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1082 typedef struct efx_mae_action_desc_s {
1083 /* Action specific handler */
1084 efx_rc_t (*emad_add)(efx_mae_actions_t *,
1085 size_t, const uint8_t *);
1086 } efx_mae_action_desc_t;
1088 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
1089 [EFX_MAE_ACTION_VLAN_POP] = {
1090 .emad_add = efx_mae_action_set_add_vlan_pop
1092 [EFX_MAE_ACTION_VLAN_PUSH] = {
1093 .emad_add = efx_mae_action_set_add_vlan_push
1095 [EFX_MAE_ACTION_FLAG] = {
1096 .emad_add = efx_mae_action_set_add_flag
1098 [EFX_MAE_ACTION_MARK] = {
1099 .emad_add = efx_mae_action_set_add_mark
1101 [EFX_MAE_ACTION_DELIVER] = {
1102 .emad_add = efx_mae_action_set_add_deliver
1106 static const uint32_t efx_mae_action_ordered_map =
1107 (1U << EFX_MAE_ACTION_VLAN_POP) |
1108 (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1109 (1U << EFX_MAE_ACTION_FLAG) |
1110 (1U << EFX_MAE_ACTION_MARK) |
1111 (1U << EFX_MAE_ACTION_DELIVER);
1114 * These actions must not be added after DELIVER, but
1115 * they can have any place among the rest of
1116 * strictly ordered actions.
1118 static const uint32_t efx_mae_action_nonstrict_map =
1119 (1U << EFX_MAE_ACTION_FLAG) |
1120 (1U << EFX_MAE_ACTION_MARK);
1122 static const uint32_t efx_mae_action_repeat_map =
1123 (1U << EFX_MAE_ACTION_VLAN_POP) |
1124 (1U << EFX_MAE_ACTION_VLAN_PUSH);
1127 * Add an action to an action set.
1129 * This has to be invoked in the desired action order.
1130 * An out-of-order action request will be turned down.
1132 static __checkReturn efx_rc_t
1133 efx_mae_action_set_spec_populate(
1134 __in efx_mae_actions_t *spec,
1135 __in efx_mae_action_t type,
1136 __in size_t arg_size,
1137 __in_bcount(arg_size) const uint8_t *arg)
1139 uint32_t action_mask;
1142 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1143 (sizeof (efx_mae_action_ordered_map) * 8));
1144 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1145 (sizeof (efx_mae_action_repeat_map) * 8));
1147 EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1148 EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1149 EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1151 if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1156 action_mask = (1U << type);
1158 if ((spec->ema_actions & action_mask) != 0) {
1159 /* The action set already contains this action. */
1160 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1161 /* Cannot add another non-repeatable action. */
1167 if ((efx_mae_action_ordered_map & action_mask) != 0) {
1168 uint32_t strict_ordered_map =
1169 efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1170 uint32_t later_actions_mask =
1171 strict_ordered_map & ~(action_mask | (action_mask - 1));
1173 if ((spec->ema_actions & later_actions_mask) != 0) {
1174 /* Cannot add an action after later ordered actions. */
1180 if (efx_mae_actions[type].emad_add != NULL) {
1181 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1186 spec->ema_actions |= action_mask;
1197 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1201 __checkReturn efx_rc_t
1202 efx_mae_action_set_populate_vlan_pop(
1203 __in efx_mae_actions_t *spec)
1205 return (efx_mae_action_set_spec_populate(spec,
1206 EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1209 __checkReturn efx_rc_t
1210 efx_mae_action_set_populate_vlan_push(
1211 __in efx_mae_actions_t *spec,
1212 __in uint16_t tpid_be,
1213 __in uint16_t tci_be)
1215 efx_mae_action_vlan_push_t action;
1216 const uint8_t *arg = (const uint8_t *)&action;
1218 action.emavp_tpid_be = tpid_be;
1219 action.emavp_tci_be = tci_be;
1221 return (efx_mae_action_set_spec_populate(spec,
1222 EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1225 __checkReturn efx_rc_t
1226 efx_mae_action_set_populate_flag(
1227 __in efx_mae_actions_t *spec)
1229 return (efx_mae_action_set_spec_populate(spec,
1230 EFX_MAE_ACTION_FLAG, 0, NULL));
1233 __checkReturn efx_rc_t
1234 efx_mae_action_set_populate_mark(
1235 __in efx_mae_actions_t *spec,
1236 __in uint32_t mark_value)
1238 const uint8_t *arg = (const uint8_t *)&mark_value;
1240 return (efx_mae_action_set_spec_populate(spec,
1241 EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1244 __checkReturn efx_rc_t
1245 efx_mae_action_set_populate_deliver(
1246 __in efx_mae_actions_t *spec,
1247 __in const efx_mport_sel_t *mportp)
1252 if (mportp == NULL) {
1257 arg = (const uint8_t *)&mportp->sel;
1259 return (efx_mae_action_set_spec_populate(spec,
1260 EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1267 __checkReturn efx_rc_t
1268 efx_mae_action_set_populate_drop(
1269 __in efx_mae_actions_t *spec)
1271 efx_mport_sel_t mport;
1275 EFX_POPULATE_DWORD_1(dword,
1276 MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1278 mport.sel = dword.ed_u32[0];
1280 arg = (const uint8_t *)&mport.sel;
1282 return (efx_mae_action_set_spec_populate(spec,
1283 EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1286 __checkReturn boolean_t
1287 efx_mae_action_set_specs_equal(
1288 __in const efx_mae_actions_t *left,
1289 __in const efx_mae_actions_t *right)
1291 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1294 __checkReturn efx_rc_t
1295 efx_mae_match_specs_class_cmp(
1296 __in efx_nic_t *enp,
1297 __in const efx_mae_match_spec_t *left,
1298 __in const efx_mae_match_spec_t *right,
1299 __out boolean_t *have_same_classp)
1301 efx_mae_t *maep = enp->en_maep;
1302 unsigned int field_ncaps = maep->em_max_nfields;
1303 const efx_mae_field_cap_t *field_caps;
1304 const efx_mae_mv_desc_t *desc_setp;
1305 unsigned int desc_set_nentries;
1306 boolean_t have_same_class = B_TRUE;
1307 efx_mae_field_id_t field_id;
1308 const uint8_t *mvpl;
1309 const uint8_t *mvpr;
1312 switch (left->emms_type) {
1313 case EFX_MAE_RULE_OUTER:
1314 field_caps = maep->em_outer_rule_field_caps;
1315 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1317 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1318 mvpl = left->emms_mask_value_pairs.outer;
1319 mvpr = right->emms_mask_value_pairs.outer;
1321 case EFX_MAE_RULE_ACTION:
1322 field_caps = maep->em_action_rule_field_caps;
1323 desc_setp = __efx_mae_action_rule_mv_desc_set;
1325 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1326 mvpl = left->emms_mask_value_pairs.action;
1327 mvpr = right->emms_mask_value_pairs.action;
1334 if (field_caps == NULL) {
1339 if (left->emms_type != right->emms_type ||
1340 left->emms_prio != right->emms_prio) {
1342 * Rules of different types can never map to the same class.
1344 * The FW can support some set of match criteria for one
1345 * priority and not support the very same set for
1346 * another priority. Thus, two rules which have
1347 * different priorities can never map to
1350 *have_same_classp = B_FALSE;
1354 for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
1356 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1357 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1359 if (descp->emmd_mask_size == 0)
1360 continue; /* Skip array gap */
1362 if ((unsigned int)field_cap_id >= field_ncaps)
1365 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1366 const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1367 const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1368 size_t mask_size = descp->emmd_mask_size;
1370 if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1371 have_same_class = B_FALSE;
1376 if (field_caps[field_cap_id].emfc_match_affects_class) {
1377 const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1378 const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1379 size_t value_size = descp->emmd_value_size;
1381 if (memcmp(lvalp, rvalp, value_size) != 0) {
1382 have_same_class = B_FALSE;
1388 *have_same_classp = have_same_class;
1395 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1399 __checkReturn efx_rc_t
1400 efx_mae_outer_rule_insert(
1401 __in efx_nic_t *enp,
1402 __in const efx_mae_match_spec_t *spec,
1403 __in efx_tunnel_protocol_t encap_type,
1404 __out efx_mae_rule_id_t *or_idp)
1406 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1408 EFX_MCDI_DECLARE_BUF(payload,
1409 MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
1410 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
1411 uint32_t encap_type_mcdi;
1412 efx_mae_rule_id_t or_id;
1416 EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
1417 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
1419 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1420 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
1422 if (encp->enc_mae_supported == B_FALSE) {
1427 if (spec->emms_type != EFX_MAE_RULE_OUTER) {
1432 switch (encap_type) {
1433 case EFX_TUNNEL_PROTOCOL_NONE:
1434 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
1436 case EFX_TUNNEL_PROTOCOL_VXLAN:
1437 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
1439 case EFX_TUNNEL_PROTOCOL_GENEVE:
1440 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
1442 case EFX_TUNNEL_PROTOCOL_NVGRE:
1443 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
1450 req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
1451 req.emr_in_buf = payload;
1452 req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
1453 req.emr_out_buf = payload;
1454 req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
1456 MCDI_IN_SET_DWORD(req,
1457 MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
1459 MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
1462 * Mask-value pairs have been stored in the byte order needed for the
1463 * MCDI request and are thus safe to be copied directly to the buffer.
1464 * The library cares about byte order in efx_mae_match_spec_field_set().
1466 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
1467 MAE_ENC_FIELD_PAIRS_LEN);
1468 offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
1469 memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
1470 MAE_ENC_FIELD_PAIRS_LEN);
1472 efx_mcdi_execute(enp, &req);
1474 if (req.emr_rc != 0) {
1479 if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
1484 or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
1485 if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
1490 or_idp->id = or_id.id;
1505 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1509 __checkReturn efx_rc_t
1510 efx_mae_outer_rule_remove(
1511 __in efx_nic_t *enp,
1512 __in const efx_mae_rule_id_t *or_idp)
1514 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1516 EFX_MCDI_DECLARE_BUF(payload,
1517 MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
1518 MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
1521 if (encp->enc_mae_supported == B_FALSE) {
1526 req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
1527 req.emr_in_buf = payload;
1528 req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
1529 req.emr_out_buf = payload;
1530 req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
1532 MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
1534 efx_mcdi_execute(enp, &req);
1536 if (req.emr_rc != 0) {
1541 if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
1543 /* Firmware failed to remove the outer rule. */
1555 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1559 __checkReturn efx_rc_t
1560 efx_mae_match_spec_outer_rule_id_set(
1561 __in efx_mae_match_spec_t *spec,
1562 __in const efx_mae_rule_id_t *or_idp)
1564 uint32_t full_mask = UINT32_MAX;
1567 if (spec->emms_type != EFX_MAE_RULE_ACTION) {
1572 if (or_idp == NULL) {
1577 rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
1578 sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
1579 sizeof (full_mask), (const uint8_t *)&full_mask);
1590 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1594 __checkReturn efx_rc_t
1595 efx_mae_action_set_alloc(
1596 __in efx_nic_t *enp,
1597 __in const efx_mae_actions_t *spec,
1598 __out efx_mae_aset_id_t *aset_idp)
1600 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1602 EFX_MCDI_DECLARE_BUF(payload,
1603 MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1604 MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1605 efx_mae_aset_id_t aset_id;
1608 if (encp->enc_mae_supported == B_FALSE) {
1613 req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1614 req.emr_in_buf = payload;
1615 req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1616 req.emr_out_buf = payload;
1617 req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1620 * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1621 * corresponding resource types are supported by the implementation.
1622 * Use proper resource ID assignments instead.
1624 MCDI_IN_SET_DWORD(req,
1625 MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1626 MCDI_IN_SET_DWORD(req,
1627 MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1628 MCDI_IN_SET_DWORD(req,
1629 MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1631 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1632 MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1634 if (spec->ema_n_vlan_tags_to_push > 0) {
1635 unsigned int outer_tag_idx;
1637 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1638 MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1639 spec->ema_n_vlan_tags_to_push);
1641 if (spec->ema_n_vlan_tags_to_push ==
1642 EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1643 MCDI_IN_SET_WORD(req,
1644 MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1645 spec->ema_vlan_push_descs[0].emavp_tpid_be);
1646 MCDI_IN_SET_WORD(req,
1647 MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1648 spec->ema_vlan_push_descs[0].emavp_tci_be);
1651 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1653 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1654 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1655 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1656 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1659 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1660 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1661 MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1664 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1665 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1666 MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1668 MCDI_IN_SET_DWORD(req,
1669 MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1672 MCDI_IN_SET_DWORD(req,
1673 MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1675 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1676 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1677 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1678 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1680 efx_mcdi_execute(enp, &req);
1682 if (req.emr_rc != 0) {
1687 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1692 aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1693 if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1698 aset_idp->id = aset_id.id;
1709 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1713 __checkReturn efx_rc_t
1714 efx_mae_action_set_free(
1715 __in efx_nic_t *enp,
1716 __in const efx_mae_aset_id_t *aset_idp)
1718 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1720 EFX_MCDI_DECLARE_BUF(payload,
1721 MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1722 MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1725 if (encp->enc_mae_supported == B_FALSE) {
1730 req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1731 req.emr_in_buf = payload;
1732 req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1733 req.emr_out_buf = payload;
1734 req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1736 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1738 efx_mcdi_execute(enp, &req);
1740 if (req.emr_rc != 0) {
1745 if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1747 /* Firmware failed to free the action set. */
1759 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1763 __checkReturn efx_rc_t
1764 efx_mae_action_rule_insert(
1765 __in efx_nic_t *enp,
1766 __in const efx_mae_match_spec_t *spec,
1767 __in const efx_mae_aset_list_id_t *asl_idp,
1768 __in const efx_mae_aset_id_t *as_idp,
1769 __out efx_mae_rule_id_t *ar_idp)
1771 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1773 EFX_MCDI_DECLARE_BUF(payload,
1774 MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1775 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1776 efx_oword_t *rule_response;
1777 efx_mae_rule_id_t ar_id;
1781 EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1782 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1784 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1785 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1787 if (encp->enc_mae_supported == B_FALSE) {
1792 if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1793 (asl_idp != NULL && as_idp != NULL) ||
1794 (asl_idp == NULL && as_idp == NULL)) {
1799 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1800 req.emr_in_buf = payload;
1801 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1802 req.emr_out_buf = payload;
1803 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1805 EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1806 MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1807 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1808 rule_response = (efx_oword_t *)(payload + offset);
1809 EFX_POPULATE_OWORD_3(*rule_response,
1810 MAE_ACTION_RULE_RESPONSE_ASL_ID,
1811 (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1812 MAE_ACTION_RULE_RESPONSE_AS_ID,
1813 (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1814 MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1816 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1819 * Mask-value pairs have been stored in the byte order needed for the
1820 * MCDI request and are thus safe to be copied directly to the buffer.
1822 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1823 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1824 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1825 memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1826 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1828 efx_mcdi_execute(enp, &req);
1830 if (req.emr_rc != 0) {
1835 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1840 ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1841 if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1846 ar_idp->id = ar_id.id;
1859 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1863 __checkReturn efx_rc_t
1864 efx_mae_action_rule_remove(
1865 __in efx_nic_t *enp,
1866 __in const efx_mae_rule_id_t *ar_idp)
1868 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1870 EFX_MCDI_DECLARE_BUF(payload,
1871 MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1872 MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1875 if (encp->enc_mae_supported == B_FALSE) {
1880 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1881 req.emr_in_buf = payload;
1882 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1883 req.emr_out_buf = payload;
1884 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1886 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1888 efx_mcdi_execute(enp, &req);
1890 if (req.emr_rc != 0) {
1895 if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1897 /* Firmware failed to delete the action rule. */
1909 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1913 #endif /* EFSYS_OPT_MAE */