1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
13 static __checkReturn efx_rc_t
14 efx_mae_get_capabilities(
18 EFX_MCDI_DECLARE_BUF(payload,
19 MC_CMD_MAE_GET_CAPS_IN_LEN,
20 MC_CMD_MAE_GET_CAPS_OUT_LEN);
21 struct efx_mae_s *maep = enp->en_maep;
24 req.emr_cmd = MC_CMD_MAE_GET_CAPS;
25 req.emr_in_buf = payload;
26 req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
27 req.emr_out_buf = payload;
28 req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
30 efx_mcdi_execute(enp, &req);
32 if (req.emr_rc != 0) {
37 if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
42 maep->em_max_n_outer_prios =
43 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
45 maep->em_max_n_action_prios =
46 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
48 maep->em_encap_types_supported = 0;
50 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
51 maep->em_encap_types_supported |=
52 (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
55 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
56 maep->em_encap_types_supported |=
57 (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
60 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
61 maep->em_encap_types_supported |=
62 (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
65 maep->em_max_nfields =
66 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
73 EFSYS_PROBE1(fail1, efx_rc_t, rc);
77 static __checkReturn efx_rc_t
78 efx_mae_get_action_rule_caps(
80 __in unsigned int field_ncaps,
81 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
84 EFX_MCDI_DECLARE_BUF(payload,
85 MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
86 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
87 unsigned int mcdi_field_ncaps;
91 if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
92 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
97 req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
98 req.emr_in_buf = payload;
99 req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
100 req.emr_out_buf = payload;
101 req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
103 efx_mcdi_execute(enp, &req);
105 if (req.emr_rc != 0) {
110 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
112 if (req.emr_out_length_used <
113 MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
118 if (mcdi_field_ncaps > field_ncaps) {
123 for (i = 0; i < mcdi_field_ncaps; ++i) {
127 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
128 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
129 MAE_FIELD_FLAGS_SUPPORT_STATUS);
131 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
132 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
133 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
135 field_caps[i].emfc_match_affects_class =
136 (match_flag != 0) ? B_TRUE : B_FALSE;
138 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
139 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
140 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
142 field_caps[i].emfc_mask_affects_class =
143 (mask_flag != 0) ? B_TRUE : B_FALSE;
155 EFSYS_PROBE1(fail1, efx_rc_t, rc);
159 __checkReturn efx_rc_t
163 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
164 efx_mae_field_cap_t *ar_fcaps;
165 size_t ar_fcaps_size;
169 if (encp->enc_mae_supported == B_FALSE) {
174 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
182 rc = efx_mae_get_capabilities(enp);
186 ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
187 EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
188 if (ar_fcaps == NULL) {
193 maep->em_action_rule_field_caps_size = ar_fcaps_size;
194 maep->em_action_rule_field_caps = ar_fcaps;
196 rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
204 EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
209 EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
214 EFSYS_PROBE1(fail1, efx_rc_t, rc);
222 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
223 efx_mae_t *maep = enp->en_maep;
225 if (encp->enc_mae_supported == B_FALSE)
228 EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
229 maep->em_action_rule_field_caps);
230 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
234 __checkReturn efx_rc_t
237 __out efx_mae_limits_t *emlp)
239 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
240 struct efx_mae_s *maep = enp->en_maep;
243 if (encp->enc_mae_supported == B_FALSE) {
248 emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
249 emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
250 emlp->eml_encap_types_supported = maep->em_encap_types_supported;
255 EFSYS_PROBE1(fail1, efx_rc_t, rc);
259 __checkReturn efx_rc_t
260 efx_mae_match_spec_init(
262 __in efx_mae_rule_type_t type,
264 __out efx_mae_match_spec_t **specp)
266 efx_mae_match_spec_t *spec;
270 case EFX_MAE_RULE_OUTER:
272 case EFX_MAE_RULE_ACTION:
279 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
285 spec->emms_type = type;
286 spec->emms_prio = prio;
295 EFSYS_PROBE1(fail1, efx_rc_t, rc);
300 efx_mae_match_spec_fini(
302 __in efx_mae_match_spec_t *spec)
304 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
307 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
308 typedef enum efx_mae_field_cap_id_e {
309 EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
310 EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
311 EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
312 EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
313 EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
314 EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
315 EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
316 EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
317 EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
318 EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
319 EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
320 EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
321 EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
322 EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
323 EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
324 EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
325 EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
326 EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
327 EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
328 EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
329 EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
330 EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
331 EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
332 EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
333 EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
334 EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
335 EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
336 EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
337 EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
338 EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
339 EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
340 EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
341 EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
342 EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
344 EFX_MAE_FIELD_CAP_NIDS
345 } efx_mae_field_cap_id_t;
347 typedef enum efx_mae_field_endianness_e {
348 EFX_MAE_FIELD_LE = 0,
351 EFX_MAE_FIELD_ENDIANNESS_NTYPES
352 } efx_mae_field_endianness_t;
355 * The following structure is a means to describe an MAE field.
356 * The information in it is meant to be used internally by
357 * APIs for addressing a given field in a mask-value pairs
358 * structure and for validation purposes.
360 typedef struct efx_mae_mv_desc_s {
361 efx_mae_field_cap_id_t emmd_field_cap_id;
363 size_t emmd_value_size;
364 size_t emmd_value_offset;
365 size_t emmd_mask_size;
366 size_t emmd_mask_offset;
368 efx_mae_field_endianness_t emmd_endianness;
371 /* Indices to this array are provided by efx_mae_field_id_t */
372 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
373 #define EFX_MAE_MV_DESC(_name, _endianness) \
374 [EFX_MAE_FIELD_##_name] = \
376 EFX_MAE_FIELD_ID_##_name, \
377 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN, \
378 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST, \
379 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN, \
380 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST, \
384 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
385 EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
386 EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
387 EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
388 EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
389 EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
390 EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
391 EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
392 EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
393 EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
394 EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
395 EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
396 EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
397 EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
398 EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
399 EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
400 EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
401 EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
403 #undef EFX_MAE_MV_DESC
406 /* Indices to this array are provided by efx_mae_field_id_t */
407 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
408 #define EFX_MAE_MV_DESC(_name, _endianness) \
409 [EFX_MAE_FIELD_##_name] = \
411 EFX_MAE_FIELD_ID_##_name, \
412 MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
413 MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
414 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
415 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
419 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
420 EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
421 EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
422 EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
423 EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
424 EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
425 EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
426 EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
427 EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
428 EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
429 EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
430 EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
431 EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
432 EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
433 EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
434 EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
435 EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
437 #undef EFX_MAE_MV_DESC
440 __checkReturn efx_rc_t
441 efx_mae_mport_by_phy_port(
442 __in uint32_t phy_port,
443 __out efx_mport_sel_t *mportp)
448 if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
453 EFX_POPULATE_DWORD_2(dword,
454 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
455 MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
457 memset(mportp, 0, sizeof (*mportp));
458 mportp->sel = dword.ed_u32[0];
463 EFSYS_PROBE1(fail1, efx_rc_t, rc);
467 __checkReturn efx_rc_t
468 efx_mae_mport_by_pcie_function(
471 __out efx_mport_sel_t *mportp)
476 EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
477 MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
479 if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
484 if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
489 EFX_POPULATE_DWORD_3(dword,
490 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
491 MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
492 MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
494 memset(mportp, 0, sizeof (*mportp));
495 mportp->sel = dword.ed_u32[0];
502 EFSYS_PROBE1(fail1, efx_rc_t, rc);
506 __checkReturn efx_rc_t
507 efx_mae_match_spec_field_set(
508 __in efx_mae_match_spec_t *spec,
509 __in efx_mae_field_id_t field_id,
510 __in size_t value_size,
511 __in_bcount(value_size) const uint8_t *value,
512 __in size_t mask_size,
513 __in_bcount(mask_size) const uint8_t *mask)
515 const efx_mae_mv_desc_t *descp;
519 if (field_id >= EFX_MAE_FIELD_NIDS) {
524 switch (spec->emms_type) {
525 case EFX_MAE_RULE_OUTER:
526 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
527 mvp = spec->emms_mask_value_pairs.outer;
529 case EFX_MAE_RULE_ACTION:
530 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
531 mvp = spec->emms_mask_value_pairs.action;
538 if (value_size != descp->emmd_value_size) {
543 if (mask_size != descp->emmd_mask_size) {
548 if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
550 * The mask/value are in network (big endian) order.
551 * The MCDI request field is also big endian.
553 memcpy(mvp + descp->emmd_value_offset, value, value_size);
554 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
559 * The mask/value are in host byte order.
560 * The MCDI request field is little endian.
562 switch (value_size) {
564 EFX_POPULATE_DWORD_1(dword,
565 EFX_DWORD_0, *(const uint32_t *)value);
567 memcpy(mvp + descp->emmd_value_offset,
568 &dword, sizeof (dword));
571 EFSYS_ASSERT(B_FALSE);
576 EFX_POPULATE_DWORD_1(dword,
577 EFX_DWORD_0, *(const uint32_t *)mask);
579 memcpy(mvp + descp->emmd_mask_offset,
580 &dword, sizeof (dword));
583 EFSYS_ASSERT(B_FALSE);
596 EFSYS_PROBE1(fail1, efx_rc_t, rc);
600 __checkReturn efx_rc_t
601 efx_mae_match_spec_mport_set(
602 __in efx_mae_match_spec_t *spec,
603 __in const efx_mport_sel_t *valuep,
604 __in_opt const efx_mport_sel_t *maskp)
606 uint32_t full_mask = UINT32_MAX;
611 if (valuep == NULL) {
616 vp = (const uint8_t *)&valuep->sel;
618 mp = (const uint8_t *)&maskp->sel;
620 mp = (const uint8_t *)&full_mask;
622 rc = efx_mae_match_spec_field_set(spec,
623 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
624 sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
633 EFSYS_PROBE1(fail1, efx_rc_t, rc);
637 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit) \
638 ((_mask)[(_bit) / (_mask_page_nbits)] & \
639 (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
641 static inline boolean_t
643 __in size_t mask_nbytes,
644 __in_bcount(mask_nbytes) const uint8_t *maskp)
646 boolean_t prev_bit_is_set = B_TRUE;
649 for (i = 0; i < 8 * mask_nbytes; ++i) {
650 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
652 if (!prev_bit_is_set && bit_is_set)
655 prev_bit_is_set = bit_is_set;
661 static inline boolean_t
662 efx_mask_is_all_ones(
663 __in size_t mask_nbytes,
664 __in_bcount(mask_nbytes) const uint8_t *maskp)
669 for (i = 0; i < mask_nbytes; ++i)
672 return (t == (uint8_t)(~0));
675 static inline boolean_t
676 efx_mask_is_all_zeros(
677 __in size_t mask_nbytes,
678 __in_bcount(mask_nbytes) const uint8_t *maskp)
683 for (i = 0; i < mask_nbytes; ++i)
689 __checkReturn boolean_t
690 efx_mae_match_spec_is_valid(
692 __in const efx_mae_match_spec_t *spec)
694 efx_mae_t *maep = enp->en_maep;
695 unsigned int field_ncaps = maep->em_max_nfields;
696 const efx_mae_field_cap_t *field_caps;
697 const efx_mae_mv_desc_t *desc_setp;
698 unsigned int desc_set_nentries;
699 boolean_t is_valid = B_TRUE;
700 efx_mae_field_id_t field_id;
703 switch (spec->emms_type) {
704 case EFX_MAE_RULE_ACTION:
705 field_caps = maep->em_action_rule_field_caps;
706 desc_setp = __efx_mae_action_rule_mv_desc_set;
708 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
709 mvp = spec->emms_mask_value_pairs.action;
715 if (field_caps == NULL)
718 for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
719 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
720 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
721 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
722 size_t m_size = descp->emmd_mask_size;
725 continue; /* Skip array gap */
727 if (field_cap_id >= field_ncaps)
730 switch (field_caps[field_cap_id].emfc_support) {
731 case MAE_FIELD_SUPPORTED_MATCH_MASK:
734 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
735 is_valid = efx_mask_is_prefix(m_size, m_buf);
737 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
738 is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
739 efx_mask_is_all_zeros(m_size, m_buf));
741 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
742 is_valid = efx_mask_is_all_ones(m_size, m_buf);
744 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
745 case MAE_FIELD_UNSUPPORTED:
747 is_valid = efx_mask_is_all_zeros(m_size, m_buf);
751 if (is_valid == B_FALSE)
758 __checkReturn efx_rc_t
759 efx_mae_action_set_spec_init(
761 __out efx_mae_actions_t **specp)
763 efx_mae_actions_t *spec;
766 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
777 EFSYS_PROBE1(fail1, efx_rc_t, rc);
782 efx_mae_action_set_spec_fini(
784 __in efx_mae_actions_t *spec)
786 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
789 static __checkReturn efx_rc_t
790 efx_mae_action_set_add_vlan_pop(
791 __in efx_mae_actions_t *spec,
792 __in size_t arg_size,
793 __in_bcount(arg_size) const uint8_t *arg)
807 if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
812 ++spec->ema_n_vlan_tags_to_pop;
821 EFSYS_PROBE1(fail1, efx_rc_t, rc);
825 static __checkReturn efx_rc_t
826 efx_mae_action_set_add_vlan_push(
827 __in efx_mae_actions_t *spec,
828 __in size_t arg_size,
829 __in_bcount(arg_size) const uint8_t *arg)
831 unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
834 if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
844 if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
849 memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
850 ++(spec->ema_n_vlan_tags_to_push);
859 EFSYS_PROBE1(fail1, efx_rc_t, rc);
863 static __checkReturn efx_rc_t
864 efx_mae_action_set_add_flag(
865 __in efx_mae_actions_t *spec,
866 __in size_t arg_size,
867 __in_bcount(arg_size) const uint8_t *arg)
871 _NOTE(ARGUNUSED(spec))
883 /* This action does not have any arguments, so do nothing here. */
890 EFSYS_PROBE1(fail1, efx_rc_t, rc);
894 static __checkReturn efx_rc_t
895 efx_mae_action_set_add_mark(
896 __in efx_mae_actions_t *spec,
897 __in size_t arg_size,
898 __in_bcount(arg_size) const uint8_t *arg)
902 if (arg_size != sizeof (spec->ema_mark_value)) {
912 memcpy(&spec->ema_mark_value, arg, arg_size);
919 EFSYS_PROBE1(fail1, efx_rc_t, rc);
923 static __checkReturn efx_rc_t
924 efx_mae_action_set_add_deliver(
925 __in efx_mae_actions_t *spec,
926 __in size_t arg_size,
927 __in_bcount(arg_size) const uint8_t *arg)
931 if (arg_size != sizeof (spec->ema_deliver_mport)) {
941 memcpy(&spec->ema_deliver_mport, arg, arg_size);
948 EFSYS_PROBE1(fail1, efx_rc_t, rc);
952 typedef struct efx_mae_action_desc_s {
953 /* Action specific handler */
954 efx_rc_t (*emad_add)(efx_mae_actions_t *,
955 size_t, const uint8_t *);
956 } efx_mae_action_desc_t;
958 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
959 [EFX_MAE_ACTION_VLAN_POP] = {
960 .emad_add = efx_mae_action_set_add_vlan_pop
962 [EFX_MAE_ACTION_VLAN_PUSH] = {
963 .emad_add = efx_mae_action_set_add_vlan_push
965 [EFX_MAE_ACTION_FLAG] = {
966 .emad_add = efx_mae_action_set_add_flag
968 [EFX_MAE_ACTION_MARK] = {
969 .emad_add = efx_mae_action_set_add_mark
971 [EFX_MAE_ACTION_DELIVER] = {
972 .emad_add = efx_mae_action_set_add_deliver
976 static const uint32_t efx_mae_action_ordered_map =
977 (1U << EFX_MAE_ACTION_VLAN_POP) |
978 (1U << EFX_MAE_ACTION_VLAN_PUSH) |
979 (1U << EFX_MAE_ACTION_FLAG) |
980 (1U << EFX_MAE_ACTION_MARK) |
981 (1U << EFX_MAE_ACTION_DELIVER);
984 * These actions must not be added after DELIVER, but
985 * they can have any place among the rest of
986 * strictly ordered actions.
988 static const uint32_t efx_mae_action_nonstrict_map =
989 (1U << EFX_MAE_ACTION_FLAG) |
990 (1U << EFX_MAE_ACTION_MARK);
992 static const uint32_t efx_mae_action_repeat_map =
993 (1U << EFX_MAE_ACTION_VLAN_POP) |
994 (1U << EFX_MAE_ACTION_VLAN_PUSH);
997 * Add an action to an action set.
999 * This has to be invoked in the desired action order.
1000 * An out-of-order action request will be turned down.
1002 static __checkReturn efx_rc_t
1003 efx_mae_action_set_spec_populate(
1004 __in efx_mae_actions_t *spec,
1005 __in efx_mae_action_t type,
1006 __in size_t arg_size,
1007 __in_bcount(arg_size) const uint8_t *arg)
1009 uint32_t action_mask;
1012 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1013 (sizeof (efx_mae_action_ordered_map) * 8));
1014 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1015 (sizeof (efx_mae_action_repeat_map) * 8));
1017 EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1018 EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1019 EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1021 if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1026 action_mask = (1U << type);
1028 if ((spec->ema_actions & action_mask) != 0) {
1029 /* The action set already contains this action. */
1030 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1031 /* Cannot add another non-repeatable action. */
1037 if ((efx_mae_action_ordered_map & action_mask) != 0) {
1038 uint32_t strict_ordered_map =
1039 efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1040 uint32_t later_actions_mask =
1041 strict_ordered_map & ~(action_mask | (action_mask - 1));
1043 if ((spec->ema_actions & later_actions_mask) != 0) {
1044 /* Cannot add an action after later ordered actions. */
1050 if (efx_mae_actions[type].emad_add != NULL) {
1051 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1056 spec->ema_actions |= action_mask;
1067 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1071 __checkReturn efx_rc_t
1072 efx_mae_action_set_populate_vlan_pop(
1073 __in efx_mae_actions_t *spec)
1075 return (efx_mae_action_set_spec_populate(spec,
1076 EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1079 __checkReturn efx_rc_t
1080 efx_mae_action_set_populate_vlan_push(
1081 __in efx_mae_actions_t *spec,
1082 __in uint16_t tpid_be,
1083 __in uint16_t tci_be)
1085 efx_mae_action_vlan_push_t action;
1086 const uint8_t *arg = (const uint8_t *)&action;
1088 action.emavp_tpid_be = tpid_be;
1089 action.emavp_tci_be = tci_be;
1091 return (efx_mae_action_set_spec_populate(spec,
1092 EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1095 __checkReturn efx_rc_t
1096 efx_mae_action_set_populate_flag(
1097 __in efx_mae_actions_t *spec)
1099 return (efx_mae_action_set_spec_populate(spec,
1100 EFX_MAE_ACTION_FLAG, 0, NULL));
1103 __checkReturn efx_rc_t
1104 efx_mae_action_set_populate_mark(
1105 __in efx_mae_actions_t *spec,
1106 __in uint32_t mark_value)
1108 const uint8_t *arg = (const uint8_t *)&mark_value;
1110 return (efx_mae_action_set_spec_populate(spec,
1111 EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1114 __checkReturn efx_rc_t
1115 efx_mae_action_set_populate_deliver(
1116 __in efx_mae_actions_t *spec,
1117 __in const efx_mport_sel_t *mportp)
1122 if (mportp == NULL) {
1127 arg = (const uint8_t *)&mportp->sel;
1129 return (efx_mae_action_set_spec_populate(spec,
1130 EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1133 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1137 __checkReturn efx_rc_t
1138 efx_mae_action_set_populate_drop(
1139 __in efx_mae_actions_t *spec)
1141 efx_mport_sel_t mport;
1145 EFX_POPULATE_DWORD_1(dword,
1146 MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1148 mport.sel = dword.ed_u32[0];
1150 arg = (const uint8_t *)&mport.sel;
1152 return (efx_mae_action_set_spec_populate(spec,
1153 EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1156 __checkReturn boolean_t
1157 efx_mae_action_set_specs_equal(
1158 __in const efx_mae_actions_t *left,
1159 __in const efx_mae_actions_t *right)
1161 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1164 __checkReturn efx_rc_t
1165 efx_mae_match_specs_class_cmp(
1166 __in efx_nic_t *enp,
1167 __in const efx_mae_match_spec_t *left,
1168 __in const efx_mae_match_spec_t *right,
1169 __out boolean_t *have_same_classp)
1171 efx_mae_t *maep = enp->en_maep;
1172 unsigned int field_ncaps = maep->em_max_nfields;
1173 const efx_mae_field_cap_t *field_caps;
1174 const efx_mae_mv_desc_t *desc_setp;
1175 unsigned int desc_set_nentries;
1176 boolean_t have_same_class = B_TRUE;
1177 efx_mae_field_id_t field_id;
1178 const uint8_t *mvpl;
1179 const uint8_t *mvpr;
1182 switch (left->emms_type) {
1183 case EFX_MAE_RULE_ACTION:
1184 field_caps = maep->em_action_rule_field_caps;
1185 desc_setp = __efx_mae_action_rule_mv_desc_set;
1187 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1188 mvpl = left->emms_mask_value_pairs.action;
1189 mvpr = right->emms_mask_value_pairs.action;
1196 if (field_caps == NULL) {
1201 if (left->emms_type != right->emms_type ||
1202 left->emms_prio != right->emms_prio) {
1204 * Rules of different types can never map to the same class.
1206 * The FW can support some set of match criteria for one
1207 * priority and not support the very same set for
1208 * another priority. Thus, two rules which have
1209 * different priorities can never map to
1212 *have_same_classp = B_FALSE;
1216 for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
1217 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1218 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1220 if (descp->emmd_mask_size == 0)
1221 continue; /* Skip array gap */
1223 if (field_cap_id >= field_ncaps)
1226 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1227 const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1228 const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1229 size_t mask_size = descp->emmd_mask_size;
1231 if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1232 have_same_class = B_FALSE;
1237 if (field_caps[field_cap_id].emfc_match_affects_class) {
1238 const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1239 const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1240 size_t value_size = descp->emmd_value_size;
1242 if (memcmp(lvalp, rvalp, value_size) != 0) {
1243 have_same_class = B_FALSE;
1249 *have_same_classp = have_same_class;
1256 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1260 __checkReturn efx_rc_t
1261 efx_mae_action_set_alloc(
1262 __in efx_nic_t *enp,
1263 __in const efx_mae_actions_t *spec,
1264 __out efx_mae_aset_id_t *aset_idp)
1266 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1268 EFX_MCDI_DECLARE_BUF(payload,
1269 MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1270 MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1271 efx_mae_aset_id_t aset_id;
1274 if (encp->enc_mae_supported == B_FALSE) {
1279 req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1280 req.emr_in_buf = payload;
1281 req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1282 req.emr_out_buf = payload;
1283 req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1286 * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1287 * corresponding resource types are supported by the implementation.
1288 * Use proper resource ID assignments instead.
1290 MCDI_IN_SET_DWORD(req,
1291 MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1292 MCDI_IN_SET_DWORD(req,
1293 MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1294 MCDI_IN_SET_DWORD(req,
1295 MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1297 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1298 MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1300 if (spec->ema_n_vlan_tags_to_push > 0) {
1301 unsigned int outer_tag_idx;
1303 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1304 MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1305 spec->ema_n_vlan_tags_to_push);
1307 if (spec->ema_n_vlan_tags_to_push ==
1308 EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1309 MCDI_IN_SET_WORD(req,
1310 MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1311 spec->ema_vlan_push_descs[0].emavp_tpid_be);
1312 MCDI_IN_SET_WORD(req,
1313 MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1314 spec->ema_vlan_push_descs[0].emavp_tci_be);
1317 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1319 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1320 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1321 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1322 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1325 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1326 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1327 MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1330 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1331 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1332 MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1334 MCDI_IN_SET_DWORD(req,
1335 MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1338 MCDI_IN_SET_DWORD(req,
1339 MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1341 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1342 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1343 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1344 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1346 efx_mcdi_execute(enp, &req);
1348 if (req.emr_rc != 0) {
1353 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1358 aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1359 if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1364 aset_idp->id = aset_id.id;
1375 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1379 __checkReturn efx_rc_t
1380 efx_mae_action_set_free(
1381 __in efx_nic_t *enp,
1382 __in const efx_mae_aset_id_t *aset_idp)
1384 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1386 EFX_MCDI_DECLARE_BUF(payload,
1387 MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1388 MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1391 if (encp->enc_mae_supported == B_FALSE) {
1396 req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1397 req.emr_in_buf = payload;
1398 req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1399 req.emr_out_buf = payload;
1400 req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1402 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1404 efx_mcdi_execute(enp, &req);
1406 if (req.emr_rc != 0) {
1411 if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1413 /* Firmware failed to free the action set. */
1425 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1429 __checkReturn efx_rc_t
1430 efx_mae_action_rule_insert(
1431 __in efx_nic_t *enp,
1432 __in const efx_mae_match_spec_t *spec,
1433 __in const efx_mae_aset_list_id_t *asl_idp,
1434 __in const efx_mae_aset_id_t *as_idp,
1435 __out efx_mae_rule_id_t *ar_idp)
1437 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1439 EFX_MCDI_DECLARE_BUF(payload,
1440 MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1441 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1442 efx_oword_t *rule_response;
1443 efx_mae_rule_id_t ar_id;
1447 EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1448 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1450 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1451 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1453 if (encp->enc_mae_supported == B_FALSE) {
1458 if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1459 (asl_idp != NULL && as_idp != NULL) ||
1460 (asl_idp == NULL && as_idp == NULL)) {
1465 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1466 req.emr_in_buf = payload;
1467 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1468 req.emr_out_buf = payload;
1469 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1471 EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1472 MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1473 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1474 rule_response = (efx_oword_t *)(payload + offset);
1475 EFX_POPULATE_OWORD_3(*rule_response,
1476 MAE_ACTION_RULE_RESPONSE_ASL_ID,
1477 (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1478 MAE_ACTION_RULE_RESPONSE_AS_ID,
1479 (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1480 MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1482 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1485 * Mask-value pairs have been stored in the byte order needed for the
1486 * MCDI request and are thus safe to be copied directly to the buffer.
1488 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1489 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1490 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1491 memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1492 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1494 efx_mcdi_execute(enp, &req);
1496 if (req.emr_rc != 0) {
1501 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1506 ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1507 if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1512 ar_idp->id = ar_id.id;
1525 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1529 __checkReturn efx_rc_t
1530 efx_mae_action_rule_remove(
1531 __in efx_nic_t *enp,
1532 __in const efx_mae_rule_id_t *ar_idp)
1534 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1536 EFX_MCDI_DECLARE_BUF(payload,
1537 MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1538 MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1541 if (encp->enc_mae_supported == B_FALSE) {
1546 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1547 req.emr_in_buf = payload;
1548 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1549 req.emr_out_buf = payload;
1550 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1552 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1554 efx_mcdi_execute(enp, &req);
1556 if (req.emr_rc != 0) {
1561 if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1563 /* Firmware failed to delete the action rule. */
1575 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1579 #endif /* EFSYS_OPT_MAE */