1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
13 static __checkReturn efx_rc_t
14 efx_mae_get_capabilities(
18 EFX_MCDI_DECLARE_BUF(payload,
19 MC_CMD_MAE_GET_CAPS_IN_LEN,
20 MC_CMD_MAE_GET_CAPS_OUT_LEN);
21 struct efx_mae_s *maep = enp->en_maep;
24 req.emr_cmd = MC_CMD_MAE_GET_CAPS;
25 req.emr_in_buf = payload;
26 req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
27 req.emr_out_buf = payload;
28 req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
30 efx_mcdi_execute(enp, &req);
32 if (req.emr_rc != 0) {
37 if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
42 maep->em_max_n_outer_prios =
43 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
45 maep->em_max_n_action_prios =
46 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
48 maep->em_encap_types_supported = 0;
50 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
51 maep->em_encap_types_supported |=
52 (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
55 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
56 maep->em_encap_types_supported |=
57 (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
60 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
61 maep->em_encap_types_supported |=
62 (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
65 maep->em_max_nfields =
66 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
73 EFSYS_PROBE1(fail1, efx_rc_t, rc);
77 static __checkReturn efx_rc_t
78 efx_mae_get_action_rule_caps(
80 __in unsigned int field_ncaps,
81 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
84 EFX_MCDI_DECLARE_BUF(payload,
85 MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
86 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
87 unsigned int mcdi_field_ncaps;
91 if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
92 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
97 req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
98 req.emr_in_buf = payload;
99 req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
100 req.emr_out_buf = payload;
101 req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
103 efx_mcdi_execute(enp, &req);
105 if (req.emr_rc != 0) {
110 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
112 if (req.emr_out_length_used <
113 MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
118 if (mcdi_field_ncaps > field_ncaps) {
123 for (i = 0; i < mcdi_field_ncaps; ++i) {
127 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
128 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
129 MAE_FIELD_FLAGS_SUPPORT_STATUS);
131 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
132 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
133 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
135 field_caps[i].emfc_match_affects_class =
136 (match_flag != 0) ? B_TRUE : B_FALSE;
138 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
139 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
140 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
142 field_caps[i].emfc_mask_affects_class =
143 (mask_flag != 0) ? B_TRUE : B_FALSE;
155 EFSYS_PROBE1(fail1, efx_rc_t, rc);
159 __checkReturn efx_rc_t
163 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
164 efx_mae_field_cap_t *ar_fcaps;
165 size_t ar_fcaps_size;
169 if (encp->enc_mae_supported == B_FALSE) {
174 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
182 rc = efx_mae_get_capabilities(enp);
186 ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
187 EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
188 if (ar_fcaps == NULL) {
193 maep->em_action_rule_field_caps_size = ar_fcaps_size;
194 maep->em_action_rule_field_caps = ar_fcaps;
196 rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
204 EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
209 EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
214 EFSYS_PROBE1(fail1, efx_rc_t, rc);
222 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
223 efx_mae_t *maep = enp->en_maep;
225 if (encp->enc_mae_supported == B_FALSE)
228 EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
229 maep->em_action_rule_field_caps);
230 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
234 __checkReturn efx_rc_t
237 __out efx_mae_limits_t *emlp)
239 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
240 struct efx_mae_s *maep = enp->en_maep;
243 if (encp->enc_mae_supported == B_FALSE) {
248 emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
249 emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
250 emlp->eml_encap_types_supported = maep->em_encap_types_supported;
255 EFSYS_PROBE1(fail1, efx_rc_t, rc);
259 __checkReturn efx_rc_t
260 efx_mae_match_spec_init(
262 __in efx_mae_rule_type_t type,
264 __out efx_mae_match_spec_t **specp)
266 efx_mae_match_spec_t *spec;
270 case EFX_MAE_RULE_OUTER:
272 case EFX_MAE_RULE_ACTION:
279 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
285 spec->emms_type = type;
286 spec->emms_prio = prio;
295 EFSYS_PROBE1(fail1, efx_rc_t, rc);
300 efx_mae_match_spec_fini(
302 __in efx_mae_match_spec_t *spec)
304 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
307 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
308 typedef enum efx_mae_field_cap_id_e {
309 EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
310 EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
311 EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
312 EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
313 EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
314 EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
315 EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
316 EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
317 EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
318 EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
319 EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
320 EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
321 EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
322 EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
323 EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
324 EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
325 EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
326 EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
327 EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
328 EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
329 EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
330 EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
331 EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
332 EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
333 EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
334 EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
335 EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
336 EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
337 EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
338 EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
339 EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
340 EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
341 EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
342 EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
343 EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
345 EFX_MAE_FIELD_CAP_NIDS
346 } efx_mae_field_cap_id_t;
348 typedef enum efx_mae_field_endianness_e {
349 EFX_MAE_FIELD_LE = 0,
352 EFX_MAE_FIELD_ENDIANNESS_NTYPES
353 } efx_mae_field_endianness_t;
356 * The following structure is a means to describe an MAE field.
357 * The information in it is meant to be used internally by
358 * APIs for addressing a given field in a mask-value pairs
359 * structure and for validation purposes.
361 typedef struct efx_mae_mv_desc_s {
362 efx_mae_field_cap_id_t emmd_field_cap_id;
364 size_t emmd_value_size;
365 size_t emmd_value_offset;
366 size_t emmd_mask_size;
367 size_t emmd_mask_offset;
369 efx_mae_field_endianness_t emmd_endianness;
372 /* Indices to this array are provided by efx_mae_field_id_t */
373 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
374 #define EFX_MAE_MV_DESC(_name, _endianness) \
375 [EFX_MAE_FIELD_##_name] = \
377 EFX_MAE_FIELD_ID_##_name, \
378 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN, \
379 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST, \
380 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN, \
381 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST, \
385 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
386 EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
387 EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
388 EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
389 EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
390 EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
391 EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
392 EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
393 EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
394 EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
395 EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
396 EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
397 EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
398 EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
399 EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
400 EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
401 EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
402 EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
403 EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
405 #undef EFX_MAE_MV_DESC
408 /* Indices to this array are provided by efx_mae_field_id_t */
409 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
410 #define EFX_MAE_MV_DESC(_name, _endianness) \
411 [EFX_MAE_FIELD_##_name] = \
413 EFX_MAE_FIELD_ID_##_name, \
414 MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
415 MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
416 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
417 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
421 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
422 EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
423 EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
424 EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
425 EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
426 EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
427 EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
428 EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
429 EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
430 EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
431 EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
432 EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
433 EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
434 EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
435 EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
436 EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
437 EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
439 #undef EFX_MAE_MV_DESC
442 __checkReturn efx_rc_t
443 efx_mae_mport_by_phy_port(
444 __in uint32_t phy_port,
445 __out efx_mport_sel_t *mportp)
450 if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
455 EFX_POPULATE_DWORD_2(dword,
456 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
457 MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
459 memset(mportp, 0, sizeof (*mportp));
460 mportp->sel = dword.ed_u32[0];
465 EFSYS_PROBE1(fail1, efx_rc_t, rc);
469 __checkReturn efx_rc_t
470 efx_mae_mport_by_pcie_function(
473 __out efx_mport_sel_t *mportp)
478 EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
479 MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
481 if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
486 if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
491 EFX_POPULATE_DWORD_3(dword,
492 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
493 MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
494 MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
496 memset(mportp, 0, sizeof (*mportp));
497 mportp->sel = dword.ed_u32[0];
504 EFSYS_PROBE1(fail1, efx_rc_t, rc);
508 __checkReturn efx_rc_t
509 efx_mae_match_spec_field_set(
510 __in efx_mae_match_spec_t *spec,
511 __in efx_mae_field_id_t field_id,
512 __in size_t value_size,
513 __in_bcount(value_size) const uint8_t *value,
514 __in size_t mask_size,
515 __in_bcount(mask_size) const uint8_t *mask)
517 const efx_mae_mv_desc_t *descp;
521 if (field_id >= EFX_MAE_FIELD_NIDS) {
526 switch (spec->emms_type) {
527 case EFX_MAE_RULE_OUTER:
528 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
529 mvp = spec->emms_mask_value_pairs.outer;
531 case EFX_MAE_RULE_ACTION:
532 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
533 mvp = spec->emms_mask_value_pairs.action;
540 if (value_size != descp->emmd_value_size) {
545 if (mask_size != descp->emmd_mask_size) {
550 if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
552 * The mask/value are in network (big endian) order.
553 * The MCDI request field is also big endian.
555 memcpy(mvp + descp->emmd_value_offset, value, value_size);
556 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
561 * The mask/value are in host byte order.
562 * The MCDI request field is little endian.
564 switch (value_size) {
566 EFX_POPULATE_DWORD_1(dword,
567 EFX_DWORD_0, *(const uint32_t *)value);
569 memcpy(mvp + descp->emmd_value_offset,
570 &dword, sizeof (dword));
573 EFSYS_ASSERT(B_FALSE);
578 EFX_POPULATE_DWORD_1(dword,
579 EFX_DWORD_0, *(const uint32_t *)mask);
581 memcpy(mvp + descp->emmd_mask_offset,
582 &dword, sizeof (dword));
585 EFSYS_ASSERT(B_FALSE);
598 EFSYS_PROBE1(fail1, efx_rc_t, rc);
602 __checkReturn efx_rc_t
603 efx_mae_match_spec_mport_set(
604 __in efx_mae_match_spec_t *spec,
605 __in const efx_mport_sel_t *valuep,
606 __in_opt const efx_mport_sel_t *maskp)
608 uint32_t full_mask = UINT32_MAX;
613 if (valuep == NULL) {
618 vp = (const uint8_t *)&valuep->sel;
620 mp = (const uint8_t *)&maskp->sel;
622 mp = (const uint8_t *)&full_mask;
624 rc = efx_mae_match_spec_field_set(spec,
625 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
626 sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
635 EFSYS_PROBE1(fail1, efx_rc_t, rc);
639 __checkReturn boolean_t
640 efx_mae_match_specs_equal(
641 __in const efx_mae_match_spec_t *left,
642 __in const efx_mae_match_spec_t *right)
644 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
647 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit) \
648 ((_mask)[(_bit) / (_mask_page_nbits)] & \
649 (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
651 static inline boolean_t
653 __in size_t mask_nbytes,
654 __in_bcount(mask_nbytes) const uint8_t *maskp)
656 boolean_t prev_bit_is_set = B_TRUE;
659 for (i = 0; i < 8 * mask_nbytes; ++i) {
660 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
662 if (!prev_bit_is_set && bit_is_set)
665 prev_bit_is_set = bit_is_set;
671 static inline boolean_t
672 efx_mask_is_all_ones(
673 __in size_t mask_nbytes,
674 __in_bcount(mask_nbytes) const uint8_t *maskp)
679 for (i = 0; i < mask_nbytes; ++i)
682 return (t == (uint8_t)(~0));
685 static inline boolean_t
686 efx_mask_is_all_zeros(
687 __in size_t mask_nbytes,
688 __in_bcount(mask_nbytes) const uint8_t *maskp)
693 for (i = 0; i < mask_nbytes; ++i)
699 __checkReturn boolean_t
700 efx_mae_match_spec_is_valid(
702 __in const efx_mae_match_spec_t *spec)
704 efx_mae_t *maep = enp->en_maep;
705 unsigned int field_ncaps = maep->em_max_nfields;
706 const efx_mae_field_cap_t *field_caps;
707 const efx_mae_mv_desc_t *desc_setp;
708 unsigned int desc_set_nentries;
709 boolean_t is_valid = B_TRUE;
710 efx_mae_field_id_t field_id;
713 switch (spec->emms_type) {
714 case EFX_MAE_RULE_ACTION:
715 field_caps = maep->em_action_rule_field_caps;
716 desc_setp = __efx_mae_action_rule_mv_desc_set;
718 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
719 mvp = spec->emms_mask_value_pairs.action;
725 if (field_caps == NULL)
728 for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
729 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
730 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
731 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
732 size_t m_size = descp->emmd_mask_size;
735 continue; /* Skip array gap */
737 if (field_cap_id >= field_ncaps)
740 switch (field_caps[field_cap_id].emfc_support) {
741 case MAE_FIELD_SUPPORTED_MATCH_MASK:
744 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
745 is_valid = efx_mask_is_prefix(m_size, m_buf);
747 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
748 is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
749 efx_mask_is_all_zeros(m_size, m_buf));
751 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
752 is_valid = efx_mask_is_all_ones(m_size, m_buf);
754 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
755 case MAE_FIELD_UNSUPPORTED:
757 is_valid = efx_mask_is_all_zeros(m_size, m_buf);
761 if (is_valid == B_FALSE)
768 __checkReturn efx_rc_t
769 efx_mae_action_set_spec_init(
771 __out efx_mae_actions_t **specp)
773 efx_mae_actions_t *spec;
776 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
787 EFSYS_PROBE1(fail1, efx_rc_t, rc);
792 efx_mae_action_set_spec_fini(
794 __in efx_mae_actions_t *spec)
796 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
799 static __checkReturn efx_rc_t
800 efx_mae_action_set_add_vlan_pop(
801 __in efx_mae_actions_t *spec,
802 __in size_t arg_size,
803 __in_bcount(arg_size) const uint8_t *arg)
817 if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
822 ++spec->ema_n_vlan_tags_to_pop;
831 EFSYS_PROBE1(fail1, efx_rc_t, rc);
835 static __checkReturn efx_rc_t
836 efx_mae_action_set_add_vlan_push(
837 __in efx_mae_actions_t *spec,
838 __in size_t arg_size,
839 __in_bcount(arg_size) const uint8_t *arg)
841 unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
844 if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
854 if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
859 memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
860 ++(spec->ema_n_vlan_tags_to_push);
869 EFSYS_PROBE1(fail1, efx_rc_t, rc);
873 static __checkReturn efx_rc_t
874 efx_mae_action_set_add_flag(
875 __in efx_mae_actions_t *spec,
876 __in size_t arg_size,
877 __in_bcount(arg_size) const uint8_t *arg)
881 _NOTE(ARGUNUSED(spec))
893 /* This action does not have any arguments, so do nothing here. */
900 EFSYS_PROBE1(fail1, efx_rc_t, rc);
904 static __checkReturn efx_rc_t
905 efx_mae_action_set_add_mark(
906 __in efx_mae_actions_t *spec,
907 __in size_t arg_size,
908 __in_bcount(arg_size) const uint8_t *arg)
912 if (arg_size != sizeof (spec->ema_mark_value)) {
922 memcpy(&spec->ema_mark_value, arg, arg_size);
929 EFSYS_PROBE1(fail1, efx_rc_t, rc);
933 static __checkReturn efx_rc_t
934 efx_mae_action_set_add_deliver(
935 __in efx_mae_actions_t *spec,
936 __in size_t arg_size,
937 __in_bcount(arg_size) const uint8_t *arg)
941 if (arg_size != sizeof (spec->ema_deliver_mport)) {
951 memcpy(&spec->ema_deliver_mport, arg, arg_size);
958 EFSYS_PROBE1(fail1, efx_rc_t, rc);
962 typedef struct efx_mae_action_desc_s {
963 /* Action specific handler */
964 efx_rc_t (*emad_add)(efx_mae_actions_t *,
965 size_t, const uint8_t *);
966 } efx_mae_action_desc_t;
968 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
969 [EFX_MAE_ACTION_VLAN_POP] = {
970 .emad_add = efx_mae_action_set_add_vlan_pop
972 [EFX_MAE_ACTION_VLAN_PUSH] = {
973 .emad_add = efx_mae_action_set_add_vlan_push
975 [EFX_MAE_ACTION_FLAG] = {
976 .emad_add = efx_mae_action_set_add_flag
978 [EFX_MAE_ACTION_MARK] = {
979 .emad_add = efx_mae_action_set_add_mark
981 [EFX_MAE_ACTION_DELIVER] = {
982 .emad_add = efx_mae_action_set_add_deliver
986 static const uint32_t efx_mae_action_ordered_map =
987 (1U << EFX_MAE_ACTION_VLAN_POP) |
988 (1U << EFX_MAE_ACTION_VLAN_PUSH) |
989 (1U << EFX_MAE_ACTION_FLAG) |
990 (1U << EFX_MAE_ACTION_MARK) |
991 (1U << EFX_MAE_ACTION_DELIVER);
994 * These actions must not be added after DELIVER, but
995 * they can have any place among the rest of
996 * strictly ordered actions.
998 static const uint32_t efx_mae_action_nonstrict_map =
999 (1U << EFX_MAE_ACTION_FLAG) |
1000 (1U << EFX_MAE_ACTION_MARK);
1002 static const uint32_t efx_mae_action_repeat_map =
1003 (1U << EFX_MAE_ACTION_VLAN_POP) |
1004 (1U << EFX_MAE_ACTION_VLAN_PUSH);
1007 * Add an action to an action set.
1009 * This has to be invoked in the desired action order.
1010 * An out-of-order action request will be turned down.
1012 static __checkReturn efx_rc_t
1013 efx_mae_action_set_spec_populate(
1014 __in efx_mae_actions_t *spec,
1015 __in efx_mae_action_t type,
1016 __in size_t arg_size,
1017 __in_bcount(arg_size) const uint8_t *arg)
1019 uint32_t action_mask;
1022 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1023 (sizeof (efx_mae_action_ordered_map) * 8));
1024 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1025 (sizeof (efx_mae_action_repeat_map) * 8));
1027 EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1028 EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1029 EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1031 if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1036 action_mask = (1U << type);
1038 if ((spec->ema_actions & action_mask) != 0) {
1039 /* The action set already contains this action. */
1040 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1041 /* Cannot add another non-repeatable action. */
1047 if ((efx_mae_action_ordered_map & action_mask) != 0) {
1048 uint32_t strict_ordered_map =
1049 efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1050 uint32_t later_actions_mask =
1051 strict_ordered_map & ~(action_mask | (action_mask - 1));
1053 if ((spec->ema_actions & later_actions_mask) != 0) {
1054 /* Cannot add an action after later ordered actions. */
1060 if (efx_mae_actions[type].emad_add != NULL) {
1061 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1066 spec->ema_actions |= action_mask;
1077 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1081 __checkReturn efx_rc_t
1082 efx_mae_action_set_populate_vlan_pop(
1083 __in efx_mae_actions_t *spec)
1085 return (efx_mae_action_set_spec_populate(spec,
1086 EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1089 __checkReturn efx_rc_t
1090 efx_mae_action_set_populate_vlan_push(
1091 __in efx_mae_actions_t *spec,
1092 __in uint16_t tpid_be,
1093 __in uint16_t tci_be)
1095 efx_mae_action_vlan_push_t action;
1096 const uint8_t *arg = (const uint8_t *)&action;
1098 action.emavp_tpid_be = tpid_be;
1099 action.emavp_tci_be = tci_be;
1101 return (efx_mae_action_set_spec_populate(spec,
1102 EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1105 __checkReturn efx_rc_t
1106 efx_mae_action_set_populate_flag(
1107 __in efx_mae_actions_t *spec)
1109 return (efx_mae_action_set_spec_populate(spec,
1110 EFX_MAE_ACTION_FLAG, 0, NULL));
1113 __checkReturn efx_rc_t
1114 efx_mae_action_set_populate_mark(
1115 __in efx_mae_actions_t *spec,
1116 __in uint32_t mark_value)
1118 const uint8_t *arg = (const uint8_t *)&mark_value;
1120 return (efx_mae_action_set_spec_populate(spec,
1121 EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1124 __checkReturn efx_rc_t
1125 efx_mae_action_set_populate_deliver(
1126 __in efx_mae_actions_t *spec,
1127 __in const efx_mport_sel_t *mportp)
1132 if (mportp == NULL) {
1137 arg = (const uint8_t *)&mportp->sel;
1139 return (efx_mae_action_set_spec_populate(spec,
1140 EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1143 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1147 __checkReturn efx_rc_t
1148 efx_mae_action_set_populate_drop(
1149 __in efx_mae_actions_t *spec)
1151 efx_mport_sel_t mport;
1155 EFX_POPULATE_DWORD_1(dword,
1156 MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1158 mport.sel = dword.ed_u32[0];
1160 arg = (const uint8_t *)&mport.sel;
1162 return (efx_mae_action_set_spec_populate(spec,
1163 EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1166 __checkReturn boolean_t
1167 efx_mae_action_set_specs_equal(
1168 __in const efx_mae_actions_t *left,
1169 __in const efx_mae_actions_t *right)
1171 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1174 __checkReturn efx_rc_t
1175 efx_mae_match_specs_class_cmp(
1176 __in efx_nic_t *enp,
1177 __in const efx_mae_match_spec_t *left,
1178 __in const efx_mae_match_spec_t *right,
1179 __out boolean_t *have_same_classp)
1181 efx_mae_t *maep = enp->en_maep;
1182 unsigned int field_ncaps = maep->em_max_nfields;
1183 const efx_mae_field_cap_t *field_caps;
1184 const efx_mae_mv_desc_t *desc_setp;
1185 unsigned int desc_set_nentries;
1186 boolean_t have_same_class = B_TRUE;
1187 efx_mae_field_id_t field_id;
1188 const uint8_t *mvpl;
1189 const uint8_t *mvpr;
1192 switch (left->emms_type) {
1193 case EFX_MAE_RULE_ACTION:
1194 field_caps = maep->em_action_rule_field_caps;
1195 desc_setp = __efx_mae_action_rule_mv_desc_set;
1197 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1198 mvpl = left->emms_mask_value_pairs.action;
1199 mvpr = right->emms_mask_value_pairs.action;
1206 if (field_caps == NULL) {
1211 if (left->emms_type != right->emms_type ||
1212 left->emms_prio != right->emms_prio) {
1214 * Rules of different types can never map to the same class.
1216 * The FW can support some set of match criteria for one
1217 * priority and not support the very same set for
1218 * another priority. Thus, two rules which have
1219 * different priorities can never map to
1222 *have_same_classp = B_FALSE;
1226 for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
1227 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1228 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1230 if (descp->emmd_mask_size == 0)
1231 continue; /* Skip array gap */
1233 if (field_cap_id >= field_ncaps)
1236 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1237 const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1238 const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1239 size_t mask_size = descp->emmd_mask_size;
1241 if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1242 have_same_class = B_FALSE;
1247 if (field_caps[field_cap_id].emfc_match_affects_class) {
1248 const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1249 const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1250 size_t value_size = descp->emmd_value_size;
1252 if (memcmp(lvalp, rvalp, value_size) != 0) {
1253 have_same_class = B_FALSE;
1259 *have_same_classp = have_same_class;
1266 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1270 __checkReturn efx_rc_t
1271 efx_mae_action_set_alloc(
1272 __in efx_nic_t *enp,
1273 __in const efx_mae_actions_t *spec,
1274 __out efx_mae_aset_id_t *aset_idp)
1276 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1278 EFX_MCDI_DECLARE_BUF(payload,
1279 MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1280 MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1281 efx_mae_aset_id_t aset_id;
1284 if (encp->enc_mae_supported == B_FALSE) {
1289 req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1290 req.emr_in_buf = payload;
1291 req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1292 req.emr_out_buf = payload;
1293 req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1296 * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1297 * corresponding resource types are supported by the implementation.
1298 * Use proper resource ID assignments instead.
1300 MCDI_IN_SET_DWORD(req,
1301 MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1302 MCDI_IN_SET_DWORD(req,
1303 MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1304 MCDI_IN_SET_DWORD(req,
1305 MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1307 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1308 MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1310 if (spec->ema_n_vlan_tags_to_push > 0) {
1311 unsigned int outer_tag_idx;
1313 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1314 MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1315 spec->ema_n_vlan_tags_to_push);
1317 if (spec->ema_n_vlan_tags_to_push ==
1318 EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1319 MCDI_IN_SET_WORD(req,
1320 MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1321 spec->ema_vlan_push_descs[0].emavp_tpid_be);
1322 MCDI_IN_SET_WORD(req,
1323 MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1324 spec->ema_vlan_push_descs[0].emavp_tci_be);
1327 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1329 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1330 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1331 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1332 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1335 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1336 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1337 MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1340 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1341 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1342 MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1344 MCDI_IN_SET_DWORD(req,
1345 MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1348 MCDI_IN_SET_DWORD(req,
1349 MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1351 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1352 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1353 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1354 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1356 efx_mcdi_execute(enp, &req);
1358 if (req.emr_rc != 0) {
1363 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1368 aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1369 if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1374 aset_idp->id = aset_id.id;
1385 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1389 __checkReturn efx_rc_t
1390 efx_mae_action_set_free(
1391 __in efx_nic_t *enp,
1392 __in const efx_mae_aset_id_t *aset_idp)
1394 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1396 EFX_MCDI_DECLARE_BUF(payload,
1397 MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1398 MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1401 if (encp->enc_mae_supported == B_FALSE) {
1406 req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1407 req.emr_in_buf = payload;
1408 req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1409 req.emr_out_buf = payload;
1410 req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1412 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1414 efx_mcdi_execute(enp, &req);
1416 if (req.emr_rc != 0) {
1421 if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1423 /* Firmware failed to free the action set. */
1435 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1439 __checkReturn efx_rc_t
1440 efx_mae_action_rule_insert(
1441 __in efx_nic_t *enp,
1442 __in const efx_mae_match_spec_t *spec,
1443 __in const efx_mae_aset_list_id_t *asl_idp,
1444 __in const efx_mae_aset_id_t *as_idp,
1445 __out efx_mae_rule_id_t *ar_idp)
1447 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1449 EFX_MCDI_DECLARE_BUF(payload,
1450 MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1451 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1452 efx_oword_t *rule_response;
1453 efx_mae_rule_id_t ar_id;
1457 EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1458 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1460 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1461 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1463 if (encp->enc_mae_supported == B_FALSE) {
1468 if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1469 (asl_idp != NULL && as_idp != NULL) ||
1470 (asl_idp == NULL && as_idp == NULL)) {
1475 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1476 req.emr_in_buf = payload;
1477 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1478 req.emr_out_buf = payload;
1479 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1481 EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1482 MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1483 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1484 rule_response = (efx_oword_t *)(payload + offset);
1485 EFX_POPULATE_OWORD_3(*rule_response,
1486 MAE_ACTION_RULE_RESPONSE_ASL_ID,
1487 (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1488 MAE_ACTION_RULE_RESPONSE_AS_ID,
1489 (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1490 MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1492 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1495 * Mask-value pairs have been stored in the byte order needed for the
1496 * MCDI request and are thus safe to be copied directly to the buffer.
1498 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1499 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1500 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1501 memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1502 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1504 efx_mcdi_execute(enp, &req);
1506 if (req.emr_rc != 0) {
1511 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1516 ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1517 if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1522 ar_idp->id = ar_id.id;
1535 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1539 __checkReturn efx_rc_t
1540 efx_mae_action_rule_remove(
1541 __in efx_nic_t *enp,
1542 __in const efx_mae_rule_id_t *ar_idp)
1544 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1546 EFX_MCDI_DECLARE_BUF(payload,
1547 MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1548 MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1551 if (encp->enc_mae_supported == B_FALSE) {
1556 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1557 req.emr_in_buf = payload;
1558 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1559 req.emr_out_buf = payload;
1560 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1562 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1564 efx_mcdi_execute(enp, &req);
1566 if (req.emr_rc != 0) {
1571 if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1573 /* Firmware failed to delete the action rule. */
1585 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1589 #endif /* EFSYS_OPT_MAE */