drivers/common/sfc_efx/base/efx_mae.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2021 Xilinx, Inc.
   4  */
   5
   6 #include "efx.h"
   7 #include "efx_impl.h"
   8
   9
  10 #if EFSYS_OPT_MAE
  11
  12 static  __checkReturn                   efx_rc_t
  13 efx_mae_get_capabilities(
  14         __in                            efx_nic_t *enp)
  15 {
  16         efx_mcdi_req_t req;
  17         EFX_MCDI_DECLARE_BUF(payload,
  18             MC_CMD_MAE_GET_CAPS_IN_LEN,
  19             MC_CMD_MAE_GET_CAPS_OUT_LEN);
  20         struct efx_mae_s *maep = enp->en_maep;
  21         efx_rc_t rc;
  22
  23         req.emr_cmd = MC_CMD_MAE_GET_CAPS;
  24         req.emr_in_buf = payload;
  25         req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
  26         req.emr_out_buf = payload;
  27         req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
  28
  29         efx_mcdi_execute(enp, &req);
  30
  31         if (req.emr_rc != 0) {
  32                 rc = req.emr_rc;
  33                 goto fail1;
  34         }
  35
  36         if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
  37                 rc = EMSGSIZE;
  38                 goto fail2;
  39         }
  40
  41         maep->em_max_n_outer_prios =
  42             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
  43
  44         maep->em_max_n_action_prios =
  45             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
  46
  47         maep->em_encap_types_supported = 0;
  48
  49         if (MCDI_OUT_DWORD_FIELD(req, MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED,
  50             MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) != 0) {
  51                 maep->em_encap_types_supported |=
  52                     (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
  53         }
  54
  55         if (MCDI_OUT_DWORD_FIELD(req, MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED,
  56             MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) != 0) {
  57                 maep->em_encap_types_supported |=
  58                     (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
  59         }
  60
  61         if (MCDI_OUT_DWORD_FIELD(req, MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED,
  62             MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) != 0) {
  63                 maep->em_encap_types_supported |=
  64                     (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
  65         }
  66
  67         maep->em_max_nfields =
  68             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
  69
  70         maep->em_max_ncounters =
  71             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_COUNTERS);
  72
  73         return (0);
  74
  75 fail2:
  76         EFSYS_PROBE(fail2);
  77 fail1:
  78         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  79         return (rc);
  80 }
  81
  82 static  __checkReturn                   efx_rc_t
  83 efx_mae_get_outer_rule_caps(
  84         __in                            efx_nic_t *enp,
  85         __in                            unsigned int field_ncaps,
  86         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
  87 {
  88         efx_mcdi_req_t req;
  89         EFX_MCDI_DECLARE_BUF(payload,
  90             MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
  91             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
  92         unsigned int mcdi_field_ncaps;
  93         unsigned int i;
  94         efx_rc_t rc;
  95
  96         if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
  97             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
  98                 rc = EINVAL;
  99                 goto fail1;
 100         }
 101
 102         req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
 103         req.emr_in_buf = payload;
 104         req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
 105         req.emr_out_buf = payload;
 106         req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
 107
 108         efx_mcdi_execute(enp, &req);
 109
 110         if (req.emr_rc != 0) {
 111                 rc = req.emr_rc;
 112                 goto fail2;
 113         }
 114
 115         if (req.emr_out_length_used < MC_CMD_MAE_GET_OR_CAPS_OUT_LENMIN) {
 116                 rc = EMSGSIZE;
 117                 goto fail3;
 118         }
 119
 120         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 121
 122         if (req.emr_out_length_used <
 123             MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 124                 rc = EMSGSIZE;
 125                 goto fail4;
 126         }
 127
 128         if (mcdi_field_ncaps > field_ncaps) {
 129                 rc = EMSGSIZE;
 130                 goto fail5;
 131         }
 132
 133         for (i = 0; i < mcdi_field_ncaps; ++i) {
 134                 uint32_t match_flag;
 135                 uint32_t mask_flag;
 136
 137                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 138                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 139                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 140
 141                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 142                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 143                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 144
 145                 field_caps[i].emfc_match_affects_class =
 146                     (match_flag != 0) ? B_TRUE : B_FALSE;
 147
 148                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 149                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 150                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 151
 152                 field_caps[i].emfc_mask_affects_class =
 153                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 154         }
 155
 156         return (0);
 157
 158 fail5:
 159         EFSYS_PROBE(fail5);
 160 fail4:
 161         EFSYS_PROBE(fail4);
 162 fail3:
 163         EFSYS_PROBE(fail3);
 164 fail2:
 165         EFSYS_PROBE(fail2);
 166 fail1:
 167         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 168         return (rc);
 169 }
 170
 171 static  __checkReturn                   efx_rc_t
 172 efx_mae_get_action_rule_caps(
 173         __in                            efx_nic_t *enp,
 174         __in                            unsigned int field_ncaps,
 175         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
 176 {
 177         efx_mcdi_req_t req;
 178         EFX_MCDI_DECLARE_BUF(payload,
 179             MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
 180             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
 181         unsigned int mcdi_field_ncaps;
 182         unsigned int i;
 183         efx_rc_t rc;
 184
 185         if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
 186             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
 187                 rc = EINVAL;
 188                 goto fail1;
 189         }
 190
 191         req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
 192         req.emr_in_buf = payload;
 193         req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
 194         req.emr_out_buf = payload;
 195         req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
 196
 197         efx_mcdi_execute(enp, &req);
 198
 199         if (req.emr_rc != 0) {
 200                 rc = req.emr_rc;
 201                 goto fail2;
 202         }
 203
 204         if (req.emr_out_length_used < MC_CMD_MAE_GET_AR_CAPS_OUT_LENMIN) {
 205                 rc = EMSGSIZE;
 206                 goto fail3;
 207         }
 208
 209         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_AR_CAPS_OUT_COUNT);
 210
 211         if (req.emr_out_length_used <
 212             MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 213                 rc = EMSGSIZE;
 214                 goto fail4;
 215         }
 216
 217         if (mcdi_field_ncaps > field_ncaps) {
 218                 rc = EMSGSIZE;
 219                 goto fail5;
 220         }
 221
 222         for (i = 0; i < mcdi_field_ncaps; ++i) {
 223                 uint32_t match_flag;
 224                 uint32_t mask_flag;
 225
 226                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 227                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 228                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 229
 230                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 231                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 232                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 233
 234                 field_caps[i].emfc_match_affects_class =
 235                     (match_flag != 0) ? B_TRUE : B_FALSE;
 236
 237                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 238                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 239                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 240
 241                 field_caps[i].emfc_mask_affects_class =
 242                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 243         }
 244
 245         return (0);
 246
 247 fail5:
 248         EFSYS_PROBE(fail5);
 249 fail4:
 250         EFSYS_PROBE(fail4);
 251 fail3:
 252         EFSYS_PROBE(fail3);
 253 fail2:
 254         EFSYS_PROBE(fail2);
 255 fail1:
 256         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 257         return (rc);
 258 }
 259
 260         __checkReturn                   efx_rc_t
 261 efx_mae_init(
 262         __in                            efx_nic_t *enp)
 263 {
 264         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 265         efx_mae_field_cap_t *or_fcaps;
 266         size_t or_fcaps_size;
 267         efx_mae_field_cap_t *ar_fcaps;
 268         size_t ar_fcaps_size;
 269         efx_mae_t *maep;
 270         efx_rc_t rc;
 271
 272         if (encp->enc_mae_supported == B_FALSE) {
 273                 rc = ENOTSUP;
 274                 goto fail1;
 275         }
 276
 277         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
 278         if (maep == NULL) {
 279                 rc = ENOMEM;
 280                 goto fail2;
 281         }
 282
 283         enp->en_maep = maep;
 284
 285         rc = efx_mae_get_capabilities(enp);
 286         if (rc != 0)
 287                 goto fail3;
 288
 289         or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
 290         EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
 291         if (or_fcaps == NULL) {
 292                 rc = ENOMEM;
 293                 goto fail4;
 294         }
 295
 296         maep->em_outer_rule_field_caps_size = or_fcaps_size;
 297         maep->em_outer_rule_field_caps = or_fcaps;
 298
 299         rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
 300         if (rc != 0)
 301                 goto fail5;
 302
 303         ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
 304         EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
 305         if (ar_fcaps == NULL) {
 306                 rc = ENOMEM;
 307                 goto fail6;
 308         }
 309
 310         maep->em_action_rule_field_caps_size = ar_fcaps_size;
 311         maep->em_action_rule_field_caps = ar_fcaps;
 312
 313         rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
 314         if (rc != 0)
 315                 goto fail7;
 316
 317         return (0);
 318
 319 fail7:
 320         EFSYS_PROBE(fail5);
 321         EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
 322 fail6:
 323         EFSYS_PROBE(fail4);
 324 fail5:
 325         EFSYS_PROBE(fail5);
 326         EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
 327 fail4:
 328         EFSYS_PROBE(fail4);
 329 fail3:
 330         EFSYS_PROBE(fail3);
 331         EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
 332         enp->en_maep = NULL;
 333 fail2:
 334         EFSYS_PROBE(fail2);
 335 fail1:
 336         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 337         return (rc);
 338 }
 339
 340                                         void
 341 efx_mae_fini(
 342         __in                            efx_nic_t *enp)
 343 {
 344         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 345         efx_mae_t *maep = enp->en_maep;
 346
 347         if (encp->enc_mae_supported == B_FALSE)
 348                 return;
 349
 350         EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
 351             maep->em_action_rule_field_caps);
 352         EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
 353             maep->em_outer_rule_field_caps);
 354         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
 355         enp->en_maep = NULL;
 356 }
 357
 358         __checkReturn                   efx_rc_t
 359 efx_mae_get_limits(
 360         __in                            efx_nic_t *enp,
 361         __out                           efx_mae_limits_t *emlp)
 362 {
 363         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 364         struct efx_mae_s *maep = enp->en_maep;
 365         efx_rc_t rc;
 366
 367         if (encp->enc_mae_supported == B_FALSE) {
 368                 rc = ENOTSUP;
 369                 goto fail1;
 370         }
 371
 372         emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
 373         emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
 374         emlp->eml_encap_types_supported = maep->em_encap_types_supported;
 375         emlp->eml_encap_header_size_limit =
 376             MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MAXNUM_MCDI2;
 377         emlp->eml_max_n_counters = maep->em_max_ncounters;
 378
 379         return (0);
 380
 381 fail1:
 382         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 383         return (rc);
 384 }
 385
 386         __checkReturn                   efx_rc_t
 387 efx_mae_match_spec_init(
 388         __in                            efx_nic_t *enp,
 389         __in                            efx_mae_rule_type_t type,
 390         __in                            uint32_t prio,
 391         __out                           efx_mae_match_spec_t **specp)
 392 {
 393         efx_mae_match_spec_t *spec;
 394         efx_rc_t rc;
 395
 396         switch (type) {
 397         case EFX_MAE_RULE_OUTER:
 398                 break;
 399         case EFX_MAE_RULE_ACTION:
 400                 break;
 401         default:
 402                 rc = ENOTSUP;
 403                 goto fail1;
 404         }
 405
 406         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 407         if (spec == NULL) {
 408                 rc = ENOMEM;
 409                 goto fail2;
 410         }
 411
 412         spec->emms_type = type;
 413         spec->emms_prio = prio;
 414
 415         *specp = spec;
 416
 417         return (0);
 418
 419 fail2:
 420         EFSYS_PROBE(fail2);
 421 fail1:
 422         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 423         return (rc);
 424 }
 425
 426                                         void
 427 efx_mae_match_spec_fini(
 428         __in                            efx_nic_t *enp,
 429         __in                            efx_mae_match_spec_t *spec)
 430 {
 431         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 432 }
 433
 434 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
 435 typedef enum efx_mae_field_cap_id_e {
 436         EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
 437         EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
 438         EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
 439         EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
 440         EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
 441         EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
 442         EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
 443         EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
 444         EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
 445         EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
 446         EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
 447         EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
 448         EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
 449         EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
 450         EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
 451         EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
 452         EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
 453         EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
 454         EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
 455         EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
 456         EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
 457         EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
 458         EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
 459         EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
 460         EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
 461         EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
 462         EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
 463         EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
 464         EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
 465         EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
 466         EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
 467         EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
 468         EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
 469         EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 470         EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
 471         EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
 472         EFX_MAE_FIELD_ID_HAS_OVLAN = MAE_FIELD_HAS_OVLAN,
 473         EFX_MAE_FIELD_ID_HAS_IVLAN = MAE_FIELD_HAS_IVLAN,
 474         EFX_MAE_FIELD_ID_ENC_HAS_OVLAN = MAE_FIELD_ENC_HAS_OVLAN,
 475         EFX_MAE_FIELD_ID_ENC_HAS_IVLAN = MAE_FIELD_ENC_HAS_IVLAN,
 476
 477         EFX_MAE_FIELD_CAP_NIDS
 478 } efx_mae_field_cap_id_t;
 479
 480 typedef enum efx_mae_field_endianness_e {
 481         EFX_MAE_FIELD_LE = 0,
 482         EFX_MAE_FIELD_BE,
 483
 484         EFX_MAE_FIELD_ENDIANNESS_NTYPES
 485 } efx_mae_field_endianness_t;
 486
 487 /*
 488  * The following structure is a means to describe an MAE field.
 489  * The information in it is meant to be used internally by
 490  * APIs for addressing a given field in a mask-value pairs
 491  * structure and for validation purposes.
 492  *
 493  * A field may have an alternative one. This structure
 494  * has additional members to reference the alternative
 495  * field's mask. See efx_mae_match_spec_is_valid().
 496  */
 497 typedef struct efx_mae_mv_desc_s {
 498         efx_mae_field_cap_id_t          emmd_field_cap_id;
 499
 500         size_t                          emmd_value_size;
 501         size_t                          emmd_value_offset;
 502         size_t                          emmd_mask_size;
 503         size_t                          emmd_mask_offset;
 504
 505         /*
 506          * Having the alternative field's mask size set to 0
 507          * means that there's no alternative field specified.
 508          */
 509         size_t                          emmd_alt_mask_size;
 510         size_t                          emmd_alt_mask_offset;
 511
 512         /* Primary field and the alternative one are of the same endianness. */
 513         efx_mae_field_endianness_t      emmd_endianness;
 514 } efx_mae_mv_desc_t;
 515
 516 /* Indices to this array are provided by efx_mae_field_id_t */
 517 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 518 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 519         [EFX_MAE_FIELD_##_name] =                                       \
 520         {                                                               \
 521                 EFX_MAE_FIELD_ID_##_name,                               \
 522                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,               \
 523                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,              \
 524                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,          \
 525                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,         \
 526                 0, 0 /* no alternative field */,                        \
 527                 _endianness                                             \
 528         }
 529
 530         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 531         EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 532         EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 533         EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 534         EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 535         EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 536         EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 537         EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 538         EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
 539         EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
 540         EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
 541         EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
 542         EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
 543         EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
 544         EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
 545         EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
 546         EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
 547         EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 548         EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
 549         EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
 550
 551 #undef EFX_MAE_MV_DESC
 552 };
 553
 554 /* Indices to this array are provided by efx_mae_field_id_t */
 555 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 556 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 557         [EFX_MAE_FIELD_##_name] =                                       \
 558         {                                                               \
 559                 EFX_MAE_FIELD_ID_##_name,                               \
 560                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 561                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 562                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 563                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 564                 0, 0 /* no alternative field */,                        \
 565                 _endianness                                             \
 566         }
 567
 568 /* Same as EFX_MAE_MV_DESC(), but also indicates an alternative field. */
 569 #define EFX_MAE_MV_DESC_ALT(_name, _alt_name, _endianness)              \
 570         [EFX_MAE_FIELD_##_name] =                                       \
 571         {                                                               \
 572                 EFX_MAE_FIELD_ID_##_name,                               \
 573                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 574                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 575                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 576                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 577                 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_LEN,             \
 578                 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_OFST,            \
 579                 _endianness                                             \
 580         }
 581
 582         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 583         EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 584         EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 585         EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 586         EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 587         EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 588         EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 589         EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 590         EFX_MAE_MV_DESC_ALT(ENC_SRC_IP4_BE, ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
 591         EFX_MAE_MV_DESC_ALT(ENC_DST_IP4_BE, ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 592         EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 593         EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 594         EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
 595         EFX_MAE_MV_DESC_ALT(ENC_SRC_IP6_BE, ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
 596         EFX_MAE_MV_DESC_ALT(ENC_DST_IP6_BE, ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 597         EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 598         EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 599
 600 #undef EFX_MAE_MV_DESC_ALT
 601 #undef EFX_MAE_MV_DESC
 602 };
 603
 604 /*
 605  * The following structure is a means to describe an MAE bit.
 606  * The information in it is meant to be used internally by
 607  * APIs for addressing a given flag in a mask-value pairs
 608  * structure and for validation purposes.
 609  */
 610 typedef struct efx_mae_mv_bit_desc_s {
 611         /*
 612          * Arrays using this struct are indexed by field IDs.
 613          * Fields which aren't meant to be referenced by these
 614          * arrays comprise gaps (invalid entries). Below field
 615          * helps to identify such entries.
 616          */
 617         boolean_t                       emmbd_entry_is_valid;
 618         efx_mae_field_cap_id_t          emmbd_bit_cap_id;
 619         size_t                          emmbd_value_ofst;
 620         unsigned int                    emmbd_value_lbn;
 621         size_t                          emmbd_mask_ofst;
 622         unsigned int                    emmbd_mask_lbn;
 623 } efx_mae_mv_bit_desc_t;
 624
 625 static const efx_mae_mv_bit_desc_t __efx_mae_outer_rule_mv_bit_desc_set[] = {
 626 #define EFX_MAE_MV_BIT_DESC(_name)                                      \
 627         [EFX_MAE_FIELD_##_name] =                                       \
 628         {                                                               \
 629                 B_TRUE,                                                 \
 630                 EFX_MAE_FIELD_ID_##_name,                               \
 631                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 632                 MAE_ENC_FIELD_PAIRS_##_name##_LBN,                      \
 633                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 634                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LBN,                 \
 635         }
 636
 637         EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
 638         EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
 639
 640 #undef EFX_MAE_MV_BIT_DESC
 641 };
 642
 643 static const efx_mae_mv_bit_desc_t __efx_mae_action_rule_mv_bit_desc_set[] = {
 644 #define EFX_MAE_MV_BIT_DESC(_name)                                      \
 645         [EFX_MAE_FIELD_##_name] =                                       \
 646         {                                                               \
 647                 B_TRUE,                                                 \
 648                 EFX_MAE_FIELD_ID_##_name,                               \
 649                 MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_OFST,               \
 650                 MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN,            \
 651                 MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_OFST,          \
 652                 MAE_FIELD_MASK_VALUE_PAIRS_V2_##_name##_LBN,            \
 653         }
 654
 655         EFX_MAE_MV_BIT_DESC(HAS_OVLAN),
 656         EFX_MAE_MV_BIT_DESC(HAS_IVLAN),
 657         EFX_MAE_MV_BIT_DESC(ENC_HAS_OVLAN),
 658         EFX_MAE_MV_BIT_DESC(ENC_HAS_IVLAN),
 659
 660 #undef EFX_MAE_MV_BIT_DESC
 661 };
 662
 663         __checkReturn                   efx_rc_t
 664 efx_mae_mport_invalid(
 665         __out                           efx_mport_sel_t *mportp)
 666 {
 667         efx_dword_t dword;
 668         efx_rc_t rc;
 669
 670         if (mportp == NULL) {
 671                 rc = EINVAL;
 672                 goto fail1;
 673         }
 674
 675         EFX_POPULATE_DWORD_1(dword,
 676             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_INVALID);
 677
 678         memset(mportp, 0, sizeof (*mportp));
 679         mportp->sel = dword.ed_u32[0];
 680
 681         return (0);
 682
 683 fail1:
 684         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 685         return (rc);
 686 }
 687
 688         __checkReturn                   efx_rc_t
 689 efx_mae_mport_by_phy_port(
 690         __in                            uint32_t phy_port,
 691         __out                           efx_mport_sel_t *mportp)
 692 {
 693         efx_dword_t dword;
 694         efx_rc_t rc;
 695
 696         if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
 697                 rc = EINVAL;
 698                 goto fail1;
 699         }
 700
 701         EFX_POPULATE_DWORD_2(dword,
 702             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
 703             MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 704
 705         memset(mportp, 0, sizeof (*mportp));
 706         /*
 707          * The constructed DWORD is little-endian,
 708          * but the resulting value is meant to be
 709          * passed to MCDIs, where it will undergo
 710          * host-order to little endian conversion.
 711          */
 712         mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 713
 714         return (0);
 715
 716 fail1:
 717         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 718         return (rc);
 719 }
 720
 721         __checkReturn                   efx_rc_t
 722 efx_mae_mport_by_pcie_function(
 723         __in                            uint32_t pf,
 724         __in                            uint32_t vf,
 725         __out                           efx_mport_sel_t *mportp)
 726 {
 727         efx_dword_t dword;
 728         efx_rc_t rc;
 729
 730         EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
 731             MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
 732
 733         if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
 734                 rc = EINVAL;
 735                 goto fail1;
 736         }
 737
 738         if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
 739                 rc = EINVAL;
 740                 goto fail2;
 741         }
 742
 743         EFX_POPULATE_DWORD_3(dword,
 744             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
 745             MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
 746             MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 747
 748         memset(mportp, 0, sizeof (*mportp));
 749         /*
 750          * The constructed DWORD is little-endian,
 751          * but the resulting value is meant to be
 752          * passed to MCDIs, where it will undergo
 753          * host-order to little endian conversion.
 754          */
 755         mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 756
 757         return (0);
 758
 759 fail2:
 760         EFSYS_PROBE(fail2);
 761 fail1:
 762         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 763         return (rc);
 764 }
 765
 766 static  __checkReturn                   efx_rc_t
 767 efx_mcdi_mae_mport_lookup(
 768         __in                            efx_nic_t *enp,
 769         __in                            const efx_mport_sel_t *mport_selectorp,
 770         __out                           efx_mport_id_t *mport_idp)
 771 {
 772         efx_mcdi_req_t req;
 773         EFX_MCDI_DECLARE_BUF(payload,
 774             MC_CMD_MAE_MPORT_LOOKUP_IN_LEN,
 775             MC_CMD_MAE_MPORT_LOOKUP_OUT_LEN);
 776         efx_rc_t rc;
 777
 778         req.emr_cmd = MC_CMD_MAE_MPORT_LOOKUP;
 779         req.emr_in_buf = payload;
 780         req.emr_in_length = MC_CMD_MAE_MPORT_LOOKUP_IN_LEN;
 781         req.emr_out_buf = payload;
 782         req.emr_out_length = MC_CMD_MAE_MPORT_LOOKUP_OUT_LEN;
 783
 784         MCDI_IN_SET_DWORD(req, MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR,
 785             mport_selectorp->sel);
 786
 787         efx_mcdi_execute(enp, &req);
 788
 789         if (req.emr_rc != 0) {
 790                 rc = req.emr_rc;
 791                 goto fail1;
 792         }
 793
 794         mport_idp->id = MCDI_OUT_DWORD(req, MAE_MPORT_LOOKUP_OUT_MPORT_ID);
 795
 796         return (0);
 797
 798 fail1:
 799         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 800         return (rc);
 801 }
 802
 803         __checkReturn                   efx_rc_t
 804 efx_mae_mport_id_by_selector(
 805         __in                            efx_nic_t *enp,
 806         __in                            const efx_mport_sel_t *mport_selectorp,
 807         __out                           efx_mport_id_t *mport_idp)
 808 {
 809         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 810         efx_rc_t rc;
 811
 812         if (encp->enc_mae_supported == B_FALSE) {
 813                 rc = ENOTSUP;
 814                 goto fail1;
 815         }
 816
 817         rc = efx_mcdi_mae_mport_lookup(enp, mport_selectorp, mport_idp);
 818         if (rc != 0)
 819                 goto fail2;
 820
 821         return (0);
 822
 823 fail2:
 824         EFSYS_PROBE(fail2);
 825 fail1:
 826         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 827         return (rc);
 828 }
 829
 830         __checkReturn                   efx_rc_t
 831 efx_mae_match_spec_field_set(
 832         __in                            efx_mae_match_spec_t *spec,
 833         __in                            efx_mae_field_id_t field_id,
 834         __in                            size_t value_size,
 835         __in_bcount(value_size)         const uint8_t *value,
 836         __in                            size_t mask_size,
 837         __in_bcount(mask_size)          const uint8_t *mask)
 838 {
 839         const efx_mae_mv_desc_t *descp;
 840         unsigned int desc_set_nentries;
 841         uint8_t *mvp;
 842         efx_rc_t rc;
 843
 844         switch (spec->emms_type) {
 845         case EFX_MAE_RULE_OUTER:
 846                 desc_set_nentries =
 847                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
 848                 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
 849                 mvp = spec->emms_mask_value_pairs.outer;
 850                 break;
 851         case EFX_MAE_RULE_ACTION:
 852                 desc_set_nentries =
 853                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 854                 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
 855                 mvp = spec->emms_mask_value_pairs.action;
 856                 break;
 857         default:
 858                 rc = ENOTSUP;
 859                 goto fail1;
 860         }
 861
 862         if ((unsigned int)field_id >= desc_set_nentries) {
 863                 rc = EINVAL;
 864                 goto fail2;
 865         }
 866
 867         if (descp->emmd_mask_size == 0) {
 868                 /* The ID points to a gap in the array of field descriptors. */
 869                 rc = EINVAL;
 870                 goto fail3;
 871         }
 872
 873         if (value_size != descp->emmd_value_size) {
 874                 rc = EINVAL;
 875                 goto fail4;
 876         }
 877
 878         if (mask_size != descp->emmd_mask_size) {
 879                 rc = EINVAL;
 880                 goto fail5;
 881         }
 882
 883         if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
 884                 unsigned int i;
 885
 886                 /*
 887                  * The mask/value are in network (big endian) order.
 888                  * The MCDI request field is also big endian.
 889                  */
 890
 891                 EFSYS_ASSERT3U(value_size, ==, mask_size);
 892
 893                 for (i = 0; i < value_size; ++i) {
 894                         uint8_t *v_bytep = mvp + descp->emmd_value_offset + i;
 895                         uint8_t *m_bytep = mvp + descp->emmd_mask_offset + i;
 896
 897                         /*
 898                          * Apply the mask (which may be all-zeros) to the value.
 899                          *
 900                          * If this API is provided with some value to set for a
 901                          * given field in one specification and with some other
 902                          * value to set for this field in another specification,
 903                          * then, if the two masks are all-zeros, the field will
 904                          * avoid being counted as a mismatch when comparing the
 905                          * specifications using efx_mae_match_specs_equal() API.
 906                          */
 907                         *v_bytep = value[i] & mask[i];
 908                         *m_bytep = mask[i];
 909                 }
 910         } else {
 911                 efx_dword_t dword;
 912
 913                 /*
 914                  * The mask/value are in host byte order.
 915                  * The MCDI request field is little endian.
 916                  */
 917                 switch (value_size) {
 918                 case 4:
 919                         EFX_POPULATE_DWORD_1(dword,
 920                             EFX_DWORD_0, *(const uint32_t *)value);
 921
 922                         memcpy(mvp + descp->emmd_value_offset,
 923                             &dword, sizeof (dword));
 924                         break;
 925                 default:
 926                         EFSYS_ASSERT(B_FALSE);
 927                 }
 928
 929                 switch (mask_size) {
 930                 case 4:
 931                         EFX_POPULATE_DWORD_1(dword,
 932                             EFX_DWORD_0, *(const uint32_t *)mask);
 933
 934                         memcpy(mvp + descp->emmd_mask_offset,
 935                             &dword, sizeof (dword));
 936                         break;
 937                 default:
 938                         EFSYS_ASSERT(B_FALSE);
 939                 }
 940         }
 941
 942         return (0);
 943
 944 fail5:
 945         EFSYS_PROBE(fail5);
 946 fail4:
 947         EFSYS_PROBE(fail4);
 948 fail3:
 949         EFSYS_PROBE(fail3);
 950 fail2:
 951         EFSYS_PROBE(fail2);
 952 fail1:
 953         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 954         return (rc);
 955 }
 956
 957         __checkReturn                   efx_rc_t
 958 efx_mae_match_spec_bit_set(
 959         __in                            efx_mae_match_spec_t *spec,
 960         __in                            efx_mae_field_id_t field_id,
 961         __in                            boolean_t value)
 962 {
 963         const efx_mae_mv_bit_desc_t *bit_descp;
 964         unsigned int bit_desc_set_nentries;
 965         unsigned int byte_idx;
 966         unsigned int bit_idx;
 967         uint8_t *mvp;
 968         efx_rc_t rc;
 969
 970         switch (spec->emms_type) {
 971         case EFX_MAE_RULE_OUTER:
 972                 bit_desc_set_nentries =
 973                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
 974                 bit_descp = &__efx_mae_outer_rule_mv_bit_desc_set[field_id];
 975                 mvp = spec->emms_mask_value_pairs.outer;
 976                 break;
 977         case EFX_MAE_RULE_ACTION:
 978                 bit_desc_set_nentries =
 979                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
 980                 bit_descp = &__efx_mae_action_rule_mv_bit_desc_set[field_id];
 981                 mvp = spec->emms_mask_value_pairs.action;
 982                 break;
 983         default:
 984                 rc = ENOTSUP;
 985                 goto fail1;
 986         }
 987
 988         if ((unsigned int)field_id >= bit_desc_set_nentries) {
 989                 rc = EINVAL;
 990                 goto fail2;
 991         }
 992
 993         if (bit_descp->emmbd_entry_is_valid == B_FALSE) {
 994                 rc = EINVAL;
 995                 goto fail3;
 996         }
 997
 998         byte_idx = bit_descp->emmbd_value_ofst + bit_descp->emmbd_value_lbn / 8;
 999         bit_idx = bit_descp->emmbd_value_lbn % 8;
1000
1001         if (value != B_FALSE)
1002                 mvp[byte_idx] |= (1U << bit_idx);
1003         else
1004                 mvp[byte_idx] &= ~(1U << bit_idx);
1005
1006         byte_idx = bit_descp->emmbd_mask_ofst + bit_descp->emmbd_mask_lbn / 8;
1007         bit_idx = bit_descp->emmbd_mask_lbn % 8;
1008         mvp[byte_idx] |= (1U << bit_idx);
1009
1010         return (0);
1011
1012 fail3:
1013         EFSYS_PROBE(fail3);
1014 fail2:
1015         EFSYS_PROBE(fail2);
1016 fail1:
1017         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1018         return (rc);
1019 }
1020
1021         __checkReturn                   efx_rc_t
1022 efx_mae_match_spec_mport_set(
1023         __in                            efx_mae_match_spec_t *spec,
1024         __in                            const efx_mport_sel_t *valuep,
1025         __in_opt                        const efx_mport_sel_t *maskp)
1026 {
1027         uint32_t full_mask = UINT32_MAX;
1028         const uint8_t *vp;
1029         const uint8_t *mp;
1030         efx_rc_t rc;
1031
1032         if (valuep == NULL) {
1033                 rc = EINVAL;
1034                 goto fail1;
1035         }
1036
1037         vp = (const uint8_t *)&valuep->sel;
1038         if (maskp != NULL)
1039                 mp = (const uint8_t *)&maskp->sel;
1040         else
1041                 mp = (const uint8_t *)&full_mask;
1042
1043         rc = efx_mae_match_spec_field_set(spec,
1044             EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
1045             sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
1046         if (rc != 0)
1047                 goto fail2;
1048
1049         return (0);
1050
1051 fail2:
1052         EFSYS_PROBE(fail2);
1053 fail1:
1054         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1055         return (rc);
1056 }
1057
1058         __checkReturn                   boolean_t
1059 efx_mae_match_specs_equal(
1060         __in                            const efx_mae_match_spec_t *left,
1061         __in                            const efx_mae_match_spec_t *right)
1062 {
1063         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1064 }
1065
1066 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)              \
1067             ((_mask)[(_bit) / (_mask_page_nbits)] &                     \
1068                     (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
1069
1070 static                                  boolean_t
1071 efx_mask_is_prefix(
1072         __in                            size_t mask_nbytes,
1073         __in_bcount(mask_nbytes)        const uint8_t *maskp)
1074 {
1075         boolean_t prev_bit_is_set = B_TRUE;
1076         unsigned int i;
1077
1078         for (i = 0; i < 8 * mask_nbytes; ++i) {
1079                 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
1080
1081                 if (!prev_bit_is_set && bit_is_set)
1082                         return B_FALSE;
1083
1084                 prev_bit_is_set = bit_is_set;
1085         }
1086
1087         return B_TRUE;
1088 }
1089
1090 static                                  boolean_t
1091 efx_mask_is_all_ones(
1092         __in                            size_t mask_nbytes,
1093         __in_bcount(mask_nbytes)        const uint8_t *maskp)
1094 {
1095         unsigned int i;
1096         uint8_t t = ~0;
1097
1098         for (i = 0; i < mask_nbytes; ++i)
1099                 t &= maskp[i];
1100
1101         return (t == (uint8_t)(~0));
1102 }
1103
1104 static                                  boolean_t
1105 efx_mask_is_all_zeros(
1106         __in                            size_t mask_nbytes,
1107         __in_bcount(mask_nbytes)        const uint8_t *maskp)
1108 {
1109         unsigned int i;
1110         uint8_t t = 0;
1111
1112         for (i = 0; i < mask_nbytes; ++i)
1113                 t |= maskp[i];
1114
1115         return (t == 0);
1116 }
1117
1118         __checkReturn                   boolean_t
1119 efx_mae_match_spec_is_valid(
1120         __in                            efx_nic_t *enp,
1121         __in                            const efx_mae_match_spec_t *spec)
1122 {
1123         efx_mae_t *maep = enp->en_maep;
1124         unsigned int field_ncaps = maep->em_max_nfields;
1125         const efx_mae_field_cap_t *field_caps;
1126         const efx_mae_mv_desc_t *desc_setp;
1127         unsigned int desc_set_nentries;
1128         const efx_mae_mv_bit_desc_t *bit_desc_setp;
1129         unsigned int bit_desc_set_nentries;
1130         boolean_t is_valid = B_TRUE;
1131         efx_mae_field_id_t field_id;
1132         const uint8_t *mvp;
1133
1134         switch (spec->emms_type) {
1135         case EFX_MAE_RULE_OUTER:
1136                 field_caps = maep->em_outer_rule_field_caps;
1137                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1138                 desc_set_nentries =
1139                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1140                 bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
1141                 bit_desc_set_nentries =
1142                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
1143                 mvp = spec->emms_mask_value_pairs.outer;
1144                 break;
1145         case EFX_MAE_RULE_ACTION:
1146                 field_caps = maep->em_action_rule_field_caps;
1147                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1148                 desc_set_nentries =
1149                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1150                 bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
1151                 bit_desc_set_nentries =
1152                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
1153                 mvp = spec->emms_mask_value_pairs.action;
1154                 break;
1155         default:
1156                 return (B_FALSE);
1157         }
1158
1159         if (field_caps == NULL)
1160                 return (B_FALSE);
1161
1162         for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
1163              ++field_id) {
1164                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1165                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1166                 const uint8_t *alt_m_buf = mvp + descp->emmd_alt_mask_offset;
1167                 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
1168                 size_t alt_m_size = descp->emmd_alt_mask_size;
1169                 size_t m_size = descp->emmd_mask_size;
1170
1171                 if (m_size == 0)
1172                         continue; /* Skip array gap */
1173
1174                 if ((unsigned int)field_cap_id >= field_ncaps) {
1175                         /*
1176                          * The FW has not reported capability status for
1177                          * this field. Make sure that its mask is zeroed.
1178                          */
1179                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
1180                         if (is_valid != B_FALSE)
1181                                 continue;
1182                         else
1183                                 break;
1184                 }
1185
1186                 switch (field_caps[field_cap_id].emfc_support) {
1187                 case MAE_FIELD_SUPPORTED_MATCH_MASK:
1188                         is_valid = B_TRUE;
1189                         break;
1190                 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
1191                         is_valid = efx_mask_is_prefix(m_size, m_buf);
1192                         break;
1193                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
1194                         is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
1195                             efx_mask_is_all_zeros(m_size, m_buf));
1196                         break;
1197                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
1198                         is_valid = efx_mask_is_all_ones(m_size, m_buf);
1199
1200                         if ((is_valid == B_FALSE) && (alt_m_size != 0)) {
1201                                 /*
1202                                  * This field has an alternative one. The FW
1203                                  * reports ALWAYS for both implying that one
1204                                  * of them is required to have all-ones mask.
1205                                  *
1206                                  * The primary field's mask is incorrect; go
1207                                  * on to check that of the alternative field.
1208                                  */
1209                                 is_valid = efx_mask_is_all_ones(alt_m_size,
1210                                                                 alt_m_buf);
1211                         }
1212                         break;
1213                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
1214                 case MAE_FIELD_UNSUPPORTED:
1215                 default:
1216                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
1217                         break;
1218                 }
1219
1220                 if (is_valid == B_FALSE)
1221                         return (B_FALSE);
1222         }
1223
1224         for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
1225              ++field_id) {
1226                 const efx_mae_mv_bit_desc_t *bit_descp =
1227                     &bit_desc_setp[field_id];
1228                 unsigned int byte_idx =
1229                     bit_descp->emmbd_mask_ofst +
1230                     bit_descp->emmbd_mask_lbn / 8;
1231                 unsigned int bit_idx =
1232                     bit_descp->emmbd_mask_lbn % 8;
1233                 efx_mae_field_cap_id_t bit_cap_id =
1234                     bit_descp->emmbd_bit_cap_id;
1235
1236                 if (bit_descp->emmbd_entry_is_valid == B_FALSE)
1237                         continue; /* Skip array gap */
1238
1239                 if ((unsigned int)bit_cap_id >= field_ncaps) {
1240                         /* No capability for this bit = unsupported. */
1241                         is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
1242                         if (is_valid == B_FALSE)
1243                                 break;
1244                         else
1245                                 continue;
1246                 }
1247
1248                 switch (field_caps[bit_cap_id].emfc_support) {
1249                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
1250                         is_valid = B_TRUE;
1251                         break;
1252                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
1253                         is_valid = ((mvp[byte_idx] & (1U << bit_idx)) != 0);
1254                         break;
1255                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
1256                 case MAE_FIELD_UNSUPPORTED:
1257                 default:
1258                         is_valid = ((mvp[byte_idx] & (1U << bit_idx)) == 0);
1259                         break;
1260                 }
1261
1262                 if (is_valid == B_FALSE)
1263                         break;
1264         }
1265
1266         return (is_valid);
1267 }
1268
1269         __checkReturn                   efx_rc_t
1270 efx_mae_action_set_spec_init(
1271         __in                            efx_nic_t *enp,
1272         __out                           efx_mae_actions_t **specp)
1273 {
1274         efx_mae_actions_t *spec;
1275         efx_rc_t rc;
1276
1277         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
1278         if (spec == NULL) {
1279                 rc = ENOMEM;
1280                 goto fail1;
1281         }
1282
1283         spec->ema_rsrc.emar_eh_id.id = EFX_MAE_RSRC_ID_INVALID;
1284         spec->ema_rsrc.emar_counter_id.id = EFX_MAE_RSRC_ID_INVALID;
1285
1286         *specp = spec;
1287
1288         return (0);
1289
1290 fail1:
1291         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1292         return (rc);
1293 }
1294
1295                                         void
1296 efx_mae_action_set_spec_fini(
1297         __in                            efx_nic_t *enp,
1298         __in                            efx_mae_actions_t *spec)
1299 {
1300         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
1301 }
1302
1303 static  __checkReturn                   efx_rc_t
1304 efx_mae_action_set_add_decap(
1305         __in                            efx_mae_actions_t *spec,
1306         __in                            size_t arg_size,
1307         __in_bcount(arg_size)           const uint8_t *arg)
1308 {
1309         efx_rc_t rc;
1310
1311         _NOTE(ARGUNUSED(spec))
1312
1313         if (arg_size != 0) {
1314                 rc = EINVAL;
1315                 goto fail1;
1316         }
1317
1318         if (arg != NULL) {
1319                 rc = EINVAL;
1320                 goto fail2;
1321         }
1322
1323         /* This action does not have any arguments, so do nothing here. */
1324
1325         return (0);
1326
1327 fail2:
1328         EFSYS_PROBE(fail2);
1329 fail1:
1330         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1331         return (rc);
1332 }
1333
1334 static  __checkReturn                   efx_rc_t
1335 efx_mae_action_set_add_vlan_pop(
1336         __in                            efx_mae_actions_t *spec,
1337         __in                            size_t arg_size,
1338         __in_bcount(arg_size)           const uint8_t *arg)
1339 {
1340         efx_rc_t rc;
1341
1342         if (arg_size != 0) {
1343                 rc = EINVAL;
1344                 goto fail1;
1345         }
1346
1347         if (arg != NULL) {
1348                 rc = EINVAL;
1349                 goto fail2;
1350         }
1351
1352         if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
1353                 rc = ENOTSUP;
1354                 goto fail3;
1355         }
1356
1357         ++spec->ema_n_vlan_tags_to_pop;
1358
1359         return (0);
1360
1361 fail3:
1362         EFSYS_PROBE(fail3);
1363 fail2:
1364         EFSYS_PROBE(fail2);
1365 fail1:
1366         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1367         return (rc);
1368 }
1369
1370 static  __checkReturn                   efx_rc_t
1371 efx_mae_action_set_add_vlan_push(
1372         __in                            efx_mae_actions_t *spec,
1373         __in                            size_t arg_size,
1374         __in_bcount(arg_size)           const uint8_t *arg)
1375 {
1376         unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
1377         efx_rc_t rc;
1378
1379         if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
1380                 rc = EINVAL;
1381                 goto fail1;
1382         }
1383
1384         if (arg == NULL) {
1385                 rc = EINVAL;
1386                 goto fail2;
1387         }
1388
1389         if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1390                 rc = ENOTSUP;
1391                 goto fail3;
1392         }
1393
1394         memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
1395         ++(spec->ema_n_vlan_tags_to_push);
1396
1397         return (0);
1398
1399 fail3:
1400         EFSYS_PROBE(fail3);
1401 fail2:
1402         EFSYS_PROBE(fail2);
1403 fail1:
1404         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1405         return (rc);
1406 }
1407
1408 static  __checkReturn                   efx_rc_t
1409 efx_mae_action_set_add_encap(
1410         __in                            efx_mae_actions_t *spec,
1411         __in                            size_t arg_size,
1412         __in_bcount(arg_size)           const uint8_t *arg)
1413 {
1414         efx_rc_t rc;
1415
1416         /*
1417          * Adding this specific action to an action set spec and setting encap.
1418          * header ID in the spec are two individual steps. This design allows
1419          * the client driver to avoid encap. header allocation when it simply
1420          * needs to check the order of actions submitted by user ("validate"),
1421          * without actually allocating an action set and inserting a rule.
1422          *
1423          * For now, mark encap. header ID as invalid; the caller will invoke
1424          * efx_mae_action_set_fill_in_eh_id() to override the field prior
1425          * to action set allocation; otherwise, the allocation will fail.
1426          */
1427         spec->ema_rsrc.emar_eh_id.id = EFX_MAE_RSRC_ID_INVALID;
1428
1429         /*
1430          * As explained above, there are no arguments to handle here.
1431          * efx_mae_action_set_fill_in_eh_id() will take care of them.
1432          */
1433         if (arg_size != 0) {
1434                 rc = EINVAL;
1435                 goto fail1;
1436         }
1437
1438         if (arg != NULL) {
1439                 rc = EINVAL;
1440                 goto fail2;
1441         }
1442
1443         return (0);
1444
1445 fail2:
1446         EFSYS_PROBE(fail2);
1447 fail1:
1448         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1449         return (rc);
1450 }
1451
1452 static  __checkReturn                   efx_rc_t
1453 efx_mae_action_set_add_count(
1454         __in                            efx_mae_actions_t *spec,
1455         __in                            size_t arg_size,
1456         __in_bcount(arg_size)           const uint8_t *arg)
1457 {
1458         efx_rc_t rc;
1459
1460         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1461                           MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NULL);
1462
1463         /*
1464          * Preparing an action set spec to update a counter requires
1465          * two steps: first add this action to the action spec, and then
1466          * add the counter ID to the spec. This allows validity checking
1467          * and resource allocation to be done separately.
1468          * Mark the counter ID as invalid in the spec to ensure that the
1469          * caller must also invoke efx_mae_action_set_fill_in_counter_id()
1470          * before action set allocation.
1471          */
1472         spec->ema_rsrc.emar_counter_id.id = EFX_MAE_RSRC_ID_INVALID;
1473
1474         /* Nothing else is supposed to take place over here. */
1475         if (arg_size != 0) {
1476                 rc = EINVAL;
1477                 goto fail1;
1478         }
1479
1480         if (arg != NULL) {
1481                 rc = EINVAL;
1482                 goto fail2;
1483         }
1484
1485         ++(spec->ema_n_count_actions);
1486
1487         return (0);
1488
1489 fail2:
1490         EFSYS_PROBE(fail2);
1491 fail1:
1492         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1493         return (rc);
1494 }
1495
1496 static  __checkReturn                   efx_rc_t
1497 efx_mae_action_set_add_flag(
1498         __in                            efx_mae_actions_t *spec,
1499         __in                            size_t arg_size,
1500         __in_bcount(arg_size)           const uint8_t *arg)
1501 {
1502         efx_rc_t rc;
1503
1504         _NOTE(ARGUNUSED(spec))
1505
1506         if (arg_size != 0) {
1507                 rc = EINVAL;
1508                 goto fail1;
1509         }
1510
1511         if (arg != NULL) {
1512                 rc = EINVAL;
1513                 goto fail2;
1514         }
1515
1516         /* This action does not have any arguments, so do nothing here. */
1517
1518         return (0);
1519
1520 fail2:
1521         EFSYS_PROBE(fail2);
1522 fail1:
1523         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1524         return (rc);
1525 }
1526
1527 static  __checkReturn                   efx_rc_t
1528 efx_mae_action_set_add_mark(
1529         __in                            efx_mae_actions_t *spec,
1530         __in                            size_t arg_size,
1531         __in_bcount(arg_size)           const uint8_t *arg)
1532 {
1533         efx_rc_t rc;
1534
1535         if (arg_size != sizeof (spec->ema_mark_value)) {
1536                 rc = EINVAL;
1537                 goto fail1;
1538         }
1539
1540         if (arg == NULL) {
1541                 rc = EINVAL;
1542                 goto fail2;
1543         }
1544
1545         memcpy(&spec->ema_mark_value, arg, arg_size);
1546
1547         return (0);
1548
1549 fail2:
1550         EFSYS_PROBE(fail2);
1551 fail1:
1552         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1553         return (rc);
1554 }
1555
1556 static  __checkReturn                   efx_rc_t
1557 efx_mae_action_set_add_deliver(
1558         __in                            efx_mae_actions_t *spec,
1559         __in                            size_t arg_size,
1560         __in_bcount(arg_size)           const uint8_t *arg)
1561 {
1562         efx_rc_t rc;
1563
1564         if (arg_size != sizeof (spec->ema_deliver_mport)) {
1565                 rc = EINVAL;
1566                 goto fail1;
1567         }
1568
1569         if (arg == NULL) {
1570                 rc = EINVAL;
1571                 goto fail2;
1572         }
1573
1574         memcpy(&spec->ema_deliver_mport, arg, arg_size);
1575
1576         return (0);
1577
1578 fail2:
1579         EFSYS_PROBE(fail2);
1580 fail1:
1581         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1582         return (rc);
1583 }
1584
1585 typedef struct efx_mae_action_desc_s {
1586         /* Action specific handler */
1587         efx_rc_t        (*emad_add)(efx_mae_actions_t *,
1588                                     size_t, const uint8_t *);
1589 } efx_mae_action_desc_t;
1590
1591 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
1592         [EFX_MAE_ACTION_DECAP] = {
1593                 .emad_add = efx_mae_action_set_add_decap
1594         },
1595         [EFX_MAE_ACTION_VLAN_POP] = {
1596                 .emad_add = efx_mae_action_set_add_vlan_pop
1597         },
1598         [EFX_MAE_ACTION_VLAN_PUSH] = {
1599                 .emad_add = efx_mae_action_set_add_vlan_push
1600         },
1601         [EFX_MAE_ACTION_ENCAP] = {
1602                 .emad_add = efx_mae_action_set_add_encap
1603         },
1604         [EFX_MAE_ACTION_COUNT] = {
1605                 .emad_add = efx_mae_action_set_add_count
1606         },
1607         [EFX_MAE_ACTION_FLAG] = {
1608                 .emad_add = efx_mae_action_set_add_flag
1609         },
1610         [EFX_MAE_ACTION_MARK] = {
1611                 .emad_add = efx_mae_action_set_add_mark
1612         },
1613         [EFX_MAE_ACTION_DELIVER] = {
1614                 .emad_add = efx_mae_action_set_add_deliver
1615         }
1616 };
1617
1618 static const uint32_t efx_mae_action_ordered_map =
1619         (1U << EFX_MAE_ACTION_DECAP) |
1620         (1U << EFX_MAE_ACTION_VLAN_POP) |
1621         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1622         /*
1623          * HW will conduct action COUNT after
1624          * the matching packet has been modified by
1625          * length-affecting actions except for ENCAP.
1626          */
1627         (1U << EFX_MAE_ACTION_COUNT) |
1628         (1U << EFX_MAE_ACTION_ENCAP) |
1629         (1U << EFX_MAE_ACTION_FLAG) |
1630         (1U << EFX_MAE_ACTION_MARK) |
1631         (1U << EFX_MAE_ACTION_DELIVER);
1632
1633 /*
1634  * These actions must not be added after DELIVER, but
1635  * they can have any place among the rest of
1636  * strictly ordered actions.
1637  */
1638 static const uint32_t efx_mae_action_nonstrict_map =
1639         (1U << EFX_MAE_ACTION_COUNT) |
1640         (1U << EFX_MAE_ACTION_FLAG) |
1641         (1U << EFX_MAE_ACTION_MARK);
1642
1643 static const uint32_t efx_mae_action_repeat_map =
1644         (1U << EFX_MAE_ACTION_VLAN_POP) |
1645         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1646         (1U << EFX_MAE_ACTION_COUNT);
1647
1648 /*
1649  * Add an action to an action set.
1650  *
1651  * This has to be invoked in the desired action order.
1652  * An out-of-order action request will be turned down.
1653  */
1654 static  __checkReturn                   efx_rc_t
1655 efx_mae_action_set_spec_populate(
1656         __in                            efx_mae_actions_t *spec,
1657         __in                            efx_mae_action_t type,
1658         __in                            size_t arg_size,
1659         __in_bcount(arg_size)           const uint8_t *arg)
1660 {
1661         uint32_t action_mask;
1662         efx_rc_t rc;
1663
1664         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1665             (sizeof (efx_mae_action_ordered_map) * 8));
1666         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1667             (sizeof (efx_mae_action_repeat_map) * 8));
1668
1669         EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1670         EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1671         EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1672
1673         if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1674                 rc = EINVAL;
1675                 goto fail1;
1676         }
1677
1678         action_mask = (1U << type);
1679
1680         if ((spec->ema_actions & action_mask) != 0) {
1681                 /* The action set already contains this action. */
1682                 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1683                         /* Cannot add another non-repeatable action. */
1684                         rc = ENOTSUP;
1685                         goto fail2;
1686                 }
1687         }
1688
1689         if ((efx_mae_action_ordered_map & action_mask) != 0) {
1690                 uint32_t strict_ordered_map =
1691                     efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1692                 uint32_t later_actions_mask =
1693                     strict_ordered_map & ~(action_mask | (action_mask - 1));
1694
1695                 if ((spec->ema_actions & later_actions_mask) != 0) {
1696                         /* Cannot add an action after later ordered actions. */
1697                         rc = ENOTSUP;
1698                         goto fail3;
1699                 }
1700         }
1701
1702         if (efx_mae_actions[type].emad_add != NULL) {
1703                 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1704                 if (rc != 0)
1705                         goto fail4;
1706         }
1707
1708         spec->ema_actions |= action_mask;
1709
1710         return (0);
1711
1712 fail4:
1713         EFSYS_PROBE(fail4);
1714 fail3:
1715         EFSYS_PROBE(fail3);
1716 fail2:
1717         EFSYS_PROBE(fail2);
1718 fail1:
1719         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1720         return (rc);
1721 }
1722
1723         __checkReturn                   efx_rc_t
1724 efx_mae_action_set_populate_decap(
1725         __in                            efx_mae_actions_t *spec)
1726 {
1727         return (efx_mae_action_set_spec_populate(spec,
1728             EFX_MAE_ACTION_DECAP, 0, NULL));
1729 }
1730
1731         __checkReturn                   efx_rc_t
1732 efx_mae_action_set_populate_vlan_pop(
1733         __in                            efx_mae_actions_t *spec)
1734 {
1735         return (efx_mae_action_set_spec_populate(spec,
1736             EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1737 }
1738
1739         __checkReturn                   efx_rc_t
1740 efx_mae_action_set_populate_vlan_push(
1741         __in                            efx_mae_actions_t *spec,
1742         __in                            uint16_t tpid_be,
1743         __in                            uint16_t tci_be)
1744 {
1745         efx_mae_action_vlan_push_t action;
1746         const uint8_t *arg = (const uint8_t *)&action;
1747
1748         action.emavp_tpid_be = tpid_be;
1749         action.emavp_tci_be = tci_be;
1750
1751         return (efx_mae_action_set_spec_populate(spec,
1752             EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1753 }
1754
1755         __checkReturn                   efx_rc_t
1756 efx_mae_action_set_populate_encap(
1757         __in                            efx_mae_actions_t *spec)
1758 {
1759         /*
1760          * There is no argument to pass encap. header ID, thus, one does not
1761          * need to allocate an encap. header while parsing application input.
1762          * This is useful since building an action set may be done simply to
1763          * validate a rule, whilst resource allocation usually consumes time.
1764          */
1765         return (efx_mae_action_set_spec_populate(spec,
1766             EFX_MAE_ACTION_ENCAP, 0, NULL));
1767 }
1768
1769         __checkReturn                   efx_rc_t
1770 efx_mae_action_set_populate_count(
1771         __in                            efx_mae_actions_t *spec)
1772 {
1773         /*
1774          * There is no argument to pass counter ID, thus, one does not
1775          * need to allocate a counter while parsing application input.
1776          * This is useful since building an action set may be done simply to
1777          * validate a rule, whilst resource allocation usually consumes time.
1778          */
1779         return (efx_mae_action_set_spec_populate(spec,
1780             EFX_MAE_ACTION_COUNT, 0, NULL));
1781 }
1782
1783         __checkReturn                   efx_rc_t
1784 efx_mae_action_set_populate_flag(
1785         __in                            efx_mae_actions_t *spec)
1786 {
1787         return (efx_mae_action_set_spec_populate(spec,
1788             EFX_MAE_ACTION_FLAG, 0, NULL));
1789 }
1790
1791         __checkReturn                   efx_rc_t
1792 efx_mae_action_set_populate_mark(
1793         __in                            efx_mae_actions_t *spec,
1794         __in                            uint32_t mark_value)
1795 {
1796         const uint8_t *arg = (const uint8_t *)&mark_value;
1797
1798         return (efx_mae_action_set_spec_populate(spec,
1799             EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1800 }
1801
1802         __checkReturn                   efx_rc_t
1803 efx_mae_action_set_populate_deliver(
1804         __in                            efx_mae_actions_t *spec,
1805         __in                            const efx_mport_sel_t *mportp)
1806 {
1807         const uint8_t *arg;
1808         efx_rc_t rc;
1809
1810         if (mportp == NULL) {
1811                 rc = EINVAL;
1812                 goto fail1;
1813         }
1814
1815         arg = (const uint8_t *)&mportp->sel;
1816
1817         return (efx_mae_action_set_spec_populate(spec,
1818             EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1819
1820 fail1:
1821         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1822         return (rc);
1823 }
1824
1825         __checkReturn                   efx_rc_t
1826 efx_mae_action_set_populate_drop(
1827         __in                            efx_mae_actions_t *spec)
1828 {
1829         efx_mport_sel_t mport;
1830         const uint8_t *arg;
1831         efx_dword_t dword;
1832
1833         EFX_POPULATE_DWORD_1(dword,
1834             MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1835
1836         /*
1837          * The constructed DWORD is little-endian,
1838          * but the resulting value is meant to be
1839          * passed to MCDIs, where it will undergo
1840          * host-order to little endian conversion.
1841          */
1842         mport.sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
1843
1844         arg = (const uint8_t *)&mport.sel;
1845
1846         return (efx_mae_action_set_spec_populate(spec,
1847             EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1848 }
1849
1850         __checkReturn                   boolean_t
1851 efx_mae_action_set_specs_equal(
1852         __in                            const efx_mae_actions_t *left,
1853         __in                            const efx_mae_actions_t *right)
1854 {
1855         size_t cmp_size = EFX_FIELD_OFFSET(efx_mae_actions_t, ema_rsrc);
1856
1857         /*
1858          * An action set specification consists of two parts. The first part
1859          * indicates what actions are included in the action set, as well as
1860          * extra quantitative values (in example, the number of VLAN tags to
1861          * push). The second part comprises resource IDs used by the actions.
1862          *
1863          * A resource, in example, a counter, is allocated from the hardware
1864          * by the client, and it's the client who is responsible for keeping
1865          * track of allocated resources and comparing resource IDs if needed.
1866          *
1867          * In this API, don't compare resource IDs in the two specifications.
1868          */
1869
1870         return ((memcmp(left, right, cmp_size) == 0) ? B_TRUE : B_FALSE);
1871 }
1872
1873         __checkReturn                   efx_rc_t
1874 efx_mae_match_specs_class_cmp(
1875         __in                            efx_nic_t *enp,
1876         __in                            const efx_mae_match_spec_t *left,
1877         __in                            const efx_mae_match_spec_t *right,
1878         __out                           boolean_t *have_same_classp)
1879 {
1880         efx_mae_t *maep = enp->en_maep;
1881         unsigned int field_ncaps = maep->em_max_nfields;
1882         const efx_mae_field_cap_t *field_caps;
1883         const efx_mae_mv_desc_t *desc_setp;
1884         unsigned int desc_set_nentries;
1885         const efx_mae_mv_bit_desc_t *bit_desc_setp;
1886         unsigned int bit_desc_set_nentries;
1887         boolean_t have_same_class = B_TRUE;
1888         efx_mae_field_id_t field_id;
1889         const uint8_t *mvpl;
1890         const uint8_t *mvpr;
1891         efx_rc_t rc;
1892
1893         switch (left->emms_type) {
1894         case EFX_MAE_RULE_OUTER:
1895                 field_caps = maep->em_outer_rule_field_caps;
1896                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1897                 desc_set_nentries =
1898                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1899                 bit_desc_setp = __efx_mae_outer_rule_mv_bit_desc_set;
1900                 bit_desc_set_nentries =
1901                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_bit_desc_set);
1902                 mvpl = left->emms_mask_value_pairs.outer;
1903                 mvpr = right->emms_mask_value_pairs.outer;
1904                 break;
1905         case EFX_MAE_RULE_ACTION:
1906                 field_caps = maep->em_action_rule_field_caps;
1907                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1908                 desc_set_nentries =
1909                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1910                 bit_desc_setp = __efx_mae_action_rule_mv_bit_desc_set;
1911                 bit_desc_set_nentries =
1912                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_bit_desc_set);
1913                 mvpl = left->emms_mask_value_pairs.action;
1914                 mvpr = right->emms_mask_value_pairs.action;
1915                 break;
1916         default:
1917                 rc = ENOTSUP;
1918                 goto fail1;
1919         }
1920
1921         if (field_caps == NULL) {
1922                 rc = EAGAIN;
1923                 goto fail2;
1924         }
1925
1926         if (left->emms_type != right->emms_type ||
1927             left->emms_prio != right->emms_prio) {
1928                 /*
1929                  * Rules of different types can never map to the same class.
1930                  *
1931                  * The FW can support some set of match criteria for one
1932                  * priority and not support the very same set for
1933                  * another priority. Thus, two rules which have
1934                  * different priorities can never map to
1935                  * the same class.
1936                  */
1937                 *have_same_classp = B_FALSE;
1938                 return (0);
1939         }
1940
1941         for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
1942              ++field_id) {
1943                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1944                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1945                 const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1946                 const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1947                 size_t mask_size = descp->emmd_mask_size;
1948                 const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1949                 const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1950                 size_t value_size = descp->emmd_value_size;
1951
1952                 if (mask_size == 0)
1953                         continue; /* Skip array gap */
1954
1955                 if ((unsigned int)field_cap_id >= field_ncaps) {
1956                         /*
1957                          * The FW has not reported capability status for this
1958                          * field. It's unknown whether any difference between
1959                          * the two masks / values affects the class. The only
1960                          * case when the class must be the same is when these
1961                          * mask-value pairs match. Otherwise, report mismatch.
1962                          */
1963                         if ((memcmp(lmaskp, rmaskp, mask_size) == 0) &&
1964                             (memcmp(lvalp, rvalp, value_size) == 0))
1965                                 continue;
1966                         else
1967                                 break;
1968                 }
1969
1970                 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1971                         if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1972                                 have_same_class = B_FALSE;
1973                                 break;
1974                         }
1975                 }
1976
1977                 if (field_caps[field_cap_id].emfc_match_affects_class) {
1978                         if (memcmp(lvalp, rvalp, value_size) != 0) {
1979                                 have_same_class = B_FALSE;
1980                                 break;
1981                         }
1982                 }
1983         }
1984
1985         if (have_same_class == B_FALSE)
1986                 goto done;
1987
1988         for (field_id = 0; (unsigned int)field_id < bit_desc_set_nentries;
1989              ++field_id) {
1990                 const efx_mae_mv_bit_desc_t *bit_descp =
1991                     &bit_desc_setp[field_id];
1992                 efx_mae_field_cap_id_t bit_cap_id =
1993                     bit_descp->emmbd_bit_cap_id;
1994                 unsigned int byte_idx;
1995                 unsigned int bit_idx;
1996
1997                 if (bit_descp->emmbd_entry_is_valid == B_FALSE)
1998                         continue; /* Skip array gap */
1999
2000                 if ((unsigned int)bit_cap_id >= field_ncaps)
2001                         break;
2002
2003                 byte_idx =
2004                     bit_descp->emmbd_mask_ofst +
2005                     bit_descp->emmbd_mask_lbn / 8;
2006                 bit_idx =
2007                     bit_descp->emmbd_mask_lbn % 8;
2008
2009                 if (field_caps[bit_cap_id].emfc_mask_affects_class &&
2010                     (mvpl[byte_idx] & (1U << bit_idx)) !=
2011                     (mvpr[byte_idx] & (1U << bit_idx))) {
2012                         have_same_class = B_FALSE;
2013                         break;
2014                 }
2015
2016                 byte_idx =
2017                     bit_descp->emmbd_value_ofst +
2018                     bit_descp->emmbd_value_lbn / 8;
2019                 bit_idx =
2020                     bit_descp->emmbd_value_lbn % 8;
2021
2022                 if (field_caps[bit_cap_id].emfc_match_affects_class &&
2023                     (mvpl[byte_idx] & (1U << bit_idx)) !=
2024                     (mvpr[byte_idx] & (1U << bit_idx))) {
2025                         have_same_class = B_FALSE;
2026                         break;
2027                 }
2028         }
2029
2030 done:
2031         *have_same_classp = have_same_class;
2032
2033         return (0);
2034
2035 fail2:
2036         EFSYS_PROBE(fail2);
2037 fail1:
2038         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2039         return (rc);
2040 }
2041
2042         __checkReturn           efx_rc_t
2043 efx_mae_outer_rule_insert(
2044         __in                    efx_nic_t *enp,
2045         __in                    const efx_mae_match_spec_t *spec,
2046         __in                    efx_tunnel_protocol_t encap_type,
2047         __out                   efx_mae_rule_id_t *or_idp)
2048 {
2049         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
2050         efx_mcdi_req_t req;
2051         EFX_MCDI_DECLARE_BUF(payload,
2052             MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
2053             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
2054         uint32_t encap_type_mcdi;
2055         efx_mae_rule_id_t or_id;
2056         size_t offset;
2057         efx_rc_t rc;
2058
2059         EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
2060             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
2061
2062         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
2063             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
2064
2065         if (encp->enc_mae_supported == B_FALSE) {
2066                 rc = ENOTSUP;
2067                 goto fail1;
2068         }
2069
2070         if (spec->emms_type != EFX_MAE_RULE_OUTER) {
2071                 rc = EINVAL;
2072                 goto fail2;
2073         }
2074
2075         switch (encap_type) {
2076         case EFX_TUNNEL_PROTOCOL_NONE:
2077                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
2078                 break;
2079         case EFX_TUNNEL_PROTOCOL_VXLAN:
2080                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
2081                 break;
2082         case EFX_TUNNEL_PROTOCOL_GENEVE:
2083                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
2084                 break;
2085         case EFX_TUNNEL_PROTOCOL_NVGRE:
2086                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
2087                 break;
2088         default:
2089                 rc = ENOTSUP;
2090                 goto fail3;
2091         }
2092
2093         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
2094         req.emr_in_buf = payload;
2095         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
2096         req.emr_out_buf = payload;
2097         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
2098
2099         MCDI_IN_SET_DWORD(req,
2100             MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
2101
2102         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
2103
2104         /*
2105          * Mask-value pairs have been stored in the byte order needed for the
2106          * MCDI request and are thus safe to be copied directly to the buffer.
2107          * The library cares about byte order in efx_mae_match_spec_field_set().
2108          */
2109         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
2110             MAE_ENC_FIELD_PAIRS_LEN);
2111         offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
2112         memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
2113             MAE_ENC_FIELD_PAIRS_LEN);
2114
2115         efx_mcdi_execute(enp, &req);
2116
2117         if (req.emr_rc != 0) {
2118                 rc = req.emr_rc;
2119                 goto fail4;
2120         }
2121
2122         if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
2123                 rc = EMSGSIZE;
2124                 goto fail5;
2125         }
2126
2127         or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
2128         if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
2129                 rc = ENOENT;
2130                 goto fail6;
2131         }
2132
2133         or_idp->id = or_id.id;
2134
2135         return (0);
2136
2137 fail6:
2138         EFSYS_PROBE(fail6);
2139 fail5:
2140         EFSYS_PROBE(fail5);
2141 fail4:
2142         EFSYS_PROBE(fail4);
2143 fail3:
2144         EFSYS_PROBE(fail3);
2145 fail2:
2146         EFSYS_PROBE(fail2);
2147 fail1:
2148         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2149         return (rc);
2150 }
2151
2152         __checkReturn           efx_rc_t
2153 efx_mae_outer_rule_remove(
2154         __in                    efx_nic_t *enp,
2155         __in                    const efx_mae_rule_id_t *or_idp)
2156 {
2157         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
2158         efx_mcdi_req_t req;
2159         EFX_MCDI_DECLARE_BUF(payload,
2160             MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
2161             MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
2162         efx_rc_t rc;
2163
2164         if (encp->enc_mae_supported == B_FALSE) {
2165                 rc = ENOTSUP;
2166                 goto fail1;
2167         }
2168
2169         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
2170         req.emr_in_buf = payload;
2171         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
2172         req.emr_out_buf = payload;
2173         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
2174
2175         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
2176
2177         efx_mcdi_execute(enp, &req);
2178
2179         if (req.emr_rc != 0) {
2180                 rc = req.emr_rc;
2181                 goto fail2;
2182         }
2183
2184         if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMIN) {
2185                 rc = EMSGSIZE;
2186                 goto fail3;
2187         }
2188
2189         if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
2190             or_idp->id) {
2191                 /* Firmware failed to remove the outer rule. */
2192                 rc = EAGAIN;
2193                 goto fail4;
2194         }
2195
2196         return (0);
2197
2198 fail4:
2199         EFSYS_PROBE(fail4);
2200 fail3:
2201         EFSYS_PROBE(fail3);
2202 fail2:
2203         EFSYS_PROBE(fail2);
2204 fail1:
2205         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2206         return (rc);
2207 }
2208
2209         __checkReturn                   efx_rc_t
2210 efx_mae_match_spec_outer_rule_id_set(
2211         __in                            efx_mae_match_spec_t *spec,
2212         __in                            const efx_mae_rule_id_t *or_idp)
2213 {
2214         uint32_t full_mask = UINT32_MAX;
2215         efx_rc_t rc;
2216
2217         if (spec->emms_type != EFX_MAE_RULE_ACTION) {
2218                 rc = EINVAL;
2219                 goto fail1;
2220         }
2221
2222         if (or_idp == NULL) {
2223                 rc = EINVAL;
2224                 goto fail2;
2225         }
2226
2227         rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
2228             sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
2229             sizeof (full_mask), (const uint8_t *)&full_mask);
2230         if (rc != 0)
2231                 goto fail3;
2232
2233         return (0);
2234
2235 fail3:
2236         EFSYS_PROBE(fail3);
2237 fail2:
2238         EFSYS_PROBE(fail2);
2239 fail1:
2240         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2241         return (rc);
2242 }
2243
2244          __checkReturn                  efx_rc_t
2245 efx_mae_encap_header_alloc(
2246         __in                            efx_nic_t *enp,
2247         __in                            efx_tunnel_protocol_t encap_type,
2248         __in_bcount(header_size)        uint8_t *header_data,
2249         __in                            size_t header_size,
2250         __out                           efx_mae_eh_id_t *eh_idp)
2251 {
2252         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
2253         efx_mcdi_req_t req;
2254         EFX_MCDI_DECLARE_BUF(payload,
2255             MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMAX_MCDI2,
2256             MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN);
2257         uint32_t encap_type_mcdi;
2258         efx_mae_eh_id_t eh_id;
2259         efx_rc_t rc;
2260
2261         EFX_STATIC_ASSERT(sizeof (eh_idp->id) ==
2262             MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_LEN);
2263
2264         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
2265             MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_NULL);
2266
2267         if (encp->enc_mae_supported == B_FALSE) {
2268                 rc = ENOTSUP;
2269                 goto fail1;
2270         }
2271
2272         switch (encap_type) {
2273         case EFX_TUNNEL_PROTOCOL_NONE:
2274                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
2275                 break;
2276         case EFX_TUNNEL_PROTOCOL_VXLAN:
2277                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
2278                 break;
2279         case EFX_TUNNEL_PROTOCOL_GENEVE:
2280                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
2281                 break;
2282         case EFX_TUNNEL_PROTOCOL_NVGRE:
2283                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
2284                 break;
2285         default:
2286                 rc = ENOTSUP;
2287                 goto fail2;
2288         }
2289
2290         if (header_size >
2291             MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MAXNUM_MCDI2) {
2292                 rc = EINVAL;
2293                 goto fail3;
2294         }
2295
2296         req.emr_cmd = MC_CMD_MAE_ENCAP_HEADER_ALLOC;
2297         req.emr_in_buf = payload;
2298         req.emr_in_length = MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LEN(header_size);
2299         req.emr_out_buf = payload;
2300         req.emr_out_length = MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN;
2301
2302         MCDI_IN_SET_DWORD(req,
2303             MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE, encap_type_mcdi);
2304
2305         memcpy(payload + MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_OFST,
2306             header_data, header_size);
2307
2308         efx_mcdi_execute(enp, &req);
2309
2310         if (req.emr_rc != 0) {
2311                 rc = req.emr_rc;
2312                 goto fail4;
2313         }
2314
2315         if (req.emr_out_length_used < MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN) {
2316                 rc = EMSGSIZE;
2317                 goto fail5;
2318         }
2319
2320         eh_id.id = MCDI_OUT_DWORD(req,
2321             MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID);
2322
2323         if (eh_id.id == EFX_MAE_RSRC_ID_INVALID) {
2324                 rc = ENOENT;
2325                 goto fail6;
2326         }
2327
2328         eh_idp->id = eh_id.id;
2329
2330         return (0);
2331
2332 fail6:
2333         EFSYS_PROBE(fail6);
2334 fail5:
2335         EFSYS_PROBE(fail5);
2336 fail4:
2337         EFSYS_PROBE(fail4);
2338 fail3:
2339         EFSYS_PROBE(fail3);
2340 fail2:
2341         EFSYS_PROBE(fail2);
2342 fail1:
2343         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2344         return (rc);
2345 }
2346
2347         __checkReturn                   efx_rc_t
2348 efx_mae_encap_header_free(
2349         __in                            efx_nic_t *enp,
2350         __in                            const efx_mae_eh_id_t *eh_idp)
2351 {
2352         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
2353         efx_mcdi_req_t req;
2354         EFX_MCDI_DECLARE_BUF(payload,
2355             MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(1),
2356             MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(1));
2357         efx_rc_t rc;
2358
2359         if (encp->enc_mae_supported == B_FALSE) {
2360                 rc = ENOTSUP;
2361                 goto fail1;
2362         }
2363
2364         req.emr_cmd = MC_CMD_MAE_ENCAP_HEADER_FREE;
2365         req.emr_in_buf = payload;
2366         req.emr_in_length = MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(1);
2367         req.emr_out_buf = payload;
2368         req.emr_out_length = MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(1);
2369
2370         MCDI_IN_SET_DWORD(req, MAE_ENCAP_HEADER_FREE_IN_EH_ID, eh_idp->id);
2371
2372         efx_mcdi_execute(enp, &req);
2373
2374         if (req.emr_rc != 0) {
2375                 rc = req.emr_rc;
2376                 goto fail2;
2377         }
2378
2379         if (MCDI_OUT_DWORD(req, MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID) !=
2380             eh_idp->id) {
2381                 /* Firmware failed to remove the encap. header. */
2382                 rc = EAGAIN;
2383                 goto fail3;
2384         }
2385
2386         return (0);
2387
2388 fail3:
2389         EFSYS_PROBE(fail3);
2390 fail2:
2391         EFSYS_PROBE(fail2);
2392 fail1:
2393         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2394         return (rc);
2395 }
2396
2397         __checkReturn                   efx_rc_t
2398 efx_mae_action_set_fill_in_eh_id(
2399         __in                            efx_mae_actions_t *spec,
2400         __in                            const efx_mae_eh_id_t *eh_idp)
2401 {
2402         efx_rc_t rc;
2403
2404         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_ENCAP)) == 0) {
2405                 /*
2406                  * The caller has not intended to have action ENCAP originally,
2407                  * hence, this attempt to indicate encap. header ID is invalid.
2408                  */
2409                 rc = EINVAL;
2410                 goto fail1;
2411         }
2412
2413         if (spec->ema_rsrc.emar_eh_id.id != EFX_MAE_RSRC_ID_INVALID) {
2414                 /* The caller attempts to indicate encap. header ID twice. */
2415                 rc = EINVAL;
2416                 goto fail2;
2417         }
2418
2419         if (eh_idp->id == EFX_MAE_RSRC_ID_INVALID) {
2420                 rc = EINVAL;
2421                 goto fail3;
2422         }
2423
2424         spec->ema_rsrc.emar_eh_id.id = eh_idp->id;
2425
2426         return (0);
2427
2428 fail3:
2429         EFSYS_PROBE(fail3);
2430 fail2:
2431         EFSYS_PROBE(fail2);
2432 fail1:
2433         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2434         return (rc);
2435 }
2436
2437         __checkReturn                   efx_rc_t
2438 efx_mae_action_set_alloc(
2439         __in                            efx_nic_t *enp,
2440         __in                            const efx_mae_actions_t *spec,
2441         __out                           efx_mae_aset_id_t *aset_idp)
2442 {
2443         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
2444         efx_mcdi_req_t req;
2445         EFX_MCDI_DECLARE_BUF(payload,
2446             MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
2447             MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
2448         efx_mae_aset_id_t aset_id;
2449         efx_rc_t rc;
2450
2451         if (encp->enc_mae_supported == B_FALSE) {
2452                 rc = ENOTSUP;
2453                 goto fail1;
2454         }
2455
2456         req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
2457         req.emr_in_buf = payload;
2458         req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
2459         req.emr_out_buf = payload;
2460         req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
2461
2462         /*
2463          * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
2464          * corresponding resource types are supported by the implementation.
2465          * Use proper resource ID assignments instead.
2466          */
2467         MCDI_IN_SET_DWORD(req,
2468             MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
2469
2470         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_DECAP)) != 0) {
2471                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
2472                     MAE_ACTION_SET_ALLOC_IN_DECAP, 1);
2473         }
2474
2475         MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
2476             MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
2477
2478         if (spec->ema_n_vlan_tags_to_push > 0) {
2479                 unsigned int outer_tag_idx;
2480
2481                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
2482                     MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
2483                     spec->ema_n_vlan_tags_to_push);
2484
2485                 if (spec->ema_n_vlan_tags_to_push ==
2486                     EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
2487                         MCDI_IN_SET_WORD(req,
2488                             MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
2489                             spec->ema_vlan_push_descs[0].emavp_tpid_be);
2490                         MCDI_IN_SET_WORD(req,
2491                             MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
2492                             spec->ema_vlan_push_descs[0].emavp_tci_be);
2493                 }
2494
2495                 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
2496
2497                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
2498                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
2499                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
2500                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
2501         }
2502
2503         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID,
2504             spec->ema_rsrc.emar_eh_id.id);
2505         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_COUNTER_ID,
2506             spec->ema_rsrc.emar_counter_id.id);
2507
2508         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
2509                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
2510                     MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
2511         }
2512
2513         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
2514                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
2515                     MAE_ACTION_SET_ALLOC_IN_MARK, 1);
2516
2517                 MCDI_IN_SET_DWORD(req,
2518                     MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
2519         }
2520
2521         MCDI_IN_SET_DWORD(req,
2522             MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
2523
2524         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
2525             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
2526         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
2527             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
2528
2529         efx_mcdi_execute(enp, &req);
2530
2531         if (req.emr_rc != 0) {
2532                 rc = req.emr_rc;
2533                 goto fail2;
2534         }
2535
2536         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
2537                 rc = EMSGSIZE;
2538                 goto fail3;
2539         }
2540
2541         aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
2542         if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
2543                 rc = ENOENT;
2544                 goto fail4;
2545         }
2546
2547         aset_idp->id = aset_id.id;
2548
2549         return (0);
2550
2551 fail4:
2552         EFSYS_PROBE(fail4);
2553 fail3:
2554         EFSYS_PROBE(fail3);
2555 fail2:
2556         EFSYS_PROBE(fail2);
2557 fail1:
2558         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2559         return (rc);
2560 }
2561
2562         __checkReturn                   unsigned int
2563 efx_mae_action_set_get_nb_count(
2564         __in                            const efx_mae_actions_t *spec)
2565 {
2566         return (spec->ema_n_count_actions);
2567 }
2568
2569         __checkReturn                   efx_rc_t
2570 efx_mae_action_set_fill_in_counter_id(
2571         __in                            efx_mae_actions_t *spec,
2572         __in                            const efx_counter_t *counter_idp)
2573 {
2574         efx_rc_t rc;
2575
2576         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_COUNT)) == 0) {
2577                 /*
2578                  * Invalid to add counter ID if spec does not have COUNT action.
2579                  */
2580                 rc = EINVAL;
2581                 goto fail1;
2582         }
2583
2584         if (spec->ema_n_count_actions != 1) {
2585                 /*
2586                  * Having multiple COUNT actions in the spec requires a counter
2587                  * list to be used. This API must only be used for a single
2588                  * counter per spec. Turn down the request as inappropriate.
2589                  */
2590                 rc = EINVAL;
2591                 goto fail2;
2592         }
2593
2594         if (spec->ema_rsrc.emar_counter_id.id != EFX_MAE_RSRC_ID_INVALID) {
2595                 /* The caller attempts to indicate counter ID twice. */
2596                 rc = EALREADY;
2597                 goto fail3;
2598         }
2599
2600         if (counter_idp->id == EFX_MAE_RSRC_ID_INVALID) {
2601                 rc = EINVAL;
2602                 goto fail4;
2603         }
2604
2605         spec->ema_rsrc.emar_counter_id.id = counter_idp->id;
2606
2607         return (0);
2608
2609 fail4:
2610         EFSYS_PROBE(fail4);
2611 fail3:
2612         EFSYS_PROBE(fail3);
2613 fail2:
2614         EFSYS_PROBE(fail2);
2615 fail1:
2616         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2617         return (rc);
2618 }
2619
2620         __checkReturn                   efx_rc_t
2621 efx_mae_counters_alloc(
2622         __in                            efx_nic_t *enp,
2623         __in                            uint32_t n_counters,
2624         __out                           uint32_t *n_allocatedp,
2625         __out_ecount(n_counters)        efx_counter_t *countersp,
2626         __out_opt                       uint32_t *gen_countp)
2627 {
2628         EFX_MCDI_DECLARE_BUF(payload,
2629             MC_CMD_MAE_COUNTER_ALLOC_IN_LEN,
2630             MC_CMD_MAE_COUNTER_ALLOC_OUT_LENMAX_MCDI2);
2631         efx_mae_t *maep = enp->en_maep;
2632         uint32_t n_allocated;
2633         efx_mcdi_req_t req;
2634         unsigned int i;
2635         efx_rc_t rc;
2636
2637         if (n_counters > maep->em_max_ncounters ||
2638             n_counters < MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM ||
2639             n_counters > MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MAXNUM_MCDI2) {
2640                 rc = EINVAL;
2641                 goto fail1;
2642         }
2643
2644         req.emr_cmd = MC_CMD_MAE_COUNTER_ALLOC;
2645         req.emr_in_buf = payload;
2646         req.emr_in_length = MC_CMD_MAE_COUNTER_ALLOC_IN_LEN;
2647         req.emr_out_buf = payload;
2648         req.emr_out_length = MC_CMD_MAE_COUNTER_ALLOC_OUT_LEN(n_counters);
2649
2650         MCDI_IN_SET_DWORD(req, MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT,
2651             n_counters);
2652
2653         efx_mcdi_execute(enp, &req);
2654
2655         if (req.emr_rc != 0) {
2656                 rc = req.emr_rc;
2657                 goto fail2;
2658         }
2659
2660         if (req.emr_out_length_used < MC_CMD_MAE_COUNTER_ALLOC_OUT_LENMIN) {
2661                 rc = EMSGSIZE;
2662                 goto fail3;
2663         }
2664
2665         n_allocated = MCDI_OUT_DWORD(req,
2666             MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT);
2667         if (n_allocated < MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_MINNUM) {
2668                 rc = EFAULT;
2669                 goto fail4;
2670         }
2671
2672         for (i = 0; i < n_allocated; i++) {
2673                 countersp[i].id = MCDI_OUT_INDEXED_DWORD(req,
2674                     MAE_COUNTER_ALLOC_OUT_COUNTER_ID, i);
2675         }
2676
2677         if (gen_countp != NULL) {
2678                 *gen_countp = MCDI_OUT_DWORD(req,
2679                                     MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT);
2680         }
2681
2682         *n_allocatedp = n_allocated;
2683
2684         return (0);
2685
2686 fail4:
2687         EFSYS_PROBE(fail4);
2688 fail3:
2689         EFSYS_PROBE(fail3);
2690 fail2:
2691         EFSYS_PROBE(fail2);
2692 fail1:
2693         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2694
2695         return (rc);
2696 }
2697
2698         __checkReturn                   efx_rc_t
2699 efx_mae_counters_free(
2700         __in                            efx_nic_t *enp,
2701         __in                            uint32_t n_counters,
2702         __out                           uint32_t *n_freedp,
2703         __in_ecount(n_counters)         const efx_counter_t *countersp,
2704         __out_opt                       uint32_t *gen_countp)
2705 {
2706         EFX_MCDI_DECLARE_BUF(payload,
2707             MC_CMD_MAE_COUNTER_FREE_IN_LENMAX_MCDI2,
2708             MC_CMD_MAE_COUNTER_FREE_OUT_LENMAX_MCDI2);
2709         efx_mae_t *maep = enp->en_maep;
2710         efx_mcdi_req_t req;
2711         uint32_t n_freed;
2712         unsigned int i;
2713         efx_rc_t rc;
2714
2715         if (n_counters > maep->em_max_ncounters ||
2716             n_counters < MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MINNUM ||
2717             n_counters >
2718             MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_MAXNUM_MCDI2) {
2719                 rc = EINVAL;
2720                 goto fail1;
2721         }
2722
2723         req.emr_cmd = MC_CMD_MAE_COUNTER_FREE;
2724         req.emr_in_buf = payload;
2725         req.emr_in_length = MC_CMD_MAE_COUNTER_FREE_IN_LEN(n_counters);
2726         req.emr_out_buf = payload;
2727         req.emr_out_length = MC_CMD_MAE_COUNTER_FREE_OUT_LEN(n_counters);
2728
2729         for (i = 0; i < n_counters; i++) {
2730                 MCDI_IN_SET_INDEXED_DWORD(req,
2731                     MAE_COUNTER_FREE_IN_FREE_COUNTER_ID, i, countersp[i].id);
2732         }
2733         MCDI_IN_SET_DWORD(req, MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT,
2734                           n_counters);
2735
2736         efx_mcdi_execute(enp, &req);
2737
2738         if (req.emr_rc != 0) {
2739                 rc = req.emr_rc;
2740                 goto fail2;
2741         }
2742
2743         if (req.emr_out_length_used < MC_CMD_MAE_COUNTER_FREE_OUT_LENMIN) {
2744                 rc = EMSGSIZE;
2745                 goto fail3;
2746         }
2747
2748         n_freed = MCDI_OUT_DWORD(req, MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT);
2749
2750         if (n_freed < MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_MINNUM) {
2751                 rc = EFAULT;
2752                 goto fail4;
2753         }
2754
2755         if (gen_countp != NULL) {
2756                 *gen_countp = MCDI_OUT_DWORD(req,
2757                                     MAE_COUNTER_FREE_OUT_GENERATION_COUNT);
2758         }
2759
2760         *n_freedp = n_freed;
2761
2762         return (0);
2763
2764 fail4:
2765         EFSYS_PROBE(fail4);
2766 fail3:
2767         EFSYS_PROBE(fail3);
2768 fail2:
2769         EFSYS_PROBE(fail2);
2770 fail1:
2771         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2772
2773         return (rc);
2774 }
2775
2776         __checkReturn                   efx_rc_t
2777 efx_mae_counters_stream_start(
2778         __in                            efx_nic_t *enp,
2779         __in                            uint16_t rxq_id,
2780         __in                            uint16_t packet_size,
2781         __in                            uint32_t flags_in,
2782         __out                           uint32_t *flags_out)
2783 {
2784         efx_mcdi_req_t req;
2785         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_MAE_COUNTERS_STREAM_START_IN_LEN,
2786                              MC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN);
2787         efx_rc_t rc;
2788
2789         EFX_STATIC_ASSERT(EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE ==
2790             1U << MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_LBN);
2791
2792         EFX_STATIC_ASSERT(EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS ==
2793             1U << MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_LBN);
2794
2795         req.emr_cmd = MC_CMD_MAE_COUNTERS_STREAM_START;
2796         req.emr_in_buf = payload;
2797         req.emr_in_length = MC_CMD_MAE_COUNTERS_STREAM_START_IN_LEN;
2798         req.emr_out_buf = payload;
2799         req.emr_out_length = MC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN;
2800
2801         MCDI_IN_SET_WORD(req, MAE_COUNTERS_STREAM_START_IN_QID, rxq_id);
2802         MCDI_IN_SET_WORD(req, MAE_COUNTERS_STREAM_START_IN_PACKET_SIZE,
2803                          packet_size);
2804         MCDI_IN_SET_DWORD(req, MAE_COUNTERS_STREAM_START_IN_FLAGS, flags_in);
2805
2806         efx_mcdi_execute(enp, &req);
2807
2808         if (req.emr_rc != 0) {
2809                 rc = req.emr_rc;
2810                 goto fail1;
2811         }
2812
2813         if (req.emr_out_length_used <
2814             MC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN) {
2815                 rc = EMSGSIZE;
2816                 goto fail2;
2817         }
2818
2819         *flags_out = MCDI_OUT_DWORD(req, MAE_COUNTERS_STREAM_START_OUT_FLAGS);
2820
2821         return (0);
2822
2823 fail2:
2824         EFSYS_PROBE(fail2);
2825 fail1:
2826         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2827
2828         return (rc);
2829 }
2830
2831         __checkReturn                   efx_rc_t
2832 efx_mae_counters_stream_stop(
2833         __in                            efx_nic_t *enp,
2834         __in                            uint16_t rxq_id,
2835         __out_opt                       uint32_t *gen_countp)
2836 {
2837         efx_mcdi_req_t req;
2838         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_LEN,
2839                              MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN);
2840         efx_rc_t rc;
2841
2842         req.emr_cmd = MC_CMD_MAE_COUNTERS_STREAM_STOP;
2843         req.emr_in_buf = payload;
2844         req.emr_in_length = MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_LEN;
2845         req.emr_out_buf = payload;
2846         req.emr_out_length = MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN;
2847
2848         MCDI_IN_SET_WORD(req, MAE_COUNTERS_STREAM_STOP_IN_QID, rxq_id);
2849
2850         efx_mcdi_execute(enp, &req);
2851
2852         if (req.emr_rc != 0) {
2853                 rc = req.emr_rc;
2854                 goto fail1;
2855         }
2856
2857         if (req.emr_out_length_used <
2858             MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN) {
2859                 rc = EMSGSIZE;
2860                 goto fail2;
2861         }
2862
2863         if (gen_countp != NULL) {
2864                 *gen_countp = MCDI_OUT_DWORD(req,
2865                             MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT);
2866         }
2867
2868         return (0);
2869
2870 fail2:
2871         EFSYS_PROBE(fail2);
2872 fail1:
2873         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2874
2875         return (rc);
2876 }
2877
2878         __checkReturn                   efx_rc_t
2879 efx_mae_counters_stream_give_credits(
2880         __in                            efx_nic_t *enp,
2881         __in                            uint32_t n_credits)
2882 {
2883         efx_mcdi_req_t req;
2884         EFX_MCDI_DECLARE_BUF(payload,
2885                              MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN,
2886                              MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT_LEN);
2887         efx_rc_t rc;
2888
2889         req.emr_cmd = MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS;
2890         req.emr_in_buf = payload;
2891         req.emr_in_length = MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN;
2892         req.emr_out_buf = payload;
2893         req.emr_out_length = MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT_LEN;
2894
2895         MCDI_IN_SET_DWORD(req, MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS,
2896                          n_credits);
2897
2898         efx_mcdi_execute(enp, &req);
2899
2900         if (req.emr_rc != 0) {
2901                 rc = req.emr_rc;
2902                 goto fail1;
2903         }
2904
2905         return (0);
2906
2907 fail1:
2908         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2909
2910         return (rc);
2911 }
2912
2913         __checkReturn                   efx_rc_t
2914 efx_mae_action_set_free(
2915         __in                            efx_nic_t *enp,
2916         __in                            const efx_mae_aset_id_t *aset_idp)
2917 {
2918         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
2919         efx_mcdi_req_t req;
2920         EFX_MCDI_DECLARE_BUF(payload,
2921             MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
2922             MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
2923         efx_rc_t rc;
2924
2925         if (encp->enc_mae_supported == B_FALSE) {
2926                 rc = ENOTSUP;
2927                 goto fail1;
2928         }
2929
2930         req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
2931         req.emr_in_buf = payload;
2932         req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
2933         req.emr_out_buf = payload;
2934         req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
2935
2936         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
2937
2938         efx_mcdi_execute(enp, &req);
2939
2940         if (req.emr_rc != 0) {
2941                 rc = req.emr_rc;
2942                 goto fail2;
2943         }
2944
2945         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMIN) {
2946                 rc = EMSGSIZE;
2947                 goto fail3;
2948         }
2949
2950         if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
2951             aset_idp->id) {
2952                 /* Firmware failed to free the action set. */
2953                 rc = EAGAIN;
2954                 goto fail4;
2955         }
2956
2957         return (0);
2958
2959 fail4:
2960         EFSYS_PROBE(fail4);
2961 fail3:
2962         EFSYS_PROBE(fail3);
2963 fail2:
2964         EFSYS_PROBE(fail2);
2965 fail1:
2966         EFSYS_PROBE1(fail1, efx_rc_t, rc);
2967         return (rc);
2968 }
2969
2970         __checkReturn                   efx_rc_t
2971 efx_mae_action_rule_insert(
2972         __in                            efx_nic_t *enp,
2973         __in                            const efx_mae_match_spec_t *spec,
2974         __in                            const efx_mae_aset_list_id_t *asl_idp,
2975         __in                            const efx_mae_aset_id_t *as_idp,
2976         __out                           efx_mae_rule_id_t *ar_idp)
2977 {
2978         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
2979         efx_mcdi_req_t req;
2980         EFX_MCDI_DECLARE_BUF(payload,
2981             MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
2982             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
2983         efx_oword_t *rule_response;
2984         efx_mae_rule_id_t ar_id;
2985         size_t offset;
2986         efx_rc_t rc;
2987
2988         EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
2989             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
2990
2991         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
2992             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
2993
2994         if (encp->enc_mae_supported == B_FALSE) {
2995                 rc = ENOTSUP;
2996                 goto fail1;
2997         }
2998
2999         if (spec->emms_type != EFX_MAE_RULE_ACTION ||
3000             (asl_idp != NULL && as_idp != NULL) ||
3001             (asl_idp == NULL && as_idp == NULL)) {
3002                 rc = EINVAL;
3003                 goto fail2;
3004         }
3005
3006         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
3007         req.emr_in_buf = payload;
3008         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
3009         req.emr_out_buf = payload;
3010         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
3011
3012         EFX_STATIC_ASSERT(sizeof (*rule_response) <=
3013             MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
3014         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
3015         rule_response = (efx_oword_t *)(payload + offset);
3016         EFX_POPULATE_OWORD_3(*rule_response,
3017             MAE_ACTION_RULE_RESPONSE_ASL_ID,
3018             (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
3019             MAE_ACTION_RULE_RESPONSE_AS_ID,
3020             (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
3021             MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
3022
3023         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
3024
3025         /*
3026          * Mask-value pairs have been stored in the byte order needed for the
3027          * MCDI request and are thus safe to be copied directly to the buffer.
3028          */
3029         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
3030             MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
3031         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
3032         memcpy(payload + offset, spec->emms_mask_value_pairs.action,
3033             MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN);
3034
3035         efx_mcdi_execute(enp, &req);
3036
3037         if (req.emr_rc != 0) {
3038                 rc = req.emr_rc;
3039                 goto fail3;
3040         }
3041
3042         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
3043                 rc = EMSGSIZE;
3044                 goto fail4;
3045         }
3046
3047         ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
3048         if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
3049                 rc = ENOENT;
3050                 goto fail5;
3051         }
3052
3053         ar_idp->id = ar_id.id;
3054
3055         return (0);
3056
3057 fail5:
3058         EFSYS_PROBE(fail5);
3059 fail4:
3060         EFSYS_PROBE(fail4);
3061 fail3:
3062         EFSYS_PROBE(fail3);
3063 fail2:
3064         EFSYS_PROBE(fail2);
3065 fail1:
3066         EFSYS_PROBE1(fail1, efx_rc_t, rc);
3067         return (rc);
3068 }
3069
3070         __checkReturn                   efx_rc_t
3071 efx_mae_action_rule_remove(
3072         __in                            efx_nic_t *enp,
3073         __in                            const efx_mae_rule_id_t *ar_idp)
3074 {
3075         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
3076         efx_mcdi_req_t req;
3077         EFX_MCDI_DECLARE_BUF(payload,
3078             MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
3079             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
3080         efx_rc_t rc;
3081
3082         if (encp->enc_mae_supported == B_FALSE) {
3083                 rc = ENOTSUP;
3084                 goto fail1;
3085         }
3086
3087         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
3088         req.emr_in_buf = payload;
3089         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
3090         req.emr_out_buf = payload;
3091         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
3092
3093         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
3094
3095         efx_mcdi_execute(enp, &req);
3096
3097         if (req.emr_rc != 0) {
3098                 rc = req.emr_rc;
3099                 goto fail2;
3100         }
3101
3102         if (req.emr_out_length_used <
3103             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMIN) {
3104                 rc = EMSGSIZE;
3105                 goto fail3;
3106         }
3107
3108         if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
3109             ar_idp->id) {
3110                 /* Firmware failed to delete the action rule. */
3111                 rc = EAGAIN;
3112                 goto fail4;
3113         }
3114
3115         return (0);
3116
3117 fail4:
3118         EFSYS_PROBE(fail4);
3119 fail3:
3120         EFSYS_PROBE(fail3);
3121 fail2:
3122         EFSYS_PROBE(fail2);
3123 fail1:
3124         EFSYS_PROBE1(fail1, efx_rc_t, rc);
3125         return (rc);
3126 }
3127
3128 #endif /* EFSYS_OPT_MAE */