1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
13 static __checkReturn efx_rc_t
14 efx_mae_get_capabilities(
18 EFX_MCDI_DECLARE_BUF(payload,
19 MC_CMD_MAE_GET_CAPS_IN_LEN,
20 MC_CMD_MAE_GET_CAPS_OUT_LEN);
21 struct efx_mae_s *maep = enp->en_maep;
24 req.emr_cmd = MC_CMD_MAE_GET_CAPS;
25 req.emr_in_buf = payload;
26 req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
27 req.emr_out_buf = payload;
28 req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
30 efx_mcdi_execute(enp, &req);
32 if (req.emr_rc != 0) {
37 if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
42 maep->em_max_n_outer_prios =
43 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
45 maep->em_max_n_action_prios =
46 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
48 maep->em_encap_types_supported = 0;
50 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
51 maep->em_encap_types_supported |=
52 (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
55 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
56 maep->em_encap_types_supported |=
57 (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
60 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
61 maep->em_encap_types_supported |=
62 (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
65 maep->em_max_nfields =
66 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
73 EFSYS_PROBE1(fail1, efx_rc_t, rc);
77 static __checkReturn efx_rc_t
78 efx_mae_get_action_rule_caps(
80 __in unsigned int field_ncaps,
81 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
84 EFX_MCDI_DECLARE_BUF(payload,
85 MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
86 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
87 unsigned int mcdi_field_ncaps;
91 if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
92 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
97 req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
98 req.emr_in_buf = payload;
99 req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
100 req.emr_out_buf = payload;
101 req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
103 efx_mcdi_execute(enp, &req);
105 if (req.emr_rc != 0) {
110 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
112 if (req.emr_out_length_used <
113 MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
118 if (mcdi_field_ncaps > field_ncaps) {
123 for (i = 0; i < mcdi_field_ncaps; ++i) {
127 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
128 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
129 MAE_FIELD_FLAGS_SUPPORT_STATUS);
131 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
132 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
133 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
135 field_caps[i].emfc_match_affects_class =
136 (match_flag != 0) ? B_TRUE : B_FALSE;
138 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
139 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
140 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
142 field_caps[i].emfc_mask_affects_class =
143 (mask_flag != 0) ? B_TRUE : B_FALSE;
155 EFSYS_PROBE1(fail1, efx_rc_t, rc);
159 __checkReturn efx_rc_t
163 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
164 efx_mae_field_cap_t *ar_fcaps;
165 size_t ar_fcaps_size;
169 if (encp->enc_mae_supported == B_FALSE) {
174 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
182 rc = efx_mae_get_capabilities(enp);
186 ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
187 EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
188 if (ar_fcaps == NULL) {
193 maep->em_action_rule_field_caps_size = ar_fcaps_size;
194 maep->em_action_rule_field_caps = ar_fcaps;
196 rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
204 EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
209 EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
214 EFSYS_PROBE1(fail1, efx_rc_t, rc);
222 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
223 efx_mae_t *maep = enp->en_maep;
225 if (encp->enc_mae_supported == B_FALSE)
228 EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
229 maep->em_action_rule_field_caps);
230 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
234 __checkReturn efx_rc_t
237 __out efx_mae_limits_t *emlp)
239 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
240 struct efx_mae_s *maep = enp->en_maep;
243 if (encp->enc_mae_supported == B_FALSE) {
248 emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
249 emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
250 emlp->eml_encap_types_supported = maep->em_encap_types_supported;
255 EFSYS_PROBE1(fail1, efx_rc_t, rc);
259 __checkReturn efx_rc_t
260 efx_mae_match_spec_init(
262 __in efx_mae_rule_type_t type,
264 __out efx_mae_match_spec_t **specp)
266 efx_mae_match_spec_t *spec;
270 case EFX_MAE_RULE_OUTER:
272 case EFX_MAE_RULE_ACTION:
279 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
285 spec->emms_type = type;
286 spec->emms_prio = prio;
295 EFSYS_PROBE1(fail1, efx_rc_t, rc);
300 efx_mae_match_spec_fini(
302 __in efx_mae_match_spec_t *spec)
304 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
307 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
308 typedef enum efx_mae_field_cap_id_e {
309 EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
310 EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
311 EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
312 EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
313 EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
314 EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
315 EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
316 EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
317 EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
318 EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
319 EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
320 EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
321 EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
322 EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
323 EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
324 EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
325 EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
326 EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
327 EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
328 EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
329 EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
330 EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
331 EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
332 EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
333 EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
334 EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
335 EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
336 EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
337 EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
338 EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
339 EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
340 EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
341 EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
342 EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
343 EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
345 EFX_MAE_FIELD_CAP_NIDS
346 } efx_mae_field_cap_id_t;
348 typedef enum efx_mae_field_endianness_e {
349 EFX_MAE_FIELD_LE = 0,
352 EFX_MAE_FIELD_ENDIANNESS_NTYPES
353 } efx_mae_field_endianness_t;
356 * The following structure is a means to describe an MAE field.
357 * The information in it is meant to be used internally by
358 * APIs for addressing a given field in a mask-value pairs
359 * structure and for validation purposes.
361 typedef struct efx_mae_mv_desc_s {
362 efx_mae_field_cap_id_t emmd_field_cap_id;
364 size_t emmd_value_size;
365 size_t emmd_value_offset;
366 size_t emmd_mask_size;
367 size_t emmd_mask_offset;
369 efx_mae_field_endianness_t emmd_endianness;
372 /* Indices to this array are provided by efx_mae_field_id_t */
373 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
374 #define EFX_MAE_MV_DESC(_name, _endianness) \
375 [EFX_MAE_FIELD_##_name] = \
377 EFX_MAE_FIELD_ID_##_name, \
378 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN, \
379 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST, \
380 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN, \
381 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST, \
385 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
386 EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
387 EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
388 EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
389 EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
390 EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
391 EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
392 EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
393 EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
394 EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
395 EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
396 EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
397 EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
398 EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
399 EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
400 EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
401 EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
402 EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
403 EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
405 #undef EFX_MAE_MV_DESC
408 /* Indices to this array are provided by efx_mae_field_id_t */
409 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
410 #define EFX_MAE_MV_DESC(_name, _endianness) \
411 [EFX_MAE_FIELD_##_name] = \
413 EFX_MAE_FIELD_ID_##_name, \
414 MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
415 MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
416 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
417 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
421 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
422 EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
423 EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
424 EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
425 EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
426 EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
427 EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
428 EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
429 EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
430 EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
431 EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
432 EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
433 EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
434 EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
435 EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
436 EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
437 EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
439 #undef EFX_MAE_MV_DESC
442 __checkReturn efx_rc_t
443 efx_mae_mport_by_phy_port(
444 __in uint32_t phy_port,
445 __out efx_mport_sel_t *mportp)
450 if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
455 EFX_POPULATE_DWORD_2(dword,
456 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
457 MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
459 memset(mportp, 0, sizeof (*mportp));
460 mportp->sel = dword.ed_u32[0];
465 EFSYS_PROBE1(fail1, efx_rc_t, rc);
469 __checkReturn efx_rc_t
470 efx_mae_mport_by_pcie_function(
473 __out efx_mport_sel_t *mportp)
478 EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
479 MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
481 if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
486 if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
491 EFX_POPULATE_DWORD_3(dword,
492 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
493 MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
494 MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
496 memset(mportp, 0, sizeof (*mportp));
497 mportp->sel = dword.ed_u32[0];
504 EFSYS_PROBE1(fail1, efx_rc_t, rc);
508 __checkReturn efx_rc_t
509 efx_mae_match_spec_field_set(
510 __in efx_mae_match_spec_t *spec,
511 __in efx_mae_field_id_t field_id,
512 __in size_t value_size,
513 __in_bcount(value_size) const uint8_t *value,
514 __in size_t mask_size,
515 __in_bcount(mask_size) const uint8_t *mask)
517 const efx_mae_mv_desc_t *descp;
521 if (field_id >= EFX_MAE_FIELD_NIDS) {
526 switch (spec->emms_type) {
527 case EFX_MAE_RULE_OUTER:
528 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
529 mvp = spec->emms_mask_value_pairs.outer;
531 case EFX_MAE_RULE_ACTION:
532 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
533 mvp = spec->emms_mask_value_pairs.action;
540 if (value_size != descp->emmd_value_size) {
545 if (mask_size != descp->emmd_mask_size) {
550 if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
552 * The mask/value are in network (big endian) order.
553 * The MCDI request field is also big endian.
555 memcpy(mvp + descp->emmd_value_offset, value, value_size);
556 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
561 * The mask/value are in host byte order.
562 * The MCDI request field is little endian.
564 switch (value_size) {
566 EFX_POPULATE_DWORD_1(dword,
567 EFX_DWORD_0, *(const uint32_t *)value);
569 memcpy(mvp + descp->emmd_value_offset,
570 &dword, sizeof (dword));
573 EFSYS_ASSERT(B_FALSE);
578 EFX_POPULATE_DWORD_1(dword,
579 EFX_DWORD_0, *(const uint32_t *)mask);
581 memcpy(mvp + descp->emmd_mask_offset,
582 &dword, sizeof (dword));
585 EFSYS_ASSERT(B_FALSE);
598 EFSYS_PROBE1(fail1, efx_rc_t, rc);
602 __checkReturn efx_rc_t
603 efx_mae_match_spec_mport_set(
604 __in efx_mae_match_spec_t *spec,
605 __in const efx_mport_sel_t *valuep,
606 __in_opt const efx_mport_sel_t *maskp)
608 uint32_t full_mask = UINT32_MAX;
613 if (valuep == NULL) {
618 vp = (const uint8_t *)&valuep->sel;
620 mp = (const uint8_t *)&maskp->sel;
622 mp = (const uint8_t *)&full_mask;
624 rc = efx_mae_match_spec_field_set(spec,
625 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
626 sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
635 EFSYS_PROBE1(fail1, efx_rc_t, rc);
639 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit) \
640 ((_mask)[(_bit) / (_mask_page_nbits)] & \
641 (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
643 static inline boolean_t
645 __in size_t mask_nbytes,
646 __in_bcount(mask_nbytes) const uint8_t *maskp)
648 boolean_t prev_bit_is_set = B_TRUE;
651 for (i = 0; i < 8 * mask_nbytes; ++i) {
652 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
654 if (!prev_bit_is_set && bit_is_set)
657 prev_bit_is_set = bit_is_set;
663 static inline boolean_t
664 efx_mask_is_all_ones(
665 __in size_t mask_nbytes,
666 __in_bcount(mask_nbytes) const uint8_t *maskp)
671 for (i = 0; i < mask_nbytes; ++i)
674 return (t == (uint8_t)(~0));
677 static inline boolean_t
678 efx_mask_is_all_zeros(
679 __in size_t mask_nbytes,
680 __in_bcount(mask_nbytes) const uint8_t *maskp)
685 for (i = 0; i < mask_nbytes; ++i)
691 __checkReturn boolean_t
692 efx_mae_match_spec_is_valid(
694 __in const efx_mae_match_spec_t *spec)
696 efx_mae_t *maep = enp->en_maep;
697 unsigned int field_ncaps = maep->em_max_nfields;
698 const efx_mae_field_cap_t *field_caps;
699 const efx_mae_mv_desc_t *desc_setp;
700 unsigned int desc_set_nentries;
701 boolean_t is_valid = B_TRUE;
702 efx_mae_field_id_t field_id;
705 switch (spec->emms_type) {
706 case EFX_MAE_RULE_ACTION:
707 field_caps = maep->em_action_rule_field_caps;
708 desc_setp = __efx_mae_action_rule_mv_desc_set;
710 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
711 mvp = spec->emms_mask_value_pairs.action;
717 if (field_caps == NULL)
720 for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
721 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
722 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
723 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
724 size_t m_size = descp->emmd_mask_size;
727 continue; /* Skip array gap */
729 if (field_cap_id >= field_ncaps)
732 switch (field_caps[field_cap_id].emfc_support) {
733 case MAE_FIELD_SUPPORTED_MATCH_MASK:
736 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
737 is_valid = efx_mask_is_prefix(m_size, m_buf);
739 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
740 is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
741 efx_mask_is_all_zeros(m_size, m_buf));
743 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
744 is_valid = efx_mask_is_all_ones(m_size, m_buf);
746 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
747 case MAE_FIELD_UNSUPPORTED:
749 is_valid = efx_mask_is_all_zeros(m_size, m_buf);
753 if (is_valid == B_FALSE)
760 __checkReturn efx_rc_t
761 efx_mae_action_set_spec_init(
763 __out efx_mae_actions_t **specp)
765 efx_mae_actions_t *spec;
768 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
779 EFSYS_PROBE1(fail1, efx_rc_t, rc);
784 efx_mae_action_set_spec_fini(
786 __in efx_mae_actions_t *spec)
788 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
791 static __checkReturn efx_rc_t
792 efx_mae_action_set_add_vlan_pop(
793 __in efx_mae_actions_t *spec,
794 __in size_t arg_size,
795 __in_bcount(arg_size) const uint8_t *arg)
809 if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
814 ++spec->ema_n_vlan_tags_to_pop;
823 EFSYS_PROBE1(fail1, efx_rc_t, rc);
827 static __checkReturn efx_rc_t
828 efx_mae_action_set_add_vlan_push(
829 __in efx_mae_actions_t *spec,
830 __in size_t arg_size,
831 __in_bcount(arg_size) const uint8_t *arg)
833 unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
836 if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
846 if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
851 memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
852 ++(spec->ema_n_vlan_tags_to_push);
861 EFSYS_PROBE1(fail1, efx_rc_t, rc);
865 static __checkReturn efx_rc_t
866 efx_mae_action_set_add_flag(
867 __in efx_mae_actions_t *spec,
868 __in size_t arg_size,
869 __in_bcount(arg_size) const uint8_t *arg)
873 _NOTE(ARGUNUSED(spec))
885 /* This action does not have any arguments, so do nothing here. */
892 EFSYS_PROBE1(fail1, efx_rc_t, rc);
896 static __checkReturn efx_rc_t
897 efx_mae_action_set_add_mark(
898 __in efx_mae_actions_t *spec,
899 __in size_t arg_size,
900 __in_bcount(arg_size) const uint8_t *arg)
904 if (arg_size != sizeof (spec->ema_mark_value)) {
914 memcpy(&spec->ema_mark_value, arg, arg_size);
921 EFSYS_PROBE1(fail1, efx_rc_t, rc);
925 static __checkReturn efx_rc_t
926 efx_mae_action_set_add_deliver(
927 __in efx_mae_actions_t *spec,
928 __in size_t arg_size,
929 __in_bcount(arg_size) const uint8_t *arg)
933 if (arg_size != sizeof (spec->ema_deliver_mport)) {
943 memcpy(&spec->ema_deliver_mport, arg, arg_size);
950 EFSYS_PROBE1(fail1, efx_rc_t, rc);
954 typedef struct efx_mae_action_desc_s {
955 /* Action specific handler */
956 efx_rc_t (*emad_add)(efx_mae_actions_t *,
957 size_t, const uint8_t *);
958 } efx_mae_action_desc_t;
960 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
961 [EFX_MAE_ACTION_VLAN_POP] = {
962 .emad_add = efx_mae_action_set_add_vlan_pop
964 [EFX_MAE_ACTION_VLAN_PUSH] = {
965 .emad_add = efx_mae_action_set_add_vlan_push
967 [EFX_MAE_ACTION_FLAG] = {
968 .emad_add = efx_mae_action_set_add_flag
970 [EFX_MAE_ACTION_MARK] = {
971 .emad_add = efx_mae_action_set_add_mark
973 [EFX_MAE_ACTION_DELIVER] = {
974 .emad_add = efx_mae_action_set_add_deliver
978 static const uint32_t efx_mae_action_ordered_map =
979 (1U << EFX_MAE_ACTION_VLAN_POP) |
980 (1U << EFX_MAE_ACTION_VLAN_PUSH) |
981 (1U << EFX_MAE_ACTION_FLAG) |
982 (1U << EFX_MAE_ACTION_MARK) |
983 (1U << EFX_MAE_ACTION_DELIVER);
986 * These actions must not be added after DELIVER, but
987 * they can have any place among the rest of
988 * strictly ordered actions.
990 static const uint32_t efx_mae_action_nonstrict_map =
991 (1U << EFX_MAE_ACTION_FLAG) |
992 (1U << EFX_MAE_ACTION_MARK);
994 static const uint32_t efx_mae_action_repeat_map =
995 (1U << EFX_MAE_ACTION_VLAN_POP) |
996 (1U << EFX_MAE_ACTION_VLAN_PUSH);
999 * Add an action to an action set.
1001 * This has to be invoked in the desired action order.
1002 * An out-of-order action request will be turned down.
1004 static __checkReturn efx_rc_t
1005 efx_mae_action_set_spec_populate(
1006 __in efx_mae_actions_t *spec,
1007 __in efx_mae_action_t type,
1008 __in size_t arg_size,
1009 __in_bcount(arg_size) const uint8_t *arg)
1011 uint32_t action_mask;
1014 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1015 (sizeof (efx_mae_action_ordered_map) * 8));
1016 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1017 (sizeof (efx_mae_action_repeat_map) * 8));
1019 EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1020 EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1021 EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1023 if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1028 action_mask = (1U << type);
1030 if ((spec->ema_actions & action_mask) != 0) {
1031 /* The action set already contains this action. */
1032 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1033 /* Cannot add another non-repeatable action. */
1039 if ((efx_mae_action_ordered_map & action_mask) != 0) {
1040 uint32_t strict_ordered_map =
1041 efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1042 uint32_t later_actions_mask =
1043 strict_ordered_map & ~(action_mask | (action_mask - 1));
1045 if ((spec->ema_actions & later_actions_mask) != 0) {
1046 /* Cannot add an action after later ordered actions. */
1052 if (efx_mae_actions[type].emad_add != NULL) {
1053 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1058 spec->ema_actions |= action_mask;
1069 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1073 __checkReturn efx_rc_t
1074 efx_mae_action_set_populate_vlan_pop(
1075 __in efx_mae_actions_t *spec)
1077 return (efx_mae_action_set_spec_populate(spec,
1078 EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1081 __checkReturn efx_rc_t
1082 efx_mae_action_set_populate_vlan_push(
1083 __in efx_mae_actions_t *spec,
1084 __in uint16_t tpid_be,
1085 __in uint16_t tci_be)
1087 efx_mae_action_vlan_push_t action;
1088 const uint8_t *arg = (const uint8_t *)&action;
1090 action.emavp_tpid_be = tpid_be;
1091 action.emavp_tci_be = tci_be;
1093 return (efx_mae_action_set_spec_populate(spec,
1094 EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1097 __checkReturn efx_rc_t
1098 efx_mae_action_set_populate_flag(
1099 __in efx_mae_actions_t *spec)
1101 return (efx_mae_action_set_spec_populate(spec,
1102 EFX_MAE_ACTION_FLAG, 0, NULL));
1105 __checkReturn efx_rc_t
1106 efx_mae_action_set_populate_mark(
1107 __in efx_mae_actions_t *spec,
1108 __in uint32_t mark_value)
1110 const uint8_t *arg = (const uint8_t *)&mark_value;
1112 return (efx_mae_action_set_spec_populate(spec,
1113 EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1116 __checkReturn efx_rc_t
1117 efx_mae_action_set_populate_deliver(
1118 __in efx_mae_actions_t *spec,
1119 __in const efx_mport_sel_t *mportp)
1124 if (mportp == NULL) {
1129 arg = (const uint8_t *)&mportp->sel;
1131 return (efx_mae_action_set_spec_populate(spec,
1132 EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1135 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1139 __checkReturn efx_rc_t
1140 efx_mae_action_set_populate_drop(
1141 __in efx_mae_actions_t *spec)
1143 efx_mport_sel_t mport;
1147 EFX_POPULATE_DWORD_1(dword,
1148 MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1150 mport.sel = dword.ed_u32[0];
1152 arg = (const uint8_t *)&mport.sel;
1154 return (efx_mae_action_set_spec_populate(spec,
1155 EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1158 __checkReturn boolean_t
1159 efx_mae_action_set_specs_equal(
1160 __in const efx_mae_actions_t *left,
1161 __in const efx_mae_actions_t *right)
1163 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1166 __checkReturn efx_rc_t
1167 efx_mae_match_specs_class_cmp(
1168 __in efx_nic_t *enp,
1169 __in const efx_mae_match_spec_t *left,
1170 __in const efx_mae_match_spec_t *right,
1171 __out boolean_t *have_same_classp)
1173 efx_mae_t *maep = enp->en_maep;
1174 unsigned int field_ncaps = maep->em_max_nfields;
1175 const efx_mae_field_cap_t *field_caps;
1176 const efx_mae_mv_desc_t *desc_setp;
1177 unsigned int desc_set_nentries;
1178 boolean_t have_same_class = B_TRUE;
1179 efx_mae_field_id_t field_id;
1180 const uint8_t *mvpl;
1181 const uint8_t *mvpr;
1184 switch (left->emms_type) {
1185 case EFX_MAE_RULE_ACTION:
1186 field_caps = maep->em_action_rule_field_caps;
1187 desc_setp = __efx_mae_action_rule_mv_desc_set;
1189 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1190 mvpl = left->emms_mask_value_pairs.action;
1191 mvpr = right->emms_mask_value_pairs.action;
1198 if (field_caps == NULL) {
1203 if (left->emms_type != right->emms_type ||
1204 left->emms_prio != right->emms_prio) {
1206 * Rules of different types can never map to the same class.
1208 * The FW can support some set of match criteria for one
1209 * priority and not support the very same set for
1210 * another priority. Thus, two rules which have
1211 * different priorities can never map to
1214 *have_same_classp = B_FALSE;
1218 for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
1219 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1220 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1222 if (descp->emmd_mask_size == 0)
1223 continue; /* Skip array gap */
1225 if (field_cap_id >= field_ncaps)
1228 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1229 const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1230 const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1231 size_t mask_size = descp->emmd_mask_size;
1233 if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1234 have_same_class = B_FALSE;
1239 if (field_caps[field_cap_id].emfc_match_affects_class) {
1240 const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1241 const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1242 size_t value_size = descp->emmd_value_size;
1244 if (memcmp(lvalp, rvalp, value_size) != 0) {
1245 have_same_class = B_FALSE;
1251 *have_same_classp = have_same_class;
1258 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1262 __checkReturn efx_rc_t
1263 efx_mae_action_set_alloc(
1264 __in efx_nic_t *enp,
1265 __in const efx_mae_actions_t *spec,
1266 __out efx_mae_aset_id_t *aset_idp)
1268 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1270 EFX_MCDI_DECLARE_BUF(payload,
1271 MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1272 MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1273 efx_mae_aset_id_t aset_id;
1276 if (encp->enc_mae_supported == B_FALSE) {
1281 req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1282 req.emr_in_buf = payload;
1283 req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1284 req.emr_out_buf = payload;
1285 req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1288 * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1289 * corresponding resource types are supported by the implementation.
1290 * Use proper resource ID assignments instead.
1292 MCDI_IN_SET_DWORD(req,
1293 MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1294 MCDI_IN_SET_DWORD(req,
1295 MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1296 MCDI_IN_SET_DWORD(req,
1297 MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1299 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1300 MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1302 if (spec->ema_n_vlan_tags_to_push > 0) {
1303 unsigned int outer_tag_idx;
1305 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1306 MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1307 spec->ema_n_vlan_tags_to_push);
1309 if (spec->ema_n_vlan_tags_to_push ==
1310 EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1311 MCDI_IN_SET_WORD(req,
1312 MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1313 spec->ema_vlan_push_descs[0].emavp_tpid_be);
1314 MCDI_IN_SET_WORD(req,
1315 MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1316 spec->ema_vlan_push_descs[0].emavp_tci_be);
1319 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1321 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1322 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1323 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1324 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1327 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1328 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1329 MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1332 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1333 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1334 MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1336 MCDI_IN_SET_DWORD(req,
1337 MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1340 MCDI_IN_SET_DWORD(req,
1341 MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1343 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1344 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1345 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1346 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1348 efx_mcdi_execute(enp, &req);
1350 if (req.emr_rc != 0) {
1355 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1360 aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1361 if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1366 aset_idp->id = aset_id.id;
1377 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1381 __checkReturn efx_rc_t
1382 efx_mae_action_set_free(
1383 __in efx_nic_t *enp,
1384 __in const efx_mae_aset_id_t *aset_idp)
1386 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1388 EFX_MCDI_DECLARE_BUF(payload,
1389 MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1390 MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1393 if (encp->enc_mae_supported == B_FALSE) {
1398 req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1399 req.emr_in_buf = payload;
1400 req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1401 req.emr_out_buf = payload;
1402 req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1404 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1406 efx_mcdi_execute(enp, &req);
1408 if (req.emr_rc != 0) {
1413 if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1415 /* Firmware failed to free the action set. */
1427 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1431 __checkReturn efx_rc_t
1432 efx_mae_action_rule_insert(
1433 __in efx_nic_t *enp,
1434 __in const efx_mae_match_spec_t *spec,
1435 __in const efx_mae_aset_list_id_t *asl_idp,
1436 __in const efx_mae_aset_id_t *as_idp,
1437 __out efx_mae_rule_id_t *ar_idp)
1439 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1441 EFX_MCDI_DECLARE_BUF(payload,
1442 MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1443 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1444 efx_oword_t *rule_response;
1445 efx_mae_rule_id_t ar_id;
1449 EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1450 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1452 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1453 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1455 if (encp->enc_mae_supported == B_FALSE) {
1460 if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1461 (asl_idp != NULL && as_idp != NULL) ||
1462 (asl_idp == NULL && as_idp == NULL)) {
1467 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1468 req.emr_in_buf = payload;
1469 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1470 req.emr_out_buf = payload;
1471 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1473 EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1474 MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1475 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1476 rule_response = (efx_oword_t *)(payload + offset);
1477 EFX_POPULATE_OWORD_3(*rule_response,
1478 MAE_ACTION_RULE_RESPONSE_ASL_ID,
1479 (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1480 MAE_ACTION_RULE_RESPONSE_AS_ID,
1481 (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1482 MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1484 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1487 * Mask-value pairs have been stored in the byte order needed for the
1488 * MCDI request and are thus safe to be copied directly to the buffer.
1490 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1491 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1492 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1493 memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1494 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1496 efx_mcdi_execute(enp, &req);
1498 if (req.emr_rc != 0) {
1503 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1508 ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1509 if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1514 ar_idp->id = ar_id.id;
1527 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1531 __checkReturn efx_rc_t
1532 efx_mae_action_rule_remove(
1533 __in efx_nic_t *enp,
1534 __in const efx_mae_rule_id_t *ar_idp)
1536 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1538 EFX_MCDI_DECLARE_BUF(payload,
1539 MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1540 MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1543 if (encp->enc_mae_supported == B_FALSE) {
1548 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1549 req.emr_in_buf = payload;
1550 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1551 req.emr_out_buf = payload;
1552 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1554 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1556 efx_mcdi_execute(enp, &req);
1558 if (req.emr_rc != 0) {
1563 if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1565 /* Firmware failed to delete the action rule. */
1577 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1581 #endif /* EFSYS_OPT_MAE */