drivers/common/sfc_efx/base/efx_mae.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_MAE
  12
  13 static  __checkReturn                   efx_rc_t
  14 efx_mae_get_capabilities(
  15         __in                            efx_nic_t *enp)
  16 {
  17         efx_mcdi_req_t req;
  18         EFX_MCDI_DECLARE_BUF(payload,
  19             MC_CMD_MAE_GET_CAPS_IN_LEN,
  20             MC_CMD_MAE_GET_CAPS_OUT_LEN);
  21         struct efx_mae_s *maep = enp->en_maep;
  22         efx_rc_t rc;
  23
  24         req.emr_cmd = MC_CMD_MAE_GET_CAPS;
  25         req.emr_in_buf = payload;
  26         req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
  27         req.emr_out_buf = payload;
  28         req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
  29
  30         efx_mcdi_execute(enp, &req);
  31
  32         if (req.emr_rc != 0) {
  33                 rc = req.emr_rc;
  34                 goto fail1;
  35         }
  36
  37         if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
  38                 rc = EMSGSIZE;
  39                 goto fail2;
  40         }
  41
  42         maep->em_max_n_outer_prios =
  43             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
  44
  45         maep->em_max_n_action_prios =
  46             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
  47
  48         maep->em_encap_types_supported = 0;
  49
  50         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
  51                 maep->em_encap_types_supported |=
  52                     (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
  53         }
  54
  55         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
  56                 maep->em_encap_types_supported |=
  57                     (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
  58         }
  59
  60         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
  61                 maep->em_encap_types_supported |=
  62                     (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
  63         }
  64
  65         maep->em_max_nfields =
  66             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
  67
  68         return (0);
  69
  70 fail2:
  71         EFSYS_PROBE(fail2);
  72 fail1:
  73         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  74         return (rc);
  75 }
  76
  77 static  __checkReturn                   efx_rc_t
  78 efx_mae_get_action_rule_caps(
  79         __in                            efx_nic_t *enp,
  80         __in                            unsigned int field_ncaps,
  81         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
  82 {
  83         efx_mcdi_req_t req;
  84         EFX_MCDI_DECLARE_BUF(payload,
  85             MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
  86             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
  87         unsigned int mcdi_field_ncaps;
  88         unsigned int i;
  89         efx_rc_t rc;
  90
  91         if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
  92             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
  93                 rc = EINVAL;
  94                 goto fail1;
  95         }
  96
  97         req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
  98         req.emr_in_buf = payload;
  99         req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
 100         req.emr_out_buf = payload;
 101         req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
 102
 103         efx_mcdi_execute(enp, &req);
 104
 105         if (req.emr_rc != 0) {
 106                 rc = req.emr_rc;
 107                 goto fail2;
 108         }
 109
 110         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 111
 112         if (req.emr_out_length_used <
 113             MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 114                 rc = EMSGSIZE;
 115                 goto fail3;
 116         }
 117
 118         if (mcdi_field_ncaps > field_ncaps) {
 119                 rc = EMSGSIZE;
 120                 goto fail4;
 121         }
 122
 123         for (i = 0; i < mcdi_field_ncaps; ++i) {
 124                 uint32_t match_flag;
 125                 uint32_t mask_flag;
 126
 127                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 128                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 129                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 130
 131                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 132                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 133                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 134
 135                 field_caps[i].emfc_match_affects_class =
 136                     (match_flag != 0) ? B_TRUE : B_FALSE;
 137
 138                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 139                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 140                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 141
 142                 field_caps[i].emfc_mask_affects_class =
 143                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 144         }
 145
 146         return (0);
 147
 148 fail4:
 149         EFSYS_PROBE(fail4);
 150 fail3:
 151         EFSYS_PROBE(fail3);
 152 fail2:
 153         EFSYS_PROBE(fail2);
 154 fail1:
 155         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 156         return (rc);
 157 }
 158
 159         __checkReturn                   efx_rc_t
 160 efx_mae_init(
 161         __in                            efx_nic_t *enp)
 162 {
 163         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 164         efx_mae_field_cap_t *ar_fcaps;
 165         size_t ar_fcaps_size;
 166         efx_mae_t *maep;
 167         efx_rc_t rc;
 168
 169         if (encp->enc_mae_supported == B_FALSE) {
 170                 rc = ENOTSUP;
 171                 goto fail1;
 172         }
 173
 174         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
 175         if (maep == NULL) {
 176                 rc = ENOMEM;
 177                 goto fail2;
 178         }
 179
 180         enp->en_maep = maep;
 181
 182         rc = efx_mae_get_capabilities(enp);
 183         if (rc != 0)
 184                 goto fail3;
 185
 186         ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
 187         EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
 188         if (ar_fcaps == NULL) {
 189                 rc = ENOMEM;
 190                 goto fail4;
 191         }
 192
 193         maep->em_action_rule_field_caps_size = ar_fcaps_size;
 194         maep->em_action_rule_field_caps = ar_fcaps;
 195
 196         rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
 197         if (rc != 0)
 198                 goto fail5;
 199
 200         return (0);
 201
 202 fail5:
 203         EFSYS_PROBE(fail5);
 204         EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
 205 fail4:
 206         EFSYS_PROBE(fail4);
 207 fail3:
 208         EFSYS_PROBE(fail3);
 209         EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
 210         enp->en_maep = NULL;
 211 fail2:
 212         EFSYS_PROBE(fail2);
 213 fail1:
 214         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 215         return (rc);
 216 }
 217
 218                                         void
 219 efx_mae_fini(
 220         __in                            efx_nic_t *enp)
 221 {
 222         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 223         efx_mae_t *maep = enp->en_maep;
 224
 225         if (encp->enc_mae_supported == B_FALSE)
 226                 return;
 227
 228         EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
 229             maep->em_action_rule_field_caps);
 230         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
 231         enp->en_maep = NULL;
 232 }
 233
 234         __checkReturn                   efx_rc_t
 235 efx_mae_get_limits(
 236         __in                            efx_nic_t *enp,
 237         __out                           efx_mae_limits_t *emlp)
 238 {
 239         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 240         struct efx_mae_s *maep = enp->en_maep;
 241         efx_rc_t rc;
 242
 243         if (encp->enc_mae_supported == B_FALSE) {
 244                 rc = ENOTSUP;
 245                 goto fail1;
 246         }
 247
 248         emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
 249         emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
 250         emlp->eml_encap_types_supported = maep->em_encap_types_supported;
 251
 252         return (0);
 253
 254 fail1:
 255         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 256         return (rc);
 257 }
 258
 259         __checkReturn                   efx_rc_t
 260 efx_mae_match_spec_init(
 261         __in                            efx_nic_t *enp,
 262         __in                            efx_mae_rule_type_t type,
 263         __in                            uint32_t prio,
 264         __out                           efx_mae_match_spec_t **specp)
 265 {
 266         efx_mae_match_spec_t *spec;
 267         efx_rc_t rc;
 268
 269         switch (type) {
 270         case EFX_MAE_RULE_OUTER:
 271                 break;
 272         case EFX_MAE_RULE_ACTION:
 273                 break;
 274         default:
 275                 rc = ENOTSUP;
 276                 goto fail1;
 277         }
 278
 279         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 280         if (spec == NULL) {
 281                 rc = ENOMEM;
 282                 goto fail2;
 283         }
 284
 285         spec->emms_type = type;
 286         spec->emms_prio = prio;
 287
 288         *specp = spec;
 289
 290         return (0);
 291
 292 fail2:
 293         EFSYS_PROBE(fail2);
 294 fail1:
 295         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 296         return (rc);
 297 }
 298
 299                                         void
 300 efx_mae_match_spec_fini(
 301         __in                            efx_nic_t *enp,
 302         __in                            efx_mae_match_spec_t *spec)
 303 {
 304         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 305 }
 306
 307 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
 308 typedef enum efx_mae_field_cap_id_e {
 309         EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
 310         EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
 311         EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
 312         EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
 313         EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
 314         EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
 315         EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
 316         EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
 317         EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
 318         EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
 319         EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
 320         EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
 321         EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
 322         EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
 323         EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
 324         EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
 325         EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
 326         EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
 327         EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
 328         EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
 329         EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
 330         EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
 331         EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
 332         EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
 333         EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
 334         EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
 335         EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
 336         EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
 337         EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
 338         EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
 339         EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
 340         EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
 341         EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
 342         EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 343
 344         EFX_MAE_FIELD_CAP_NIDS
 345 } efx_mae_field_cap_id_t;
 346
 347 typedef enum efx_mae_field_endianness_e {
 348         EFX_MAE_FIELD_LE = 0,
 349         EFX_MAE_FIELD_BE,
 350
 351         EFX_MAE_FIELD_ENDIANNESS_NTYPES
 352 } efx_mae_field_endianness_t;
 353
 354 /*
 355  * The following structure is a means to describe an MAE field.
 356  * The information in it is meant to be used internally by
 357  * APIs for addressing a given field in a mask-value pairs
 358  * structure and for validation purposes.
 359  */
 360 typedef struct efx_mae_mv_desc_s {
 361         efx_mae_field_cap_id_t          emmd_field_cap_id;
 362
 363         size_t                          emmd_value_size;
 364         size_t                          emmd_value_offset;
 365         size_t                          emmd_mask_size;
 366         size_t                          emmd_mask_offset;
 367
 368         efx_mae_field_endianness_t      emmd_endianness;
 369 } efx_mae_mv_desc_t;
 370
 371 /* Indices to this array are provided by efx_mae_field_id_t */
 372 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 373 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 374         [EFX_MAE_FIELD_##_name] =                                       \
 375         {                                                               \
 376                 EFX_MAE_FIELD_ID_##_name,                               \
 377                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,               \
 378                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,              \
 379                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,          \
 380                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,         \
 381                 _endianness                                             \
 382         }
 383
 384         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 385         EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 386         EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 387         EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 388         EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 389         EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 390         EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 391         EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 392         EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
 393         EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
 394         EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
 395         EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
 396         EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
 397         EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
 398         EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
 399         EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
 400         EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
 401         EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 402
 403 #undef EFX_MAE_MV_DESC
 404 };
 405
 406 /* Indices to this array are provided by efx_mae_field_id_t */
 407 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 408 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 409         [EFX_MAE_FIELD_##_name] =                                       \
 410         {                                                               \
 411                 EFX_MAE_FIELD_ID_##_name,                               \
 412                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 413                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 414                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 415                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 416                 _endianness                                             \
 417         }
 418
 419         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 420         EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 421         EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 422         EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 423         EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 424         EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 425         EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 426         EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 427         EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
 428         EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 429         EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 430         EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 431         EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
 432         EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
 433         EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 434         EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 435         EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 436
 437 #undef EFX_MAE_MV_DESC
 438 };
 439
 440         __checkReturn                   efx_rc_t
 441 efx_mae_mport_by_phy_port(
 442         __in                            uint32_t phy_port,
 443         __out                           efx_mport_sel_t *mportp)
 444 {
 445         efx_dword_t dword;
 446         efx_rc_t rc;
 447
 448         if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
 449                 rc = EINVAL;
 450                 goto fail1;
 451         }
 452
 453         EFX_POPULATE_DWORD_2(dword,
 454             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
 455             MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 456
 457         memset(mportp, 0, sizeof (*mportp));
 458         mportp->sel = dword.ed_u32[0];
 459
 460         return (0);
 461
 462 fail1:
 463         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 464         return (rc);
 465 }
 466
 467         __checkReturn                   efx_rc_t
 468 efx_mae_mport_by_pcie_function(
 469         __in                            uint32_t pf,
 470         __in                            uint32_t vf,
 471         __out                           efx_mport_sel_t *mportp)
 472 {
 473         efx_dword_t dword;
 474         efx_rc_t rc;
 475
 476         EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
 477             MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
 478
 479         if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
 480                 rc = EINVAL;
 481                 goto fail1;
 482         }
 483
 484         if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
 485                 rc = EINVAL;
 486                 goto fail2;
 487         }
 488
 489         EFX_POPULATE_DWORD_3(dword,
 490             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
 491             MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
 492             MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 493
 494         memset(mportp, 0, sizeof (*mportp));
 495         mportp->sel = dword.ed_u32[0];
 496
 497         return (0);
 498
 499 fail2:
 500         EFSYS_PROBE(fail2);
 501 fail1:
 502         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 503         return (rc);
 504 }
 505
 506         __checkReturn                   efx_rc_t
 507 efx_mae_match_spec_field_set(
 508         __in                            efx_mae_match_spec_t *spec,
 509         __in                            efx_mae_field_id_t field_id,
 510         __in                            size_t value_size,
 511         __in_bcount(value_size)         const uint8_t *value,
 512         __in                            size_t mask_size,
 513         __in_bcount(mask_size)          const uint8_t *mask)
 514 {
 515         const efx_mae_mv_desc_t *descp;
 516         uint8_t *mvp;
 517         efx_rc_t rc;
 518
 519         if (field_id >= EFX_MAE_FIELD_NIDS) {
 520                 rc = EINVAL;
 521                 goto fail1;
 522         }
 523
 524         switch (spec->emms_type) {
 525         case EFX_MAE_RULE_OUTER:
 526                 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
 527                 mvp = spec->emms_mask_value_pairs.outer;
 528                 break;
 529         case EFX_MAE_RULE_ACTION:
 530                 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
 531                 mvp = spec->emms_mask_value_pairs.action;
 532                 break;
 533         default:
 534                 rc = ENOTSUP;
 535                 goto fail2;
 536         }
 537
 538         if (value_size != descp->emmd_value_size) {
 539                 rc = EINVAL;
 540                 goto fail3;
 541         }
 542
 543         if (mask_size != descp->emmd_mask_size) {
 544                 rc = EINVAL;
 545                 goto fail4;
 546         }
 547
 548         if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
 549                 /*
 550                  * The mask/value are in network (big endian) order.
 551                  * The MCDI request field is also big endian.
 552                  */
 553                 memcpy(mvp + descp->emmd_value_offset, value, value_size);
 554                 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
 555         } else {
 556                 efx_dword_t dword;
 557
 558                 /*
 559                  * The mask/value are in host byte order.
 560                  * The MCDI request field is little endian.
 561                  */
 562                 switch (value_size) {
 563                 case 4:
 564                         EFX_POPULATE_DWORD_1(dword,
 565                             EFX_DWORD_0, *(const uint32_t *)value);
 566
 567                         memcpy(mvp + descp->emmd_value_offset,
 568                             &dword, sizeof (dword));
 569                         break;
 570                 default:
 571                         EFSYS_ASSERT(B_FALSE);
 572                 }
 573
 574                 switch (mask_size) {
 575                 case 4:
 576                         EFX_POPULATE_DWORD_1(dword,
 577                             EFX_DWORD_0, *(const uint32_t *)mask);
 578
 579                         memcpy(mvp + descp->emmd_mask_offset,
 580                             &dword, sizeof (dword));
 581                         break;
 582                 default:
 583                         EFSYS_ASSERT(B_FALSE);
 584                 }
 585         }
 586
 587         return (0);
 588
 589 fail4:
 590         EFSYS_PROBE(fail4);
 591 fail3:
 592         EFSYS_PROBE(fail3);
 593 fail2:
 594         EFSYS_PROBE(fail2);
 595 fail1:
 596         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 597         return (rc);
 598 }
 599
 600         __checkReturn                   efx_rc_t
 601 efx_mae_match_spec_mport_set(
 602         __in                            efx_mae_match_spec_t *spec,
 603         __in                            const efx_mport_sel_t *valuep,
 604         __in_opt                        const efx_mport_sel_t *maskp)
 605 {
 606         uint32_t full_mask = UINT32_MAX;
 607         const uint8_t *vp;
 608         const uint8_t *mp;
 609         efx_rc_t rc;
 610
 611         if (valuep == NULL) {
 612                 rc = EINVAL;
 613                 goto fail1;
 614         }
 615
 616         vp = (const uint8_t *)&valuep->sel;
 617         if (maskp != NULL)
 618                 mp = (const uint8_t *)&maskp->sel;
 619         else
 620                 mp = (const uint8_t *)&full_mask;
 621
 622         rc = efx_mae_match_spec_field_set(spec,
 623             EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
 624             sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
 625         if (rc != 0)
 626                 goto fail2;
 627
 628         return (0);
 629
 630 fail2:
 631         EFSYS_PROBE(fail2);
 632 fail1:
 633         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 634         return (rc);
 635 }
 636
 637 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)              \
 638             ((_mask)[(_bit) / (_mask_page_nbits)] &                     \
 639                     (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
 640
 641 static inline                           boolean_t
 642 efx_mask_is_prefix(
 643         __in                            size_t mask_nbytes,
 644         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 645 {
 646         boolean_t prev_bit_is_set = B_TRUE;
 647         unsigned int i;
 648
 649         for (i = 0; i < 8 * mask_nbytes; ++i) {
 650                 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
 651
 652                 if (!prev_bit_is_set && bit_is_set)
 653                         return B_FALSE;
 654
 655                 prev_bit_is_set = bit_is_set;
 656         }
 657
 658         return B_TRUE;
 659 }
 660
 661 static inline                           boolean_t
 662 efx_mask_is_all_ones(
 663         __in                            size_t mask_nbytes,
 664         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 665 {
 666         unsigned int i;
 667         uint8_t t = ~0;
 668
 669         for (i = 0; i < mask_nbytes; ++i)
 670                 t &= maskp[i];
 671
 672         return (t == (uint8_t)(~0));
 673 }
 674
 675 static inline                           boolean_t
 676 efx_mask_is_all_zeros(
 677         __in                            size_t mask_nbytes,
 678         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 679 {
 680         unsigned int i;
 681         uint8_t t = 0;
 682
 683         for (i = 0; i < mask_nbytes; ++i)
 684                 t |= maskp[i];
 685
 686         return (t == 0);
 687 }
 688
 689         __checkReturn                   boolean_t
 690 efx_mae_match_spec_is_valid(
 691         __in                            efx_nic_t *enp,
 692         __in                            const efx_mae_match_spec_t *spec)
 693 {
 694         efx_mae_t *maep = enp->en_maep;
 695         unsigned int field_ncaps = maep->em_max_nfields;
 696         const efx_mae_field_cap_t *field_caps;
 697         const efx_mae_mv_desc_t *desc_setp;
 698         unsigned int desc_set_nentries;
 699         boolean_t is_valid = B_TRUE;
 700         efx_mae_field_id_t field_id;
 701         const uint8_t *mvp;
 702
 703         switch (spec->emms_type) {
 704         case EFX_MAE_RULE_ACTION:
 705                 field_caps = maep->em_action_rule_field_caps;
 706                 desc_setp = __efx_mae_action_rule_mv_desc_set;
 707                 desc_set_nentries =
 708                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 709                 mvp = spec->emms_mask_value_pairs.action;
 710                 break;
 711         default:
 712                 return (B_FALSE);
 713         }
 714
 715         if (field_caps == NULL)
 716                 return (B_FALSE);
 717
 718         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
 719                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 720                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
 721                 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
 722                 size_t m_size = descp->emmd_mask_size;
 723
 724                 if (m_size == 0)
 725                         continue; /* Skip array gap */
 726
 727                 if (field_cap_id >= field_ncaps)
 728                         break;
 729
 730                 switch (field_caps[field_cap_id].emfc_support) {
 731                 case MAE_FIELD_SUPPORTED_MATCH_MASK:
 732                         is_valid = B_TRUE;
 733                         break;
 734                 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
 735                         is_valid = efx_mask_is_prefix(m_size, m_buf);
 736                         break;
 737                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
 738                         is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
 739                             efx_mask_is_all_zeros(m_size, m_buf));
 740                         break;
 741                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
 742                         is_valid = efx_mask_is_all_ones(m_size, m_buf);
 743                         break;
 744                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
 745                 case MAE_FIELD_UNSUPPORTED:
 746                 default:
 747                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
 748                         break;
 749                 }
 750
 751                 if (is_valid == B_FALSE)
 752                         break;
 753         }
 754
 755         return (is_valid);
 756 }
 757
 758         __checkReturn                   efx_rc_t
 759 efx_mae_action_set_spec_init(
 760         __in                            efx_nic_t *enp,
 761         __out                           efx_mae_actions_t **specp)
 762 {
 763         efx_mae_actions_t *spec;
 764         efx_rc_t rc;
 765
 766         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 767         if (spec == NULL) {
 768                 rc = ENOMEM;
 769                 goto fail1;
 770         }
 771
 772         *specp = spec;
 773
 774         return (0);
 775
 776 fail1:
 777         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 778         return (rc);
 779 }
 780
 781                                         void
 782 efx_mae_action_set_spec_fini(
 783         __in                            efx_nic_t *enp,
 784         __in                            efx_mae_actions_t *spec)
 785 {
 786         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 787 }
 788
 789 static  __checkReturn                   efx_rc_t
 790 efx_mae_action_set_add_vlan_pop(
 791         __in                            efx_mae_actions_t *spec,
 792         __in                            size_t arg_size,
 793         __in_bcount(arg_size)           const uint8_t *arg)
 794 {
 795         efx_rc_t rc;
 796
 797         if (arg_size != 0) {
 798                 rc = EINVAL;
 799                 goto fail1;
 800         }
 801
 802         if (arg != NULL) {
 803                 rc = EINVAL;
 804                 goto fail2;
 805         }
 806
 807         if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
 808                 rc = ENOTSUP;
 809                 goto fail3;
 810         }
 811
 812         ++spec->ema_n_vlan_tags_to_pop;
 813
 814         return (0);
 815
 816 fail3:
 817         EFSYS_PROBE(fail3);
 818 fail2:
 819         EFSYS_PROBE(fail2);
 820 fail1:
 821         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 822         return (rc);
 823 }
 824
 825 static  __checkReturn                   efx_rc_t
 826 efx_mae_action_set_add_vlan_push(
 827         __in                            efx_mae_actions_t *spec,
 828         __in                            size_t arg_size,
 829         __in_bcount(arg_size)           const uint8_t *arg)
 830 {
 831         unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
 832         efx_rc_t rc;
 833
 834         if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
 835                 rc = EINVAL;
 836                 goto fail1;
 837         }
 838
 839         if (arg == NULL) {
 840                 rc = EINVAL;
 841                 goto fail2;
 842         }
 843
 844         if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
 845                 rc = ENOTSUP;
 846                 goto fail3;
 847         }
 848
 849         memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
 850         ++(spec->ema_n_vlan_tags_to_push);
 851
 852         return (0);
 853
 854 fail3:
 855         EFSYS_PROBE(fail3);
 856 fail2:
 857         EFSYS_PROBE(fail2);
 858 fail1:
 859         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 860         return (rc);
 861 }
 862
 863 static  __checkReturn                   efx_rc_t
 864 efx_mae_action_set_add_flag(
 865         __in                            efx_mae_actions_t *spec,
 866         __in                            size_t arg_size,
 867         __in_bcount(arg_size)           const uint8_t *arg)
 868 {
 869         efx_rc_t rc;
 870
 871         _NOTE(ARGUNUSED(spec))
 872
 873         if (arg_size != 0) {
 874                 rc = EINVAL;
 875                 goto fail1;
 876         }
 877
 878         if (arg != NULL) {
 879                 rc = EINVAL;
 880                 goto fail2;
 881         }
 882
 883         /* This action does not have any arguments, so do nothing here. */
 884
 885         return (0);
 886
 887 fail2:
 888         EFSYS_PROBE(fail2);
 889 fail1:
 890         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 891         return (rc);
 892 }
 893
 894 static  __checkReturn                   efx_rc_t
 895 efx_mae_action_set_add_mark(
 896         __in                            efx_mae_actions_t *spec,
 897         __in                            size_t arg_size,
 898         __in_bcount(arg_size)           const uint8_t *arg)
 899 {
 900         efx_rc_t rc;
 901
 902         if (arg_size != sizeof (spec->ema_mark_value)) {
 903                 rc = EINVAL;
 904                 goto fail1;
 905         }
 906
 907         if (arg == NULL) {
 908                 rc = EINVAL;
 909                 goto fail2;
 910         }
 911
 912         memcpy(&spec->ema_mark_value, arg, arg_size);
 913
 914         return (0);
 915
 916 fail2:
 917         EFSYS_PROBE(fail2);
 918 fail1:
 919         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 920         return (rc);
 921 }
 922
 923 static  __checkReturn                   efx_rc_t
 924 efx_mae_action_set_add_deliver(
 925         __in                            efx_mae_actions_t *spec,
 926         __in                            size_t arg_size,
 927         __in_bcount(arg_size)           const uint8_t *arg)
 928 {
 929         efx_rc_t rc;
 930
 931         if (arg_size != sizeof (spec->ema_deliver_mport)) {
 932                 rc = EINVAL;
 933                 goto fail1;
 934         }
 935
 936         if (arg == NULL) {
 937                 rc = EINVAL;
 938                 goto fail2;
 939         }
 940
 941         memcpy(&spec->ema_deliver_mport, arg, arg_size);
 942
 943         return (0);
 944
 945 fail2:
 946         EFSYS_PROBE(fail2);
 947 fail1:
 948         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 949         return (rc);
 950 }
 951
 952 typedef struct efx_mae_action_desc_s {
 953         /* Action specific handler */
 954         efx_rc_t        (*emad_add)(efx_mae_actions_t *,
 955                                     size_t, const uint8_t *);
 956 } efx_mae_action_desc_t;
 957
 958 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
 959         [EFX_MAE_ACTION_VLAN_POP] = {
 960                 .emad_add = efx_mae_action_set_add_vlan_pop
 961         },
 962         [EFX_MAE_ACTION_VLAN_PUSH] = {
 963                 .emad_add = efx_mae_action_set_add_vlan_push
 964         },
 965         [EFX_MAE_ACTION_FLAG] = {
 966                 .emad_add = efx_mae_action_set_add_flag
 967         },
 968         [EFX_MAE_ACTION_MARK] = {
 969                 .emad_add = efx_mae_action_set_add_mark
 970         },
 971         [EFX_MAE_ACTION_DELIVER] = {
 972                 .emad_add = efx_mae_action_set_add_deliver
 973         }
 974 };
 975
 976 static const uint32_t efx_mae_action_ordered_map =
 977         (1U << EFX_MAE_ACTION_VLAN_POP) |
 978         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
 979         (1U << EFX_MAE_ACTION_FLAG) |
 980         (1U << EFX_MAE_ACTION_MARK) |
 981         (1U << EFX_MAE_ACTION_DELIVER);
 982
 983 /*
 984  * These actions must not be added after DELIVER, but
 985  * they can have any place among the rest of
 986  * strictly ordered actions.
 987  */
 988 static const uint32_t efx_mae_action_nonstrict_map =
 989         (1U << EFX_MAE_ACTION_FLAG) |
 990         (1U << EFX_MAE_ACTION_MARK);
 991
 992 static const uint32_t efx_mae_action_repeat_map =
 993         (1U << EFX_MAE_ACTION_VLAN_POP) |
 994         (1U << EFX_MAE_ACTION_VLAN_PUSH);
 995
 996 /*
 997  * Add an action to an action set.
 998  *
 999  * This has to be invoked in the desired action order.
1000  * An out-of-order action request will be turned down.
1001  */
1002 static  __checkReturn                   efx_rc_t
1003 efx_mae_action_set_spec_populate(
1004         __in                            efx_mae_actions_t *spec,
1005         __in                            efx_mae_action_t type,
1006         __in                            size_t arg_size,
1007         __in_bcount(arg_size)           const uint8_t *arg)
1008 {
1009         uint32_t action_mask;
1010         efx_rc_t rc;
1011
1012         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1013             (sizeof (efx_mae_action_ordered_map) * 8));
1014         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1015             (sizeof (efx_mae_action_repeat_map) * 8));
1016
1017         EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1018         EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1019         EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1020
1021         if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1022                 rc = EINVAL;
1023                 goto fail1;
1024         }
1025
1026         action_mask = (1U << type);
1027
1028         if ((spec->ema_actions & action_mask) != 0) {
1029                 /* The action set already contains this action. */
1030                 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1031                         /* Cannot add another non-repeatable action. */
1032                         rc = ENOTSUP;
1033                         goto fail2;
1034                 }
1035         }
1036
1037         if ((efx_mae_action_ordered_map & action_mask) != 0) {
1038                 uint32_t strict_ordered_map =
1039                     efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1040                 uint32_t later_actions_mask =
1041                     strict_ordered_map & ~(action_mask | (action_mask - 1));
1042
1043                 if ((spec->ema_actions & later_actions_mask) != 0) {
1044                         /* Cannot add an action after later ordered actions. */
1045                         rc = ENOTSUP;
1046                         goto fail3;
1047                 }
1048         }
1049
1050         if (efx_mae_actions[type].emad_add != NULL) {
1051                 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1052                 if (rc != 0)
1053                         goto fail4;
1054         }
1055
1056         spec->ema_actions |= action_mask;
1057
1058         return (0);
1059
1060 fail4:
1061         EFSYS_PROBE(fail4);
1062 fail3:
1063         EFSYS_PROBE(fail3);
1064 fail2:
1065         EFSYS_PROBE(fail2);
1066 fail1:
1067         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1068         return (rc);
1069 }
1070
1071         __checkReturn                   efx_rc_t
1072 efx_mae_action_set_populate_vlan_pop(
1073         __in                            efx_mae_actions_t *spec)
1074 {
1075         return (efx_mae_action_set_spec_populate(spec,
1076             EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1077 }
1078
1079         __checkReturn                   efx_rc_t
1080 efx_mae_action_set_populate_vlan_push(
1081         __in                            efx_mae_actions_t *spec,
1082         __in                            uint16_t tpid_be,
1083         __in                            uint16_t tci_be)
1084 {
1085         efx_mae_action_vlan_push_t action;
1086         const uint8_t *arg = (const uint8_t *)&action;
1087
1088         action.emavp_tpid_be = tpid_be;
1089         action.emavp_tci_be = tci_be;
1090
1091         return (efx_mae_action_set_spec_populate(spec,
1092             EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1093 }
1094
1095         __checkReturn                   efx_rc_t
1096 efx_mae_action_set_populate_flag(
1097         __in                            efx_mae_actions_t *spec)
1098 {
1099         return (efx_mae_action_set_spec_populate(spec,
1100             EFX_MAE_ACTION_FLAG, 0, NULL));
1101 }
1102
1103         __checkReturn                   efx_rc_t
1104 efx_mae_action_set_populate_mark(
1105         __in                            efx_mae_actions_t *spec,
1106         __in                            uint32_t mark_value)
1107 {
1108         const uint8_t *arg = (const uint8_t *)&mark_value;
1109
1110         return (efx_mae_action_set_spec_populate(spec,
1111             EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1112 }
1113
1114         __checkReturn                   efx_rc_t
1115 efx_mae_action_set_populate_deliver(
1116         __in                            efx_mae_actions_t *spec,
1117         __in                            const efx_mport_sel_t *mportp)
1118 {
1119         const uint8_t *arg;
1120         efx_rc_t rc;
1121
1122         if (mportp == NULL) {
1123                 rc = EINVAL;
1124                 goto fail1;
1125         }
1126
1127         arg = (const uint8_t *)&mportp->sel;
1128
1129         return (efx_mae_action_set_spec_populate(spec,
1130             EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1131
1132 fail1:
1133         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1134         return (rc);
1135 }
1136
1137         __checkReturn                   efx_rc_t
1138 efx_mae_action_set_populate_drop(
1139         __in                            efx_mae_actions_t *spec)
1140 {
1141         efx_mport_sel_t mport;
1142         const uint8_t *arg;
1143         efx_dword_t dword;
1144
1145         EFX_POPULATE_DWORD_1(dword,
1146             MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1147
1148         mport.sel = dword.ed_u32[0];
1149
1150         arg = (const uint8_t *)&mport.sel;
1151
1152         return (efx_mae_action_set_spec_populate(spec,
1153             EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1154 }
1155
1156         __checkReturn                   boolean_t
1157 efx_mae_action_set_specs_equal(
1158         __in                            const efx_mae_actions_t *left,
1159         __in                            const efx_mae_actions_t *right)
1160 {
1161         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1162 }
1163
1164         __checkReturn                   efx_rc_t
1165 efx_mae_match_specs_class_cmp(
1166         __in                            efx_nic_t *enp,
1167         __in                            const efx_mae_match_spec_t *left,
1168         __in                            const efx_mae_match_spec_t *right,
1169         __out                           boolean_t *have_same_classp)
1170 {
1171         efx_mae_t *maep = enp->en_maep;
1172         unsigned int field_ncaps = maep->em_max_nfields;
1173         const efx_mae_field_cap_t *field_caps;
1174         const efx_mae_mv_desc_t *desc_setp;
1175         unsigned int desc_set_nentries;
1176         boolean_t have_same_class = B_TRUE;
1177         efx_mae_field_id_t field_id;
1178         const uint8_t *mvpl;
1179         const uint8_t *mvpr;
1180         efx_rc_t rc;
1181
1182         switch (left->emms_type) {
1183         case EFX_MAE_RULE_ACTION:
1184                 field_caps = maep->em_action_rule_field_caps;
1185                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1186                 desc_set_nentries =
1187                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1188                 mvpl = left->emms_mask_value_pairs.action;
1189                 mvpr = right->emms_mask_value_pairs.action;
1190                 break;
1191         default:
1192                 rc = ENOTSUP;
1193                 goto fail1;
1194         }
1195
1196         if (field_caps == NULL) {
1197                 rc = EAGAIN;
1198                 goto fail2;
1199         }
1200
1201         if (left->emms_type != right->emms_type ||
1202             left->emms_prio != right->emms_prio) {
1203                 /*
1204                  * Rules of different types can never map to the same class.
1205                  *
1206                  * The FW can support some set of match criteria for one
1207                  * priority and not support the very same set for
1208                  * another priority. Thus, two rules which have
1209                  * different priorities can never map to
1210                  * the same class.
1211                  */
1212                 *have_same_classp = B_FALSE;
1213                 return (0);
1214         }
1215
1216         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
1217                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1218                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1219
1220                 if (descp->emmd_mask_size == 0)
1221                         continue; /* Skip array gap */
1222
1223                 if (field_cap_id >= field_ncaps)
1224                         break;
1225
1226                 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1227                         const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1228                         const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1229                         size_t mask_size = descp->emmd_mask_size;
1230
1231                         if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1232                                 have_same_class = B_FALSE;
1233                                 break;
1234                         }
1235                 }
1236
1237                 if (field_caps[field_cap_id].emfc_match_affects_class) {
1238                         const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1239                         const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1240                         size_t value_size = descp->emmd_value_size;
1241
1242                         if (memcmp(lvalp, rvalp, value_size) != 0) {
1243                                 have_same_class = B_FALSE;
1244                                 break;
1245                         }
1246                 }
1247         }
1248
1249         *have_same_classp = have_same_class;
1250
1251         return (0);
1252
1253 fail2:
1254         EFSYS_PROBE(fail2);
1255 fail1:
1256         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1257         return (rc);
1258 }
1259
1260         __checkReturn                   efx_rc_t
1261 efx_mae_action_set_alloc(
1262         __in                            efx_nic_t *enp,
1263         __in                            const efx_mae_actions_t *spec,
1264         __out                           efx_mae_aset_id_t *aset_idp)
1265 {
1266         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1267         efx_mcdi_req_t req;
1268         EFX_MCDI_DECLARE_BUF(payload,
1269             MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1270             MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1271         efx_mae_aset_id_t aset_id;
1272         efx_rc_t rc;
1273
1274         if (encp->enc_mae_supported == B_FALSE) {
1275                 rc = ENOTSUP;
1276                 goto fail1;
1277         }
1278
1279         req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1280         req.emr_in_buf = payload;
1281         req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1282         req.emr_out_buf = payload;
1283         req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1284
1285         /*
1286          * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1287          * corresponding resource types are supported by the implementation.
1288          * Use proper resource ID assignments instead.
1289          */
1290         MCDI_IN_SET_DWORD(req,
1291             MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1292         MCDI_IN_SET_DWORD(req,
1293             MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1294         MCDI_IN_SET_DWORD(req,
1295             MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1296
1297         MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1298             MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1299
1300         if (spec->ema_n_vlan_tags_to_push > 0) {
1301                 unsigned int outer_tag_idx;
1302
1303                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1304                     MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1305                     spec->ema_n_vlan_tags_to_push);
1306
1307                 if (spec->ema_n_vlan_tags_to_push ==
1308                     EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1309                         MCDI_IN_SET_WORD(req,
1310                             MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1311                             spec->ema_vlan_push_descs[0].emavp_tpid_be);
1312                         MCDI_IN_SET_WORD(req,
1313                             MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1314                             spec->ema_vlan_push_descs[0].emavp_tci_be);
1315                 }
1316
1317                 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1318
1319                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1320                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1321                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1322                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1323         }
1324
1325         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1326                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1327                     MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1328         }
1329
1330         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1331                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1332                     MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1333
1334                 MCDI_IN_SET_DWORD(req,
1335                     MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1336         }
1337
1338         MCDI_IN_SET_DWORD(req,
1339             MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1340
1341         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1342             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1343         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1344             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1345
1346         efx_mcdi_execute(enp, &req);
1347
1348         if (req.emr_rc != 0) {
1349                 rc = req.emr_rc;
1350                 goto fail2;
1351         }
1352
1353         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1354                 rc = EMSGSIZE;
1355                 goto fail3;
1356         }
1357
1358         aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1359         if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1360                 rc = ENOENT;
1361                 goto fail4;
1362         }
1363
1364         aset_idp->id = aset_id.id;
1365
1366         return (0);
1367
1368 fail4:
1369         EFSYS_PROBE(fail4);
1370 fail3:
1371         EFSYS_PROBE(fail3);
1372 fail2:
1373         EFSYS_PROBE(fail2);
1374 fail1:
1375         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1376         return (rc);
1377 }
1378
1379         __checkReturn                   efx_rc_t
1380 efx_mae_action_set_free(
1381         __in                            efx_nic_t *enp,
1382         __in                            const efx_mae_aset_id_t *aset_idp)
1383 {
1384         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1385         efx_mcdi_req_t req;
1386         EFX_MCDI_DECLARE_BUF(payload,
1387             MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1388             MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1389         efx_rc_t rc;
1390
1391         if (encp->enc_mae_supported == B_FALSE) {
1392                 rc = ENOTSUP;
1393                 goto fail1;
1394         }
1395
1396         req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1397         req.emr_in_buf = payload;
1398         req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1399         req.emr_out_buf = payload;
1400         req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1401
1402         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1403
1404         efx_mcdi_execute(enp, &req);
1405
1406         if (req.emr_rc != 0) {
1407                 rc = req.emr_rc;
1408                 goto fail2;
1409         }
1410
1411         if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1412             aset_idp->id) {
1413                 /* Firmware failed to free the action set. */
1414                 rc = EAGAIN;
1415                 goto fail3;
1416         }
1417
1418         return (0);
1419
1420 fail3:
1421         EFSYS_PROBE(fail3);
1422 fail2:
1423         EFSYS_PROBE(fail2);
1424 fail1:
1425         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1426         return (rc);
1427 }
1428
1429         __checkReturn                   efx_rc_t
1430 efx_mae_action_rule_insert(
1431         __in                            efx_nic_t *enp,
1432         __in                            const efx_mae_match_spec_t *spec,
1433         __in                            const efx_mae_aset_list_id_t *asl_idp,
1434         __in                            const efx_mae_aset_id_t *as_idp,
1435         __out                           efx_mae_rule_id_t *ar_idp)
1436 {
1437         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1438         efx_mcdi_req_t req;
1439         EFX_MCDI_DECLARE_BUF(payload,
1440             MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1441             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1442         efx_oword_t *rule_response;
1443         efx_mae_rule_id_t ar_id;
1444         size_t offset;
1445         efx_rc_t rc;
1446
1447         EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1448             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1449
1450         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1451             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1452
1453         if (encp->enc_mae_supported == B_FALSE) {
1454                 rc = ENOTSUP;
1455                 goto fail1;
1456         }
1457
1458         if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1459             (asl_idp != NULL && as_idp != NULL) ||
1460             (asl_idp == NULL && as_idp == NULL)) {
1461                 rc = EINVAL;
1462                 goto fail2;
1463         }
1464
1465         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1466         req.emr_in_buf = payload;
1467         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1468         req.emr_out_buf = payload;
1469         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1470
1471         EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1472             MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1473         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1474         rule_response = (efx_oword_t *)(payload + offset);
1475         EFX_POPULATE_OWORD_3(*rule_response,
1476             MAE_ACTION_RULE_RESPONSE_ASL_ID,
1477             (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1478             MAE_ACTION_RULE_RESPONSE_AS_ID,
1479             (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1480             MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1481
1482         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1483
1484         /*
1485          * Mask-value pairs have been stored in the byte order needed for the
1486          * MCDI request and are thus safe to be copied directly to the buffer.
1487          */
1488         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1489             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1490         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1491         memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1492             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1493
1494         efx_mcdi_execute(enp, &req);
1495
1496         if (req.emr_rc != 0) {
1497                 rc = req.emr_rc;
1498                 goto fail3;
1499         }
1500
1501         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1502                 rc = EMSGSIZE;
1503                 goto fail4;
1504         }
1505
1506         ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1507         if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1508                 rc = ENOENT;
1509                 goto fail5;
1510         }
1511
1512         ar_idp->id = ar_id.id;
1513
1514         return (0);
1515
1516 fail5:
1517         EFSYS_PROBE(fail5);
1518 fail4:
1519         EFSYS_PROBE(fail4);
1520 fail3:
1521         EFSYS_PROBE(fail3);
1522 fail2:
1523         EFSYS_PROBE(fail2);
1524 fail1:
1525         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1526         return (rc);
1527 }
1528
1529         __checkReturn                   efx_rc_t
1530 efx_mae_action_rule_remove(
1531         __in                            efx_nic_t *enp,
1532         __in                            const efx_mae_rule_id_t *ar_idp)
1533 {
1534         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1535         efx_mcdi_req_t req;
1536         EFX_MCDI_DECLARE_BUF(payload,
1537             MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1538             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1539         efx_rc_t rc;
1540
1541         if (encp->enc_mae_supported == B_FALSE) {
1542                 rc = ENOTSUP;
1543                 goto fail1;
1544         }
1545
1546         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1547         req.emr_in_buf = payload;
1548         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1549         req.emr_out_buf = payload;
1550         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1551
1552         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1553
1554         efx_mcdi_execute(enp, &req);
1555
1556         if (req.emr_rc != 0) {
1557                 rc = req.emr_rc;
1558                 goto fail2;
1559         }
1560
1561         if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1562             ar_idp->id) {
1563                 /* Firmware failed to delete the action rule. */
1564                 rc = EAGAIN;
1565                 goto fail3;
1566         }
1567
1568         return (0);
1569
1570 fail3:
1571         EFSYS_PROBE(fail3);
1572 fail2:
1573         EFSYS_PROBE(fail2);
1574 fail1:
1575         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1576         return (rc);
1577 }
1578
1579 #endif /* EFSYS_OPT_MAE */