drivers/common/sfc_efx/base/efx_mae.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_MAE
  12
  13 static  __checkReturn                   efx_rc_t
  14 efx_mae_get_capabilities(
  15         __in                            efx_nic_t *enp)
  16 {
  17         efx_mcdi_req_t req;
  18         EFX_MCDI_DECLARE_BUF(payload,
  19             MC_CMD_MAE_GET_CAPS_IN_LEN,
  20             MC_CMD_MAE_GET_CAPS_OUT_LEN);
  21         struct efx_mae_s *maep = enp->en_maep;
  22         efx_rc_t rc;
  23
  24         req.emr_cmd = MC_CMD_MAE_GET_CAPS;
  25         req.emr_in_buf = payload;
  26         req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
  27         req.emr_out_buf = payload;
  28         req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
  29
  30         efx_mcdi_execute(enp, &req);
  31
  32         if (req.emr_rc != 0) {
  33                 rc = req.emr_rc;
  34                 goto fail1;
  35         }
  36
  37         if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
  38                 rc = EMSGSIZE;
  39                 goto fail2;
  40         }
  41
  42         maep->em_max_n_outer_prios =
  43             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
  44
  45         maep->em_max_n_action_prios =
  46             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
  47
  48         maep->em_encap_types_supported = 0;
  49
  50         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
  51                 maep->em_encap_types_supported |=
  52                     (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
  53         }
  54
  55         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
  56                 maep->em_encap_types_supported |=
  57                     (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
  58         }
  59
  60         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
  61                 maep->em_encap_types_supported |=
  62                     (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
  63         }
  64
  65         maep->em_max_nfields =
  66             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
  67
  68         return (0);
  69
  70 fail2:
  71         EFSYS_PROBE(fail2);
  72 fail1:
  73         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  74         return (rc);
  75 }
  76
  77 static  __checkReturn                   efx_rc_t
  78 efx_mae_get_action_rule_caps(
  79         __in                            efx_nic_t *enp,
  80         __in                            unsigned int field_ncaps,
  81         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
  82 {
  83         efx_mcdi_req_t req;
  84         EFX_MCDI_DECLARE_BUF(payload,
  85             MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
  86             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
  87         unsigned int mcdi_field_ncaps;
  88         unsigned int i;
  89         efx_rc_t rc;
  90
  91         if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
  92             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
  93                 rc = EINVAL;
  94                 goto fail1;
  95         }
  96
  97         req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
  98         req.emr_in_buf = payload;
  99         req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
 100         req.emr_out_buf = payload;
 101         req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
 102
 103         efx_mcdi_execute(enp, &req);
 104
 105         if (req.emr_rc != 0) {
 106                 rc = req.emr_rc;
 107                 goto fail2;
 108         }
 109
 110         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 111
 112         if (req.emr_out_length_used <
 113             MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 114                 rc = EMSGSIZE;
 115                 goto fail3;
 116         }
 117
 118         if (mcdi_field_ncaps > field_ncaps) {
 119                 rc = EMSGSIZE;
 120                 goto fail4;
 121         }
 122
 123         for (i = 0; i < mcdi_field_ncaps; ++i) {
 124                 uint32_t match_flag;
 125                 uint32_t mask_flag;
 126
 127                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 128                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 129                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 130
 131                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 132                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 133                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 134
 135                 field_caps[i].emfc_match_affects_class =
 136                     (match_flag != 0) ? B_TRUE : B_FALSE;
 137
 138                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 139                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 140                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 141
 142                 field_caps[i].emfc_mask_affects_class =
 143                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 144         }
 145
 146         return (0);
 147
 148 fail4:
 149         EFSYS_PROBE(fail4);
 150 fail3:
 151         EFSYS_PROBE(fail3);
 152 fail2:
 153         EFSYS_PROBE(fail2);
 154 fail1:
 155         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 156         return (rc);
 157 }
 158
 159         __checkReturn                   efx_rc_t
 160 efx_mae_init(
 161         __in                            efx_nic_t *enp)
 162 {
 163         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 164         efx_mae_field_cap_t *ar_fcaps;
 165         size_t ar_fcaps_size;
 166         efx_mae_t *maep;
 167         efx_rc_t rc;
 168
 169         if (encp->enc_mae_supported == B_FALSE) {
 170                 rc = ENOTSUP;
 171                 goto fail1;
 172         }
 173
 174         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
 175         if (maep == NULL) {
 176                 rc = ENOMEM;
 177                 goto fail2;
 178         }
 179
 180         enp->en_maep = maep;
 181
 182         rc = efx_mae_get_capabilities(enp);
 183         if (rc != 0)
 184                 goto fail3;
 185
 186         ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
 187         EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
 188         if (ar_fcaps == NULL) {
 189                 rc = ENOMEM;
 190                 goto fail4;
 191         }
 192
 193         maep->em_action_rule_field_caps_size = ar_fcaps_size;
 194         maep->em_action_rule_field_caps = ar_fcaps;
 195
 196         rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
 197         if (rc != 0)
 198                 goto fail5;
 199
 200         return (0);
 201
 202 fail5:
 203         EFSYS_PROBE(fail5);
 204         EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
 205 fail4:
 206         EFSYS_PROBE(fail4);
 207 fail3:
 208         EFSYS_PROBE(fail3);
 209         EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
 210         enp->en_maep = NULL;
 211 fail2:
 212         EFSYS_PROBE(fail2);
 213 fail1:
 214         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 215         return (rc);
 216 }
 217
 218                                         void
 219 efx_mae_fini(
 220         __in                            efx_nic_t *enp)
 221 {
 222         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 223         efx_mae_t *maep = enp->en_maep;
 224
 225         if (encp->enc_mae_supported == B_FALSE)
 226                 return;
 227
 228         EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
 229             maep->em_action_rule_field_caps);
 230         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
 231         enp->en_maep = NULL;
 232 }
 233
 234         __checkReturn                   efx_rc_t
 235 efx_mae_get_limits(
 236         __in                            efx_nic_t *enp,
 237         __out                           efx_mae_limits_t *emlp)
 238 {
 239         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 240         struct efx_mae_s *maep = enp->en_maep;
 241         efx_rc_t rc;
 242
 243         if (encp->enc_mae_supported == B_FALSE) {
 244                 rc = ENOTSUP;
 245                 goto fail1;
 246         }
 247
 248         emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
 249         emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
 250         emlp->eml_encap_types_supported = maep->em_encap_types_supported;
 251
 252         return (0);
 253
 254 fail1:
 255         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 256         return (rc);
 257 }
 258
 259         __checkReturn                   efx_rc_t
 260 efx_mae_match_spec_init(
 261         __in                            efx_nic_t *enp,
 262         __in                            efx_mae_rule_type_t type,
 263         __in                            uint32_t prio,
 264         __out                           efx_mae_match_spec_t **specp)
 265 {
 266         efx_mae_match_spec_t *spec;
 267         efx_rc_t rc;
 268
 269         switch (type) {
 270         case EFX_MAE_RULE_OUTER:
 271                 break;
 272         case EFX_MAE_RULE_ACTION:
 273                 break;
 274         default:
 275                 rc = ENOTSUP;
 276                 goto fail1;
 277         }
 278
 279         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 280         if (spec == NULL) {
 281                 rc = ENOMEM;
 282                 goto fail2;
 283         }
 284
 285         spec->emms_type = type;
 286         spec->emms_prio = prio;
 287
 288         *specp = spec;
 289
 290         return (0);
 291
 292 fail2:
 293         EFSYS_PROBE(fail2);
 294 fail1:
 295         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 296         return (rc);
 297 }
 298
 299                                         void
 300 efx_mae_match_spec_fini(
 301         __in                            efx_nic_t *enp,
 302         __in                            efx_mae_match_spec_t *spec)
 303 {
 304         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 305 }
 306
 307 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
 308 typedef enum efx_mae_field_cap_id_e {
 309         EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
 310         EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
 311         EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
 312         EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
 313         EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
 314         EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
 315         EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
 316         EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
 317         EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
 318         EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
 319         EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
 320         EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
 321         EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
 322         EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
 323         EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
 324         EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
 325         EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
 326         EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
 327         EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
 328         EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
 329         EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
 330         EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
 331         EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
 332         EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
 333         EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
 334         EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
 335         EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
 336         EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
 337         EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
 338         EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
 339         EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
 340         EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
 341         EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
 342         EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 343         EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
 344
 345         EFX_MAE_FIELD_CAP_NIDS
 346 } efx_mae_field_cap_id_t;
 347
 348 typedef enum efx_mae_field_endianness_e {
 349         EFX_MAE_FIELD_LE = 0,
 350         EFX_MAE_FIELD_BE,
 351
 352         EFX_MAE_FIELD_ENDIANNESS_NTYPES
 353 } efx_mae_field_endianness_t;
 354
 355 /*
 356  * The following structure is a means to describe an MAE field.
 357  * The information in it is meant to be used internally by
 358  * APIs for addressing a given field in a mask-value pairs
 359  * structure and for validation purposes.
 360  */
 361 typedef struct efx_mae_mv_desc_s {
 362         efx_mae_field_cap_id_t          emmd_field_cap_id;
 363
 364         size_t                          emmd_value_size;
 365         size_t                          emmd_value_offset;
 366         size_t                          emmd_mask_size;
 367         size_t                          emmd_mask_offset;
 368
 369         efx_mae_field_endianness_t      emmd_endianness;
 370 } efx_mae_mv_desc_t;
 371
 372 /* Indices to this array are provided by efx_mae_field_id_t */
 373 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 374 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 375         [EFX_MAE_FIELD_##_name] =                                       \
 376         {                                                               \
 377                 EFX_MAE_FIELD_ID_##_name,                               \
 378                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,               \
 379                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,              \
 380                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,          \
 381                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,         \
 382                 _endianness                                             \
 383         }
 384
 385         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 386         EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 387         EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 388         EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 389         EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 390         EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 391         EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 392         EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 393         EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
 394         EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
 395         EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
 396         EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
 397         EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
 398         EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
 399         EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
 400         EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
 401         EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
 402         EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 403         EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
 404
 405 #undef EFX_MAE_MV_DESC
 406 };
 407
 408 /* Indices to this array are provided by efx_mae_field_id_t */
 409 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 410 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 411         [EFX_MAE_FIELD_##_name] =                                       \
 412         {                                                               \
 413                 EFX_MAE_FIELD_ID_##_name,                               \
 414                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 415                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 416                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 417                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 418                 _endianness                                             \
 419         }
 420
 421         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 422         EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 423         EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 424         EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 425         EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 426         EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 427         EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 428         EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 429         EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
 430         EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 431         EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 432         EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 433         EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
 434         EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
 435         EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 436         EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 437         EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 438
 439 #undef EFX_MAE_MV_DESC
 440 };
 441
 442         __checkReturn                   efx_rc_t
 443 efx_mae_mport_by_phy_port(
 444         __in                            uint32_t phy_port,
 445         __out                           efx_mport_sel_t *mportp)
 446 {
 447         efx_dword_t dword;
 448         efx_rc_t rc;
 449
 450         if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
 451                 rc = EINVAL;
 452                 goto fail1;
 453         }
 454
 455         EFX_POPULATE_DWORD_2(dword,
 456             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
 457             MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 458
 459         memset(mportp, 0, sizeof (*mportp));
 460         mportp->sel = dword.ed_u32[0];
 461
 462         return (0);
 463
 464 fail1:
 465         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 466         return (rc);
 467 }
 468
 469         __checkReturn                   efx_rc_t
 470 efx_mae_mport_by_pcie_function(
 471         __in                            uint32_t pf,
 472         __in                            uint32_t vf,
 473         __out                           efx_mport_sel_t *mportp)
 474 {
 475         efx_dword_t dword;
 476         efx_rc_t rc;
 477
 478         EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
 479             MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
 480
 481         if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
 482                 rc = EINVAL;
 483                 goto fail1;
 484         }
 485
 486         if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
 487                 rc = EINVAL;
 488                 goto fail2;
 489         }
 490
 491         EFX_POPULATE_DWORD_3(dword,
 492             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
 493             MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
 494             MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 495
 496         memset(mportp, 0, sizeof (*mportp));
 497         mportp->sel = dword.ed_u32[0];
 498
 499         return (0);
 500
 501 fail2:
 502         EFSYS_PROBE(fail2);
 503 fail1:
 504         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 505         return (rc);
 506 }
 507
 508         __checkReturn                   efx_rc_t
 509 efx_mae_match_spec_field_set(
 510         __in                            efx_mae_match_spec_t *spec,
 511         __in                            efx_mae_field_id_t field_id,
 512         __in                            size_t value_size,
 513         __in_bcount(value_size)         const uint8_t *value,
 514         __in                            size_t mask_size,
 515         __in_bcount(mask_size)          const uint8_t *mask)
 516 {
 517         const efx_mae_mv_desc_t *descp;
 518         uint8_t *mvp;
 519         efx_rc_t rc;
 520
 521         if (field_id >= EFX_MAE_FIELD_NIDS) {
 522                 rc = EINVAL;
 523                 goto fail1;
 524         }
 525
 526         switch (spec->emms_type) {
 527         case EFX_MAE_RULE_OUTER:
 528                 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
 529                 mvp = spec->emms_mask_value_pairs.outer;
 530                 break;
 531         case EFX_MAE_RULE_ACTION:
 532                 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
 533                 mvp = spec->emms_mask_value_pairs.action;
 534                 break;
 535         default:
 536                 rc = ENOTSUP;
 537                 goto fail2;
 538         }
 539
 540         if (value_size != descp->emmd_value_size) {
 541                 rc = EINVAL;
 542                 goto fail3;
 543         }
 544
 545         if (mask_size != descp->emmd_mask_size) {
 546                 rc = EINVAL;
 547                 goto fail4;
 548         }
 549
 550         if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
 551                 /*
 552                  * The mask/value are in network (big endian) order.
 553                  * The MCDI request field is also big endian.
 554                  */
 555                 memcpy(mvp + descp->emmd_value_offset, value, value_size);
 556                 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
 557         } else {
 558                 efx_dword_t dword;
 559
 560                 /*
 561                  * The mask/value are in host byte order.
 562                  * The MCDI request field is little endian.
 563                  */
 564                 switch (value_size) {
 565                 case 4:
 566                         EFX_POPULATE_DWORD_1(dword,
 567                             EFX_DWORD_0, *(const uint32_t *)value);
 568
 569                         memcpy(mvp + descp->emmd_value_offset,
 570                             &dword, sizeof (dword));
 571                         break;
 572                 default:
 573                         EFSYS_ASSERT(B_FALSE);
 574                 }
 575
 576                 switch (mask_size) {
 577                 case 4:
 578                         EFX_POPULATE_DWORD_1(dword,
 579                             EFX_DWORD_0, *(const uint32_t *)mask);
 580
 581                         memcpy(mvp + descp->emmd_mask_offset,
 582                             &dword, sizeof (dword));
 583                         break;
 584                 default:
 585                         EFSYS_ASSERT(B_FALSE);
 586                 }
 587         }
 588
 589         return (0);
 590
 591 fail4:
 592         EFSYS_PROBE(fail4);
 593 fail3:
 594         EFSYS_PROBE(fail3);
 595 fail2:
 596         EFSYS_PROBE(fail2);
 597 fail1:
 598         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 599         return (rc);
 600 }
 601
 602         __checkReturn                   efx_rc_t
 603 efx_mae_match_spec_mport_set(
 604         __in                            efx_mae_match_spec_t *spec,
 605         __in                            const efx_mport_sel_t *valuep,
 606         __in_opt                        const efx_mport_sel_t *maskp)
 607 {
 608         uint32_t full_mask = UINT32_MAX;
 609         const uint8_t *vp;
 610         const uint8_t *mp;
 611         efx_rc_t rc;
 612
 613         if (valuep == NULL) {
 614                 rc = EINVAL;
 615                 goto fail1;
 616         }
 617
 618         vp = (const uint8_t *)&valuep->sel;
 619         if (maskp != NULL)
 620                 mp = (const uint8_t *)&maskp->sel;
 621         else
 622                 mp = (const uint8_t *)&full_mask;
 623
 624         rc = efx_mae_match_spec_field_set(spec,
 625             EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
 626             sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
 627         if (rc != 0)
 628                 goto fail2;
 629
 630         return (0);
 631
 632 fail2:
 633         EFSYS_PROBE(fail2);
 634 fail1:
 635         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 636         return (rc);
 637 }
 638
 639         __checkReturn                   boolean_t
 640 efx_mae_match_specs_equal(
 641         __in                            const efx_mae_match_spec_t *left,
 642         __in                            const efx_mae_match_spec_t *right)
 643 {
 644         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
 645 }
 646
 647 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)              \
 648             ((_mask)[(_bit) / (_mask_page_nbits)] &                     \
 649                     (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
 650
 651 static inline                           boolean_t
 652 efx_mask_is_prefix(
 653         __in                            size_t mask_nbytes,
 654         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 655 {
 656         boolean_t prev_bit_is_set = B_TRUE;
 657         unsigned int i;
 658
 659         for (i = 0; i < 8 * mask_nbytes; ++i) {
 660                 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
 661
 662                 if (!prev_bit_is_set && bit_is_set)
 663                         return B_FALSE;
 664
 665                 prev_bit_is_set = bit_is_set;
 666         }
 667
 668         return B_TRUE;
 669 }
 670
 671 static inline                           boolean_t
 672 efx_mask_is_all_ones(
 673         __in                            size_t mask_nbytes,
 674         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 675 {
 676         unsigned int i;
 677         uint8_t t = ~0;
 678
 679         for (i = 0; i < mask_nbytes; ++i)
 680                 t &= maskp[i];
 681
 682         return (t == (uint8_t)(~0));
 683 }
 684
 685 static inline                           boolean_t
 686 efx_mask_is_all_zeros(
 687         __in                            size_t mask_nbytes,
 688         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 689 {
 690         unsigned int i;
 691         uint8_t t = 0;
 692
 693         for (i = 0; i < mask_nbytes; ++i)
 694                 t |= maskp[i];
 695
 696         return (t == 0);
 697 }
 698
 699         __checkReturn                   boolean_t
 700 efx_mae_match_spec_is_valid(
 701         __in                            efx_nic_t *enp,
 702         __in                            const efx_mae_match_spec_t *spec)
 703 {
 704         efx_mae_t *maep = enp->en_maep;
 705         unsigned int field_ncaps = maep->em_max_nfields;
 706         const efx_mae_field_cap_t *field_caps;
 707         const efx_mae_mv_desc_t *desc_setp;
 708         unsigned int desc_set_nentries;
 709         boolean_t is_valid = B_TRUE;
 710         efx_mae_field_id_t field_id;
 711         const uint8_t *mvp;
 712
 713         switch (spec->emms_type) {
 714         case EFX_MAE_RULE_ACTION:
 715                 field_caps = maep->em_action_rule_field_caps;
 716                 desc_setp = __efx_mae_action_rule_mv_desc_set;
 717                 desc_set_nentries =
 718                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 719                 mvp = spec->emms_mask_value_pairs.action;
 720                 break;
 721         default:
 722                 return (B_FALSE);
 723         }
 724
 725         if (field_caps == NULL)
 726                 return (B_FALSE);
 727
 728         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
 729                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 730                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
 731                 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
 732                 size_t m_size = descp->emmd_mask_size;
 733
 734                 if (m_size == 0)
 735                         continue; /* Skip array gap */
 736
 737                 if (field_cap_id >= field_ncaps)
 738                         break;
 739
 740                 switch (field_caps[field_cap_id].emfc_support) {
 741                 case MAE_FIELD_SUPPORTED_MATCH_MASK:
 742                         is_valid = B_TRUE;
 743                         break;
 744                 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
 745                         is_valid = efx_mask_is_prefix(m_size, m_buf);
 746                         break;
 747                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
 748                         is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
 749                             efx_mask_is_all_zeros(m_size, m_buf));
 750                         break;
 751                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
 752                         is_valid = efx_mask_is_all_ones(m_size, m_buf);
 753                         break;
 754                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
 755                 case MAE_FIELD_UNSUPPORTED:
 756                 default:
 757                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
 758                         break;
 759                 }
 760
 761                 if (is_valid == B_FALSE)
 762                         break;
 763         }
 764
 765         return (is_valid);
 766 }
 767
 768         __checkReturn                   efx_rc_t
 769 efx_mae_action_set_spec_init(
 770         __in                            efx_nic_t *enp,
 771         __out                           efx_mae_actions_t **specp)
 772 {
 773         efx_mae_actions_t *spec;
 774         efx_rc_t rc;
 775
 776         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 777         if (spec == NULL) {
 778                 rc = ENOMEM;
 779                 goto fail1;
 780         }
 781
 782         *specp = spec;
 783
 784         return (0);
 785
 786 fail1:
 787         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 788         return (rc);
 789 }
 790
 791                                         void
 792 efx_mae_action_set_spec_fini(
 793         __in                            efx_nic_t *enp,
 794         __in                            efx_mae_actions_t *spec)
 795 {
 796         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 797 }
 798
 799 static  __checkReturn                   efx_rc_t
 800 efx_mae_action_set_add_vlan_pop(
 801         __in                            efx_mae_actions_t *spec,
 802         __in                            size_t arg_size,
 803         __in_bcount(arg_size)           const uint8_t *arg)
 804 {
 805         efx_rc_t rc;
 806
 807         if (arg_size != 0) {
 808                 rc = EINVAL;
 809                 goto fail1;
 810         }
 811
 812         if (arg != NULL) {
 813                 rc = EINVAL;
 814                 goto fail2;
 815         }
 816
 817         if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
 818                 rc = ENOTSUP;
 819                 goto fail3;
 820         }
 821
 822         ++spec->ema_n_vlan_tags_to_pop;
 823
 824         return (0);
 825
 826 fail3:
 827         EFSYS_PROBE(fail3);
 828 fail2:
 829         EFSYS_PROBE(fail2);
 830 fail1:
 831         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 832         return (rc);
 833 }
 834
 835 static  __checkReturn                   efx_rc_t
 836 efx_mae_action_set_add_vlan_push(
 837         __in                            efx_mae_actions_t *spec,
 838         __in                            size_t arg_size,
 839         __in_bcount(arg_size)           const uint8_t *arg)
 840 {
 841         unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
 842         efx_rc_t rc;
 843
 844         if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
 845                 rc = EINVAL;
 846                 goto fail1;
 847         }
 848
 849         if (arg == NULL) {
 850                 rc = EINVAL;
 851                 goto fail2;
 852         }
 853
 854         if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
 855                 rc = ENOTSUP;
 856                 goto fail3;
 857         }
 858
 859         memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
 860         ++(spec->ema_n_vlan_tags_to_push);
 861
 862         return (0);
 863
 864 fail3:
 865         EFSYS_PROBE(fail3);
 866 fail2:
 867         EFSYS_PROBE(fail2);
 868 fail1:
 869         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 870         return (rc);
 871 }
 872
 873 static  __checkReturn                   efx_rc_t
 874 efx_mae_action_set_add_flag(
 875         __in                            efx_mae_actions_t *spec,
 876         __in                            size_t arg_size,
 877         __in_bcount(arg_size)           const uint8_t *arg)
 878 {
 879         efx_rc_t rc;
 880
 881         _NOTE(ARGUNUSED(spec))
 882
 883         if (arg_size != 0) {
 884                 rc = EINVAL;
 885                 goto fail1;
 886         }
 887
 888         if (arg != NULL) {
 889                 rc = EINVAL;
 890                 goto fail2;
 891         }
 892
 893         /* This action does not have any arguments, so do nothing here. */
 894
 895         return (0);
 896
 897 fail2:
 898         EFSYS_PROBE(fail2);
 899 fail1:
 900         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 901         return (rc);
 902 }
 903
 904 static  __checkReturn                   efx_rc_t
 905 efx_mae_action_set_add_mark(
 906         __in                            efx_mae_actions_t *spec,
 907         __in                            size_t arg_size,
 908         __in_bcount(arg_size)           const uint8_t *arg)
 909 {
 910         efx_rc_t rc;
 911
 912         if (arg_size != sizeof (spec->ema_mark_value)) {
 913                 rc = EINVAL;
 914                 goto fail1;
 915         }
 916
 917         if (arg == NULL) {
 918                 rc = EINVAL;
 919                 goto fail2;
 920         }
 921
 922         memcpy(&spec->ema_mark_value, arg, arg_size);
 923
 924         return (0);
 925
 926 fail2:
 927         EFSYS_PROBE(fail2);
 928 fail1:
 929         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 930         return (rc);
 931 }
 932
 933 static  __checkReturn                   efx_rc_t
 934 efx_mae_action_set_add_deliver(
 935         __in                            efx_mae_actions_t *spec,
 936         __in                            size_t arg_size,
 937         __in_bcount(arg_size)           const uint8_t *arg)
 938 {
 939         efx_rc_t rc;
 940
 941         if (arg_size != sizeof (spec->ema_deliver_mport)) {
 942                 rc = EINVAL;
 943                 goto fail1;
 944         }
 945
 946         if (arg == NULL) {
 947                 rc = EINVAL;
 948                 goto fail2;
 949         }
 950
 951         memcpy(&spec->ema_deliver_mport, arg, arg_size);
 952
 953         return (0);
 954
 955 fail2:
 956         EFSYS_PROBE(fail2);
 957 fail1:
 958         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 959         return (rc);
 960 }
 961
 962 typedef struct efx_mae_action_desc_s {
 963         /* Action specific handler */
 964         efx_rc_t        (*emad_add)(efx_mae_actions_t *,
 965                                     size_t, const uint8_t *);
 966 } efx_mae_action_desc_t;
 967
 968 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
 969         [EFX_MAE_ACTION_VLAN_POP] = {
 970                 .emad_add = efx_mae_action_set_add_vlan_pop
 971         },
 972         [EFX_MAE_ACTION_VLAN_PUSH] = {
 973                 .emad_add = efx_mae_action_set_add_vlan_push
 974         },
 975         [EFX_MAE_ACTION_FLAG] = {
 976                 .emad_add = efx_mae_action_set_add_flag
 977         },
 978         [EFX_MAE_ACTION_MARK] = {
 979                 .emad_add = efx_mae_action_set_add_mark
 980         },
 981         [EFX_MAE_ACTION_DELIVER] = {
 982                 .emad_add = efx_mae_action_set_add_deliver
 983         }
 984 };
 985
 986 static const uint32_t efx_mae_action_ordered_map =
 987         (1U << EFX_MAE_ACTION_VLAN_POP) |
 988         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
 989         (1U << EFX_MAE_ACTION_FLAG) |
 990         (1U << EFX_MAE_ACTION_MARK) |
 991         (1U << EFX_MAE_ACTION_DELIVER);
 992
 993 /*
 994  * These actions must not be added after DELIVER, but
 995  * they can have any place among the rest of
 996  * strictly ordered actions.
 997  */
 998 static const uint32_t efx_mae_action_nonstrict_map =
 999         (1U << EFX_MAE_ACTION_FLAG) |
1000         (1U << EFX_MAE_ACTION_MARK);
1001
1002 static const uint32_t efx_mae_action_repeat_map =
1003         (1U << EFX_MAE_ACTION_VLAN_POP) |
1004         (1U << EFX_MAE_ACTION_VLAN_PUSH);
1005
1006 /*
1007  * Add an action to an action set.
1008  *
1009  * This has to be invoked in the desired action order.
1010  * An out-of-order action request will be turned down.
1011  */
1012 static  __checkReturn                   efx_rc_t
1013 efx_mae_action_set_spec_populate(
1014         __in                            efx_mae_actions_t *spec,
1015         __in                            efx_mae_action_t type,
1016         __in                            size_t arg_size,
1017         __in_bcount(arg_size)           const uint8_t *arg)
1018 {
1019         uint32_t action_mask;
1020         efx_rc_t rc;
1021
1022         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1023             (sizeof (efx_mae_action_ordered_map) * 8));
1024         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1025             (sizeof (efx_mae_action_repeat_map) * 8));
1026
1027         EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1028         EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1029         EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1030
1031         if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1032                 rc = EINVAL;
1033                 goto fail1;
1034         }
1035
1036         action_mask = (1U << type);
1037
1038         if ((spec->ema_actions & action_mask) != 0) {
1039                 /* The action set already contains this action. */
1040                 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1041                         /* Cannot add another non-repeatable action. */
1042                         rc = ENOTSUP;
1043                         goto fail2;
1044                 }
1045         }
1046
1047         if ((efx_mae_action_ordered_map & action_mask) != 0) {
1048                 uint32_t strict_ordered_map =
1049                     efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1050                 uint32_t later_actions_mask =
1051                     strict_ordered_map & ~(action_mask | (action_mask - 1));
1052
1053                 if ((spec->ema_actions & later_actions_mask) != 0) {
1054                         /* Cannot add an action after later ordered actions. */
1055                         rc = ENOTSUP;
1056                         goto fail3;
1057                 }
1058         }
1059
1060         if (efx_mae_actions[type].emad_add != NULL) {
1061                 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1062                 if (rc != 0)
1063                         goto fail4;
1064         }
1065
1066         spec->ema_actions |= action_mask;
1067
1068         return (0);
1069
1070 fail4:
1071         EFSYS_PROBE(fail4);
1072 fail3:
1073         EFSYS_PROBE(fail3);
1074 fail2:
1075         EFSYS_PROBE(fail2);
1076 fail1:
1077         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1078         return (rc);
1079 }
1080
1081         __checkReturn                   efx_rc_t
1082 efx_mae_action_set_populate_vlan_pop(
1083         __in                            efx_mae_actions_t *spec)
1084 {
1085         return (efx_mae_action_set_spec_populate(spec,
1086             EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1087 }
1088
1089         __checkReturn                   efx_rc_t
1090 efx_mae_action_set_populate_vlan_push(
1091         __in                            efx_mae_actions_t *spec,
1092         __in                            uint16_t tpid_be,
1093         __in                            uint16_t tci_be)
1094 {
1095         efx_mae_action_vlan_push_t action;
1096         const uint8_t *arg = (const uint8_t *)&action;
1097
1098         action.emavp_tpid_be = tpid_be;
1099         action.emavp_tci_be = tci_be;
1100
1101         return (efx_mae_action_set_spec_populate(spec,
1102             EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1103 }
1104
1105         __checkReturn                   efx_rc_t
1106 efx_mae_action_set_populate_flag(
1107         __in                            efx_mae_actions_t *spec)
1108 {
1109         return (efx_mae_action_set_spec_populate(spec,
1110             EFX_MAE_ACTION_FLAG, 0, NULL));
1111 }
1112
1113         __checkReturn                   efx_rc_t
1114 efx_mae_action_set_populate_mark(
1115         __in                            efx_mae_actions_t *spec,
1116         __in                            uint32_t mark_value)
1117 {
1118         const uint8_t *arg = (const uint8_t *)&mark_value;
1119
1120         return (efx_mae_action_set_spec_populate(spec,
1121             EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1122 }
1123
1124         __checkReturn                   efx_rc_t
1125 efx_mae_action_set_populate_deliver(
1126         __in                            efx_mae_actions_t *spec,
1127         __in                            const efx_mport_sel_t *mportp)
1128 {
1129         const uint8_t *arg;
1130         efx_rc_t rc;
1131
1132         if (mportp == NULL) {
1133                 rc = EINVAL;
1134                 goto fail1;
1135         }
1136
1137         arg = (const uint8_t *)&mportp->sel;
1138
1139         return (efx_mae_action_set_spec_populate(spec,
1140             EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1141
1142 fail1:
1143         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1144         return (rc);
1145 }
1146
1147         __checkReturn                   efx_rc_t
1148 efx_mae_action_set_populate_drop(
1149         __in                            efx_mae_actions_t *spec)
1150 {
1151         efx_mport_sel_t mport;
1152         const uint8_t *arg;
1153         efx_dword_t dword;
1154
1155         EFX_POPULATE_DWORD_1(dword,
1156             MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1157
1158         mport.sel = dword.ed_u32[0];
1159
1160         arg = (const uint8_t *)&mport.sel;
1161
1162         return (efx_mae_action_set_spec_populate(spec,
1163             EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1164 }
1165
1166         __checkReturn                   boolean_t
1167 efx_mae_action_set_specs_equal(
1168         __in                            const efx_mae_actions_t *left,
1169         __in                            const efx_mae_actions_t *right)
1170 {
1171         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1172 }
1173
1174         __checkReturn                   efx_rc_t
1175 efx_mae_match_specs_class_cmp(
1176         __in                            efx_nic_t *enp,
1177         __in                            const efx_mae_match_spec_t *left,
1178         __in                            const efx_mae_match_spec_t *right,
1179         __out                           boolean_t *have_same_classp)
1180 {
1181         efx_mae_t *maep = enp->en_maep;
1182         unsigned int field_ncaps = maep->em_max_nfields;
1183         const efx_mae_field_cap_t *field_caps;
1184         const efx_mae_mv_desc_t *desc_setp;
1185         unsigned int desc_set_nentries;
1186         boolean_t have_same_class = B_TRUE;
1187         efx_mae_field_id_t field_id;
1188         const uint8_t *mvpl;
1189         const uint8_t *mvpr;
1190         efx_rc_t rc;
1191
1192         switch (left->emms_type) {
1193         case EFX_MAE_RULE_ACTION:
1194                 field_caps = maep->em_action_rule_field_caps;
1195                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1196                 desc_set_nentries =
1197                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1198                 mvpl = left->emms_mask_value_pairs.action;
1199                 mvpr = right->emms_mask_value_pairs.action;
1200                 break;
1201         default:
1202                 rc = ENOTSUP;
1203                 goto fail1;
1204         }
1205
1206         if (field_caps == NULL) {
1207                 rc = EAGAIN;
1208                 goto fail2;
1209         }
1210
1211         if (left->emms_type != right->emms_type ||
1212             left->emms_prio != right->emms_prio) {
1213                 /*
1214                  * Rules of different types can never map to the same class.
1215                  *
1216                  * The FW can support some set of match criteria for one
1217                  * priority and not support the very same set for
1218                  * another priority. Thus, two rules which have
1219                  * different priorities can never map to
1220                  * the same class.
1221                  */
1222                 *have_same_classp = B_FALSE;
1223                 return (0);
1224         }
1225
1226         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
1227                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1228                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1229
1230                 if (descp->emmd_mask_size == 0)
1231                         continue; /* Skip array gap */
1232
1233                 if (field_cap_id >= field_ncaps)
1234                         break;
1235
1236                 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1237                         const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1238                         const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1239                         size_t mask_size = descp->emmd_mask_size;
1240
1241                         if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1242                                 have_same_class = B_FALSE;
1243                                 break;
1244                         }
1245                 }
1246
1247                 if (field_caps[field_cap_id].emfc_match_affects_class) {
1248                         const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1249                         const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1250                         size_t value_size = descp->emmd_value_size;
1251
1252                         if (memcmp(lvalp, rvalp, value_size) != 0) {
1253                                 have_same_class = B_FALSE;
1254                                 break;
1255                         }
1256                 }
1257         }
1258
1259         *have_same_classp = have_same_class;
1260
1261         return (0);
1262
1263 fail2:
1264         EFSYS_PROBE(fail2);
1265 fail1:
1266         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1267         return (rc);
1268 }
1269
1270         __checkReturn                   efx_rc_t
1271 efx_mae_action_set_alloc(
1272         __in                            efx_nic_t *enp,
1273         __in                            const efx_mae_actions_t *spec,
1274         __out                           efx_mae_aset_id_t *aset_idp)
1275 {
1276         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1277         efx_mcdi_req_t req;
1278         EFX_MCDI_DECLARE_BUF(payload,
1279             MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1280             MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1281         efx_mae_aset_id_t aset_id;
1282         efx_rc_t rc;
1283
1284         if (encp->enc_mae_supported == B_FALSE) {
1285                 rc = ENOTSUP;
1286                 goto fail1;
1287         }
1288
1289         req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1290         req.emr_in_buf = payload;
1291         req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1292         req.emr_out_buf = payload;
1293         req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1294
1295         /*
1296          * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1297          * corresponding resource types are supported by the implementation.
1298          * Use proper resource ID assignments instead.
1299          */
1300         MCDI_IN_SET_DWORD(req,
1301             MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1302         MCDI_IN_SET_DWORD(req,
1303             MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1304         MCDI_IN_SET_DWORD(req,
1305             MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1306
1307         MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1308             MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1309
1310         if (spec->ema_n_vlan_tags_to_push > 0) {
1311                 unsigned int outer_tag_idx;
1312
1313                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1314                     MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1315                     spec->ema_n_vlan_tags_to_push);
1316
1317                 if (spec->ema_n_vlan_tags_to_push ==
1318                     EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1319                         MCDI_IN_SET_WORD(req,
1320                             MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1321                             spec->ema_vlan_push_descs[0].emavp_tpid_be);
1322                         MCDI_IN_SET_WORD(req,
1323                             MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1324                             spec->ema_vlan_push_descs[0].emavp_tci_be);
1325                 }
1326
1327                 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1328
1329                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1330                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1331                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1332                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1333         }
1334
1335         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1336                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1337                     MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1338         }
1339
1340         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1341                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1342                     MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1343
1344                 MCDI_IN_SET_DWORD(req,
1345                     MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1346         }
1347
1348         MCDI_IN_SET_DWORD(req,
1349             MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1350
1351         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1352             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1353         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1354             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1355
1356         efx_mcdi_execute(enp, &req);
1357
1358         if (req.emr_rc != 0) {
1359                 rc = req.emr_rc;
1360                 goto fail2;
1361         }
1362
1363         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1364                 rc = EMSGSIZE;
1365                 goto fail3;
1366         }
1367
1368         aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1369         if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1370                 rc = ENOENT;
1371                 goto fail4;
1372         }
1373
1374         aset_idp->id = aset_id.id;
1375
1376         return (0);
1377
1378 fail4:
1379         EFSYS_PROBE(fail4);
1380 fail3:
1381         EFSYS_PROBE(fail3);
1382 fail2:
1383         EFSYS_PROBE(fail2);
1384 fail1:
1385         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1386         return (rc);
1387 }
1388
1389         __checkReturn                   efx_rc_t
1390 efx_mae_action_set_free(
1391         __in                            efx_nic_t *enp,
1392         __in                            const efx_mae_aset_id_t *aset_idp)
1393 {
1394         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1395         efx_mcdi_req_t req;
1396         EFX_MCDI_DECLARE_BUF(payload,
1397             MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1398             MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1399         efx_rc_t rc;
1400
1401         if (encp->enc_mae_supported == B_FALSE) {
1402                 rc = ENOTSUP;
1403                 goto fail1;
1404         }
1405
1406         req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1407         req.emr_in_buf = payload;
1408         req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1409         req.emr_out_buf = payload;
1410         req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1411
1412         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1413
1414         efx_mcdi_execute(enp, &req);
1415
1416         if (req.emr_rc != 0) {
1417                 rc = req.emr_rc;
1418                 goto fail2;
1419         }
1420
1421         if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1422             aset_idp->id) {
1423                 /* Firmware failed to free the action set. */
1424                 rc = EAGAIN;
1425                 goto fail3;
1426         }
1427
1428         return (0);
1429
1430 fail3:
1431         EFSYS_PROBE(fail3);
1432 fail2:
1433         EFSYS_PROBE(fail2);
1434 fail1:
1435         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1436         return (rc);
1437 }
1438
1439         __checkReturn                   efx_rc_t
1440 efx_mae_action_rule_insert(
1441         __in                            efx_nic_t *enp,
1442         __in                            const efx_mae_match_spec_t *spec,
1443         __in                            const efx_mae_aset_list_id_t *asl_idp,
1444         __in                            const efx_mae_aset_id_t *as_idp,
1445         __out                           efx_mae_rule_id_t *ar_idp)
1446 {
1447         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1448         efx_mcdi_req_t req;
1449         EFX_MCDI_DECLARE_BUF(payload,
1450             MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1451             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1452         efx_oword_t *rule_response;
1453         efx_mae_rule_id_t ar_id;
1454         size_t offset;
1455         efx_rc_t rc;
1456
1457         EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1458             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1459
1460         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1461             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1462
1463         if (encp->enc_mae_supported == B_FALSE) {
1464                 rc = ENOTSUP;
1465                 goto fail1;
1466         }
1467
1468         if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1469             (asl_idp != NULL && as_idp != NULL) ||
1470             (asl_idp == NULL && as_idp == NULL)) {
1471                 rc = EINVAL;
1472                 goto fail2;
1473         }
1474
1475         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1476         req.emr_in_buf = payload;
1477         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1478         req.emr_out_buf = payload;
1479         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1480
1481         EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1482             MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1483         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1484         rule_response = (efx_oword_t *)(payload + offset);
1485         EFX_POPULATE_OWORD_3(*rule_response,
1486             MAE_ACTION_RULE_RESPONSE_ASL_ID,
1487             (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1488             MAE_ACTION_RULE_RESPONSE_AS_ID,
1489             (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1490             MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1491
1492         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1493
1494         /*
1495          * Mask-value pairs have been stored in the byte order needed for the
1496          * MCDI request and are thus safe to be copied directly to the buffer.
1497          */
1498         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1499             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1500         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1501         memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1502             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1503
1504         efx_mcdi_execute(enp, &req);
1505
1506         if (req.emr_rc != 0) {
1507                 rc = req.emr_rc;
1508                 goto fail3;
1509         }
1510
1511         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1512                 rc = EMSGSIZE;
1513                 goto fail4;
1514         }
1515
1516         ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1517         if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1518                 rc = ENOENT;
1519                 goto fail5;
1520         }
1521
1522         ar_idp->id = ar_id.id;
1523
1524         return (0);
1525
1526 fail5:
1527         EFSYS_PROBE(fail5);
1528 fail4:
1529         EFSYS_PROBE(fail4);
1530 fail3:
1531         EFSYS_PROBE(fail3);
1532 fail2:
1533         EFSYS_PROBE(fail2);
1534 fail1:
1535         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1536         return (rc);
1537 }
1538
1539         __checkReturn                   efx_rc_t
1540 efx_mae_action_rule_remove(
1541         __in                            efx_nic_t *enp,
1542         __in                            const efx_mae_rule_id_t *ar_idp)
1543 {
1544         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1545         efx_mcdi_req_t req;
1546         EFX_MCDI_DECLARE_BUF(payload,
1547             MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1548             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1549         efx_rc_t rc;
1550
1551         if (encp->enc_mae_supported == B_FALSE) {
1552                 rc = ENOTSUP;
1553                 goto fail1;
1554         }
1555
1556         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1557         req.emr_in_buf = payload;
1558         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1559         req.emr_out_buf = payload;
1560         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1561
1562         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1563
1564         efx_mcdi_execute(enp, &req);
1565
1566         if (req.emr_rc != 0) {
1567                 rc = req.emr_rc;
1568                 goto fail2;
1569         }
1570
1571         if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1572             ar_idp->id) {
1573                 /* Firmware failed to delete the action rule. */
1574                 rc = EAGAIN;
1575                 goto fail3;
1576         }
1577
1578         return (0);
1579
1580 fail3:
1581         EFSYS_PROBE(fail3);
1582 fail2:
1583         EFSYS_PROBE(fail2);
1584 fail1:
1585         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1586         return (rc);
1587 }
1588
1589 #endif /* EFSYS_OPT_MAE */