1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
13 static __checkReturn efx_rc_t
14 efx_mae_get_capabilities(
18 EFX_MCDI_DECLARE_BUF(payload,
19 MC_CMD_MAE_GET_CAPS_IN_LEN,
20 MC_CMD_MAE_GET_CAPS_OUT_LEN);
21 struct efx_mae_s *maep = enp->en_maep;
24 req.emr_cmd = MC_CMD_MAE_GET_CAPS;
25 req.emr_in_buf = payload;
26 req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
27 req.emr_out_buf = payload;
28 req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
30 efx_mcdi_execute(enp, &req);
32 if (req.emr_rc != 0) {
37 if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
42 maep->em_max_n_outer_prios =
43 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
45 maep->em_max_n_action_prios =
46 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
48 maep->em_encap_types_supported = 0;
50 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
51 maep->em_encap_types_supported |=
52 (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
55 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
56 maep->em_encap_types_supported |=
57 (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
60 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
61 maep->em_encap_types_supported |=
62 (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
65 maep->em_max_nfields =
66 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
73 EFSYS_PROBE1(fail1, efx_rc_t, rc);
77 static __checkReturn efx_rc_t
78 efx_mae_get_outer_rule_caps(
80 __in unsigned int field_ncaps,
81 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
84 EFX_MCDI_DECLARE_BUF(payload,
85 MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
86 MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
87 unsigned int mcdi_field_ncaps;
91 if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
92 MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
97 req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
98 req.emr_in_buf = payload;
99 req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
100 req.emr_out_buf = payload;
101 req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
103 efx_mcdi_execute(enp, &req);
105 if (req.emr_rc != 0) {
110 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
112 if (req.emr_out_length_used <
113 MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
118 if (mcdi_field_ncaps > field_ncaps) {
123 for (i = 0; i < mcdi_field_ncaps; ++i) {
127 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
128 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
129 MAE_FIELD_FLAGS_SUPPORT_STATUS);
131 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
132 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
133 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
135 field_caps[i].emfc_match_affects_class =
136 (match_flag != 0) ? B_TRUE : B_FALSE;
138 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
139 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
140 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
142 field_caps[i].emfc_mask_affects_class =
143 (mask_flag != 0) ? B_TRUE : B_FALSE;
155 EFSYS_PROBE1(fail1, efx_rc_t, rc);
159 static __checkReturn efx_rc_t
160 efx_mae_get_action_rule_caps(
162 __in unsigned int field_ncaps,
163 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
166 EFX_MCDI_DECLARE_BUF(payload,
167 MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
168 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
169 unsigned int mcdi_field_ncaps;
173 if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
174 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
179 req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
180 req.emr_in_buf = payload;
181 req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
182 req.emr_out_buf = payload;
183 req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
185 efx_mcdi_execute(enp, &req);
187 if (req.emr_rc != 0) {
192 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
194 if (req.emr_out_length_used <
195 MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
200 if (mcdi_field_ncaps > field_ncaps) {
205 for (i = 0; i < mcdi_field_ncaps; ++i) {
209 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
210 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
211 MAE_FIELD_FLAGS_SUPPORT_STATUS);
213 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
214 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
215 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
217 field_caps[i].emfc_match_affects_class =
218 (match_flag != 0) ? B_TRUE : B_FALSE;
220 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
221 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
222 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
224 field_caps[i].emfc_mask_affects_class =
225 (mask_flag != 0) ? B_TRUE : B_FALSE;
237 EFSYS_PROBE1(fail1, efx_rc_t, rc);
241 __checkReturn efx_rc_t
245 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
246 efx_mae_field_cap_t *or_fcaps;
247 size_t or_fcaps_size;
248 efx_mae_field_cap_t *ar_fcaps;
249 size_t ar_fcaps_size;
253 if (encp->enc_mae_supported == B_FALSE) {
258 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
266 rc = efx_mae_get_capabilities(enp);
270 or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
271 EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
272 if (or_fcaps == NULL) {
277 maep->em_outer_rule_field_caps_size = or_fcaps_size;
278 maep->em_outer_rule_field_caps = or_fcaps;
280 rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
284 ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
285 EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
286 if (ar_fcaps == NULL) {
291 maep->em_action_rule_field_caps_size = ar_fcaps_size;
292 maep->em_action_rule_field_caps = ar_fcaps;
294 rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
302 EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
307 EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
312 EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
317 EFSYS_PROBE1(fail1, efx_rc_t, rc);
325 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
326 efx_mae_t *maep = enp->en_maep;
328 if (encp->enc_mae_supported == B_FALSE)
331 EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
332 maep->em_action_rule_field_caps);
333 EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
334 maep->em_outer_rule_field_caps);
335 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
339 __checkReturn efx_rc_t
342 __out efx_mae_limits_t *emlp)
344 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
345 struct efx_mae_s *maep = enp->en_maep;
348 if (encp->enc_mae_supported == B_FALSE) {
353 emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
354 emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
355 emlp->eml_encap_types_supported = maep->em_encap_types_supported;
360 EFSYS_PROBE1(fail1, efx_rc_t, rc);
364 __checkReturn efx_rc_t
365 efx_mae_match_spec_init(
367 __in efx_mae_rule_type_t type,
369 __out efx_mae_match_spec_t **specp)
371 efx_mae_match_spec_t *spec;
375 case EFX_MAE_RULE_OUTER:
377 case EFX_MAE_RULE_ACTION:
384 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
390 spec->emms_type = type;
391 spec->emms_prio = prio;
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
405 efx_mae_match_spec_fini(
407 __in efx_mae_match_spec_t *spec)
409 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
412 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
413 typedef enum efx_mae_field_cap_id_e {
414 EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
415 EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
416 EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
417 EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
418 EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
419 EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
420 EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
421 EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
422 EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
423 EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
424 EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
425 EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
426 EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
427 EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
428 EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
429 EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
430 EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
431 EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
432 EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
433 EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
434 EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
435 EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
436 EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
437 EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
438 EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
439 EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
440 EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
441 EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
442 EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
443 EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
444 EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
445 EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
446 EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
447 EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
448 EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
449 EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
451 EFX_MAE_FIELD_CAP_NIDS
452 } efx_mae_field_cap_id_t;
454 typedef enum efx_mae_field_endianness_e {
455 EFX_MAE_FIELD_LE = 0,
458 EFX_MAE_FIELD_ENDIANNESS_NTYPES
459 } efx_mae_field_endianness_t;
462 * The following structure is a means to describe an MAE field.
463 * The information in it is meant to be used internally by
464 * APIs for addressing a given field in a mask-value pairs
465 * structure and for validation purposes.
467 * A field may have an alternative one. This structure
468 * has additional members to reference the alternative
469 * field's mask. See efx_mae_match_spec_is_valid().
471 typedef struct efx_mae_mv_desc_s {
472 efx_mae_field_cap_id_t emmd_field_cap_id;
474 size_t emmd_value_size;
475 size_t emmd_value_offset;
476 size_t emmd_mask_size;
477 size_t emmd_mask_offset;
480 * Having the alternative field's mask size set to 0
481 * means that there's no alternative field specified.
483 size_t emmd_alt_mask_size;
484 size_t emmd_alt_mask_offset;
486 /* Primary field and the alternative one are of the same endianness. */
487 efx_mae_field_endianness_t emmd_endianness;
490 /* Indices to this array are provided by efx_mae_field_id_t */
491 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
492 #define EFX_MAE_MV_DESC(_name, _endianness) \
493 [EFX_MAE_FIELD_##_name] = \
495 EFX_MAE_FIELD_ID_##_name, \
496 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN, \
497 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST, \
498 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN, \
499 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST, \
500 0, 0 /* no alternative field */, \
504 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
505 EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
506 EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
507 EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
508 EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
509 EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
510 EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
511 EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
512 EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
513 EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
514 EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
515 EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
516 EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
517 EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
518 EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
519 EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
520 EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
521 EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
522 EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
523 EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
525 #undef EFX_MAE_MV_DESC
528 /* Indices to this array are provided by efx_mae_field_id_t */
529 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
530 #define EFX_MAE_MV_DESC(_name, _endianness) \
531 [EFX_MAE_FIELD_##_name] = \
533 EFX_MAE_FIELD_ID_##_name, \
534 MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
535 MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
536 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
537 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
538 0, 0 /* no alternative field */, \
542 /* Same as EFX_MAE_MV_DESC(), but also indicates an alternative field. */
543 #define EFX_MAE_MV_DESC_ALT(_name, _alt_name, _endianness) \
544 [EFX_MAE_FIELD_##_name] = \
546 EFX_MAE_FIELD_ID_##_name, \
547 MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
548 MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
549 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
550 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
551 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_LEN, \
552 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_OFST, \
556 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
557 EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
558 EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
559 EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
560 EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
561 EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
562 EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
563 EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
564 EFX_MAE_MV_DESC_ALT(ENC_SRC_IP4_BE, ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
565 EFX_MAE_MV_DESC_ALT(ENC_DST_IP4_BE, ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
566 EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
567 EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
568 EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
569 EFX_MAE_MV_DESC_ALT(ENC_SRC_IP6_BE, ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
570 EFX_MAE_MV_DESC_ALT(ENC_DST_IP6_BE, ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
571 EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
572 EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
574 #undef EFX_MAE_MV_DESC_ALT
575 #undef EFX_MAE_MV_DESC
578 __checkReturn efx_rc_t
579 efx_mae_mport_by_phy_port(
580 __in uint32_t phy_port,
581 __out efx_mport_sel_t *mportp)
586 if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
591 EFX_POPULATE_DWORD_2(dword,
592 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
593 MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
595 memset(mportp, 0, sizeof (*mportp));
597 * The constructed DWORD is little-endian,
598 * but the resulting value is meant to be
599 * passed to MCDIs, where it will undergo
600 * host-order to little endian conversion.
602 mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
607 EFSYS_PROBE1(fail1, efx_rc_t, rc);
611 __checkReturn efx_rc_t
612 efx_mae_mport_by_pcie_function(
615 __out efx_mport_sel_t *mportp)
620 EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
621 MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
623 if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
628 if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
633 EFX_POPULATE_DWORD_3(dword,
634 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
635 MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
636 MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
638 memset(mportp, 0, sizeof (*mportp));
640 * The constructed DWORD is little-endian,
641 * but the resulting value is meant to be
642 * passed to MCDIs, where it will undergo
643 * host-order to little endian conversion.
645 mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
652 EFSYS_PROBE1(fail1, efx_rc_t, rc);
656 __checkReturn efx_rc_t
657 efx_mae_match_spec_field_set(
658 __in efx_mae_match_spec_t *spec,
659 __in efx_mae_field_id_t field_id,
660 __in size_t value_size,
661 __in_bcount(value_size) const uint8_t *value,
662 __in size_t mask_size,
663 __in_bcount(mask_size) const uint8_t *mask)
665 const efx_mae_mv_desc_t *descp;
666 unsigned int desc_set_nentries;
670 switch (spec->emms_type) {
671 case EFX_MAE_RULE_OUTER:
673 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
674 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
675 mvp = spec->emms_mask_value_pairs.outer;
677 case EFX_MAE_RULE_ACTION:
679 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
680 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
681 mvp = spec->emms_mask_value_pairs.action;
688 if ((unsigned int)field_id >= desc_set_nentries) {
693 if (descp->emmd_mask_size == 0) {
694 /* The ID points to a gap in the array of field descriptors. */
699 if (value_size != descp->emmd_value_size) {
704 if (mask_size != descp->emmd_mask_size) {
709 if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
711 * The mask/value are in network (big endian) order.
712 * The MCDI request field is also big endian.
714 memcpy(mvp + descp->emmd_value_offset, value, value_size);
715 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
720 * The mask/value are in host byte order.
721 * The MCDI request field is little endian.
723 switch (value_size) {
725 EFX_POPULATE_DWORD_1(dword,
726 EFX_DWORD_0, *(const uint32_t *)value);
728 memcpy(mvp + descp->emmd_value_offset,
729 &dword, sizeof (dword));
732 EFSYS_ASSERT(B_FALSE);
737 EFX_POPULATE_DWORD_1(dword,
738 EFX_DWORD_0, *(const uint32_t *)mask);
740 memcpy(mvp + descp->emmd_mask_offset,
741 &dword, sizeof (dword));
744 EFSYS_ASSERT(B_FALSE);
759 EFSYS_PROBE1(fail1, efx_rc_t, rc);
763 __checkReturn efx_rc_t
764 efx_mae_match_spec_mport_set(
765 __in efx_mae_match_spec_t *spec,
766 __in const efx_mport_sel_t *valuep,
767 __in_opt const efx_mport_sel_t *maskp)
769 uint32_t full_mask = UINT32_MAX;
774 if (valuep == NULL) {
779 vp = (const uint8_t *)&valuep->sel;
781 mp = (const uint8_t *)&maskp->sel;
783 mp = (const uint8_t *)&full_mask;
785 rc = efx_mae_match_spec_field_set(spec,
786 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
787 sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
796 EFSYS_PROBE1(fail1, efx_rc_t, rc);
800 __checkReturn boolean_t
801 efx_mae_match_specs_equal(
802 __in const efx_mae_match_spec_t *left,
803 __in const efx_mae_match_spec_t *right)
805 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
808 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit) \
809 ((_mask)[(_bit) / (_mask_page_nbits)] & \
810 (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
814 __in size_t mask_nbytes,
815 __in_bcount(mask_nbytes) const uint8_t *maskp)
817 boolean_t prev_bit_is_set = B_TRUE;
820 for (i = 0; i < 8 * mask_nbytes; ++i) {
821 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
823 if (!prev_bit_is_set && bit_is_set)
826 prev_bit_is_set = bit_is_set;
833 efx_mask_is_all_ones(
834 __in size_t mask_nbytes,
835 __in_bcount(mask_nbytes) const uint8_t *maskp)
840 for (i = 0; i < mask_nbytes; ++i)
843 return (t == (uint8_t)(~0));
847 efx_mask_is_all_zeros(
848 __in size_t mask_nbytes,
849 __in_bcount(mask_nbytes) const uint8_t *maskp)
854 for (i = 0; i < mask_nbytes; ++i)
860 __checkReturn boolean_t
861 efx_mae_match_spec_is_valid(
863 __in const efx_mae_match_spec_t *spec)
865 efx_mae_t *maep = enp->en_maep;
866 unsigned int field_ncaps = maep->em_max_nfields;
867 const efx_mae_field_cap_t *field_caps;
868 const efx_mae_mv_desc_t *desc_setp;
869 unsigned int desc_set_nentries;
870 boolean_t is_valid = B_TRUE;
871 efx_mae_field_id_t field_id;
874 switch (spec->emms_type) {
875 case EFX_MAE_RULE_OUTER:
876 field_caps = maep->em_outer_rule_field_caps;
877 desc_setp = __efx_mae_outer_rule_mv_desc_set;
879 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
880 mvp = spec->emms_mask_value_pairs.outer;
882 case EFX_MAE_RULE_ACTION:
883 field_caps = maep->em_action_rule_field_caps;
884 desc_setp = __efx_mae_action_rule_mv_desc_set;
886 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
887 mvp = spec->emms_mask_value_pairs.action;
893 if (field_caps == NULL)
896 for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
898 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
899 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
900 const uint8_t *alt_m_buf = mvp + descp->emmd_alt_mask_offset;
901 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
902 size_t alt_m_size = descp->emmd_alt_mask_size;
903 size_t m_size = descp->emmd_mask_size;
906 continue; /* Skip array gap */
908 if ((unsigned int)field_cap_id >= field_ncaps) {
910 * The FW has not reported capability status for
911 * this field. Make sure that its mask is zeroed.
913 is_valid = efx_mask_is_all_zeros(m_size, m_buf);
914 if (is_valid != B_FALSE)
920 switch (field_caps[field_cap_id].emfc_support) {
921 case MAE_FIELD_SUPPORTED_MATCH_MASK:
924 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
925 is_valid = efx_mask_is_prefix(m_size, m_buf);
927 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
928 is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
929 efx_mask_is_all_zeros(m_size, m_buf));
931 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
932 is_valid = efx_mask_is_all_ones(m_size, m_buf);
934 if ((is_valid == B_FALSE) && (alt_m_size != 0)) {
936 * This field has an alternative one. The FW
937 * reports ALWAYS for both implying that one
938 * of them is required to have all-ones mask.
940 * The primary field's mask is incorrect; go
941 * on to check that of the alternative field.
943 is_valid = efx_mask_is_all_ones(alt_m_size,
947 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
948 case MAE_FIELD_UNSUPPORTED:
950 is_valid = efx_mask_is_all_zeros(m_size, m_buf);
954 if (is_valid == B_FALSE)
961 __checkReturn efx_rc_t
962 efx_mae_action_set_spec_init(
964 __out efx_mae_actions_t **specp)
966 efx_mae_actions_t *spec;
969 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
980 EFSYS_PROBE1(fail1, efx_rc_t, rc);
985 efx_mae_action_set_spec_fini(
987 __in efx_mae_actions_t *spec)
989 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
992 static __checkReturn efx_rc_t
993 efx_mae_action_set_add_vlan_pop(
994 __in efx_mae_actions_t *spec,
995 __in size_t arg_size,
996 __in_bcount(arg_size) const uint8_t *arg)
1000 if (arg_size != 0) {
1010 if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
1015 ++spec->ema_n_vlan_tags_to_pop;
1024 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1028 static __checkReturn efx_rc_t
1029 efx_mae_action_set_add_vlan_push(
1030 __in efx_mae_actions_t *spec,
1031 __in size_t arg_size,
1032 __in_bcount(arg_size) const uint8_t *arg)
1034 unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
1037 if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
1047 if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1052 memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
1053 ++(spec->ema_n_vlan_tags_to_push);
1062 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1066 static __checkReturn efx_rc_t
1067 efx_mae_action_set_add_flag(
1068 __in efx_mae_actions_t *spec,
1069 __in size_t arg_size,
1070 __in_bcount(arg_size) const uint8_t *arg)
1074 _NOTE(ARGUNUSED(spec))
1076 if (arg_size != 0) {
1086 /* This action does not have any arguments, so do nothing here. */
1093 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1097 static __checkReturn efx_rc_t
1098 efx_mae_action_set_add_mark(
1099 __in efx_mae_actions_t *spec,
1100 __in size_t arg_size,
1101 __in_bcount(arg_size) const uint8_t *arg)
1105 if (arg_size != sizeof (spec->ema_mark_value)) {
1115 memcpy(&spec->ema_mark_value, arg, arg_size);
1122 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1126 static __checkReturn efx_rc_t
1127 efx_mae_action_set_add_deliver(
1128 __in efx_mae_actions_t *spec,
1129 __in size_t arg_size,
1130 __in_bcount(arg_size) const uint8_t *arg)
1134 if (arg_size != sizeof (spec->ema_deliver_mport)) {
1144 memcpy(&spec->ema_deliver_mport, arg, arg_size);
1151 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1155 typedef struct efx_mae_action_desc_s {
1156 /* Action specific handler */
1157 efx_rc_t (*emad_add)(efx_mae_actions_t *,
1158 size_t, const uint8_t *);
1159 } efx_mae_action_desc_t;
1161 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
1162 [EFX_MAE_ACTION_VLAN_POP] = {
1163 .emad_add = efx_mae_action_set_add_vlan_pop
1165 [EFX_MAE_ACTION_VLAN_PUSH] = {
1166 .emad_add = efx_mae_action_set_add_vlan_push
1168 [EFX_MAE_ACTION_FLAG] = {
1169 .emad_add = efx_mae_action_set_add_flag
1171 [EFX_MAE_ACTION_MARK] = {
1172 .emad_add = efx_mae_action_set_add_mark
1174 [EFX_MAE_ACTION_DELIVER] = {
1175 .emad_add = efx_mae_action_set_add_deliver
1179 static const uint32_t efx_mae_action_ordered_map =
1180 (1U << EFX_MAE_ACTION_VLAN_POP) |
1181 (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1182 (1U << EFX_MAE_ACTION_FLAG) |
1183 (1U << EFX_MAE_ACTION_MARK) |
1184 (1U << EFX_MAE_ACTION_DELIVER);
1187 * These actions must not be added after DELIVER, but
1188 * they can have any place among the rest of
1189 * strictly ordered actions.
1191 static const uint32_t efx_mae_action_nonstrict_map =
1192 (1U << EFX_MAE_ACTION_FLAG) |
1193 (1U << EFX_MAE_ACTION_MARK);
1195 static const uint32_t efx_mae_action_repeat_map =
1196 (1U << EFX_MAE_ACTION_VLAN_POP) |
1197 (1U << EFX_MAE_ACTION_VLAN_PUSH);
1200 * Add an action to an action set.
1202 * This has to be invoked in the desired action order.
1203 * An out-of-order action request will be turned down.
1205 static __checkReturn efx_rc_t
1206 efx_mae_action_set_spec_populate(
1207 __in efx_mae_actions_t *spec,
1208 __in efx_mae_action_t type,
1209 __in size_t arg_size,
1210 __in_bcount(arg_size) const uint8_t *arg)
1212 uint32_t action_mask;
1215 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1216 (sizeof (efx_mae_action_ordered_map) * 8));
1217 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1218 (sizeof (efx_mae_action_repeat_map) * 8));
1220 EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1221 EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1222 EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1224 if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1229 action_mask = (1U << type);
1231 if ((spec->ema_actions & action_mask) != 0) {
1232 /* The action set already contains this action. */
1233 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1234 /* Cannot add another non-repeatable action. */
1240 if ((efx_mae_action_ordered_map & action_mask) != 0) {
1241 uint32_t strict_ordered_map =
1242 efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1243 uint32_t later_actions_mask =
1244 strict_ordered_map & ~(action_mask | (action_mask - 1));
1246 if ((spec->ema_actions & later_actions_mask) != 0) {
1247 /* Cannot add an action after later ordered actions. */
1253 if (efx_mae_actions[type].emad_add != NULL) {
1254 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1259 spec->ema_actions |= action_mask;
1270 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1274 __checkReturn efx_rc_t
1275 efx_mae_action_set_populate_vlan_pop(
1276 __in efx_mae_actions_t *spec)
1278 return (efx_mae_action_set_spec_populate(spec,
1279 EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1282 __checkReturn efx_rc_t
1283 efx_mae_action_set_populate_vlan_push(
1284 __in efx_mae_actions_t *spec,
1285 __in uint16_t tpid_be,
1286 __in uint16_t tci_be)
1288 efx_mae_action_vlan_push_t action;
1289 const uint8_t *arg = (const uint8_t *)&action;
1291 action.emavp_tpid_be = tpid_be;
1292 action.emavp_tci_be = tci_be;
1294 return (efx_mae_action_set_spec_populate(spec,
1295 EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1298 __checkReturn efx_rc_t
1299 efx_mae_action_set_populate_flag(
1300 __in efx_mae_actions_t *spec)
1302 return (efx_mae_action_set_spec_populate(spec,
1303 EFX_MAE_ACTION_FLAG, 0, NULL));
1306 __checkReturn efx_rc_t
1307 efx_mae_action_set_populate_mark(
1308 __in efx_mae_actions_t *spec,
1309 __in uint32_t mark_value)
1311 const uint8_t *arg = (const uint8_t *)&mark_value;
1313 return (efx_mae_action_set_spec_populate(spec,
1314 EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1317 __checkReturn efx_rc_t
1318 efx_mae_action_set_populate_deliver(
1319 __in efx_mae_actions_t *spec,
1320 __in const efx_mport_sel_t *mportp)
1325 if (mportp == NULL) {
1330 arg = (const uint8_t *)&mportp->sel;
1332 return (efx_mae_action_set_spec_populate(spec,
1333 EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1336 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1340 __checkReturn efx_rc_t
1341 efx_mae_action_set_populate_drop(
1342 __in efx_mae_actions_t *spec)
1344 efx_mport_sel_t mport;
1348 EFX_POPULATE_DWORD_1(dword,
1349 MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1352 * The constructed DWORD is little-endian,
1353 * but the resulting value is meant to be
1354 * passed to MCDIs, where it will undergo
1355 * host-order to little endian conversion.
1357 mport.sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
1359 arg = (const uint8_t *)&mport.sel;
1361 return (efx_mae_action_set_spec_populate(spec,
1362 EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1365 __checkReturn boolean_t
1366 efx_mae_action_set_specs_equal(
1367 __in const efx_mae_actions_t *left,
1368 __in const efx_mae_actions_t *right)
1370 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1373 __checkReturn efx_rc_t
1374 efx_mae_match_specs_class_cmp(
1375 __in efx_nic_t *enp,
1376 __in const efx_mae_match_spec_t *left,
1377 __in const efx_mae_match_spec_t *right,
1378 __out boolean_t *have_same_classp)
1380 efx_mae_t *maep = enp->en_maep;
1381 unsigned int field_ncaps = maep->em_max_nfields;
1382 const efx_mae_field_cap_t *field_caps;
1383 const efx_mae_mv_desc_t *desc_setp;
1384 unsigned int desc_set_nentries;
1385 boolean_t have_same_class = B_TRUE;
1386 efx_mae_field_id_t field_id;
1387 const uint8_t *mvpl;
1388 const uint8_t *mvpr;
1391 switch (left->emms_type) {
1392 case EFX_MAE_RULE_OUTER:
1393 field_caps = maep->em_outer_rule_field_caps;
1394 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1396 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1397 mvpl = left->emms_mask_value_pairs.outer;
1398 mvpr = right->emms_mask_value_pairs.outer;
1400 case EFX_MAE_RULE_ACTION:
1401 field_caps = maep->em_action_rule_field_caps;
1402 desc_setp = __efx_mae_action_rule_mv_desc_set;
1404 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1405 mvpl = left->emms_mask_value_pairs.action;
1406 mvpr = right->emms_mask_value_pairs.action;
1413 if (field_caps == NULL) {
1418 if (left->emms_type != right->emms_type ||
1419 left->emms_prio != right->emms_prio) {
1421 * Rules of different types can never map to the same class.
1423 * The FW can support some set of match criteria for one
1424 * priority and not support the very same set for
1425 * another priority. Thus, two rules which have
1426 * different priorities can never map to
1429 *have_same_classp = B_FALSE;
1433 for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
1435 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1436 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1437 const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1438 const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1439 size_t mask_size = descp->emmd_mask_size;
1440 const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1441 const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1442 size_t value_size = descp->emmd_value_size;
1445 continue; /* Skip array gap */
1447 if ((unsigned int)field_cap_id >= field_ncaps) {
1449 * The FW has not reported capability status for this
1450 * field. It's unknown whether any difference between
1451 * the two masks / values affects the class. The only
1452 * case when the class must be the same is when these
1453 * mask-value pairs match. Otherwise, report mismatch.
1455 if ((memcmp(lmaskp, rmaskp, mask_size) == 0) &&
1456 (memcmp(lvalp, rvalp, value_size) == 0))
1462 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1463 if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1464 have_same_class = B_FALSE;
1469 if (field_caps[field_cap_id].emfc_match_affects_class) {
1470 if (memcmp(lvalp, rvalp, value_size) != 0) {
1471 have_same_class = B_FALSE;
1477 *have_same_classp = have_same_class;
1484 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1488 __checkReturn efx_rc_t
1489 efx_mae_outer_rule_insert(
1490 __in efx_nic_t *enp,
1491 __in const efx_mae_match_spec_t *spec,
1492 __in efx_tunnel_protocol_t encap_type,
1493 __out efx_mae_rule_id_t *or_idp)
1495 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1497 EFX_MCDI_DECLARE_BUF(payload,
1498 MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
1499 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
1500 uint32_t encap_type_mcdi;
1501 efx_mae_rule_id_t or_id;
1505 EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
1506 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
1508 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1509 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
1511 if (encp->enc_mae_supported == B_FALSE) {
1516 if (spec->emms_type != EFX_MAE_RULE_OUTER) {
1521 switch (encap_type) {
1522 case EFX_TUNNEL_PROTOCOL_NONE:
1523 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
1525 case EFX_TUNNEL_PROTOCOL_VXLAN:
1526 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
1528 case EFX_TUNNEL_PROTOCOL_GENEVE:
1529 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
1531 case EFX_TUNNEL_PROTOCOL_NVGRE:
1532 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
1539 req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
1540 req.emr_in_buf = payload;
1541 req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
1542 req.emr_out_buf = payload;
1543 req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
1545 MCDI_IN_SET_DWORD(req,
1546 MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
1548 MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
1551 * Mask-value pairs have been stored in the byte order needed for the
1552 * MCDI request and are thus safe to be copied directly to the buffer.
1553 * The library cares about byte order in efx_mae_match_spec_field_set().
1555 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
1556 MAE_ENC_FIELD_PAIRS_LEN);
1557 offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
1558 memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
1559 MAE_ENC_FIELD_PAIRS_LEN);
1561 efx_mcdi_execute(enp, &req);
1563 if (req.emr_rc != 0) {
1568 if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
1573 or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
1574 if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
1579 or_idp->id = or_id.id;
1594 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1598 __checkReturn efx_rc_t
1599 efx_mae_outer_rule_remove(
1600 __in efx_nic_t *enp,
1601 __in const efx_mae_rule_id_t *or_idp)
1603 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1605 EFX_MCDI_DECLARE_BUF(payload,
1606 MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
1607 MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
1610 if (encp->enc_mae_supported == B_FALSE) {
1615 req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
1616 req.emr_in_buf = payload;
1617 req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
1618 req.emr_out_buf = payload;
1619 req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
1621 MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
1623 efx_mcdi_execute(enp, &req);
1625 if (req.emr_rc != 0) {
1630 if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
1632 /* Firmware failed to remove the outer rule. */
1644 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1648 __checkReturn efx_rc_t
1649 efx_mae_match_spec_outer_rule_id_set(
1650 __in efx_mae_match_spec_t *spec,
1651 __in const efx_mae_rule_id_t *or_idp)
1653 uint32_t full_mask = UINT32_MAX;
1656 if (spec->emms_type != EFX_MAE_RULE_ACTION) {
1661 if (or_idp == NULL) {
1666 rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
1667 sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
1668 sizeof (full_mask), (const uint8_t *)&full_mask);
1679 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1683 __checkReturn efx_rc_t
1684 efx_mae_action_set_alloc(
1685 __in efx_nic_t *enp,
1686 __in const efx_mae_actions_t *spec,
1687 __out efx_mae_aset_id_t *aset_idp)
1689 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1691 EFX_MCDI_DECLARE_BUF(payload,
1692 MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1693 MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1694 efx_mae_aset_id_t aset_id;
1697 if (encp->enc_mae_supported == B_FALSE) {
1702 req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1703 req.emr_in_buf = payload;
1704 req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1705 req.emr_out_buf = payload;
1706 req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1709 * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1710 * corresponding resource types are supported by the implementation.
1711 * Use proper resource ID assignments instead.
1713 MCDI_IN_SET_DWORD(req,
1714 MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1715 MCDI_IN_SET_DWORD(req,
1716 MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1717 MCDI_IN_SET_DWORD(req,
1718 MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1720 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1721 MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1723 if (spec->ema_n_vlan_tags_to_push > 0) {
1724 unsigned int outer_tag_idx;
1726 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1727 MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1728 spec->ema_n_vlan_tags_to_push);
1730 if (spec->ema_n_vlan_tags_to_push ==
1731 EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1732 MCDI_IN_SET_WORD(req,
1733 MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1734 spec->ema_vlan_push_descs[0].emavp_tpid_be);
1735 MCDI_IN_SET_WORD(req,
1736 MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1737 spec->ema_vlan_push_descs[0].emavp_tci_be);
1740 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1742 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1743 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1744 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1745 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1748 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1749 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1750 MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1753 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1754 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1755 MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1757 MCDI_IN_SET_DWORD(req,
1758 MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1761 MCDI_IN_SET_DWORD(req,
1762 MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1764 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1765 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1766 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1767 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1769 efx_mcdi_execute(enp, &req);
1771 if (req.emr_rc != 0) {
1776 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1781 aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1782 if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1787 aset_idp->id = aset_id.id;
1798 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1802 __checkReturn efx_rc_t
1803 efx_mae_action_set_free(
1804 __in efx_nic_t *enp,
1805 __in const efx_mae_aset_id_t *aset_idp)
1807 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1809 EFX_MCDI_DECLARE_BUF(payload,
1810 MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1811 MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1814 if (encp->enc_mae_supported == B_FALSE) {
1819 req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1820 req.emr_in_buf = payload;
1821 req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1822 req.emr_out_buf = payload;
1823 req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1825 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1827 efx_mcdi_execute(enp, &req);
1829 if (req.emr_rc != 0) {
1834 if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1836 /* Firmware failed to free the action set. */
1848 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1852 __checkReturn efx_rc_t
1853 efx_mae_action_rule_insert(
1854 __in efx_nic_t *enp,
1855 __in const efx_mae_match_spec_t *spec,
1856 __in const efx_mae_aset_list_id_t *asl_idp,
1857 __in const efx_mae_aset_id_t *as_idp,
1858 __out efx_mae_rule_id_t *ar_idp)
1860 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1862 EFX_MCDI_DECLARE_BUF(payload,
1863 MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1864 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1865 efx_oword_t *rule_response;
1866 efx_mae_rule_id_t ar_id;
1870 EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1871 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1873 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1874 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1876 if (encp->enc_mae_supported == B_FALSE) {
1881 if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1882 (asl_idp != NULL && as_idp != NULL) ||
1883 (asl_idp == NULL && as_idp == NULL)) {
1888 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1889 req.emr_in_buf = payload;
1890 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1891 req.emr_out_buf = payload;
1892 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1894 EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1895 MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1896 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1897 rule_response = (efx_oword_t *)(payload + offset);
1898 EFX_POPULATE_OWORD_3(*rule_response,
1899 MAE_ACTION_RULE_RESPONSE_ASL_ID,
1900 (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1901 MAE_ACTION_RULE_RESPONSE_AS_ID,
1902 (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1903 MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1905 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1908 * Mask-value pairs have been stored in the byte order needed for the
1909 * MCDI request and are thus safe to be copied directly to the buffer.
1911 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1912 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1913 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1914 memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1915 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1917 efx_mcdi_execute(enp, &req);
1919 if (req.emr_rc != 0) {
1924 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1929 ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1930 if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1935 ar_idp->id = ar_id.id;
1948 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1952 __checkReturn efx_rc_t
1953 efx_mae_action_rule_remove(
1954 __in efx_nic_t *enp,
1955 __in const efx_mae_rule_id_t *ar_idp)
1957 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1959 EFX_MCDI_DECLARE_BUF(payload,
1960 MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1961 MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1964 if (encp->enc_mae_supported == B_FALSE) {
1969 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1970 req.emr_in_buf = payload;
1971 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1972 req.emr_out_buf = payload;
1973 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1975 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1977 efx_mcdi_execute(enp, &req);
1979 if (req.emr_rc != 0) {
1984 if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1986 /* Firmware failed to delete the action rule. */
1998 EFSYS_PROBE1(fail1, efx_rc_t, rc);
2002 #endif /* EFSYS_OPT_MAE */