drivers/common/sfc_efx/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         if (venid == EFX_PCI_VENID_XILINX) {
  89                 switch (devid) {
  90 #if EFSYS_OPT_RIVERHEAD
  91                 case EFX_PCI_DEVID_RIVERHEAD:
  92                 case EFX_PCI_DEVID_RIVERHEAD_VF:
  93                         *efp = EFX_FAMILY_RIVERHEAD;
  94                         *membarp = EFX_MEM_BAR_RIVERHEAD;
  95                         return (0);
  96 #endif /* EFSYS_OPT_RIVERHEAD */
  97                 default:
  98                         break;
  99                 }
 100         }
 101
 102         *efp = EFX_FAMILY_INVALID;
 103         return (ENOTSUP);
 104 }
 105
 106
 107 #if EFSYS_OPT_SIENA
 108
 109 static const efx_nic_ops_t      __efx_nic_siena_ops = {
 110         siena_nic_probe,                /* eno_probe */
 111         NULL,                           /* eno_board_cfg */
 112         NULL,                           /* eno_set_drv_limits */
 113         siena_nic_reset,                /* eno_reset */
 114         siena_nic_init,                 /* eno_init */
 115         NULL,                           /* eno_get_vi_pool */
 116         NULL,                           /* eno_get_bar_region */
 117         NULL,                           /* eno_hw_unavailable */
 118         NULL,                           /* eno_set_hw_unavailable */
 119 #if EFSYS_OPT_DIAG
 120         siena_nic_register_test,        /* eno_register_test */
 121 #endif  /* EFSYS_OPT_DIAG */
 122         siena_nic_fini,                 /* eno_fini */
 123         siena_nic_unprobe,              /* eno_unprobe */
 124 };
 125
 126 #endif  /* EFSYS_OPT_SIENA */
 127
 128 #if EFSYS_OPT_HUNTINGTON
 129
 130 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 131         ef10_nic_probe,                 /* eno_probe */
 132         hunt_board_cfg,                 /* eno_board_cfg */
 133         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 134         ef10_nic_reset,                 /* eno_reset */
 135         ef10_nic_init,                  /* eno_init */
 136         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 137         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 138         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 139         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 140 #if EFSYS_OPT_DIAG
 141         ef10_nic_register_test,         /* eno_register_test */
 142 #endif  /* EFSYS_OPT_DIAG */
 143         ef10_nic_fini,                  /* eno_fini */
 144         ef10_nic_unprobe,               /* eno_unprobe */
 145 };
 146
 147 #endif  /* EFSYS_OPT_HUNTINGTON */
 148
 149 #if EFSYS_OPT_MEDFORD
 150
 151 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 152         ef10_nic_probe,                 /* eno_probe */
 153         medford_board_cfg,              /* eno_board_cfg */
 154         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 155         ef10_nic_reset,                 /* eno_reset */
 156         ef10_nic_init,                  /* eno_init */
 157         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 158         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 159         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 160         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 161 #if EFSYS_OPT_DIAG
 162         ef10_nic_register_test,         /* eno_register_test */
 163 #endif  /* EFSYS_OPT_DIAG */
 164         ef10_nic_fini,                  /* eno_fini */
 165         ef10_nic_unprobe,               /* eno_unprobe */
 166 };
 167
 168 #endif  /* EFSYS_OPT_MEDFORD */
 169
 170 #if EFSYS_OPT_MEDFORD2
 171
 172 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 173         ef10_nic_probe,                 /* eno_probe */
 174         medford2_board_cfg,             /* eno_board_cfg */
 175         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 176         ef10_nic_reset,                 /* eno_reset */
 177         ef10_nic_init,                  /* eno_init */
 178         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 179         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 180         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 181         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 182 #if EFSYS_OPT_DIAG
 183         ef10_nic_register_test,         /* eno_register_test */
 184 #endif  /* EFSYS_OPT_DIAG */
 185         ef10_nic_fini,                  /* eno_fini */
 186         ef10_nic_unprobe,               /* eno_unprobe */
 187 };
 188
 189 #endif  /* EFSYS_OPT_MEDFORD2 */
 190
 191
 192         __checkReturn   efx_rc_t
 193 efx_nic_create(
 194         __in            efx_family_t family,
 195         __in            efsys_identifier_t *esip,
 196         __in            efsys_bar_t *esbp,
 197         __in            efsys_lock_t *eslp,
 198         __deref_out     efx_nic_t **enpp)
 199 {
 200         efx_nic_t *enp;
 201         efx_rc_t rc;
 202
 203         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 204         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 205
 206         /* Allocate a NIC object */
 207         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 208
 209         if (enp == NULL) {
 210                 rc = ENOMEM;
 211                 goto fail1;
 212         }
 213
 214         enp->en_magic = EFX_NIC_MAGIC;
 215
 216         switch (family) {
 217 #if EFSYS_OPT_SIENA
 218         case EFX_FAMILY_SIENA:
 219                 enp->en_enop = &__efx_nic_siena_ops;
 220                 enp->en_features =
 221                     EFX_FEATURE_IPV6 |
 222                     EFX_FEATURE_LFSR_HASH_INSERT |
 223                     EFX_FEATURE_LINK_EVENTS |
 224                     EFX_FEATURE_PERIODIC_MAC_STATS |
 225                     EFX_FEATURE_MCDI |
 226                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 227                     EFX_FEATURE_MAC_HEADER_FILTERS |
 228                     EFX_FEATURE_TX_SRC_FILTERS;
 229                 break;
 230 #endif  /* EFSYS_OPT_SIENA */
 231
 232 #if EFSYS_OPT_HUNTINGTON
 233         case EFX_FAMILY_HUNTINGTON:
 234                 enp->en_enop = &__efx_nic_hunt_ops;
 235                 enp->en_features =
 236                     EFX_FEATURE_IPV6 |
 237                     EFX_FEATURE_LINK_EVENTS |
 238                     EFX_FEATURE_PERIODIC_MAC_STATS |
 239                     EFX_FEATURE_MCDI |
 240                     EFX_FEATURE_MAC_HEADER_FILTERS |
 241                     EFX_FEATURE_MCDI_DMA |
 242                     EFX_FEATURE_PIO_BUFFERS |
 243                     EFX_FEATURE_FW_ASSISTED_TSO |
 244                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 245                     EFX_FEATURE_PACKED_STREAM |
 246                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 247                 break;
 248 #endif  /* EFSYS_OPT_HUNTINGTON */
 249
 250 #if EFSYS_OPT_MEDFORD
 251         case EFX_FAMILY_MEDFORD:
 252                 enp->en_enop = &__efx_nic_medford_ops;
 253                 /*
 254                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 255                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 256                  */
 257                 enp->en_features =
 258                     EFX_FEATURE_IPV6 |
 259                     EFX_FEATURE_LINK_EVENTS |
 260                     EFX_FEATURE_PERIODIC_MAC_STATS |
 261                     EFX_FEATURE_MCDI |
 262                     EFX_FEATURE_MAC_HEADER_FILTERS |
 263                     EFX_FEATURE_MCDI_DMA |
 264                     EFX_FEATURE_PIO_BUFFERS |
 265                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 266                     EFX_FEATURE_PACKED_STREAM |
 267                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 268                 break;
 269 #endif  /* EFSYS_OPT_MEDFORD */
 270
 271 #if EFSYS_OPT_MEDFORD2
 272         case EFX_FAMILY_MEDFORD2:
 273                 enp->en_enop = &__efx_nic_medford2_ops;
 274                 enp->en_features =
 275                     EFX_FEATURE_IPV6 |
 276                     EFX_FEATURE_LINK_EVENTS |
 277                     EFX_FEATURE_PERIODIC_MAC_STATS |
 278                     EFX_FEATURE_MCDI |
 279                     EFX_FEATURE_MAC_HEADER_FILTERS |
 280                     EFX_FEATURE_MCDI_DMA |
 281                     EFX_FEATURE_PIO_BUFFERS |
 282                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 283                     EFX_FEATURE_PACKED_STREAM |
 284                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 285                 break;
 286 #endif  /* EFSYS_OPT_MEDFORD2 */
 287
 288         default:
 289                 rc = ENOTSUP;
 290                 goto fail2;
 291         }
 292
 293         enp->en_family = family;
 294         enp->en_esip = esip;
 295         enp->en_esbp = esbp;
 296         enp->en_eslp = eslp;
 297
 298         *enpp = enp;
 299
 300         return (0);
 301
 302 fail2:
 303         EFSYS_PROBE(fail2);
 304
 305         enp->en_magic = 0;
 306
 307         /* Free the NIC object */
 308         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 309
 310 fail1:
 311         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 312
 313         return (rc);
 314 }
 315
 316         __checkReturn   efx_rc_t
 317 efx_nic_probe(
 318         __in            efx_nic_t *enp,
 319         __in            efx_fw_variant_t efv)
 320 {
 321         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 322         const efx_nic_ops_t *enop;
 323         efx_rc_t rc;
 324
 325         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 326 #if EFSYS_OPT_MCDI
 327         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 328 #endif  /* EFSYS_OPT_MCDI */
 329         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 330
 331         /* Ensure FW variant codes match with MC_CMD_FW codes */
 332         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 333             MC_CMD_FW_FULL_FEATURED);
 334         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 335             MC_CMD_FW_LOW_LATENCY);
 336         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 337             MC_CMD_FW_PACKED_STREAM);
 338         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 339             MC_CMD_FW_HIGH_TX_RATE);
 340         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 341             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 342         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 343             MC_CMD_FW_RULES_ENGINE);
 344         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 345             MC_CMD_FW_DPDK);
 346         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 347             (int)MC_CMD_FW_DONT_CARE);
 348
 349         enop = enp->en_enop;
 350         enp->efv = efv;
 351
 352         if ((rc = enop->eno_probe(enp)) != 0)
 353                 goto fail1;
 354
 355         encp->enc_features = enp->en_features;
 356
 357         if ((rc = efx_phy_probe(enp)) != 0)
 358                 goto fail2;
 359
 360         enp->en_mod_flags |= EFX_MOD_PROBE;
 361
 362         return (0);
 363
 364 fail2:
 365         EFSYS_PROBE(fail2);
 366
 367         enop->eno_unprobe(enp);
 368
 369 fail1:
 370         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 371
 372         return (rc);
 373 }
 374
 375         __checkReturn   efx_rc_t
 376 efx_nic_set_drv_limits(
 377         __inout         efx_nic_t *enp,
 378         __in            efx_drv_limits_t *edlp)
 379 {
 380         const efx_nic_ops_t *enop = enp->en_enop;
 381         efx_rc_t rc;
 382
 383         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 384         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 385
 386         if (enop->eno_set_drv_limits != NULL) {
 387                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 388                         goto fail1;
 389         }
 390
 391         return (0);
 392
 393 fail1:
 394         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 395
 396         return (rc);
 397 }
 398
 399         __checkReturn   efx_rc_t
 400 efx_nic_set_drv_version(
 401         __inout                 efx_nic_t *enp,
 402         __in_ecount(length)     char const *verp,
 403         __in                    size_t length)
 404 {
 405         efx_rc_t rc;
 406
 407         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 408         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 409
 410         /*
 411          * length is the string content length in bytes.
 412          * Accept any content which fits into the version
 413          * buffer, excluding the last byte. This is reserved
 414          * for an appended NUL terminator.
 415          */
 416         if (length >= sizeof (enp->en_drv_version)) {
 417                 rc = E2BIG;
 418                 goto fail1;
 419         }
 420
 421         (void) memset(enp->en_drv_version, 0,
 422             sizeof (enp->en_drv_version));
 423         memcpy(enp->en_drv_version, verp, length);
 424
 425         return (0);
 426
 427 fail1:
 428         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 429
 430         return (rc);
 431 }
 432
 433
 434         __checkReturn   efx_rc_t
 435 efx_nic_get_bar_region(
 436         __in            efx_nic_t *enp,
 437         __in            efx_nic_region_t region,
 438         __out           uint32_t *offsetp,
 439         __out           size_t *sizep)
 440 {
 441         const efx_nic_ops_t *enop = enp->en_enop;
 442         efx_rc_t rc;
 443
 444         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 445         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 446         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 447
 448         if (enop->eno_get_bar_region == NULL) {
 449                 rc = ENOTSUP;
 450                 goto fail1;
 451         }
 452         if ((rc = (enop->eno_get_bar_region)(enp,
 453                     region, offsetp, sizep)) != 0) {
 454                 goto fail2;
 455         }
 456
 457         return (0);
 458
 459 fail2:
 460         EFSYS_PROBE(fail2);
 461
 462 fail1:
 463         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 464
 465         return (rc);
 466 }
 467
 468
 469         __checkReturn   efx_rc_t
 470 efx_nic_get_vi_pool(
 471         __in            efx_nic_t *enp,
 472         __out           uint32_t *evq_countp,
 473         __out           uint32_t *rxq_countp,
 474         __out           uint32_t *txq_countp)
 475 {
 476         const efx_nic_ops_t *enop = enp->en_enop;
 477         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 478         efx_rc_t rc;
 479
 480         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 481         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 482         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 483
 484         if (enop->eno_get_vi_pool != NULL) {
 485                 uint32_t vi_count = 0;
 486
 487                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 488                         goto fail1;
 489
 490                 *evq_countp = vi_count;
 491                 *rxq_countp = vi_count;
 492                 *txq_countp = vi_count;
 493         } else {
 494                 /* Use NIC limits as default value */
 495                 *evq_countp = encp->enc_evq_limit;
 496                 *rxq_countp = encp->enc_rxq_limit;
 497                 *txq_countp = encp->enc_txq_limit;
 498         }
 499
 500         return (0);
 501
 502 fail1:
 503         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 504
 505         return (rc);
 506 }
 507
 508
 509         __checkReturn   efx_rc_t
 510 efx_nic_init(
 511         __in            efx_nic_t *enp)
 512 {
 513         const efx_nic_ops_t *enop = enp->en_enop;
 514         efx_rc_t rc;
 515
 516         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 517         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 518
 519         if (enp->en_mod_flags & EFX_MOD_NIC) {
 520                 rc = EINVAL;
 521                 goto fail1;
 522         }
 523
 524         if ((rc = enop->eno_init(enp)) != 0)
 525                 goto fail2;
 526
 527         enp->en_mod_flags |= EFX_MOD_NIC;
 528
 529         return (0);
 530
 531 fail2:
 532         EFSYS_PROBE(fail2);
 533 fail1:
 534         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 535
 536         return (rc);
 537 }
 538
 539                         void
 540 efx_nic_fini(
 541         __in            efx_nic_t *enp)
 542 {
 543         const efx_nic_ops_t *enop = enp->en_enop;
 544
 545         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 546         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 547         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 548         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 549         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 550         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 551         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 552
 553         enop->eno_fini(enp);
 554
 555         enp->en_mod_flags &= ~EFX_MOD_NIC;
 556 }
 557
 558                         void
 559 efx_nic_unprobe(
 560         __in            efx_nic_t *enp)
 561 {
 562         const efx_nic_ops_t *enop = enp->en_enop;
 563
 564         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 565 #if EFSYS_OPT_MCDI
 566         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 567 #endif  /* EFSYS_OPT_MCDI */
 568         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 569         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 570         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 571         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 572         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 573         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 574
 575         efx_phy_unprobe(enp);
 576
 577         enop->eno_unprobe(enp);
 578
 579         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 580 }
 581
 582                         void
 583 efx_nic_destroy(
 584         __in    efx_nic_t *enp)
 585 {
 586         efsys_identifier_t *esip = enp->en_esip;
 587
 588         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 589         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 590
 591         enp->en_family = EFX_FAMILY_INVALID;
 592         enp->en_esip = NULL;
 593         enp->en_esbp = NULL;
 594         enp->en_eslp = NULL;
 595
 596         enp->en_enop = NULL;
 597
 598         enp->en_magic = 0;
 599
 600         /* Free the NIC object */
 601         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 602 }
 603
 604         __checkReturn   efx_rc_t
 605 efx_nic_reset(
 606         __in            efx_nic_t *enp)
 607 {
 608         const efx_nic_ops_t *enop = enp->en_enop;
 609         unsigned int mod_flags;
 610         efx_rc_t rc;
 611
 612         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 613         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 614         /*
 615          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 616          * (which we do not reset here) must have been shut down or never
 617          * initialized.
 618          *
 619          * A rule of thumb here is: If the controller or MC reboots, is *any*
 620          * state lost. If it's lost and needs reapplying, then the module
 621          * *must* not be initialised during the reset.
 622          */
 623         mod_flags = enp->en_mod_flags;
 624         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 625             EFX_MOD_VPD | EFX_MOD_MON);
 626 #if EFSYS_OPT_TUNNEL
 627         mod_flags &= ~EFX_MOD_TUNNEL;
 628 #endif /* EFSYS_OPT_TUNNEL */
 629         EFSYS_ASSERT3U(mod_flags, ==, 0);
 630         if (mod_flags != 0) {
 631                 rc = EINVAL;
 632                 goto fail1;
 633         }
 634
 635         if ((rc = enop->eno_reset(enp)) != 0)
 636                 goto fail2;
 637
 638         return (0);
 639
 640 fail2:
 641         EFSYS_PROBE(fail2);
 642 fail1:
 643         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 644
 645         return (rc);
 646 }
 647
 648                         const efx_nic_cfg_t *
 649 efx_nic_cfg_get(
 650         __in            const efx_nic_t *enp)
 651 {
 652         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 653         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 654
 655         return (&(enp->en_nic_cfg));
 656 }
 657
 658         __checkReturn           efx_rc_t
 659 efx_nic_get_fw_version(
 660         __in                    efx_nic_t *enp,
 661         __out                   efx_nic_fw_info_t *enfip)
 662 {
 663         uint16_t mc_fw_version[4];
 664         efx_rc_t rc;
 665
 666         if (enfip == NULL) {
 667                 rc = EINVAL;
 668                 goto fail1;
 669         }
 670
 671         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 672         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 673
 674         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 675         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 676             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 677         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 678             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 679         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 680             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 681         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 682             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 683         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 684             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 685
 686         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 687         if (rc != 0)
 688                 goto fail2;
 689
 690         rc = efx_mcdi_get_capabilities(enp, NULL,
 691             &enfip->enfi_rx_dpcpu_fw_id,
 692             &enfip->enfi_tx_dpcpu_fw_id,
 693             NULL, NULL);
 694         if (rc == 0) {
 695                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 696         } else if (rc == ENOTSUP) {
 697                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 698                 enfip->enfi_rx_dpcpu_fw_id = 0;
 699                 enfip->enfi_tx_dpcpu_fw_id = 0;
 700         } else {
 701                 goto fail3;
 702         }
 703
 704         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 705             sizeof (mc_fw_version));
 706
 707         return (0);
 708
 709 fail3:
 710         EFSYS_PROBE(fail3);
 711 fail2:
 712         EFSYS_PROBE(fail2);
 713 fail1:
 714         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 715
 716         return (rc);
 717 }
 718
 719         __checkReturn   boolean_t
 720 efx_nic_hw_unavailable(
 721         __in            efx_nic_t *enp)
 722 {
 723         const efx_nic_ops_t *enop = enp->en_enop;
 724
 725         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 726         /* NOTE: can be used by MCDI before NIC probe */
 727
 728         if (enop->eno_hw_unavailable != NULL) {
 729                 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
 730                         goto unavail;
 731         }
 732
 733         return (B_FALSE);
 734
 735 unavail:
 736         return (B_TRUE);
 737 }
 738
 739                         void
 740 efx_nic_set_hw_unavailable(
 741         __in            efx_nic_t *enp)
 742 {
 743         const efx_nic_ops_t *enop = enp->en_enop;
 744
 745         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 746
 747         if (enop->eno_set_hw_unavailable != NULL)
 748                 enop->eno_set_hw_unavailable(enp);
 749 }
 750
 751
 752 #if EFSYS_OPT_DIAG
 753
 754         __checkReturn   efx_rc_t
 755 efx_nic_register_test(
 756         __in            efx_nic_t *enp)
 757 {
 758         const efx_nic_ops_t *enop = enp->en_enop;
 759         efx_rc_t rc;
 760
 761         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 762         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 763         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 764
 765         if ((rc = enop->eno_register_test(enp)) != 0)
 766                 goto fail1;
 767
 768         return (0);
 769
 770 fail1:
 771         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 772
 773         return (rc);
 774 }
 775
 776 #endif  /* EFSYS_OPT_DIAG */
 777
 778 #if EFSYS_OPT_LOOPBACK
 779
 780 extern                  void
 781 efx_loopback_mask(
 782         __in    efx_loopback_kind_t loopback_kind,
 783         __out   efx_qword_t *maskp)
 784 {
 785         efx_qword_t mask;
 786
 787         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 788         EFSYS_ASSERT(maskp != NULL);
 789
 790         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 791 #define LOOPBACK_CHECK(_mcdi, _efx) \
 792         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 793
 794         LOOPBACK_CHECK(NONE, OFF);
 795         LOOPBACK_CHECK(DATA, DATA);
 796         LOOPBACK_CHECK(GMAC, GMAC);
 797         LOOPBACK_CHECK(XGMII, XGMII);
 798         LOOPBACK_CHECK(XGXS, XGXS);
 799         LOOPBACK_CHECK(XAUI, XAUI);
 800         LOOPBACK_CHECK(GMII, GMII);
 801         LOOPBACK_CHECK(SGMII, SGMII);
 802         LOOPBACK_CHECK(XGBR, XGBR);
 803         LOOPBACK_CHECK(XFI, XFI);
 804         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 805         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 806         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 807         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 808         LOOPBACK_CHECK(GPHY, GPHY);
 809         LOOPBACK_CHECK(PHYXS, PHY_XS);
 810         LOOPBACK_CHECK(PCS, PCS);
 811         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 812         LOOPBACK_CHECK(XPORT, XPORT);
 813         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 814         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 815         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 816         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 817         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 818         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 819         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 820         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 821         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 822         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 823         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 824         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 825         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 826         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 827         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 828         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 829         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 830         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 831         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 832 #undef LOOPBACK_CHECK
 833
 834         /* Build bitmask of possible loopback types */
 835         EFX_ZERO_QWORD(mask);
 836
 837         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 838             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 839                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 840         }
 841
 842         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 843             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 844                 /*
 845                  * The "MAC" grouping has historically been used by drivers to
 846                  * mean loopbacks supported by on-chip hardware. Keep that
 847                  * meaning here, and include on-chip PHY layer loopbacks.
 848                  */
 849                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 850                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 851                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 852                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 853                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 854                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 855                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 856                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 857                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 858                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 859                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 860                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 861                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 862                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 863                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 864                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 865         }
 866
 867         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 868             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 869                 /*
 870                  * The "PHY" grouping has historically been used by drivers to
 871                  * mean loopbacks supported by off-chip hardware. Keep that
 872                  * meaning here.
 873                  */
 874                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 875                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 876                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 877                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 878         }
 879
 880         *maskp = mask;
 881 }
 882
 883         __checkReturn   efx_rc_t
 884 efx_mcdi_get_loopback_modes(
 885         __in            efx_nic_t *enp)
 886 {
 887         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 888         efx_mcdi_req_t req;
 889         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 890                 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
 891         efx_qword_t mask;
 892         efx_qword_t modes;
 893         efx_rc_t rc;
 894
 895         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 896         req.emr_in_buf = payload;
 897         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 898         req.emr_out_buf = payload;
 899         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 900
 901         efx_mcdi_execute(enp, &req);
 902
 903         if (req.emr_rc != 0) {
 904                 rc = req.emr_rc;
 905                 goto fail1;
 906         }
 907
 908         if (req.emr_out_length_used <
 909             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 910             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 911                 rc = EMSGSIZE;
 912                 goto fail2;
 913         }
 914
 915         /*
 916          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 917          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 918          */
 919         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 920
 921         EFX_AND_QWORD(mask,
 922             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 923
 924         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 925         EFX_AND_QWORD(modes, mask);
 926         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 927
 928         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 929         EFX_AND_QWORD(modes, mask);
 930         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 931
 932         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 933         EFX_AND_QWORD(modes, mask);
 934         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 935
 936         if (req.emr_out_length_used >=
 937             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 938             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 939                 /* Response includes 40G loopback modes */
 940                 modes = *MCDI_OUT2(req, efx_qword_t,
 941                     GET_LOOPBACK_MODES_OUT_40G);
 942                 EFX_AND_QWORD(modes, mask);
 943                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 944         }
 945
 946         if (req.emr_out_length_used >=
 947             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
 948             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
 949                 /* Response includes 25G loopback modes */
 950                 modes = *MCDI_OUT2(req, efx_qword_t,
 951                     GET_LOOPBACK_MODES_OUT_V2_25G);
 952                 EFX_AND_QWORD(modes, mask);
 953                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
 954         }
 955
 956         if (req.emr_out_length_used >=
 957             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
 958             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
 959                 /* Response includes 50G loopback modes */
 960                 modes = *MCDI_OUT2(req, efx_qword_t,
 961                     GET_LOOPBACK_MODES_OUT_V2_50G);
 962                 EFX_AND_QWORD(modes, mask);
 963                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
 964         }
 965
 966         if (req.emr_out_length_used >=
 967             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
 968             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
 969                 /* Response includes 100G loopback modes */
 970                 modes = *MCDI_OUT2(req, efx_qword_t,
 971                     GET_LOOPBACK_MODES_OUT_V2_100G);
 972                 EFX_AND_QWORD(modes, mask);
 973                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
 974         }
 975
 976         EFX_ZERO_QWORD(modes);
 977         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 978         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 979         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 980         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 981         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 982         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
 983         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
 984         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
 985         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 986
 987         return (0);
 988
 989 fail2:
 990         EFSYS_PROBE(fail2);
 991 fail1:
 992         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 993
 994         return (rc);
 995 }
 996
 997 #endif /* EFSYS_OPT_LOOPBACK */
 998
 999         __checkReturn   efx_rc_t
1000 efx_nic_calculate_pcie_link_bandwidth(
1001         __in            uint32_t pcie_link_width,
1002         __in            uint32_t pcie_link_gen,
1003         __out           uint32_t *bandwidth_mbpsp)
1004 {
1005         uint32_t lane_bandwidth;
1006         uint32_t total_bandwidth;
1007         efx_rc_t rc;
1008
1009         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
1010             !ISP2(pcie_link_width)) {
1011                 rc = EINVAL;
1012                 goto fail1;
1013         }
1014
1015         switch (pcie_link_gen) {
1016         case EFX_PCIE_LINK_SPEED_GEN1:
1017                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
1018                 lane_bandwidth = 2000;
1019                 break;
1020         case EFX_PCIE_LINK_SPEED_GEN2:
1021                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
1022                 lane_bandwidth = 4000;
1023                 break;
1024         case EFX_PCIE_LINK_SPEED_GEN3:
1025                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
1026                 lane_bandwidth = 7877;
1027                 break;
1028         default:
1029                 rc = EINVAL;
1030                 goto fail2;
1031         }
1032
1033         total_bandwidth = lane_bandwidth * pcie_link_width;
1034         *bandwidth_mbpsp = total_bandwidth;
1035
1036         return (0);
1037
1038 fail2:
1039         EFSYS_PROBE(fail2);
1040 fail1:
1041         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1042
1043         return (rc);
1044 }
1045
1046 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1047
1048         __checkReturn   efx_rc_t
1049 efx_nic_get_fw_subvariant(
1050         __in            efx_nic_t *enp,
1051         __out           efx_nic_fw_subvariant_t *subvariantp)
1052 {
1053         efx_rc_t rc;
1054         uint32_t value;
1055
1056         rc = efx_mcdi_get_nic_global(enp,
1057             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1058         if (rc != 0)
1059                 goto fail1;
1060
1061         /* Mapping is not required since values match MCDI */
1062         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1063             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1064         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1065             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1066
1067         switch (value) {
1068         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1069         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1070                 *subvariantp = value;
1071                 break;
1072         default:
1073                 rc = EINVAL;
1074                 goto fail2;
1075         }
1076
1077         return (0);
1078
1079 fail2:
1080         EFSYS_PROBE(fail2);
1081
1082 fail1:
1083         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1084
1085         return (rc);
1086 }
1087
1088         __checkReturn   efx_rc_t
1089 efx_nic_set_fw_subvariant(
1090         __in            efx_nic_t *enp,
1091         __in            efx_nic_fw_subvariant_t subvariant)
1092 {
1093         efx_rc_t rc;
1094
1095         switch (subvariant) {
1096         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1097         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1098                 /* Mapping is not required since values match MCDI */
1099                 break;
1100         default:
1101                 rc = EINVAL;
1102                 goto fail1;
1103         }
1104
1105         rc = efx_mcdi_set_nic_global(enp,
1106             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1107         if (rc != 0)
1108                 goto fail2;
1109
1110         return (0);
1111
1112 fail2:
1113         EFSYS_PROBE(fail2);
1114
1115 fail1:
1116         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1117
1118         return (rc);
1119 }
1120
1121 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1122
1123         __checkReturn   efx_rc_t
1124 efx_nic_check_pcie_link_speed(
1125         __in            efx_nic_t *enp,
1126         __in            uint32_t pcie_link_width,
1127         __in            uint32_t pcie_link_gen,
1128         __out           efx_pcie_link_performance_t *resultp)
1129 {
1130         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1131         uint32_t bandwidth;
1132         efx_pcie_link_performance_t result;
1133         efx_rc_t rc;
1134
1135         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1136             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1137             (pcie_link_gen == 0)) {
1138                 /*
1139                  * No usable info on what is required and/or in use. In virtual
1140                  * machines, sometimes the PCIe link width is reported as 0 or
1141                  * 32, or the speed as 0.
1142                  */
1143                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1144                 goto out;
1145         }
1146
1147         /* Calculate the available bandwidth in megabits per second */
1148         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1149                                             pcie_link_gen, &bandwidth);
1150         if (rc != 0)
1151                 goto fail1;
1152
1153         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1154                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1155         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1156                 /* The link provides enough bandwidth but not optimal latency */
1157                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1158         } else {
1159                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1160         }
1161
1162 out:
1163         *resultp = result;
1164
1165         return (0);
1166
1167 fail1:
1168         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1169
1170         return (rc);
1171 }