1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
11 __checkReturn efx_rc_t
15 __out efx_family_t *efp,
16 __out unsigned int *membarp)
18 if (venid == EFX_PCI_VENID_SFC) {
21 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
23 * Hardware default for PF0 of uninitialised Siena.
24 * manftest must be able to cope with this device id.
26 case EFX_PCI_DEVID_BETHPAGE:
27 case EFX_PCI_DEVID_SIENA:
28 *efp = EFX_FAMILY_SIENA;
29 *membarp = EFX_MEM_BAR_SIENA;
31 #endif /* EFSYS_OPT_SIENA */
33 #if EFSYS_OPT_HUNTINGTON
34 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
36 * Hardware default for PF0 of uninitialised Huntington.
37 * manftest must be able to cope with this device id.
39 case EFX_PCI_DEVID_FARMINGDALE:
40 case EFX_PCI_DEVID_GREENPORT:
41 *efp = EFX_FAMILY_HUNTINGTON;
42 *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
45 case EFX_PCI_DEVID_FARMINGDALE_VF:
46 case EFX_PCI_DEVID_GREENPORT_VF:
47 *efp = EFX_FAMILY_HUNTINGTON;
48 *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
50 #endif /* EFSYS_OPT_HUNTINGTON */
53 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
55 * Hardware default for PF0 of uninitialised Medford.
56 * manftest must be able to cope with this device id.
58 case EFX_PCI_DEVID_MEDFORD:
59 *efp = EFX_FAMILY_MEDFORD;
60 *membarp = EFX_MEM_BAR_MEDFORD_PF;
63 case EFX_PCI_DEVID_MEDFORD_VF:
64 *efp = EFX_FAMILY_MEDFORD;
65 *membarp = EFX_MEM_BAR_MEDFORD_VF;
67 #endif /* EFSYS_OPT_MEDFORD */
69 #if EFSYS_OPT_MEDFORD2
70 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
72 * Hardware default for PF0 of uninitialised Medford2.
73 * manftest must be able to cope with this device id.
75 case EFX_PCI_DEVID_MEDFORD2:
76 case EFX_PCI_DEVID_MEDFORD2_VF:
77 *efp = EFX_FAMILY_MEDFORD2;
78 *membarp = EFX_MEM_BAR_MEDFORD2;
80 #endif /* EFSYS_OPT_MEDFORD2 */
82 case EFX_PCI_DEVID_FALCON: /* Obsolete, not supported */
88 if (venid == EFX_PCI_VENID_XILINX) {
90 #if EFSYS_OPT_RIVERHEAD
91 case EFX_PCI_DEVID_RIVERHEAD:
92 case EFX_PCI_DEVID_RIVERHEAD_VF:
93 *efp = EFX_FAMILY_RIVERHEAD;
94 *membarp = EFX_MEM_BAR_RIVERHEAD;
96 #endif /* EFSYS_OPT_RIVERHEAD */
102 *efp = EFX_FAMILY_INVALID;
108 __checkReturn efx_rc_t
109 efx_family_probe_bar(
112 __in efsys_pci_config_t *espcp,
113 __in const efx_pci_ops_t *epop,
114 __out efx_family_t *efp,
115 __out efx_bar_region_t *ebrp)
120 if (venid == EFX_PCI_VENID_XILINX) {
122 #if EFSYS_OPT_RIVERHEAD
123 case EFX_PCI_DEVID_RIVERHEAD:
124 case EFX_PCI_DEVID_RIVERHEAD_VF:
125 rc = rhead_pci_nic_membar_lookup(espcp, epop, ebrp);
127 *efp = EFX_FAMILY_RIVERHEAD;
130 #endif /* EFSYS_OPT_RIVERHEAD */
136 rc = efx_family(venid, devid, efp, &membar);
138 ebrp->ebr_type = EFX_BAR_TYPE_MEM;
139 ebrp->ebr_index = membar;
140 ebrp->ebr_offset = 0;
141 ebrp->ebr_length = 0;
147 #endif /* EFSYS_OPT_PCI */
151 static const efx_nic_ops_t __efx_nic_siena_ops = {
152 siena_nic_probe, /* eno_probe */
153 NULL, /* eno_board_cfg */
154 NULL, /* eno_set_drv_limits */
155 siena_nic_reset, /* eno_reset */
156 siena_nic_init, /* eno_init */
157 NULL, /* eno_get_vi_pool */
158 NULL, /* eno_get_bar_region */
159 NULL, /* eno_hw_unavailable */
160 NULL, /* eno_set_hw_unavailable */
162 siena_nic_register_test, /* eno_register_test */
163 #endif /* EFSYS_OPT_DIAG */
164 siena_nic_fini, /* eno_fini */
165 siena_nic_unprobe, /* eno_unprobe */
168 #endif /* EFSYS_OPT_SIENA */
170 #if EFSYS_OPT_HUNTINGTON
172 static const efx_nic_ops_t __efx_nic_hunt_ops = {
173 ef10_nic_probe, /* eno_probe */
174 hunt_board_cfg, /* eno_board_cfg */
175 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
176 ef10_nic_reset, /* eno_reset */
177 ef10_nic_init, /* eno_init */
178 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
179 ef10_nic_get_bar_region, /* eno_get_bar_region */
180 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
181 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
183 ef10_nic_register_test, /* eno_register_test */
184 #endif /* EFSYS_OPT_DIAG */
185 ef10_nic_fini, /* eno_fini */
186 ef10_nic_unprobe, /* eno_unprobe */
189 #endif /* EFSYS_OPT_HUNTINGTON */
191 #if EFSYS_OPT_MEDFORD
193 static const efx_nic_ops_t __efx_nic_medford_ops = {
194 ef10_nic_probe, /* eno_probe */
195 medford_board_cfg, /* eno_board_cfg */
196 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
197 ef10_nic_reset, /* eno_reset */
198 ef10_nic_init, /* eno_init */
199 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
200 ef10_nic_get_bar_region, /* eno_get_bar_region */
201 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
202 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
204 ef10_nic_register_test, /* eno_register_test */
205 #endif /* EFSYS_OPT_DIAG */
206 ef10_nic_fini, /* eno_fini */
207 ef10_nic_unprobe, /* eno_unprobe */
210 #endif /* EFSYS_OPT_MEDFORD */
212 #if EFSYS_OPT_MEDFORD2
214 static const efx_nic_ops_t __efx_nic_medford2_ops = {
215 ef10_nic_probe, /* eno_probe */
216 medford2_board_cfg, /* eno_board_cfg */
217 ef10_nic_set_drv_limits, /* eno_set_drv_limits */
218 ef10_nic_reset, /* eno_reset */
219 ef10_nic_init, /* eno_init */
220 ef10_nic_get_vi_pool, /* eno_get_vi_pool */
221 ef10_nic_get_bar_region, /* eno_get_bar_region */
222 ef10_nic_hw_unavailable, /* eno_hw_unavailable */
223 ef10_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
225 ef10_nic_register_test, /* eno_register_test */
226 #endif /* EFSYS_OPT_DIAG */
227 ef10_nic_fini, /* eno_fini */
228 ef10_nic_unprobe, /* eno_unprobe */
231 #endif /* EFSYS_OPT_MEDFORD2 */
233 #if EFSYS_OPT_RIVERHEAD
235 static const efx_nic_ops_t __efx_nic_riverhead_ops = {
236 rhead_nic_probe, /* eno_probe */
237 rhead_board_cfg, /* eno_board_cfg */
238 rhead_nic_set_drv_limits, /* eno_set_drv_limits */
239 rhead_nic_reset, /* eno_reset */
240 rhead_nic_init, /* eno_init */
241 rhead_nic_get_vi_pool, /* eno_get_vi_pool */
242 rhead_nic_get_bar_region, /* eno_get_bar_region */
243 rhead_nic_hw_unavailable, /* eno_hw_unavailable */
244 rhead_nic_set_hw_unavailable, /* eno_set_hw_unavailable */
246 rhead_nic_register_test, /* eno_register_test */
247 #endif /* EFSYS_OPT_DIAG */
248 rhead_nic_fini, /* eno_fini */
249 rhead_nic_unprobe, /* eno_unprobe */
252 #endif /* EFSYS_OPT_RIVERHEAD */
255 __checkReturn efx_rc_t
257 __in efx_family_t family,
258 __in efsys_identifier_t *esip,
259 __in efsys_bar_t *esbp,
260 __in uint32_t fcw_offset,
261 __in efsys_lock_t *eslp,
262 __deref_out efx_nic_t **enpp)
267 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
268 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
270 /* Allocate a NIC object */
271 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
278 enp->en_magic = EFX_NIC_MAGIC;
282 case EFX_FAMILY_SIENA:
283 enp->en_enop = &__efx_nic_siena_ops;
286 EFX_FEATURE_LFSR_HASH_INSERT |
287 EFX_FEATURE_LINK_EVENTS |
288 EFX_FEATURE_PERIODIC_MAC_STATS |
290 EFX_FEATURE_LOOKAHEAD_SPLIT |
291 EFX_FEATURE_MAC_HEADER_FILTERS |
292 EFX_FEATURE_TX_SRC_FILTERS;
294 #endif /* EFSYS_OPT_SIENA */
296 #if EFSYS_OPT_HUNTINGTON
297 case EFX_FAMILY_HUNTINGTON:
298 enp->en_enop = &__efx_nic_hunt_ops;
301 EFX_FEATURE_LINK_EVENTS |
302 EFX_FEATURE_PERIODIC_MAC_STATS |
304 EFX_FEATURE_MAC_HEADER_FILTERS |
305 EFX_FEATURE_MCDI_DMA |
306 EFX_FEATURE_PIO_BUFFERS |
307 EFX_FEATURE_FW_ASSISTED_TSO |
308 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
309 EFX_FEATURE_PACKED_STREAM |
310 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
312 #endif /* EFSYS_OPT_HUNTINGTON */
314 #if EFSYS_OPT_MEDFORD
315 case EFX_FAMILY_MEDFORD:
316 enp->en_enop = &__efx_nic_medford_ops;
318 * FW_ASSISTED_TSO omitted as Medford only supports firmware
319 * assisted TSO version 2, not the v1 scheme used on Huntington.
323 EFX_FEATURE_LINK_EVENTS |
324 EFX_FEATURE_PERIODIC_MAC_STATS |
326 EFX_FEATURE_MAC_HEADER_FILTERS |
327 EFX_FEATURE_MCDI_DMA |
328 EFX_FEATURE_PIO_BUFFERS |
329 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
330 EFX_FEATURE_PACKED_STREAM |
331 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
333 #endif /* EFSYS_OPT_MEDFORD */
335 #if EFSYS_OPT_MEDFORD2
336 case EFX_FAMILY_MEDFORD2:
337 enp->en_enop = &__efx_nic_medford2_ops;
340 EFX_FEATURE_LINK_EVENTS |
341 EFX_FEATURE_PERIODIC_MAC_STATS |
343 EFX_FEATURE_MAC_HEADER_FILTERS |
344 EFX_FEATURE_MCDI_DMA |
345 EFX_FEATURE_PIO_BUFFERS |
346 EFX_FEATURE_FW_ASSISTED_TSO_V2 |
347 EFX_FEATURE_PACKED_STREAM |
348 EFX_FEATURE_TXQ_CKSUM_OP_DESC;
350 #endif /* EFSYS_OPT_MEDFORD2 */
352 #if EFSYS_OPT_RIVERHEAD
353 case EFX_FAMILY_RIVERHEAD:
354 enp->en_enop = &__efx_nic_riverhead_ops;
357 EFX_FEATURE_LINK_EVENTS |
358 EFX_FEATURE_PERIODIC_MAC_STATS |
360 EFX_FEATURE_MAC_HEADER_FILTERS |
361 EFX_FEATURE_MCDI_DMA;
362 enp->en_arch.ef10.ena_fcw_base = fcw_offset;
364 #endif /* EFSYS_OPT_RIVERHEAD */
371 if ((family != EFX_FAMILY_RIVERHEAD) && (fcw_offset != 0)) {
376 enp->en_family = family;
392 /* Free the NIC object */
393 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
396 EFSYS_PROBE1(fail1, efx_rc_t, rc);
401 __checkReturn efx_rc_t
404 __in efx_fw_variant_t efv)
406 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
407 const efx_nic_ops_t *enop;
410 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
412 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
413 #endif /* EFSYS_OPT_MCDI */
414 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
416 /* Ensure FW variant codes match with MC_CMD_FW codes */
417 EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
418 MC_CMD_FW_FULL_FEATURED);
419 EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
420 MC_CMD_FW_LOW_LATENCY);
421 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
422 MC_CMD_FW_PACKED_STREAM);
423 EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
424 MC_CMD_FW_HIGH_TX_RATE);
425 EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
426 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
427 EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
428 MC_CMD_FW_RULES_ENGINE);
429 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
431 EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
432 (int)MC_CMD_FW_DONT_CARE);
437 if ((rc = enop->eno_probe(enp)) != 0)
440 encp->enc_features = enp->en_features;
442 if ((rc = efx_phy_probe(enp)) != 0)
445 enp->en_mod_flags |= EFX_MOD_PROBE;
452 enop->eno_unprobe(enp);
455 EFSYS_PROBE1(fail1, efx_rc_t, rc);
460 __checkReturn efx_rc_t
461 efx_nic_set_drv_limits(
462 __inout efx_nic_t *enp,
463 __in efx_drv_limits_t *edlp)
465 const efx_nic_ops_t *enop = enp->en_enop;
468 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
469 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
471 if (enop->eno_set_drv_limits != NULL) {
472 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
479 EFSYS_PROBE1(fail1, efx_rc_t, rc);
484 __checkReturn efx_rc_t
485 efx_nic_set_drv_version(
486 __inout efx_nic_t *enp,
487 __in_ecount(length) char const *verp,
492 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
493 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
496 * length is the string content length in bytes.
497 * Accept any content which fits into the version
498 * buffer, excluding the last byte. This is reserved
499 * for an appended NUL terminator.
501 if (length >= sizeof (enp->en_drv_version)) {
506 (void) memset(enp->en_drv_version, 0,
507 sizeof (enp->en_drv_version));
508 memcpy(enp->en_drv_version, verp, length);
513 EFSYS_PROBE1(fail1, efx_rc_t, rc);
519 __checkReturn efx_rc_t
520 efx_nic_get_bar_region(
522 __in efx_nic_region_t region,
523 __out uint32_t *offsetp,
526 const efx_nic_ops_t *enop = enp->en_enop;
529 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
530 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
531 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
533 if (enop->eno_get_bar_region == NULL) {
537 if ((rc = (enop->eno_get_bar_region)(enp,
538 region, offsetp, sizep)) != 0) {
548 EFSYS_PROBE1(fail1, efx_rc_t, rc);
554 __checkReturn efx_rc_t
557 __out uint32_t *evq_countp,
558 __out uint32_t *rxq_countp,
559 __out uint32_t *txq_countp)
561 const efx_nic_ops_t *enop = enp->en_enop;
562 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
565 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
566 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
567 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
569 if (enop->eno_get_vi_pool != NULL) {
570 uint32_t vi_count = 0;
572 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
575 *evq_countp = vi_count;
576 *rxq_countp = vi_count;
577 *txq_countp = vi_count;
579 /* Use NIC limits as default value */
580 *evq_countp = encp->enc_evq_limit;
581 *rxq_countp = encp->enc_rxq_limit;
582 *txq_countp = encp->enc_txq_limit;
588 EFSYS_PROBE1(fail1, efx_rc_t, rc);
594 __checkReturn efx_rc_t
598 const efx_nic_ops_t *enop = enp->en_enop;
601 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
602 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
604 if (enp->en_mod_flags & EFX_MOD_NIC) {
609 if ((rc = enop->eno_init(enp)) != 0)
612 enp->en_mod_flags |= EFX_MOD_NIC;
619 EFSYS_PROBE1(fail1, efx_rc_t, rc);
628 const efx_nic_ops_t *enop = enp->en_enop;
630 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
631 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
632 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
633 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
634 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
635 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
636 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
640 enp->en_mod_flags &= ~EFX_MOD_NIC;
647 const efx_nic_ops_t *enop = enp->en_enop;
649 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
651 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
652 #endif /* EFSYS_OPT_MCDI */
653 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
654 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
655 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
656 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
657 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
658 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
660 efx_phy_unprobe(enp);
662 enop->eno_unprobe(enp);
664 enp->en_mod_flags &= ~EFX_MOD_PROBE;
671 efsys_identifier_t *esip = enp->en_esip;
673 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
674 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
676 enp->en_family = EFX_FAMILY_INVALID;
685 /* Free the NIC object */
686 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
689 __checkReturn efx_rc_t
693 const efx_nic_ops_t *enop = enp->en_enop;
694 unsigned int mod_flags;
697 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
698 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
700 * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
701 * (which we do not reset here) must have been shut down or never
704 * A rule of thumb here is: If the controller or MC reboots, is *any*
705 * state lost. If it's lost and needs reapplying, then the module
706 * *must* not be initialised during the reset.
708 mod_flags = enp->en_mod_flags;
709 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
710 EFX_MOD_VPD | EFX_MOD_MON);
712 mod_flags &= ~EFX_MOD_TUNNEL;
713 #endif /* EFSYS_OPT_TUNNEL */
714 EFSYS_ASSERT3U(mod_flags, ==, 0);
715 if (mod_flags != 0) {
720 if ((rc = enop->eno_reset(enp)) != 0)
728 EFSYS_PROBE1(fail1, efx_rc_t, rc);
733 const efx_nic_cfg_t *
735 __in const efx_nic_t *enp)
737 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
738 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
740 return (&(enp->en_nic_cfg));
743 __checkReturn efx_rc_t
744 efx_nic_get_fw_version(
746 __out efx_nic_fw_info_t *enfip)
748 uint16_t mc_fw_version[4];
756 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
757 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
759 /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
760 EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
761 MC_CMD_GET_CAPABILITIES_OUT_RXDP);
762 EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
763 MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
764 EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
765 MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
766 EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
767 MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
768 EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
769 MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
771 rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
775 rc = efx_mcdi_get_capabilities(enp, NULL,
776 &enfip->enfi_rx_dpcpu_fw_id,
777 &enfip->enfi_tx_dpcpu_fw_id,
780 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
781 } else if (rc == ENOTSUP) {
782 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
783 enfip->enfi_rx_dpcpu_fw_id = 0;
784 enfip->enfi_tx_dpcpu_fw_id = 0;
789 memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
790 sizeof (mc_fw_version));
799 EFSYS_PROBE1(fail1, efx_rc_t, rc);
804 __checkReturn efx_rc_t
805 efx_nic_get_board_info(
807 __out efx_nic_board_info_t *board_infop)
809 efx_mcdi_version_t ver;
812 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
813 EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
815 rc = efx_mcdi_get_version(enp, EFX_MCDI_VERSION_BOARD_INFO, &ver);
816 if (rc == EMSGSIZE) {
818 * Typically, EMSGSIZE is returned by above call in the
819 * case when the NIC does not provide extra information.
823 } else if (rc != 0) {
827 if ((ver.emv_flags & EFX_MCDI_VERSION_BOARD_INFO) == 0) {
832 memcpy(board_infop, &ver.emv_board_info, sizeof (*board_infop));
834 /* MCDI should provide NUL-terminated strings, but stay vigilant. */
835 board_infop->enbi_serial[sizeof (board_infop->enbi_serial) - 1] = '\0';
836 board_infop->enbi_name[sizeof (board_infop->enbi_name) - 1] = '\0';
845 EFSYS_PROBE1(fail1, efx_rc_t, rc);
850 __checkReturn boolean_t
851 efx_nic_hw_unavailable(
854 const efx_nic_ops_t *enop = enp->en_enop;
856 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
857 /* NOTE: can be used by MCDI before NIC probe */
859 if (enop->eno_hw_unavailable != NULL) {
860 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
871 efx_nic_set_hw_unavailable(
874 const efx_nic_ops_t *enop = enp->en_enop;
876 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
878 if (enop->eno_set_hw_unavailable != NULL)
879 enop->eno_set_hw_unavailable(enp);
885 __checkReturn efx_rc_t
886 efx_nic_register_test(
889 const efx_nic_ops_t *enop = enp->en_enop;
892 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
893 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
894 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
896 if ((rc = enop->eno_register_test(enp)) != 0)
902 EFSYS_PROBE1(fail1, efx_rc_t, rc);
907 #endif /* EFSYS_OPT_DIAG */
909 #if EFSYS_OPT_LOOPBACK
913 __in efx_loopback_kind_t loopback_kind,
914 __out efx_qword_t *maskp)
918 EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
919 EFSYS_ASSERT(maskp != NULL);
921 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
922 #define LOOPBACK_CHECK(_mcdi, _efx) \
923 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
925 LOOPBACK_CHECK(NONE, OFF);
926 LOOPBACK_CHECK(DATA, DATA);
927 LOOPBACK_CHECK(GMAC, GMAC);
928 LOOPBACK_CHECK(XGMII, XGMII);
929 LOOPBACK_CHECK(XGXS, XGXS);
930 LOOPBACK_CHECK(XAUI, XAUI);
931 LOOPBACK_CHECK(GMII, GMII);
932 LOOPBACK_CHECK(SGMII, SGMII);
933 LOOPBACK_CHECK(XGBR, XGBR);
934 LOOPBACK_CHECK(XFI, XFI);
935 LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
936 LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
937 LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
938 LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
939 LOOPBACK_CHECK(GPHY, GPHY);
940 LOOPBACK_CHECK(PHYXS, PHY_XS);
941 LOOPBACK_CHECK(PCS, PCS);
942 LOOPBACK_CHECK(PMAPMD, PMA_PMD);
943 LOOPBACK_CHECK(XPORT, XPORT);
944 LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
945 LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
946 LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
947 LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
948 LOOPBACK_CHECK(GMII_WS, GMII_WS);
949 LOOPBACK_CHECK(XFI_WS, XFI_WS);
950 LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
951 LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
952 LOOPBACK_CHECK(PMA_INT, PMA_INT);
953 LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
954 LOOPBACK_CHECK(SD_FAR, SD_FAR);
955 LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
956 LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
957 LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
958 LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
959 LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
960 LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
961 LOOPBACK_CHECK(DATA_WS, DATA_WS);
962 LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
963 #undef LOOPBACK_CHECK
965 /* Build bitmask of possible loopback types */
966 EFX_ZERO_QWORD(mask);
968 if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
969 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
970 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
973 if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
974 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
976 * The "MAC" grouping has historically been used by drivers to
977 * mean loopbacks supported by on-chip hardware. Keep that
978 * meaning here, and include on-chip PHY layer loopbacks.
980 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
981 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
982 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
983 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
984 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
985 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
986 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
987 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
988 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
989 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
990 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
991 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
992 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
993 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
994 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
995 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
998 if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
999 (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
1001 * The "PHY" grouping has historically been used by drivers to
1002 * mean loopbacks supported by off-chip hardware. Keep that
1005 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
1006 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
1007 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
1008 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
1014 __checkReturn efx_rc_t
1015 efx_mcdi_get_loopback_modes(
1016 __in efx_nic_t *enp)
1018 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1020 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
1021 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
1026 req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
1027 req.emr_in_buf = payload;
1028 req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
1029 req.emr_out_buf = payload;
1030 req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
1032 efx_mcdi_execute(enp, &req);
1034 if (req.emr_rc != 0) {
1039 if (req.emr_out_length_used <
1040 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
1041 MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
1047 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
1048 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
1050 efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
1053 *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
1055 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
1056 EFX_AND_QWORD(modes, mask);
1057 encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
1059 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
1060 EFX_AND_QWORD(modes, mask);
1061 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
1063 modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
1064 EFX_AND_QWORD(modes, mask);
1065 encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
1067 if (req.emr_out_length_used >=
1068 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
1069 MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
1070 /* Response includes 40G loopback modes */
1071 modes = *MCDI_OUT2(req, efx_qword_t,
1072 GET_LOOPBACK_MODES_OUT_40G);
1073 EFX_AND_QWORD(modes, mask);
1074 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
1077 if (req.emr_out_length_used >=
1078 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
1079 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
1080 /* Response includes 25G loopback modes */
1081 modes = *MCDI_OUT2(req, efx_qword_t,
1082 GET_LOOPBACK_MODES_OUT_V2_25G);
1083 EFX_AND_QWORD(modes, mask);
1084 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
1087 if (req.emr_out_length_used >=
1088 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
1089 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
1090 /* Response includes 50G loopback modes */
1091 modes = *MCDI_OUT2(req, efx_qword_t,
1092 GET_LOOPBACK_MODES_OUT_V2_50G);
1093 EFX_AND_QWORD(modes, mask);
1094 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
1097 if (req.emr_out_length_used >=
1098 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
1099 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
1100 /* Response includes 100G loopback modes */
1101 modes = *MCDI_OUT2(req, efx_qword_t,
1102 GET_LOOPBACK_MODES_OUT_V2_100G);
1103 EFX_AND_QWORD(modes, mask);
1104 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
1107 EFX_ZERO_QWORD(modes);
1108 EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
1109 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
1110 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
1111 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
1112 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
1113 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
1114 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
1115 EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
1116 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
1123 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1128 #endif /* EFSYS_OPT_LOOPBACK */
1130 __checkReturn efx_rc_t
1131 efx_nic_calculate_pcie_link_bandwidth(
1132 __in uint32_t pcie_link_width,
1133 __in uint32_t pcie_link_gen,
1134 __out uint32_t *bandwidth_mbpsp)
1136 uint32_t lane_bandwidth;
1137 uint32_t total_bandwidth;
1140 if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
1141 !ISP2(pcie_link_width)) {
1146 switch (pcie_link_gen) {
1147 case EFX_PCIE_LINK_SPEED_GEN1:
1148 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
1149 lane_bandwidth = 2000;
1151 case EFX_PCIE_LINK_SPEED_GEN2:
1152 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
1153 lane_bandwidth = 4000;
1155 case EFX_PCIE_LINK_SPEED_GEN3:
1156 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
1157 lane_bandwidth = 7877;
1164 total_bandwidth = lane_bandwidth * pcie_link_width;
1165 *bandwidth_mbpsp = total_bandwidth;
1172 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1177 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1179 __checkReturn efx_rc_t
1180 efx_nic_get_fw_subvariant(
1181 __in efx_nic_t *enp,
1182 __out efx_nic_fw_subvariant_t *subvariantp)
1187 rc = efx_mcdi_get_nic_global(enp,
1188 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1192 /* Mapping is not required since values match MCDI */
1193 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1194 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1195 EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1196 MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1199 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1200 case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1201 *subvariantp = value;
1214 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1219 __checkReturn efx_rc_t
1220 efx_nic_set_fw_subvariant(
1221 __in efx_nic_t *enp,
1222 __in efx_nic_fw_subvariant_t subvariant)
1226 switch (subvariant) {
1227 case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1228 case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1229 /* Mapping is not required since values match MCDI */
1236 rc = efx_mcdi_set_nic_global(enp,
1237 MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1247 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1252 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1254 __checkReturn efx_rc_t
1255 efx_nic_check_pcie_link_speed(
1256 __in efx_nic_t *enp,
1257 __in uint32_t pcie_link_width,
1258 __in uint32_t pcie_link_gen,
1259 __out efx_pcie_link_performance_t *resultp)
1261 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1263 efx_pcie_link_performance_t result;
1266 if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1267 (pcie_link_width == 0) || (pcie_link_width == 32) ||
1268 (pcie_link_gen == 0)) {
1270 * No usable info on what is required and/or in use. In virtual
1271 * machines, sometimes the PCIe link width is reported as 0 or
1272 * 32, or the speed as 0.
1274 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1278 /* Calculate the available bandwidth in megabits per second */
1279 rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1280 pcie_link_gen, &bandwidth);
1284 if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1285 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1286 } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1287 /* The link provides enough bandwidth but not optimal latency */
1288 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1290 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1299 EFSYS_PROBE1(fail1, efx_rc_t, rc);