drivers/common/sfc_efx/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         if (venid == EFX_PCI_VENID_XILINX) {
  89                 switch (devid) {
  90 #if EFSYS_OPT_RIVERHEAD
  91                 case EFX_PCI_DEVID_RIVERHEAD:
  92                 case EFX_PCI_DEVID_RIVERHEAD_VF:
  93                         *efp = EFX_FAMILY_RIVERHEAD;
  94                         *membarp = EFX_MEM_BAR_RIVERHEAD;
  95                         return (0);
  96 #endif /* EFSYS_OPT_RIVERHEAD */
  97                 default:
  98                         break;
  99                 }
 100         }
 101
 102         *efp = EFX_FAMILY_INVALID;
 103         return (ENOTSUP);
 104 }
 105
 106
 107 #if EFSYS_OPT_SIENA
 108
 109 static const efx_nic_ops_t      __efx_nic_siena_ops = {
 110         siena_nic_probe,                /* eno_probe */
 111         NULL,                           /* eno_board_cfg */
 112         NULL,                           /* eno_set_drv_limits */
 113         siena_nic_reset,                /* eno_reset */
 114         siena_nic_init,                 /* eno_init */
 115         NULL,                           /* eno_get_vi_pool */
 116         NULL,                           /* eno_get_bar_region */
 117         NULL,                           /* eno_hw_unavailable */
 118         NULL,                           /* eno_set_hw_unavailable */
 119 #if EFSYS_OPT_DIAG
 120         siena_nic_register_test,        /* eno_register_test */
 121 #endif  /* EFSYS_OPT_DIAG */
 122         siena_nic_fini,                 /* eno_fini */
 123         siena_nic_unprobe,              /* eno_unprobe */
 124 };
 125
 126 #endif  /* EFSYS_OPT_SIENA */
 127
 128 #if EFSYS_OPT_HUNTINGTON
 129
 130 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 131         ef10_nic_probe,                 /* eno_probe */
 132         hunt_board_cfg,                 /* eno_board_cfg */
 133         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 134         ef10_nic_reset,                 /* eno_reset */
 135         ef10_nic_init,                  /* eno_init */
 136         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 137         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 138         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 139         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 140 #if EFSYS_OPT_DIAG
 141         ef10_nic_register_test,         /* eno_register_test */
 142 #endif  /* EFSYS_OPT_DIAG */
 143         ef10_nic_fini,                  /* eno_fini */
 144         ef10_nic_unprobe,               /* eno_unprobe */
 145 };
 146
 147 #endif  /* EFSYS_OPT_HUNTINGTON */
 148
 149 #if EFSYS_OPT_MEDFORD
 150
 151 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 152         ef10_nic_probe,                 /* eno_probe */
 153         medford_board_cfg,              /* eno_board_cfg */
 154         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 155         ef10_nic_reset,                 /* eno_reset */
 156         ef10_nic_init,                  /* eno_init */
 157         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 158         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 159         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 160         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 161 #if EFSYS_OPT_DIAG
 162         ef10_nic_register_test,         /* eno_register_test */
 163 #endif  /* EFSYS_OPT_DIAG */
 164         ef10_nic_fini,                  /* eno_fini */
 165         ef10_nic_unprobe,               /* eno_unprobe */
 166 };
 167
 168 #endif  /* EFSYS_OPT_MEDFORD */
 169
 170 #if EFSYS_OPT_MEDFORD2
 171
 172 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 173         ef10_nic_probe,                 /* eno_probe */
 174         medford2_board_cfg,             /* eno_board_cfg */
 175         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 176         ef10_nic_reset,                 /* eno_reset */
 177         ef10_nic_init,                  /* eno_init */
 178         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 179         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 180         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 181         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 182 #if EFSYS_OPT_DIAG
 183         ef10_nic_register_test,         /* eno_register_test */
 184 #endif  /* EFSYS_OPT_DIAG */
 185         ef10_nic_fini,                  /* eno_fini */
 186         ef10_nic_unprobe,               /* eno_unprobe */
 187 };
 188
 189 #endif  /* EFSYS_OPT_MEDFORD2 */
 190
 191
 192         __checkReturn   efx_rc_t
 193 efx_nic_create(
 194         __in            efx_family_t family,
 195         __in            efsys_identifier_t *esip,
 196         __in            efsys_bar_t *esbp,
 197         __in            efsys_lock_t *eslp,
 198         __deref_out     efx_nic_t **enpp)
 199 {
 200         efx_nic_t *enp;
 201         efx_rc_t rc;
 202
 203         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 204         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 205
 206         /* Allocate a NIC object */
 207         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 208
 209         if (enp == NULL) {
 210                 rc = ENOMEM;
 211                 goto fail1;
 212         }
 213
 214         enp->en_magic = EFX_NIC_MAGIC;
 215
 216         switch (family) {
 217 #if EFSYS_OPT_SIENA
 218         case EFX_FAMILY_SIENA:
 219                 enp->en_enop = &__efx_nic_siena_ops;
 220                 enp->en_features =
 221                     EFX_FEATURE_IPV6 |
 222                     EFX_FEATURE_LFSR_HASH_INSERT |
 223                     EFX_FEATURE_LINK_EVENTS |
 224                     EFX_FEATURE_PERIODIC_MAC_STATS |
 225                     EFX_FEATURE_MCDI |
 226                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 227                     EFX_FEATURE_MAC_HEADER_FILTERS |
 228                     EFX_FEATURE_TX_SRC_FILTERS;
 229                 break;
 230 #endif  /* EFSYS_OPT_SIENA */
 231
 232 #if EFSYS_OPT_HUNTINGTON
 233         case EFX_FAMILY_HUNTINGTON:
 234                 enp->en_enop = &__efx_nic_hunt_ops;
 235                 enp->en_features =
 236                     EFX_FEATURE_IPV6 |
 237                     EFX_FEATURE_LINK_EVENTS |
 238                     EFX_FEATURE_PERIODIC_MAC_STATS |
 239                     EFX_FEATURE_MCDI |
 240                     EFX_FEATURE_MAC_HEADER_FILTERS |
 241                     EFX_FEATURE_MCDI_DMA |
 242                     EFX_FEATURE_PIO_BUFFERS |
 243                     EFX_FEATURE_FW_ASSISTED_TSO |
 244                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 245                     EFX_FEATURE_PACKED_STREAM |
 246                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 247                 break;
 248 #endif  /* EFSYS_OPT_HUNTINGTON */
 249
 250 #if EFSYS_OPT_MEDFORD
 251         case EFX_FAMILY_MEDFORD:
 252                 enp->en_enop = &__efx_nic_medford_ops;
 253                 /*
 254                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 255                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 256                  */
 257                 enp->en_features =
 258                     EFX_FEATURE_IPV6 |
 259                     EFX_FEATURE_LINK_EVENTS |
 260                     EFX_FEATURE_PERIODIC_MAC_STATS |
 261                     EFX_FEATURE_MCDI |
 262                     EFX_FEATURE_MAC_HEADER_FILTERS |
 263                     EFX_FEATURE_MCDI_DMA |
 264                     EFX_FEATURE_PIO_BUFFERS |
 265                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 266                     EFX_FEATURE_PACKED_STREAM |
 267                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 268                 break;
 269 #endif  /* EFSYS_OPT_MEDFORD */
 270
 271 #if EFSYS_OPT_MEDFORD2
 272         case EFX_FAMILY_MEDFORD2:
 273                 enp->en_enop = &__efx_nic_medford2_ops;
 274                 enp->en_features =
 275                     EFX_FEATURE_IPV6 |
 276                     EFX_FEATURE_LINK_EVENTS |
 277                     EFX_FEATURE_PERIODIC_MAC_STATS |
 278                     EFX_FEATURE_MCDI |
 279                     EFX_FEATURE_MAC_HEADER_FILTERS |
 280                     EFX_FEATURE_MCDI_DMA |
 281                     EFX_FEATURE_PIO_BUFFERS |
 282                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 283                     EFX_FEATURE_PACKED_STREAM |
 284                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 285                 break;
 286 #endif  /* EFSYS_OPT_MEDFORD2 */
 287
 288         default:
 289                 rc = ENOTSUP;
 290                 goto fail2;
 291         }
 292
 293         enp->en_family = family;
 294         enp->en_esip = esip;
 295         enp->en_esbp = esbp;
 296         enp->en_eslp = eslp;
 297
 298         *enpp = enp;
 299
 300         return (0);
 301
 302 fail2:
 303         EFSYS_PROBE(fail2);
 304
 305         enp->en_magic = 0;
 306
 307         /* Free the NIC object */
 308         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 309
 310 fail1:
 311         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 312
 313         return (rc);
 314 }
 315
 316         __checkReturn   efx_rc_t
 317 efx_nic_probe(
 318         __in            efx_nic_t *enp,
 319         __in            efx_fw_variant_t efv)
 320 {
 321         const efx_nic_ops_t *enop;
 322         efx_rc_t rc;
 323
 324         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 325 #if EFSYS_OPT_MCDI
 326         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 327 #endif  /* EFSYS_OPT_MCDI */
 328         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 329
 330         /* Ensure FW variant codes match with MC_CMD_FW codes */
 331         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 332             MC_CMD_FW_FULL_FEATURED);
 333         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 334             MC_CMD_FW_LOW_LATENCY);
 335         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 336             MC_CMD_FW_PACKED_STREAM);
 337         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 338             MC_CMD_FW_HIGH_TX_RATE);
 339         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 340             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 341         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 342             MC_CMD_FW_RULES_ENGINE);
 343         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 344             MC_CMD_FW_DPDK);
 345         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 346             (int)MC_CMD_FW_DONT_CARE);
 347
 348         enop = enp->en_enop;
 349         enp->efv = efv;
 350
 351         if ((rc = enop->eno_probe(enp)) != 0)
 352                 goto fail1;
 353
 354         if ((rc = efx_phy_probe(enp)) != 0)
 355                 goto fail2;
 356
 357         enp->en_mod_flags |= EFX_MOD_PROBE;
 358
 359         return (0);
 360
 361 fail2:
 362         EFSYS_PROBE(fail2);
 363
 364         enop->eno_unprobe(enp);
 365
 366 fail1:
 367         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 368
 369         return (rc);
 370 }
 371
 372         __checkReturn   efx_rc_t
 373 efx_nic_set_drv_limits(
 374         __inout         efx_nic_t *enp,
 375         __in            efx_drv_limits_t *edlp)
 376 {
 377         const efx_nic_ops_t *enop = enp->en_enop;
 378         efx_rc_t rc;
 379
 380         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 381         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 382
 383         if (enop->eno_set_drv_limits != NULL) {
 384                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 385                         goto fail1;
 386         }
 387
 388         return (0);
 389
 390 fail1:
 391         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 392
 393         return (rc);
 394 }
 395
 396         __checkReturn   efx_rc_t
 397 efx_nic_set_drv_version(
 398         __inout                 efx_nic_t *enp,
 399         __in_ecount(length)     char const *verp,
 400         __in                    size_t length)
 401 {
 402         efx_rc_t rc;
 403
 404         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 405         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 406
 407         /*
 408          * length is the string content length in bytes.
 409          * Accept any content which fits into the version
 410          * buffer, excluding the last byte. This is reserved
 411          * for an appended NUL terminator.
 412          */
 413         if (length >= sizeof (enp->en_drv_version)) {
 414                 rc = E2BIG;
 415                 goto fail1;
 416         }
 417
 418         (void) memset(enp->en_drv_version, 0,
 419             sizeof (enp->en_drv_version));
 420         memcpy(enp->en_drv_version, verp, length);
 421
 422         return (0);
 423
 424 fail1:
 425         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 426
 427         return (rc);
 428 }
 429
 430
 431         __checkReturn   efx_rc_t
 432 efx_nic_get_bar_region(
 433         __in            efx_nic_t *enp,
 434         __in            efx_nic_region_t region,
 435         __out           uint32_t *offsetp,
 436         __out           size_t *sizep)
 437 {
 438         const efx_nic_ops_t *enop = enp->en_enop;
 439         efx_rc_t rc;
 440
 441         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 442         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 443         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 444
 445         if (enop->eno_get_bar_region == NULL) {
 446                 rc = ENOTSUP;
 447                 goto fail1;
 448         }
 449         if ((rc = (enop->eno_get_bar_region)(enp,
 450                     region, offsetp, sizep)) != 0) {
 451                 goto fail2;
 452         }
 453
 454         return (0);
 455
 456 fail2:
 457         EFSYS_PROBE(fail2);
 458
 459 fail1:
 460         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 461
 462         return (rc);
 463 }
 464
 465
 466         __checkReturn   efx_rc_t
 467 efx_nic_get_vi_pool(
 468         __in            efx_nic_t *enp,
 469         __out           uint32_t *evq_countp,
 470         __out           uint32_t *rxq_countp,
 471         __out           uint32_t *txq_countp)
 472 {
 473         const efx_nic_ops_t *enop = enp->en_enop;
 474         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 475         efx_rc_t rc;
 476
 477         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 478         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 479         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 480
 481         if (enop->eno_get_vi_pool != NULL) {
 482                 uint32_t vi_count = 0;
 483
 484                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 485                         goto fail1;
 486
 487                 *evq_countp = vi_count;
 488                 *rxq_countp = vi_count;
 489                 *txq_countp = vi_count;
 490         } else {
 491                 /* Use NIC limits as default value */
 492                 *evq_countp = encp->enc_evq_limit;
 493                 *rxq_countp = encp->enc_rxq_limit;
 494                 *txq_countp = encp->enc_txq_limit;
 495         }
 496
 497         return (0);
 498
 499 fail1:
 500         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 501
 502         return (rc);
 503 }
 504
 505
 506         __checkReturn   efx_rc_t
 507 efx_nic_init(
 508         __in            efx_nic_t *enp)
 509 {
 510         const efx_nic_ops_t *enop = enp->en_enop;
 511         efx_rc_t rc;
 512
 513         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 514         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 515
 516         if (enp->en_mod_flags & EFX_MOD_NIC) {
 517                 rc = EINVAL;
 518                 goto fail1;
 519         }
 520
 521         if ((rc = enop->eno_init(enp)) != 0)
 522                 goto fail2;
 523
 524         enp->en_mod_flags |= EFX_MOD_NIC;
 525
 526         return (0);
 527
 528 fail2:
 529         EFSYS_PROBE(fail2);
 530 fail1:
 531         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 532
 533         return (rc);
 534 }
 535
 536                         void
 537 efx_nic_fini(
 538         __in            efx_nic_t *enp)
 539 {
 540         const efx_nic_ops_t *enop = enp->en_enop;
 541
 542         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 543         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 544         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 545         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 546         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 547         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 548         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 549
 550         enop->eno_fini(enp);
 551
 552         enp->en_mod_flags &= ~EFX_MOD_NIC;
 553 }
 554
 555                         void
 556 efx_nic_unprobe(
 557         __in            efx_nic_t *enp)
 558 {
 559         const efx_nic_ops_t *enop = enp->en_enop;
 560
 561         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 562 #if EFSYS_OPT_MCDI
 563         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 564 #endif  /* EFSYS_OPT_MCDI */
 565         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 566         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 567         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 568         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 569         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 570         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 571
 572         efx_phy_unprobe(enp);
 573
 574         enop->eno_unprobe(enp);
 575
 576         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 577 }
 578
 579                         void
 580 efx_nic_destroy(
 581         __in    efx_nic_t *enp)
 582 {
 583         efsys_identifier_t *esip = enp->en_esip;
 584
 585         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 586         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 587
 588         enp->en_family = EFX_FAMILY_INVALID;
 589         enp->en_esip = NULL;
 590         enp->en_esbp = NULL;
 591         enp->en_eslp = NULL;
 592
 593         enp->en_enop = NULL;
 594
 595         enp->en_magic = 0;
 596
 597         /* Free the NIC object */
 598         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 599 }
 600
 601         __checkReturn   efx_rc_t
 602 efx_nic_reset(
 603         __in            efx_nic_t *enp)
 604 {
 605         const efx_nic_ops_t *enop = enp->en_enop;
 606         unsigned int mod_flags;
 607         efx_rc_t rc;
 608
 609         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 610         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 611         /*
 612          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 613          * (which we do not reset here) must have been shut down or never
 614          * initialized.
 615          *
 616          * A rule of thumb here is: If the controller or MC reboots, is *any*
 617          * state lost. If it's lost and needs reapplying, then the module
 618          * *must* not be initialised during the reset.
 619          */
 620         mod_flags = enp->en_mod_flags;
 621         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 622             EFX_MOD_VPD | EFX_MOD_MON);
 623 #if EFSYS_OPT_TUNNEL
 624         mod_flags &= ~EFX_MOD_TUNNEL;
 625 #endif /* EFSYS_OPT_TUNNEL */
 626         EFSYS_ASSERT3U(mod_flags, ==, 0);
 627         if (mod_flags != 0) {
 628                 rc = EINVAL;
 629                 goto fail1;
 630         }
 631
 632         if ((rc = enop->eno_reset(enp)) != 0)
 633                 goto fail2;
 634
 635         return (0);
 636
 637 fail2:
 638         EFSYS_PROBE(fail2);
 639 fail1:
 640         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 641
 642         return (rc);
 643 }
 644
 645                         const efx_nic_cfg_t *
 646 efx_nic_cfg_get(
 647         __in            const efx_nic_t *enp)
 648 {
 649         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 650         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 651
 652         return (&(enp->en_nic_cfg));
 653 }
 654
 655         __checkReturn           efx_rc_t
 656 efx_nic_get_fw_version(
 657         __in                    efx_nic_t *enp,
 658         __out                   efx_nic_fw_info_t *enfip)
 659 {
 660         uint16_t mc_fw_version[4];
 661         efx_rc_t rc;
 662
 663         if (enfip == NULL) {
 664                 rc = EINVAL;
 665                 goto fail1;
 666         }
 667
 668         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 669         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 670
 671         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 672         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 673             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 674         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 675             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 676         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 677             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 678         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 679             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 680         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 681             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 682
 683         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 684         if (rc != 0)
 685                 goto fail2;
 686
 687         rc = efx_mcdi_get_capabilities(enp, NULL,
 688             &enfip->enfi_rx_dpcpu_fw_id,
 689             &enfip->enfi_tx_dpcpu_fw_id,
 690             NULL, NULL);
 691         if (rc == 0) {
 692                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 693         } else if (rc == ENOTSUP) {
 694                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 695                 enfip->enfi_rx_dpcpu_fw_id = 0;
 696                 enfip->enfi_tx_dpcpu_fw_id = 0;
 697         } else {
 698                 goto fail3;
 699         }
 700
 701         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 702             sizeof (mc_fw_version));
 703
 704         return (0);
 705
 706 fail3:
 707         EFSYS_PROBE(fail3);
 708 fail2:
 709         EFSYS_PROBE(fail2);
 710 fail1:
 711         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 712
 713         return (rc);
 714 }
 715
 716         __checkReturn   boolean_t
 717 efx_nic_hw_unavailable(
 718         __in            efx_nic_t *enp)
 719 {
 720         const efx_nic_ops_t *enop = enp->en_enop;
 721
 722         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 723         /* NOTE: can be used by MCDI before NIC probe */
 724
 725         if (enop->eno_hw_unavailable != NULL) {
 726                 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
 727                         goto unavail;
 728         }
 729
 730         return (B_FALSE);
 731
 732 unavail:
 733         return (B_TRUE);
 734 }
 735
 736                         void
 737 efx_nic_set_hw_unavailable(
 738         __in            efx_nic_t *enp)
 739 {
 740         const efx_nic_ops_t *enop = enp->en_enop;
 741
 742         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 743
 744         if (enop->eno_set_hw_unavailable != NULL)
 745                 enop->eno_set_hw_unavailable(enp);
 746 }
 747
 748
 749 #if EFSYS_OPT_DIAG
 750
 751         __checkReturn   efx_rc_t
 752 efx_nic_register_test(
 753         __in            efx_nic_t *enp)
 754 {
 755         const efx_nic_ops_t *enop = enp->en_enop;
 756         efx_rc_t rc;
 757
 758         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 759         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 760         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 761
 762         if ((rc = enop->eno_register_test(enp)) != 0)
 763                 goto fail1;
 764
 765         return (0);
 766
 767 fail1:
 768         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 769
 770         return (rc);
 771 }
 772
 773 #endif  /* EFSYS_OPT_DIAG */
 774
 775 #if EFSYS_OPT_LOOPBACK
 776
 777 extern                  void
 778 efx_loopback_mask(
 779         __in    efx_loopback_kind_t loopback_kind,
 780         __out   efx_qword_t *maskp)
 781 {
 782         efx_qword_t mask;
 783
 784         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 785         EFSYS_ASSERT(maskp != NULL);
 786
 787         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 788 #define LOOPBACK_CHECK(_mcdi, _efx) \
 789         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 790
 791         LOOPBACK_CHECK(NONE, OFF);
 792         LOOPBACK_CHECK(DATA, DATA);
 793         LOOPBACK_CHECK(GMAC, GMAC);
 794         LOOPBACK_CHECK(XGMII, XGMII);
 795         LOOPBACK_CHECK(XGXS, XGXS);
 796         LOOPBACK_CHECK(XAUI, XAUI);
 797         LOOPBACK_CHECK(GMII, GMII);
 798         LOOPBACK_CHECK(SGMII, SGMII);
 799         LOOPBACK_CHECK(XGBR, XGBR);
 800         LOOPBACK_CHECK(XFI, XFI);
 801         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 802         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 803         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 804         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 805         LOOPBACK_CHECK(GPHY, GPHY);
 806         LOOPBACK_CHECK(PHYXS, PHY_XS);
 807         LOOPBACK_CHECK(PCS, PCS);
 808         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 809         LOOPBACK_CHECK(XPORT, XPORT);
 810         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 811         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 812         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 813         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 814         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 815         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 816         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 817         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 818         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 819         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 820         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 821         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 822         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 823         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 824         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 825         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 826         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 827         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 828         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 829 #undef LOOPBACK_CHECK
 830
 831         /* Build bitmask of possible loopback types */
 832         EFX_ZERO_QWORD(mask);
 833
 834         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 835             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 836                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 837         }
 838
 839         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 840             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 841                 /*
 842                  * The "MAC" grouping has historically been used by drivers to
 843                  * mean loopbacks supported by on-chip hardware. Keep that
 844                  * meaning here, and include on-chip PHY layer loopbacks.
 845                  */
 846                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 847                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 848                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 849                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 850                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 851                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 852                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 853                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 854                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 855                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 856                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 857                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 858                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 859                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 860                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 861                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 862         }
 863
 864         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 865             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 866                 /*
 867                  * The "PHY" grouping has historically been used by drivers to
 868                  * mean loopbacks supported by off-chip hardware. Keep that
 869                  * meaning here.
 870                  */
 871                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 872                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 873                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 874                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 875         }
 876
 877         *maskp = mask;
 878 }
 879
 880         __checkReturn   efx_rc_t
 881 efx_mcdi_get_loopback_modes(
 882         __in            efx_nic_t *enp)
 883 {
 884         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 885         efx_mcdi_req_t req;
 886         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 887                 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
 888         efx_qword_t mask;
 889         efx_qword_t modes;
 890         efx_rc_t rc;
 891
 892         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 893         req.emr_in_buf = payload;
 894         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 895         req.emr_out_buf = payload;
 896         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 897
 898         efx_mcdi_execute(enp, &req);
 899
 900         if (req.emr_rc != 0) {
 901                 rc = req.emr_rc;
 902                 goto fail1;
 903         }
 904
 905         if (req.emr_out_length_used <
 906             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 907             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 908                 rc = EMSGSIZE;
 909                 goto fail2;
 910         }
 911
 912         /*
 913          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 914          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 915          */
 916         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 917
 918         EFX_AND_QWORD(mask,
 919             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 920
 921         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 922         EFX_AND_QWORD(modes, mask);
 923         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 924
 925         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 926         EFX_AND_QWORD(modes, mask);
 927         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 928
 929         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 930         EFX_AND_QWORD(modes, mask);
 931         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 932
 933         if (req.emr_out_length_used >=
 934             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 935             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 936                 /* Response includes 40G loopback modes */
 937                 modes = *MCDI_OUT2(req, efx_qword_t,
 938                     GET_LOOPBACK_MODES_OUT_40G);
 939                 EFX_AND_QWORD(modes, mask);
 940                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 941         }
 942
 943         if (req.emr_out_length_used >=
 944             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
 945             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
 946                 /* Response includes 25G loopback modes */
 947                 modes = *MCDI_OUT2(req, efx_qword_t,
 948                     GET_LOOPBACK_MODES_OUT_V2_25G);
 949                 EFX_AND_QWORD(modes, mask);
 950                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
 951         }
 952
 953         if (req.emr_out_length_used >=
 954             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
 955             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
 956                 /* Response includes 50G loopback modes */
 957                 modes = *MCDI_OUT2(req, efx_qword_t,
 958                     GET_LOOPBACK_MODES_OUT_V2_50G);
 959                 EFX_AND_QWORD(modes, mask);
 960                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
 961         }
 962
 963         if (req.emr_out_length_used >=
 964             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
 965             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
 966                 /* Response includes 100G loopback modes */
 967                 modes = *MCDI_OUT2(req, efx_qword_t,
 968                     GET_LOOPBACK_MODES_OUT_V2_100G);
 969                 EFX_AND_QWORD(modes, mask);
 970                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
 971         }
 972
 973         EFX_ZERO_QWORD(modes);
 974         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
 975         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
 976         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
 977         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
 978         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
 979         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
 980         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
 981         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
 982         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
 983
 984         return (0);
 985
 986 fail2:
 987         EFSYS_PROBE(fail2);
 988 fail1:
 989         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 990
 991         return (rc);
 992 }
 993
 994 #endif /* EFSYS_OPT_LOOPBACK */
 995
 996         __checkReturn   efx_rc_t
 997 efx_nic_calculate_pcie_link_bandwidth(
 998         __in            uint32_t pcie_link_width,
 999         __in            uint32_t pcie_link_gen,
1000         __out           uint32_t *bandwidth_mbpsp)
1001 {
1002         uint32_t lane_bandwidth;
1003         uint32_t total_bandwidth;
1004         efx_rc_t rc;
1005
1006         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
1007             !ISP2(pcie_link_width)) {
1008                 rc = EINVAL;
1009                 goto fail1;
1010         }
1011
1012         switch (pcie_link_gen) {
1013         case EFX_PCIE_LINK_SPEED_GEN1:
1014                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
1015                 lane_bandwidth = 2000;
1016                 break;
1017         case EFX_PCIE_LINK_SPEED_GEN2:
1018                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
1019                 lane_bandwidth = 4000;
1020                 break;
1021         case EFX_PCIE_LINK_SPEED_GEN3:
1022                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
1023                 lane_bandwidth = 7877;
1024                 break;
1025         default:
1026                 rc = EINVAL;
1027                 goto fail2;
1028         }
1029
1030         total_bandwidth = lane_bandwidth * pcie_link_width;
1031         *bandwidth_mbpsp = total_bandwidth;
1032
1033         return (0);
1034
1035 fail2:
1036         EFSYS_PROBE(fail2);
1037 fail1:
1038         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1039
1040         return (rc);
1041 }
1042
1043 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1044
1045         __checkReturn   efx_rc_t
1046 efx_nic_get_fw_subvariant(
1047         __in            efx_nic_t *enp,
1048         __out           efx_nic_fw_subvariant_t *subvariantp)
1049 {
1050         efx_rc_t rc;
1051         uint32_t value;
1052
1053         rc = efx_mcdi_get_nic_global(enp,
1054             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1055         if (rc != 0)
1056                 goto fail1;
1057
1058         /* Mapping is not required since values match MCDI */
1059         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1060             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1061         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1062             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1063
1064         switch (value) {
1065         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1066         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1067                 *subvariantp = value;
1068                 break;
1069         default:
1070                 rc = EINVAL;
1071                 goto fail2;
1072         }
1073
1074         return (0);
1075
1076 fail2:
1077         EFSYS_PROBE(fail2);
1078
1079 fail1:
1080         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1081
1082         return (rc);
1083 }
1084
1085         __checkReturn   efx_rc_t
1086 efx_nic_set_fw_subvariant(
1087         __in            efx_nic_t *enp,
1088         __in            efx_nic_fw_subvariant_t subvariant)
1089 {
1090         efx_rc_t rc;
1091
1092         switch (subvariant) {
1093         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1094         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1095                 /* Mapping is not required since values match MCDI */
1096                 break;
1097         default:
1098                 rc = EINVAL;
1099                 goto fail1;
1100         }
1101
1102         rc = efx_mcdi_set_nic_global(enp,
1103             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1104         if (rc != 0)
1105                 goto fail2;
1106
1107         return (0);
1108
1109 fail2:
1110         EFSYS_PROBE(fail2);
1111
1112 fail1:
1113         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1114
1115         return (rc);
1116 }
1117
1118 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1119
1120         __checkReturn   efx_rc_t
1121 efx_nic_check_pcie_link_speed(
1122         __in            efx_nic_t *enp,
1123         __in            uint32_t pcie_link_width,
1124         __in            uint32_t pcie_link_gen,
1125         __out           efx_pcie_link_performance_t *resultp)
1126 {
1127         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1128         uint32_t bandwidth;
1129         efx_pcie_link_performance_t result;
1130         efx_rc_t rc;
1131
1132         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1133             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1134             (pcie_link_gen == 0)) {
1135                 /*
1136                  * No usable info on what is required and/or in use. In virtual
1137                  * machines, sometimes the PCIe link width is reported as 0 or
1138                  * 32, or the speed as 0.
1139                  */
1140                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1141                 goto out;
1142         }
1143
1144         /* Calculate the available bandwidth in megabits per second */
1145         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1146                                             pcie_link_gen, &bandwidth);
1147         if (rc != 0)
1148                 goto fail1;
1149
1150         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1151                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1152         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1153                 /* The link provides enough bandwidth but not optimal latency */
1154                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1155         } else {
1156                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1157         }
1158
1159 out:
1160         *resultp = result;
1161
1162         return (0);
1163
1164 fail1:
1165         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1166
1167         return (rc);
1168 }