1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
51 static __checkReturn uint32_t
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out uint16_t *lengthp);
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t *erp);
104 static __checkReturn efx_rc_t
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in_opt const efx_rxq_type_data_t *type_data,
111 __in efsys_mem_t *esmp,
114 __in unsigned int flags,
116 __in efx_rxq_t *erp);
120 __in efx_rxq_t *erp);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
181 #endif /* EFX_OPTS_EF10() */
183 #if EFSYS_OPT_RIVERHEAD
184 static const efx_rx_ops_t __efx_rx_rhead_ops = {
185 rhead_rx_init, /* erxo_init */
186 rhead_rx_fini, /* erxo_fini */
187 #if EFSYS_OPT_RX_SCATTER
188 rhead_rx_scatter_enable, /* erxo_scatter_enable */
190 #if EFSYS_OPT_RX_SCALE
191 rhead_rx_scale_context_alloc, /* erxo_scale_context_alloc */
192 rhead_rx_scale_context_free, /* erxo_scale_context_free */
193 rhead_rx_scale_mode_set, /* erxo_scale_mode_set */
194 rhead_rx_scale_key_set, /* erxo_scale_key_set */
195 rhead_rx_scale_tbl_set, /* erxo_scale_tbl_set */
196 rhead_rx_prefix_hash, /* erxo_prefix_hash */
198 rhead_rx_prefix_pktlen, /* erxo_prefix_pktlen */
199 rhead_rx_qpost, /* erxo_qpost */
200 rhead_rx_qpush, /* erxo_qpush */
201 #if EFSYS_OPT_RX_PACKED_STREAM
202 NULL, /* erxo_qpush_ps_credits */
203 NULL, /* erxo_qps_packet_info */
205 rhead_rx_qflush, /* erxo_qflush */
206 rhead_rx_qenable, /* erxo_qenable */
207 rhead_rx_qcreate, /* erxo_qcreate */
208 rhead_rx_qdestroy, /* erxo_qdestroy */
210 #endif /* EFSYS_OPT_RIVERHEAD */
213 __checkReturn efx_rc_t
215 __inout efx_nic_t *enp)
217 const efx_rx_ops_t *erxop;
220 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
221 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
223 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
228 if (enp->en_mod_flags & EFX_MOD_RX) {
233 switch (enp->en_family) {
235 case EFX_FAMILY_SIENA:
236 erxop = &__efx_rx_siena_ops;
238 #endif /* EFSYS_OPT_SIENA */
240 #if EFSYS_OPT_HUNTINGTON
241 case EFX_FAMILY_HUNTINGTON:
242 erxop = &__efx_rx_ef10_ops;
244 #endif /* EFSYS_OPT_HUNTINGTON */
246 #if EFSYS_OPT_MEDFORD
247 case EFX_FAMILY_MEDFORD:
248 erxop = &__efx_rx_ef10_ops;
250 #endif /* EFSYS_OPT_MEDFORD */
252 #if EFSYS_OPT_MEDFORD2
253 case EFX_FAMILY_MEDFORD2:
254 erxop = &__efx_rx_ef10_ops;
256 #endif /* EFSYS_OPT_MEDFORD2 */
258 #if EFSYS_OPT_RIVERHEAD
259 case EFX_FAMILY_RIVERHEAD:
260 erxop = &__efx_rx_rhead_ops;
262 #endif /* EFSYS_OPT_RIVERHEAD */
270 if ((rc = erxop->erxo_init(enp)) != 0)
273 enp->en_erxop = erxop;
274 enp->en_mod_flags |= EFX_MOD_RX;
284 EFSYS_PROBE1(fail1, efx_rc_t, rc);
286 enp->en_erxop = NULL;
287 enp->en_mod_flags &= ~EFX_MOD_RX;
295 const efx_rx_ops_t *erxop = enp->en_erxop;
297 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
298 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
299 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
300 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
302 erxop->erxo_fini(enp);
304 enp->en_erxop = NULL;
305 enp->en_mod_flags &= ~EFX_MOD_RX;
308 #if EFSYS_OPT_RX_SCATTER
309 __checkReturn efx_rc_t
310 efx_rx_scatter_enable(
312 __in unsigned int buf_size)
314 const efx_rx_ops_t *erxop = enp->en_erxop;
317 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
318 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
320 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
326 EFSYS_PROBE1(fail1, efx_rc_t, rc);
329 #endif /* EFSYS_OPT_RX_SCATTER */
331 #if EFSYS_OPT_RX_SCALE
332 __checkReturn efx_rc_t
333 efx_rx_scale_hash_flags_get(
335 __in efx_rx_hash_alg_t hash_alg,
336 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
337 __in unsigned int max_nflags,
338 __out unsigned int *nflagsp)
340 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
341 unsigned int nflags = 0;
344 if (flagsp == NULL || nflagsp == NULL) {
349 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0) {
354 /* Helper to add flags word to flags array without buffer overflow */
355 #define INSERT_FLAGS(_flags) \
357 if (nflags >= max_nflags) { \
361 *(flagsp + nflags) = (_flags); \
364 _NOTE(CONSTANTCONDITION) \
367 if (encp->enc_rx_scale_l4_hash_supported != B_FALSE) {
368 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 4TUPLE));
369 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 4TUPLE));
372 if ((encp->enc_rx_scale_l4_hash_supported != B_FALSE) &&
373 (encp->enc_rx_scale_additional_modes_supported != B_FALSE)) {
374 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_DST));
375 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_SRC));
377 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_DST));
378 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_SRC));
380 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 4TUPLE));
381 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_DST));
382 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_SRC));
384 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 4TUPLE));
385 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_DST));
386 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_SRC));
389 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE));
390 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE));
392 INSERT_FLAGS(EFX_RX_HASH(IPV4, 2TUPLE));
393 INSERT_FLAGS(EFX_RX_HASH(IPV6, 2TUPLE));
395 if (encp->enc_rx_scale_additional_modes_supported != B_FALSE) {
396 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_DST));
397 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_SRC));
399 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_DST));
400 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_SRC));
402 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE));
403 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_DST));
404 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_SRC));
406 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE));
407 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_DST));
408 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_SRC));
410 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_DST));
411 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_SRC));
413 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_DST));
414 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_SRC));
417 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, DISABLE));
418 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, DISABLE));
420 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, DISABLE));
421 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, DISABLE));
423 INSERT_FLAGS(EFX_RX_HASH(IPV4, DISABLE));
424 INSERT_FLAGS(EFX_RX_HASH(IPV6, DISABLE));
435 EFSYS_PROBE1(fail1, efx_rc_t, rc);
440 __checkReturn efx_rc_t
441 efx_rx_hash_default_support_get(
443 __out efx_rx_hash_support_t *supportp)
447 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
448 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
450 if (supportp == NULL) {
456 * Report the hashing support the client gets by default if it
457 * does not allocate an RSS context itself.
459 *supportp = enp->en_hash_support;
464 EFSYS_PROBE1(fail1, efx_rc_t, rc);
469 __checkReturn efx_rc_t
470 efx_rx_scale_default_support_get(
472 __out efx_rx_scale_context_type_t *typep)
476 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
477 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
485 * Report the RSS support the client gets by default if it
486 * does not allocate an RSS context itself.
488 *typep = enp->en_rss_context_type;
493 EFSYS_PROBE1(fail1, efx_rc_t, rc);
497 #endif /* EFSYS_OPT_RX_SCALE */
499 #if EFSYS_OPT_RX_SCALE
500 __checkReturn efx_rc_t
501 efx_rx_scale_context_alloc(
503 __in efx_rx_scale_context_type_t type,
504 __in uint32_t num_queues,
505 __out uint32_t *rss_contextp)
507 const efx_rx_ops_t *erxop = enp->en_erxop;
510 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
511 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
513 if (erxop->erxo_scale_context_alloc == NULL) {
517 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
518 num_queues, rss_contextp)) != 0) {
527 EFSYS_PROBE1(fail1, efx_rc_t, rc);
530 #endif /* EFSYS_OPT_RX_SCALE */
532 #if EFSYS_OPT_RX_SCALE
533 __checkReturn efx_rc_t
534 efx_rx_scale_context_free(
536 __in uint32_t rss_context)
538 const efx_rx_ops_t *erxop = enp->en_erxop;
541 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
542 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
544 if (erxop->erxo_scale_context_free == NULL) {
548 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
556 EFSYS_PROBE1(fail1, efx_rc_t, rc);
559 #endif /* EFSYS_OPT_RX_SCALE */
561 #if EFSYS_OPT_RX_SCALE
562 __checkReturn efx_rc_t
563 efx_rx_scale_mode_set(
565 __in uint32_t rss_context,
566 __in efx_rx_hash_alg_t alg,
567 __in efx_rx_hash_type_t type,
568 __in boolean_t insert)
570 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
571 const efx_rx_ops_t *erxop = enp->en_erxop;
572 efx_rx_hash_type_t type_check;
576 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
577 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
580 * Legacy flags and modern bits cannot be
581 * used at the same time in the hash type.
583 if ((type & EFX_RX_HASH_LEGACY_MASK) &&
584 (type & ~EFX_RX_HASH_LEGACY_MASK)) {
590 * If RSS hash type is represented by additional bits
591 * in the value, the latter need to be verified since
592 * not all bit combinations are valid RSS modes. Also,
593 * depending on the firmware, some valid combinations
594 * may be unsupported. Discern additional bits in the
595 * type value and try to recognise valid combinations.
596 * If some bits remain unrecognised, report the error.
598 type_check = type & ~EFX_RX_HASH_LEGACY_MASK;
599 if (type_check != 0) {
600 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
601 unsigned int type_nflags;
603 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags,
604 EFX_ARRAY_SIZE(type_flags), &type_nflags);
608 for (i = 0; i < type_nflags; ++i) {
609 if ((type_check & type_flags[i]) == type_flags[i])
610 type_check &= ~(type_flags[i]);
613 if (type_check != 0) {
620 * Translate EFX_RX_HASH() flags to their legacy counterparts
621 * provided that the FW claims no support for additional modes.
623 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE) {
624 efx_rx_hash_type_t t_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE) |
625 EFX_RX_HASH(IPV4_TCP, 2TUPLE);
626 efx_rx_hash_type_t t_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE) |
627 EFX_RX_HASH(IPV6_TCP, 2TUPLE);
628 efx_rx_hash_type_t t_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
629 efx_rx_hash_type_t t_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
631 if ((type & t_ipv4) == t_ipv4)
632 type |= EFX_RX_HASH_IPV4;
633 if ((type & t_ipv6) == t_ipv6)
634 type |= EFX_RX_HASH_IPV6;
636 if (encp->enc_rx_scale_l4_hash_supported == B_TRUE) {
637 if ((type & t_ipv4_tcp) == t_ipv4_tcp)
638 type |= EFX_RX_HASH_TCPIPV4;
639 if ((type & t_ipv6_tcp) == t_ipv6_tcp)
640 type |= EFX_RX_HASH_TCPIPV6;
643 type &= EFX_RX_HASH_LEGACY_MASK;
646 if (erxop->erxo_scale_mode_set != NULL) {
647 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
661 EFSYS_PROBE1(fail1, efx_rc_t, rc);
664 #endif /* EFSYS_OPT_RX_SCALE */
666 #if EFSYS_OPT_RX_SCALE
667 __checkReturn efx_rc_t
668 efx_rx_scale_key_set(
670 __in uint32_t rss_context,
671 __in_ecount(n) uint8_t *key,
674 const efx_rx_ops_t *erxop = enp->en_erxop;
677 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
678 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
680 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
686 EFSYS_PROBE1(fail1, efx_rc_t, rc);
690 #endif /* EFSYS_OPT_RX_SCALE */
692 #if EFSYS_OPT_RX_SCALE
693 __checkReturn efx_rc_t
694 efx_rx_scale_tbl_set(
696 __in uint32_t rss_context,
697 __in_ecount(n) unsigned int *table,
700 const efx_rx_ops_t *erxop = enp->en_erxop;
703 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
704 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
706 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
712 EFSYS_PROBE1(fail1, efx_rc_t, rc);
716 #endif /* EFSYS_OPT_RX_SCALE */
721 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
723 __in unsigned int ndescs,
724 __in unsigned int completed,
725 __in unsigned int added)
727 efx_nic_t *enp = erp->er_enp;
728 const efx_rx_ops_t *erxop = enp->en_erxop;
730 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
731 EFSYS_ASSERT(erp->er_buf_size == 0 || size == erp->er_buf_size);
733 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
736 #if EFSYS_OPT_RX_PACKED_STREAM
739 efx_rx_qpush_ps_credits(
742 efx_nic_t *enp = erp->er_enp;
743 const efx_rx_ops_t *erxop = enp->en_erxop;
745 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
747 erxop->erxo_qpush_ps_credits(erp);
750 __checkReturn uint8_t *
751 efx_rx_qps_packet_info(
753 __in uint8_t *buffer,
754 __in uint32_t buffer_length,
755 __in uint32_t current_offset,
756 __out uint16_t *lengthp,
757 __out uint32_t *next_offsetp,
758 __out uint32_t *timestamp)
760 efx_nic_t *enp = erp->er_enp;
761 const efx_rx_ops_t *erxop = enp->en_erxop;
763 return (erxop->erxo_qps_packet_info(erp, buffer,
764 buffer_length, current_offset, lengthp,
765 next_offsetp, timestamp));
768 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
773 __in unsigned int added,
774 __inout unsigned int *pushedp)
776 efx_nic_t *enp = erp->er_enp;
777 const efx_rx_ops_t *erxop = enp->en_erxop;
779 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
781 erxop->erxo_qpush(erp, added, pushedp);
784 __checkReturn efx_rc_t
788 efx_nic_t *enp = erp->er_enp;
789 const efx_rx_ops_t *erxop = enp->en_erxop;
792 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
794 if ((rc = erxop->erxo_qflush(erp)) != 0)
800 EFSYS_PROBE1(fail1, efx_rc_t, rc);
807 __in const efx_nic_t *enp,
808 __in unsigned int ndescs)
810 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
812 return (ndescs * encp->enc_rx_desc_size);
815 __checkReturn unsigned int
817 __in const efx_nic_t *enp,
818 __in unsigned int ndescs)
820 return (EFX_DIV_ROUND_UP(efx_rxq_size(enp, ndescs), EFX_BUF_SIZE));
827 efx_nic_t *enp = erp->er_enp;
828 const efx_rx_ops_t *erxop = enp->en_erxop;
830 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
832 erxop->erxo_qenable(erp);
835 static __checkReturn efx_rc_t
836 efx_rx_qcreate_internal(
838 __in unsigned int index,
839 __in unsigned int label,
840 __in efx_rxq_type_t type,
841 __in_opt const efx_rxq_type_data_t *type_data,
842 __in efsys_mem_t *esmp,
845 __in unsigned int flags,
847 __deref_out efx_rxq_t **erpp)
849 const efx_rx_ops_t *erxop = enp->en_erxop;
851 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
854 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
855 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
857 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
859 EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs));
860 EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs));
862 if (index >= encp->enc_rxq_limit) {
868 ndescs < encp->enc_rxq_min_ndescs ||
869 ndescs > encp->enc_rxq_max_ndescs) {
874 /* Allocate an RXQ object */
875 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
882 erp->er_magic = EFX_RXQ_MAGIC;
884 erp->er_index = index;
885 erp->er_mask = ndescs - 1;
888 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
889 ndescs, id, flags, eep, erp)) != 0)
900 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
906 EFSYS_PROBE1(fail1, efx_rc_t, rc);
911 __checkReturn efx_rc_t
914 __in unsigned int index,
915 __in unsigned int label,
916 __in efx_rxq_type_t type,
917 __in size_t buf_size,
918 __in efsys_mem_t *esmp,
921 __in unsigned int flags,
923 __deref_out efx_rxq_t **erpp)
925 efx_rxq_type_data_t type_data;
927 memset(&type_data, 0, sizeof (type_data));
929 type_data.ertd_default.ed_buf_size = buf_size;
931 return efx_rx_qcreate_internal(enp, index, label, type, &type_data,
932 esmp, ndescs, id, flags, eep, erpp);
935 #if EFSYS_OPT_RX_PACKED_STREAM
937 __checkReturn efx_rc_t
938 efx_rx_qcreate_packed_stream(
940 __in unsigned int index,
941 __in unsigned int label,
942 __in uint32_t ps_buf_size,
943 __in efsys_mem_t *esmp,
946 __deref_out efx_rxq_t **erpp)
948 efx_rxq_type_data_t type_data;
950 memset(&type_data, 0, sizeof (type_data));
952 type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
954 return efx_rx_qcreate_internal(enp, index, label,
955 EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
956 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
961 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
963 __checkReturn efx_rc_t
964 efx_rx_qcreate_es_super_buffer(
966 __in unsigned int index,
967 __in unsigned int label,
968 __in uint32_t n_bufs_per_desc,
969 __in uint32_t max_dma_len,
970 __in uint32_t buf_stride,
971 __in uint32_t hol_block_timeout,
972 __in efsys_mem_t *esmp,
974 __in unsigned int flags,
976 __deref_out efx_rxq_t **erpp)
979 efx_rxq_type_data_t type_data;
981 if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
986 memset(&type_data, 0, sizeof (type_data));
988 type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc;
989 type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len;
990 type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride;
991 type_data.ertd_es_super_buffer.eessb_hol_block_timeout =
994 rc = efx_rx_qcreate_internal(enp, index, label,
995 EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs,
996 0 /* id unused on EF10 */, flags, eep, erpp);
1005 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1015 __in efx_rxq_t *erp)
1017 efx_nic_t *enp = erp->er_enp;
1018 const efx_rx_ops_t *erxop = enp->en_erxop;
1020 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1022 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1023 --enp->en_rx_qcount;
1025 erxop->erxo_qdestroy(erp);
1027 /* Free the RXQ object */
1028 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1031 __checkReturn efx_rc_t
1032 efx_pseudo_hdr_pkt_length_get(
1033 __in efx_rxq_t *erp,
1034 __in uint8_t *buffer,
1035 __out uint16_t *lengthp)
1037 efx_nic_t *enp = erp->er_enp;
1038 const efx_rx_ops_t *erxop = enp->en_erxop;
1040 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1042 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
1045 #if EFSYS_OPT_RX_SCALE
1046 __checkReturn uint32_t
1047 efx_pseudo_hdr_hash_get(
1048 __in efx_rxq_t *erp,
1049 __in efx_rx_hash_alg_t func,
1050 __in uint8_t *buffer)
1052 efx_nic_t *enp = erp->er_enp;
1053 const efx_rx_ops_t *erxop = enp->en_erxop;
1055 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1057 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
1058 return (erxop->erxo_prefix_hash(enp, func, buffer));
1060 #endif /* EFSYS_OPT_RX_SCALE */
1064 static __checkReturn efx_rc_t
1066 __in efx_nic_t *enp)
1071 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1073 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
1074 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
1075 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
1076 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
1077 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
1078 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
1079 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1081 /* Zero the RSS table */
1082 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
1084 EFX_ZERO_OWORD(oword);
1085 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1086 index, &oword, B_TRUE);
1089 #if EFSYS_OPT_RX_SCALE
1090 /* The RSS key and indirection table are writable. */
1091 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
1093 /* Hardware can insert RX hash with/without RSS */
1094 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
1095 #endif /* EFSYS_OPT_RX_SCALE */
1100 #if EFSYS_OPT_RX_SCATTER
1101 static __checkReturn efx_rc_t
1102 siena_rx_scatter_enable(
1103 __in efx_nic_t *enp,
1104 __in unsigned int buf_size)
1106 unsigned int nbuf32;
1110 nbuf32 = buf_size / 32;
1111 if ((nbuf32 == 0) ||
1112 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
1113 ((buf_size % 32) != 0)) {
1118 if (enp->en_rx_qcount > 0) {
1123 /* Set scatter buffer size */
1124 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1125 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
1126 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1128 /* Enable scatter for packets not matching a filter */
1129 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1130 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
1131 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1138 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1142 #endif /* EFSYS_OPT_RX_SCATTER */
1145 #define EFX_RX_LFSR_HASH(_enp, _insert) \
1147 efx_oword_t oword; \
1149 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1150 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
1151 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
1152 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
1153 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1154 (_insert) ? 1 : 0); \
1155 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1157 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
1158 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1160 EFX_SET_OWORD_FIELD(oword, \
1161 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
1162 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1166 _NOTE(CONSTANTCONDITION) \
1169 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
1171 efx_oword_t oword; \
1173 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1174 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
1175 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
1177 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
1179 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1180 (_insert) ? 1 : 0); \
1181 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1183 _NOTE(CONSTANTCONDITION) \
1186 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
1188 efx_oword_t oword; \
1190 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1191 EFX_SET_OWORD_FIELD(oword, \
1192 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
1193 EFX_SET_OWORD_FIELD(oword, \
1194 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1195 EFX_SET_OWORD_FIELD(oword, \
1196 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
1197 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1201 _NOTE(CONSTANTCONDITION) \
1205 #if EFSYS_OPT_RX_SCALE
1207 static __checkReturn efx_rc_t
1208 siena_rx_scale_mode_set(
1209 __in efx_nic_t *enp,
1210 __in uint32_t rss_context,
1211 __in efx_rx_hash_alg_t alg,
1212 __in efx_rx_hash_type_t type,
1213 __in boolean_t insert)
1217 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1223 case EFX_RX_HASHALG_LFSR:
1224 EFX_RX_LFSR_HASH(enp, insert);
1227 case EFX_RX_HASHALG_TOEPLITZ:
1228 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1229 (type & EFX_RX_HASH_IPV4) ? B_TRUE : B_FALSE,
1230 (type & EFX_RX_HASH_TCPIPV4) ? B_TRUE : B_FALSE);
1232 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1233 (type & EFX_RX_HASH_IPV6) ? B_TRUE : B_FALSE,
1234 (type & EFX_RX_HASH_TCPIPV6) ? B_TRUE : B_FALSE,
1253 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1255 EFX_RX_LFSR_HASH(enp, B_FALSE);
1261 #if EFSYS_OPT_RX_SCALE
1262 static __checkReturn efx_rc_t
1263 siena_rx_scale_key_set(
1264 __in efx_nic_t *enp,
1265 __in uint32_t rss_context,
1266 __in_ecount(n) uint8_t *key,
1271 unsigned int offset;
1274 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1281 /* Write Toeplitz IPv4 hash key */
1282 EFX_ZERO_OWORD(oword);
1283 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1284 offset > 0 && byte < n;
1286 oword.eo_u8[offset - 1] = key[byte++];
1288 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1292 /* Verify Toeplitz IPv4 hash key */
1293 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1294 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1295 offset > 0 && byte < n;
1297 if (oword.eo_u8[offset - 1] != key[byte++]) {
1303 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1308 /* Write Toeplitz IPv6 hash key 3 */
1309 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1310 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1311 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1312 offset > 0 && byte < n;
1314 oword.eo_u8[offset - 1] = key[byte++];
1316 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1318 /* Write Toeplitz IPv6 hash key 2 */
1319 EFX_ZERO_OWORD(oword);
1320 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1321 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1322 offset > 0 && byte < n;
1324 oword.eo_u8[offset - 1] = key[byte++];
1326 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1328 /* Write Toeplitz IPv6 hash key 1 */
1329 EFX_ZERO_OWORD(oword);
1330 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1331 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1332 offset > 0 && byte < n;
1334 oword.eo_u8[offset - 1] = key[byte++];
1336 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1340 /* Verify Toeplitz IPv6 hash key 3 */
1341 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1342 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1343 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1344 offset > 0 && byte < n;
1346 if (oword.eo_u8[offset - 1] != key[byte++]) {
1352 /* Verify Toeplitz IPv6 hash key 2 */
1353 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1354 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1355 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1356 offset > 0 && byte < n;
1358 if (oword.eo_u8[offset - 1] != key[byte++]) {
1364 /* Verify Toeplitz IPv6 hash key 1 */
1365 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1366 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1367 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1368 offset > 0 && byte < n;
1370 if (oword.eo_u8[offset - 1] != key[byte++]) {
1388 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1394 #if EFSYS_OPT_RX_SCALE
1395 static __checkReturn efx_rc_t
1396 siena_rx_scale_tbl_set(
1397 __in efx_nic_t *enp,
1398 __in uint32_t rss_context,
1399 __in_ecount(n) unsigned int *table,
1406 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1407 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1409 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1414 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1419 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1422 /* Calculate the entry to place in the table */
1423 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1425 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1427 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1429 /* Write the table */
1430 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1431 index, &oword, B_TRUE);
1434 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1437 /* Determine if we're starting a new batch */
1438 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1440 /* Read the table */
1441 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1442 index, &oword, B_TRUE);
1444 /* Verify the entry */
1445 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1458 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1465 * Falcon/Siena pseudo-header
1466 * --------------------------
1468 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1469 * The pseudo-header is a byte array of one of the forms:
1471 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1472 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1473 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1476 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1477 * LL.LL LFSR hash (16-bit big-endian)
1480 #if EFSYS_OPT_RX_SCALE
1481 static __checkReturn uint32_t
1482 siena_rx_prefix_hash(
1483 __in efx_nic_t *enp,
1484 __in efx_rx_hash_alg_t func,
1485 __in uint8_t *buffer)
1487 _NOTE(ARGUNUSED(enp))
1490 case EFX_RX_HASHALG_TOEPLITZ:
1491 return ((buffer[12] << 24) |
1492 (buffer[13] << 16) |
1496 case EFX_RX_HASHALG_LFSR:
1497 return ((buffer[14] << 8) | buffer[15]);
1504 #endif /* EFSYS_OPT_RX_SCALE */
1506 static __checkReturn efx_rc_t
1507 siena_rx_prefix_pktlen(
1508 __in efx_nic_t *enp,
1509 __in uint8_t *buffer,
1510 __out uint16_t *lengthp)
1512 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1514 /* Not supported by Falcon/Siena hardware */
1522 __in efx_rxq_t *erp,
1523 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1525 __in unsigned int ndescs,
1526 __in unsigned int completed,
1527 __in unsigned int added)
1531 unsigned int offset;
1534 /* The client driver must not overfill the queue */
1535 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1536 EFX_RXQ_LIMIT(erp->er_mask + 1));
1538 id = added & (erp->er_mask);
1539 for (i = 0; i < ndescs; i++) {
1540 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1541 unsigned int, id, efsys_dma_addr_t, addrp[i],
1544 EFX_POPULATE_QWORD_3(qword,
1545 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1546 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1547 (uint32_t)(addrp[i] & 0xffffffff),
1548 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1549 (uint32_t)(addrp[i] >> 32));
1551 offset = id * sizeof (efx_qword_t);
1552 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1554 id = (id + 1) & (erp->er_mask);
1560 __in efx_rxq_t *erp,
1561 __in unsigned int added,
1562 __inout unsigned int *pushedp)
1564 efx_nic_t *enp = erp->er_enp;
1565 unsigned int pushed = *pushedp;
1570 /* All descriptors are pushed */
1573 /* Push the populated descriptors out */
1574 wptr = added & erp->er_mask;
1576 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1578 /* Only write the third DWORD */
1579 EFX_POPULATE_DWORD_1(dword,
1580 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1582 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1583 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1584 wptr, pushed & erp->er_mask);
1585 EFSYS_PIO_WRITE_BARRIER();
1586 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1587 erp->er_index, &dword, B_FALSE);
1590 #if EFSYS_OPT_RX_PACKED_STREAM
1592 siena_rx_qpush_ps_credits(
1593 __in efx_rxq_t *erp)
1595 /* Not supported by Siena hardware */
1600 siena_rx_qps_packet_info(
1601 __in efx_rxq_t *erp,
1602 __in uint8_t *buffer,
1603 __in uint32_t buffer_length,
1604 __in uint32_t current_offset,
1605 __out uint16_t *lengthp,
1606 __out uint32_t *next_offsetp,
1607 __out uint32_t *timestamp)
1609 /* Not supported by Siena hardware */
1614 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1616 static __checkReturn efx_rc_t
1618 __in efx_rxq_t *erp)
1620 efx_nic_t *enp = erp->er_enp;
1624 label = erp->er_index;
1626 /* Flush the queue */
1627 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1628 FRF_AZ_RX_FLUSH_DESCQ, label);
1629 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1636 __in efx_rxq_t *erp)
1638 efx_nic_t *enp = erp->er_enp;
1641 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1643 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1644 erp->er_index, &oword, B_TRUE);
1646 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1647 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1648 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1650 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1651 erp->er_index, &oword, B_TRUE);
1654 static __checkReturn efx_rc_t
1656 __in efx_nic_t *enp,
1657 __in unsigned int index,
1658 __in unsigned int label,
1659 __in efx_rxq_type_t type,
1660 __in_opt const efx_rxq_type_data_t *type_data,
1661 __in efsys_mem_t *esmp,
1664 __in unsigned int flags,
1665 __in efx_evq_t *eep,
1666 __in efx_rxq_t *erp)
1668 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1671 boolean_t jumbo = B_FALSE;
1674 _NOTE(ARGUNUSED(esmp))
1676 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1677 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1678 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1681 (1U << size) <= encp->enc_rxq_max_ndescs / encp->enc_rxq_min_ndescs;
1683 if ((1U << size) == (uint32_t)ndescs / encp->enc_rxq_min_ndescs)
1685 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1691 case EFX_RXQ_TYPE_DEFAULT:
1692 erp->er_buf_size = type_data->ertd_default.ed_buf_size;
1700 if (flags & EFX_RXQ_FLAG_SCATTER) {
1701 #if EFSYS_OPT_RX_SCATTER
1706 #endif /* EFSYS_OPT_RX_SCATTER */
1709 /* Set up the new descriptor queue */
1710 EFX_POPULATE_OWORD_7(oword,
1711 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1712 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1713 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1714 FRF_AZ_RX_DESCQ_LABEL, label,
1715 FRF_AZ_RX_DESCQ_SIZE, size,
1716 FRF_AZ_RX_DESCQ_TYPE, 0,
1717 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1719 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1720 erp->er_index, &oword, B_TRUE);
1724 #if !EFSYS_OPT_RX_SCATTER
1731 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1738 __in efx_rxq_t *erp)
1740 efx_nic_t *enp = erp->er_enp;
1743 /* Purge descriptor queue */
1744 EFX_ZERO_OWORD(oword);
1746 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1747 erp->er_index, &oword, B_TRUE);
1752 __in efx_nic_t *enp)
1754 _NOTE(ARGUNUSED(enp))
1757 #endif /* EFSYS_OPT_SIENA */