1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
13 #if EFSYS_OPT_HUNTINGTON
15 #include "ef10_tlv_layout.h"
17 static __checkReturn efx_rc_t
18 hunt_nic_get_required_pcie_bandwidth(
20 __out uint32_t *bandwidth_mbpsp)
27 * On Huntington, the firmware may not give us the current port mode, so
28 * we need to go by the set of available port modes and assume the most
29 * capable mode is in use.
32 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
34 /* No port mode info available */
39 if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
41 * This needs the full PCIe bandwidth (and could use
42 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
44 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
45 EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
48 if (port_modes & (1U << TLV_PORT_MODE_40G)) {
50 } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
51 bandwidth = 4 * 10000;
53 /* Assume two 10G ports */
54 bandwidth = 2 * 10000;
59 *bandwidth_mbpsp = bandwidth;
64 EFSYS_PROBE1(fail1, efx_rc_t, rc);
69 __checkReturn efx_rc_t
73 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
74 efx_port_t *epp = &(enp->en_port);
75 uint32_t sysclk, dpcpu_clk;
80 * Event queue creation is complete when an
81 * EVQ_INIT_DONE_EV event is received.
83 encp->enc_evq_init_done_ev_supported = B_TRUE;
86 * Enable firmware workarounds for hardware errata.
87 * Expected responses are:
89 * Success: workaround enabled or disabled as requested.
90 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
91 * Firmware does not support the MC_CMD_WORKAROUND request.
92 * (assume that the workaround is not supported).
93 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
94 * Firmware does not support the requested workaround.
95 * - MC_CMD_ERR_EPERM (reported as EACCES):
96 * Unprivileged function cannot enable/disable workarounds.
98 * See efx_mcdi_request_errcode() for MCDI error translations.
102 * If the bug35388 workaround is enabled, then use an indirect access
103 * method to avoid unsafe EVQ writes.
105 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
107 if ((rc == 0) || (rc == EACCES))
108 encp->enc_bug35388_workaround = B_TRUE;
109 else if ((rc == ENOTSUP) || (rc == ENOENT))
110 encp->enc_bug35388_workaround = B_FALSE;
115 * If the bug41750 workaround is enabled, then do not test interrupts,
116 * as the test will fail (seen with Greenport controllers).
118 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
121 encp->enc_bug41750_workaround = B_TRUE;
122 } else if (rc == EACCES) {
123 /* Assume a controller with 40G ports needs the workaround. */
124 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
125 encp->enc_bug41750_workaround = B_TRUE;
127 encp->enc_bug41750_workaround = B_FALSE;
128 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
129 encp->enc_bug41750_workaround = B_FALSE;
133 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
134 /* Interrupt testing does not work for VFs. See bug50084. */
135 encp->enc_bug41750_workaround = B_TRUE;
138 /* Get clock frequencies (in MHz). */
139 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
143 * The Huntington timer quantum is 1536 sysclk cycles, documented for
144 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
146 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
147 if (encp->enc_bug35388_workaround) {
148 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
149 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
151 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
152 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
155 encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
157 /* Checksums for TSO sends can be incorrect on Huntington. */
158 encp->enc_bug61297_workaround = B_TRUE;
160 encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
161 encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
162 encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
164 /* Alignment for receive packet DMA buffers */
165 encp->enc_rx_buf_align_start = 1;
166 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
168 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
169 encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
171 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
172 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
175 * The workaround for bug35388 uses the top bit of transmit queue
176 * descriptor writes, preventing the use of 4096 descriptor TXQs.
178 encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ?
179 HUNT_TXQ_MAXNDESCS_BUG35388_WORKAROUND :
181 encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
183 EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
184 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
185 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
186 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
188 if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
190 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
192 /* All Huntington devices have a PCIe Gen3, 8 lane connector */
193 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
204 EFSYS_PROBE1(fail1, efx_rc_t, rc);
210 #endif /* EFSYS_OPT_HUNTINGTON */